A path optimization method, device and electronic equipment

Abstract

This application relates to the field of quantum computing technology, and in particular to a path optimization method, apparatus, and electronic device. By performing graph partitioning, this application ensures that no nodes are visited repeatedly in the delivery path corresponding to each connected subgraph, reducing unnecessary travel distances and improving the practicality and rationality of the final path planning. Simultaneously, it transforms the VRP problem into a quantum task that can be processed by the NISQ quantum computer, effectively combining the advantages of quantum computing with practical application needs.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and in particular to a path optimization method, apparatus and electronic device. Background Technology

[0002] Quantum computing technology is rapidly developing, transitioning from basic research to large-scale application. Performance evaluation results of quantum computers (also called quantum systems) are crucial for allocating quantum tasks to quantum computers when they are used on a large scale. Furthermore, they provide benchmarks for quantum computer manufacturers, algorithm developers, and end-users, enabling them to plan resources more effectively.

[0003] The Vehicle Routing Problem (VRP) is a classic combinatorial optimization problem that aims to design optimal routes for a set of vehicles to visit multiple customer points while satisfying constraints (such as vehicle capacity, time windows, etc.) and minimizing total cost or distance. VRP has wide applications in logistics, distribution, and transportation. However, as the problem size increases, classic heuristic algorithms (such as genetic algorithms and simulated annealing) struggle to obtain high-quality solutions within a reasonable timeframe and cannot guarantee optimality.

[0004] In recent years, quantum computing has provided new approaches to solving combinatorial optimization problems, especially the quantum approximation optimization algorithm (QAOA), which can be used to solve optimization problems of the Ising model form. However, current quantum computers are in the NISQ (Noisy Intermediate-Scale Quantum) era, with a limited number of qubits and high noise, making it difficult to directly handle large-scale VRP problems. Existing quantum solutions typically decompose the problem into subproblems, but still face challenges such as insufficient resources and excessive circuit depth.

[0005] Therefore, there is an urgent need for a hybrid approach that can effectively solve large-scale VRP problems on existing NISQ equipment. Summary of the Invention

[0006] This application provides a path optimization method, apparatus, and electronic device that adapts large-scale VRP problems to current NISQ devices for solving through classical graph partitioning, thereby effectively combining the advantages of quantum computing with practical application needs.

[0007] The first aspect of this application provides a path optimization method, including:

[0008] Obtain the graph structure of the vehicle routing problem to be solved, and determine the number of vehicles responsible for delivery; wherein, the graph structure includes multiple nodes, edges connecting the nodes and weights on the edges, and the multiple nodes include at least one warehouse node and multiple customer delivery nodes;

[0009] Remove the warehouse node from the graph structure, and divide the multiple customer delivery nodes into multiple subgraphs based on the number of vehicles; add the warehouse node to each subgraph to form a corresponding connected subgraph.

[0010] Each edge of a connected subgraph is mapped to a number of qubits, and a Hamiltonian is constructed based on constraints of the vehicle path problem; wherein the constraints are transformed into penalty terms of the Hamiltonian.

[0011] Based on the aforementioned qubits and Hamiltonian, a QAOA quantum circuit is constructed and run to obtain the path approximate solution of the connected subgraph. The optimal solution of the vehicle routing problem is obtained by summing the path approximate solutions of the several connected subgraphs.

[0012] Optionally, the number of vehicles is the same as the number of subgraphs.

[0013] Optionally, there exists an edge between any two nodes in the connected subgraph and there are no duplicate nodes.

[0014] Optionally, mapping each edge of a connected subgraph to a plurality of qubits includes:

[0015] Amplitude coding is used to map the edges of each connected subgraph to several qubits.

[0016] Optionally, the constraints include using the warehouse node as the starting and ending point, and each node having an out-degree and an in-degree of 1.

[0017] Optionally, constructing a QAOA quantum circuit based on the plurality of qubits and the Hamiltonian includes:

[0018] The Hamiltonian is decomposed into parameterized quantum gates;

[0019] The QAOA quantum circuit is constructed by combining the quantum gate and the plurality of qubits.

[0020] Optionally, the step of constructing a QAOA quantum circuit based on the plurality of qubits and the Hamiltonian and running it to obtain a path approximation solution for the connected subgraph includes:

[0021] When the number of qubits in the QAOA quantum circuit exceeds the maximum resource limit of the current quantum processor, the QAOA quantum circuit is split into several sub-quantum circuits and run.

[0022] By merging the results of several sub-circuits through classical post-processing, an approximate solution for the path of the connected subgraph is obtained.

[0023] A second aspect of this application provides a path optimization apparatus, comprising:

[0024] The graph structure acquisition module acquires the graph structure of the vehicle routing problem to be solved and determines the number of vehicles responsible for delivery; wherein, the graph structure includes multiple nodes, edges connecting the nodes and weights on the edges, and the multiple nodes include at least one warehouse node and multiple customer delivery nodes;

[0025] The connected subgraph determination module is used to remove the warehouse node from the graph structure, divide the multiple customer delivery nodes into multiple subgraphs according to the number of vehicles, and add the warehouse node to each subgraph to form a corresponding connected subgraph.

[0026] The mapping module is used to map the edges of each connected subgraph to several qubits, and to construct a Hamiltonian based on the constraints of the vehicle path problem; wherein the constraints are transformed into penalty terms of the Hamiltonian.

[0027] The optimal path solving module is used to construct a QAOA quantum circuit based on the aforementioned qubits and Hamiltonian, and run it to obtain the path approximate solution of the connected subgraph. The optimal solution of the vehicle path problem is obtained by summing the path approximate solutions of the aforementioned connected subgraphs.

[0028] A third aspect of this application provides an electronic device, including: a processor and a memory;

[0029] The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application.

[0030] A fourth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application.

[0031] This application ensures that no nodes are visited repeatedly in the delivery path corresponding to each connected subgraph by performing graph partitioning, thereby reducing invalid travel distances and improving the practicality and rationality of the final route planning. At the same time, it transforms the VRP problem into a quantum task that can be processed by the NISQ quantum computer, effectively combining the advantages of quantum computing with the needs of practical applications. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A system block diagram of a quantum system provided in one embodiment of this application is shown;

[0034] Figure 2 A schematic flowchart of a path optimization method provided in one embodiment of this application is shown;

[0035] Figure 3 This illustration shows a schematic diagram of subgraph partitioning provided in one embodiment of this application;

[0036] Figure 4 This illustration shows a schematic diagram of the structure of a path optimization device according to an embodiment of this application;

[0037] Figure 5 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0039] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0040] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then 2^n qubits can represent n bits of data. nA quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0041] Please refer to Figure 1 This illustrates a block diagram of a quantum system provided in one embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0042] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0043] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0044] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0045] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0046] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0047] The quantum chip of the aforementioned quantum system 110 requires full consideration of its performance from design to manufacturing and use. Only by using the quantum system after a preliminary assessment and understanding of its performance, including but not limited to assigning quantum computing tasks to the quantum system, can the effect of achieving twice the result with half the effort be achieved.

[0048] In summary, the classical computer 120 is responsible for performing classical computation and control; the quantum system 110 is responsible for running the quantum program (also called a quantum computing task or quantum circuit) to achieve quantum computing. Specifically, the quantum program is a sequence of instructions written in a quantum language such as QRunes that can run on a quantum computer. It supports quantum logic gate operations and ultimately realizes quantum computing, thus achieving the overall quantum computing task. In other words, a quantum program is a sequence of instructions that operates on quantum logic gates according to a specific timing order.

[0049] In practical applications, due to limitations in the development of quantum device hardware, quantum computing simulations are typically required to verify quantum algorithms, quantum applications, and so on. Quantum computing simulation is the process of simulating the execution of a quantum program corresponding to a specific problem using a virtual architecture (i.e., a quantum virtual machine) built with the resources of a conventional computer. Typically, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program referred to in the embodiments of this application is a program written in a classical language that represents qubits and their evolution, wherein qubits, quantum logic gates, etc., related to quantum computing all have corresponding classical code representations.

[0050] Quantum circuits, also known as quantum logic circuits, are a manifestation of quantum programming and are the most commonly used general-purpose quantum computing model. They represent circuits that operate on qubits under an abstract concept. They consist of qubits, circuits (timelines), and various quantum logic gates. Finally, the results are often read out through quantum measurement operations.

[0051] Unlike traditional circuits that use metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as being connected by time. That is, the state of a quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated on.

[0052] A quantum program corresponds to a single quantum circuit. The quantum program described in this invention refers to this single quantum circuit, where the total number of qubits in the single quantum circuit is the same as the total number of qubits in the quantum program. This can be understood as follows: a quantum program can consist of a quantum circuit, measurement operations on the qubits within the quantum circuit, registers for storing measurement results, and control flow nodes (jump instructions). A single quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution of a quantum program is the process of executing all the quantum logic gates in a specific timing order. It should be noted that the timing order refers to the chronological sequence in which individual quantum logic gates are executed.

[0053] It's important to note that in classical computing, the most basic unit is the bit, and the most fundamental control mode is the logic gate. Circuit control can be achieved through combinations of logic gates. Similarly, the way to process qubits is through quantum logic gates. Quantum logic gates enable the evolution of quantum states and are the foundation of quantum circuits. Quantum logic gates include single-qubit gates, such as Hadamard gates (H-gates), Pauli-X gates (X-gates), Pauli-Y gates (Y-gates), Pauli-Z gates (Z-gates), RX gates, RY gates, RZ gates, etc.; and multi-qubit gates, such as CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc. Quantum logic gates are generally represented using unitary matrices, which are not only matrix forms but also operations and transformations. Generally, the effect of a quantum logic gate on a quantum state is calculated by left-multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.

[0054] Please refer to Figure 2 The diagram illustrates a flowchart of a path optimization method according to this application. This method can be applied to computer equipment, which refers to electronic devices capable of data computation and processing. For example, the executing entity for each step can be... Figure 1 The method may include the following steps: a quantum computer or a classical computer (selected as needed).

[0055] S201: Obtain the graph structure of the vehicle routing problem to be solved and determine the number of vehicles responsible for delivery; wherein the graph structure includes multiple nodes, edges connecting the nodes, and weights on the edges, and the multiple nodes include at least one warehouse node and multiple customer delivery nodes; S202: Remove the warehouse node from the graph structure, and divide the multiple customer delivery nodes into multiple subgraphs according to the number of vehicles; add the warehouse node to each subgraph to form a corresponding connected subgraph; S203: Map the edges of each connected subgraph to several qubits, and construct a Hamiltonian based on the constraints of the vehicle routing problem; wherein the constraints are converted into penalty terms of the Hamiltonian; S204: Construct a QAOA quantum circuit based on the several qubits and the Hamiltonian and run it to obtain the path approximate solution of the connected subgraph, and summarize the path approximate solutions of several connected subgraphs to obtain the optimal solution of the vehicle routing problem.

[0056] Taking a supermarket chain that needs to deliver fresh produce to 200 community convenience stores (customer delivery nodes) in a city as an example, there is one central warehouse (warehouse node) and 20 delivery trucks (number of vehicles). To solve the optimal vehicle routing problem, the specific steps are as follows:

[0057] Graph Structure Acquisition and Vehicle Quantity Determination: Road network data of the delivery area is obtained through the supermarket logistics system, and a graph structure G = (V, E, w) is constructed. Here, V contains 1 warehouse node and 200 convenience store nodes, for a total of 201 nodes; E represents the traversable road routes between nodes, totaling 320 routes; w is the route weight, which is the actual driving distance (in kilometers) of the corresponding road. The number of vehicles is determined to be 20.

[0058] Subgraph partitioning and connected subgraph formation: Remove warehouse nodes from graph structure G. Using a clustering algorithm or a greedy algorithm, based on the geographical distribution of convenience store nodes, divide the 200 convenience store nodes into 20 initial subgraphs (each subgraph contains 10 customer delivery nodes). Then, add the warehouse nodes to the 20 initial subgraphs to form 20 connected subgraphs. Each connected subgraph corresponds to the delivery task of one truck.

[0059] Quantum bit mapping and Hamiltonian construction: For each connected subgraph, amplitude encoding is used to map the 16 edges (each subgraph contains an average of 16 edges) within the subgraph to 5 qubits (achieving efficient mapping between edges and qubits through amplitude superposition). Simultaneously, based on the constraints of the vehicle routing problem (warehouses as start and end points, out-degree = in-degree = 1 for each convenience store node), the Hamiltonian H of the Ising model is constructed, transforming the constraints into penalty terms incorporated into the Hamiltonian. Here, the out-degree refers to the number of edges pointing from one node to other nodes in the connected subgraph; the in-degree refers to the number of edges pointing from other nodes to that node. Taking a logistics scenario as an example, the in-degree of a node represents the number of paths entering that delivery point, and the out-degree represents the number of paths leaving that delivery point.

[0060] QAOA Quantum Circuit Construction and Path Finding: Based on 5 qubits and the Hamiltonian H, a QAOA quantum circuit (containing 12 layers of iterative gates, including Hadamard gates, CZ gates, and RX gates) is constructed. Running this circuit on a 10-qubit quantum processor yields approximate path solutions for each connected subgraph (e.g., "Warehouse → Convenience Store A → Convenience Store C → ... → Convenience Store J → Warehouse"). By summing the approximate path solutions for the 20 connected subgraphs, the total travel distance of the optimal route for the complete delivery plan involving 20 trucks is obtained.

[0061] By decomposing the large-scale VRP problem with 201 nodes into 20 smaller subproblems through subgraph partitioning, the problem of high computational resource consumption and long processing time of traditional classical algorithms when dealing with large-scale problems is solved. This ensures that no nodes are visited repeatedly in the delivery path corresponding to each connected subgraph, reducing invalid travel distance and improving the practicality and rationality of the final path planning. With the approximate optimization capability of the QAOA quantum algorithm, the total travel distance of the obtained delivery solution is significantly shortened compared with the traditional greedy algorithm, significantly reducing logistics and transportation costs.

[0062] It should be noted that this method is not limited to fresh food delivery scenarios, but can be widely applied to various VRP scenarios such as express delivery and urban public transport scheduling, and has good scenario adaptability.

[0063] Specifically, the Hamiltonian H for constructing the Ising model includes:

[0064] Base Model Selection: The Ising model is adopted as the basic framework for constructing the Hamiltonian. The core expression of the Hamiltonian in the Ising model is: in, For the Pauli-Z operator of the i-th qubit, J ij h is the coupling coefficient between qubits i and j. i Let i be the local field of qubit i.

[0065] Constraints are transformed into penalty terms:

[0066] Warehouse start and end point constraints: Let the warehouse node be v0. If the path does not start or end at v0, a penalty term is introduced. in, This represents the state of the vehicle at time t as it travels from node i to node j. Indicates driving. (Indicates no travel), T is the total path time, and λ1 is the penalty coefficient (set to 10 to ensure a high penalty percentage when constraints are violated). The Hamiltonian is described using the Ising model framework from quantum computing, in which the qubit state... With classic variables A mapping relationship exists:

[0067] when When, corresponding (Vehicles travel on this route);

[0068] when When, corresponding (Vehicles do not travel on this route);

[0069] Therefore, the penalty item In quantized expression, through (The warehouse node corresponds to a quantum bit) and The coupling term implementation (corresponding to the qubit at the client node) does not require direct writing.

[0070] The complete quantization penalty term is actually: in, Equivalent to classical variables (only when) and The value is 0 when both are 1 and 1 otherwise (i.e., penalizing cases where the message did not originate from the warehouse). Therefore, the simplified formula does not directly reflect this. However, it is logically completely consistent with the quantized expression.

[0071] Node out-degree = in-degree = 1 constraint: For each convenience store node v k (k≠0, all customer delivery nodes except warehouse nodes), where k is the customer node number. If the out-degree ≠ 1, a penalty term is introduced. Where the subscript k represents the current customer node, and j represents other nodes (including warehouses or other customer nodes); the superscript t represents the time step (representing a link in the delivery path); When the value is 1, it means that at time t, the vehicle travels from customer node k to node j (out-degree behavior); A value of 0 indicates that the route will not be traveled; if the in-degree is not equal to 1, a penalty term is introduced. in, Let λ2 represent the vehicle's journey from node j to customer node k at time t (in-degree behavior). λ2 and λ2 are penalty coefficients, which are used to strengthen the penalty for constraint violations through the squared term.

[0072] Objective function integration: The goal of the VRP problem is to minimize the total travel distance. The objective function is transformed into the energy term of the Hamiltonian. Among them, w ij Let (i, j) be the weight (distance traveled).

[0073] Complete Hamiltonian: Combining the basic model, penalty term, and objective function, we obtain the complete Hamiltonian H = H base +H obj The algorithm, consisting of +H1+H2+H3, adjusts the penalty coefficients to ensure that the constraints are satisfied preferentially while minimizing the objective function. Constructing a Hamiltonian provides data support for subsequent fast solutions using quantum computers.

[0074] Optionally, the number of vehicles is the same as the number of subgraphs.

[0075] When dividing the graph into 20 subgraphs, the goal of clustering or greedy algorithms is not only to achieve 10 subgraphs, but also to ensure load balancing. The clustering or greedy algorithms calculate the geographical coordinates and distances between all customer points. For example, K-means clustering can be used to divide 200 nodes into 20 clusters, optimizing the cluster centers so that the number of customer nodes in each cluster is as close to 50 as possible (e.g., between 48 and 52), and the total distance (weighted sum) between all customer points and the warehouse within each cluster is also as even as possible, avoiding situations where a particular vehicle's journey is too long or too short. This balanced partitioning ensures that the workload (number of customers) and travel cost (total distance) of each delivery route are roughly equivalent, avoiding uneven task distribution and better meeting actual logistics management needs. Simultaneously, balanced subproblems result in more consistent convergence speeds in subsequent quantum optimization processes, preventing any single subproblem from becoming a bottleneck in the entire computational process due to excessive complexity.

[0076] Optionally, there exists an edge between any two nodes in the connected subgraph and there are no duplicate nodes.

[0077] The algorithm checks the connected subgraph: Starting from the warehouse node, does there exist a path that visits every customer delivery node without repeating any nodes and eventually returns to the warehouse node? Connectivity is verified using depth-first search (DFS) or union-find algorithms, ensuring that there are no loops with duplicate nodes. Ultimately, the connected subgraph is confirmed as a valid Hamiltonian cycle problem instance. The connectivity and absence of duplicate nodes in the connected subgraph are prerequisites for transforming the VRP problem into a TSP (Traveling Salesman Problem) class problem and performing quantum encoding. This constraint ensures that each subproblem is well-defined, allowing the Hamiltonian of the subsequently constructed Ising model to accurately reflect the original problem. Eliminating invalid subgraph partitions in the classical stage avoids wasting resources on constructing and solving quantum paths that cannot yield valid solutions, thus improving overall computational efficiency.

[0078] Optionally, mapping each edge of a connected subgraph to a plurality of qubits includes:

[0079] Amplitude coding is used to map the edges of each connected subgraph to several qubits.

[0080] Different encoding methods can be used when performing quantum encoding. For example, amplitude encoding can use one qubit to represent one edge, or one qubit to represent multiple edges. We can compare different encoding methods and choose the one that facilitates the splitting and recombination of the quantum circuit. By selecting quantum encoding methods based on the criterion of "facilitating circuit splitting and recombination," the problem of poor compatibility between encoding and circuit splitting in existing schemes is solved, ensuring that the encoded circuit can be efficiently adapted to NISQ quantum computer resources.

[0081] Optionally, the constraints include using the warehouse node as the starting and ending point, and each node having an out-degree and an in-degree of 1.

[0082] The constraints are set as follows: the path must start and end at the warehouse node (start and end point constraints), and each customer node must have exactly one incoming edge and one outgoing edge (in-degree constraints). By transforming these constraints into high-weight penalty terms, we ensure that the final path strictly conforms to business requirements, avoid invalid paths that do not conform to actual operations, and improve the feasibility of vehicle routing solutions.

[0083] Optionally, constructing a QAOA quantum circuit based on the plurality of qubits and the Hamiltonian includes: decomposing the Hamiltonian into parameterized quantum gates; and combining the quantum gates and the plurality of qubits to construct the QAOA quantum circuit.

[0084] To leverage the fast solution characteristics of QAOA quantum circuits, the Hamiltonian is decomposed into parameterized quantum gates, and these gates, along with several qubits, are combined to construct the QAOA quantum circuit. This enables the rapid solution of the vehicle routing problem using QAOA quantum circuits.

[0085] Optionally, the step of constructing a QAOA quantum circuit based on the plurality of qubits and the Hamiltonian and running it to obtain an approximate solution for the connected subgraph includes: when the number of qubits in the QAOA quantum circuit exceeds the maximum resource limit of the current quantum processor, splitting the QAOA quantum circuit into a plurality of sub-quantum circuits and running them; and merging the running results of the plurality of sub-circuits through classical post-processing to obtain an approximate solution for the connected subgraph.

[0086] For example, a large chain retail enterprise needs to deliver goods to 300 stores (customer delivery nodes), has one regional distribution center (warehouse node), and invests in 30 delivery vehicles. A connected subgraph contains 15 store nodes, corresponding to 22 edges, which are mapped to 7 qubits using amplitude encoding. The QAOA quantum circuit requires 7 qubits, but the maximum available quantum processor has a maximum of 5 qubits (exceeding the resource limit). Therefore, the quantum circuit needs to be split, and the specific steps are as follows:

[0087] Circuit splitting judgment: It was detected that the QAOA quantum circuit requires 7 qubits, which exceeds the current quantum processor's resource limit of 5 qubits, so it was decided to split the quantum circuit.

[0088] Quantum circuit splitting: Based on the correlation between qubits (judged by the coupling coefficient of the Hamiltonian; qubits with a coupling coefficient close to 0 have weak correlation), the 7 qubits are divided into two groups: Group 1 contains qubits 0, 1, and 2 (corresponding to 10 edges), and Group 2 contains qubits 3, 4, 5, and 6 (corresponding to 12 edges). The original QAOA circuit is split into two sub-quantum circuits (sub-circuit 1: based on qubits of group 1, with 8 iterative gates; sub-quantum circuit 2: based on qubits of group 2, with 10 iterative gates). The number of qubits required for each sub-circuit (3 and 4) is within the 5-qubit resource limit.

[0089] Sub-quantum circuit operation: Sub-quantum circuit 1 and sub-quantum circuit 2 are run on a 5-qubit quantum processor respectively. Sub-quantum circuit 1 outputs measurement result M1 (probability distribution: path P1 probability 45%, path P2 probability 30%, etc.), and sub-quantum circuit 2 outputs measurement result M2 (probability distribution: path Q1 probability 50%, path Q2 probability 25%, etc.).

[0090] Classical post-processing and result summary: The "probability fusion algorithm" is used for classical post-processing to fuse the probability distributions of M1 and M2 and calculate the path probability distribution of the original route (e.g., "Warehouse → Store A → Store B → ... → Store O → Warehouse" probability 48%). This path is the approximate solution of the connected subgraph.

[0091] By using circuit splitting and classical post-processing, the QAOA quantum circuit, which originally required 7 qubits, can run on a 5-qubit quantum processor, breaking through the resource limitations of existing NISQ quantum hardware and enabling the solution of large-scale VRP problems on existing sub-devices. At the same time, the classical post-processing algorithm can effectively integrate the running results of the sub-circuits and restore the solution accuracy of the original circuit. Through the two-layer decomposition strategy of "subgraph partitioning + circuit splitting", the large-scale VRP problem is transformed into a small-scale task that can be processed by the NISQ quantum computer.

[0092] Reference Figure 3 The diagram shows the division of the subgraph into four different subgraphs. In each subgraph, the delivery customer node 1 and the warehouse node 2 form a connected subgraph.

[0093] Reference Figure 4 The model fine-tuning training device based on a quantum computing machine provided in this application includes:

[0094] The graph structure acquisition module 301 acquires the graph structure of the vehicle routing problem to be solved and determines the number of vehicles responsible for delivery; wherein, the graph structure includes multiple nodes, edges connecting the nodes and weights on the edges, and the multiple nodes include at least one warehouse node and multiple customer delivery nodes.

[0095] The connected subgraph determination module 302 is used to remove the warehouse node from the graph structure, divide the multiple customer delivery nodes into multiple subgraphs according to the number of vehicles, and add the warehouse node to each subgraph to form a corresponding connected subgraph.

[0096] The mapping module 303 is used to map the edges of each connected subgraph to a number of qubits, and to construct a Hamiltonian based on the constraints of the vehicle path problem; wherein the constraints are converted into a penalty term of the Hamiltonian.

[0097] The optimal path solving module 304 is used to construct a QAOA quantum circuit based on the plurality of qubits and the Hamiltonian and run it to obtain the path approximate solution of the connected subgraph, and to summarize the path approximate solutions of the plurality of connected subgraphs to obtain the optimal solution of the vehicle path problem.

[0098] Regarding the apparatus in the above embodiments, the process of performing each step has been described in the relevant method embodiments, and will not be repeated here.

[0099] Figure 5 The diagram illustrates the structure of a computer device according to an embodiment of this application, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the function of a path optimization method in any of the above embodiments.

[0100] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the function of a path optimization method in any of the above embodiments.

[0101] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the function of a path optimization method in any of the above embodiments.

[0102] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0103] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0104] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0105] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0106] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0107] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0108] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0110] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0111] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0112] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0113] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0114] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A path optimization method, characterized in that, include: Obtain the graph structure of the vehicle routing problem to be solved, and determine the number of vehicles responsible for delivery; wherein, the graph structure includes multiple nodes, edges connecting the nodes and weights on the edges, and the multiple nodes include at least one warehouse node and multiple customer delivery nodes; Remove the warehouse node from the graph structure, and divide the multiple customer delivery nodes into multiple subgraphs based on the number of vehicles; add the warehouse node to each subgraph to form a corresponding connected subgraph. Each edge of a connected subgraph is mapped to a number of qubits, and a Hamiltonian is constructed based on constraints of the vehicle path problem; wherein the constraints are transformed into penalty terms of the Hamiltonian. Based on the aforementioned qubits and Hamiltonian, a QAOA quantum circuit is constructed and run to obtain the path approximate solution of the connected subgraph. The optimal solution of the vehicle routing problem is obtained by summing the path approximate solutions of the several connected subgraphs.

2. The method according to claim 1, characterized in that, The number of vehicles is the same as the number of subgraphs.

3. The method according to claim 1, characterized in that, There is an edge between any two nodes in the connected subgraph and no duplicate nodes.

4. The method according to claim 1, characterized in that, The process of mapping the edges of each connected subgraph to a number of qubits includes: Amplitude coding is used to map the edges of each connected subgraph to several qubits.

5. The method according to claim 1, characterized in that, The constraints include using the warehouse node as the starting and ending point, and ensuring that the out-degree and in-degree of each node are both 1.

6. The method according to claim 1, characterized in that, The construction of the QAOA quantum circuit based on the plurality of qubits and the Hamiltonian includes: The Hamiltonian is decomposed into parameterized quantum gates; The QAOA quantum circuit is constructed by combining the quantum gate and the plurality of qubits.

7. The method according to claim 1, characterized in that, The process of constructing a QAOA quantum circuit based on the aforementioned qubits and the Hamiltonian, and then running it to obtain the path approximation solution of the connected subgraph, includes: When the number of qubits in the QAOA quantum circuit exceeds the maximum resource limit of the current quantum processor, the QAOA quantum circuit is split into several sub-quantum circuits and run. By merging the results of several sub-circuits through classical post-processing, an approximate solution for the path of the connected subgraph is obtained.

8. A path optimization device, characterized in that, include: The graph structure acquisition module acquires the graph structure of the vehicle routing problem to be solved and determines the number of vehicles responsible for delivery; wherein, the graph structure includes multiple nodes, edges connecting the nodes and weights on the edges, and the multiple nodes include at least one warehouse node and multiple customer delivery nodes; The connected subgraph determination module is used to remove the warehouse node from the graph structure, divide the multiple customer delivery nodes into multiple subgraphs according to the number of vehicles, and add the warehouse node to each subgraph to form a corresponding connected subgraph. The mapping module is used to map the edges of each connected subgraph to several qubits, and to construct a Hamiltonian based on the constraints of the vehicle path problem; wherein the constraints are transformed into penalty terms of the Hamiltonian. The optimal path solving module is used to construct a QAOA quantum circuit based on the aforementioned qubits and Hamiltonian, and run it to obtain the path approximate solution of the connected subgraph. The optimal solution of the vehicle path problem is obtained by summing the path approximate solutions of the aforementioned connected subgraphs.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-7.

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