Method and apparatus for determining sub-chip of quantum chip, and electronic device

Abstract

The present disclosure provides a method and device for determining a sub-chip of a quantum chip, and an electronic device, and relates to the technical field of computers, in particular to the technical field of quantum computing and chip characterization. The specific implementation scheme is as follows: determining a first number of quantum bits required to be used according to a computing task; determining an initial configuration according to the first number and a pre-characterization map of the quantum chip; the pre-characterization map is a square tiling map-shaped configuration with a rectangular contour, and the pre-characterization map includes a plurality of first nodes corresponding to a plurality of quantum bits of the quantum chip one by one; determining a plurality of candidate characterization maps from the pre-characterization map according to the initial configuration; each candidate characterization map includes a plurality of second nodes corresponding to part of the quantum bits of the quantum chip one by one; determining the connectivity of a plurality of candidate sub-chips corresponding to the plurality of candidate characterization maps; and determining a target sub-chip from the plurality of candidate sub-chips according to the connectivity. According to the technology of the present disclosure, the best-performing sub-chip can be selected from the quantum chip.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computing and chip fabrication technology. Background Technology

[0002] Quantum computing has become a crucial area of ​​research and development in both academia and industry in recent years. Compared to traditional computing, quantum computing has demonstrated significant advantages in solving problems such as large number factorization. Furthermore, it holds importance for cutting-edge research in areas such as quantum many-body systems and quantum chemical simulations. In terms of hardware implementation, quantum computing offers various technological solutions, including superconducting circuits, ion traps, and photonic quantum computing. Benefiting from its long decoherence time, ease of manipulation and readout, and strong scalability, superconducting circuits are considered the most promising candidate for quantum computing hardware. Summary of the Invention

[0003] This disclosure provides a method, apparatus, and electronic device for determining sub-chips of a quantum chip.

[0004] According to one aspect of this disclosure, a method for determining a sub-chip of a quantum chip is provided, comprising:

[0005] Determine the initial number of qubits required based on the computational task;

[0006] Based on the first quantity and the pre-detailed pattern of the quantum chip, the initial configuration is determined; wherein, the pre-detailed pattern is a square tessellation configuration with a rectangular outline, and the pre-detailed pattern includes multiple first nodes that correspond one-to-one with multiple qubits of the quantum chip;

[0007] Based on the initial configuration, multiple candidate characterization patterns are determined from the pre-characterization pattern; each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip;

[0008] Determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns; and

[0009] The target sub-chip is determined from multiple candidate sub-chips based on connectivity.

[0010] According to another aspect of this disclosure, a device for determining a sub-chip of a quantum chip is provided, comprising:

[0011] The first determining module is used to determine the first number of qubits to be used based on the computational task.

[0012] The second determining module is used to determine the initial configuration based on the first quantity and the pre-detailed pattern of the quantum chip; wherein the pre-detailed pattern is a square tessellation pattern with a rectangular outline, and the pre-detailed pattern includes multiple first nodes that correspond one-to-one with multiple qubits of the quantum chip;

[0013] The third determining module is used to determine multiple candidate characterization patterns from the pre-characterization pattern based on the initial configuration; wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip;

[0014] The fourth determining module is used to determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns; and

[0015] The fifth determination module is used to determine the target sub-chip from multiple candidate sub-chips based on connectivity.

[0016] According to another aspect of this disclosure, an electronic device is provided, comprising:

[0017] At least one processor; and

[0018] The memory is communicatively connected to the at least one processor; wherein,

[0019] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the methods described in the present disclosure.

[0020] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform any of the methods according to embodiments of this disclosure.

[0021] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the methods according to embodiments of this disclosure.

[0022] According to the technology disclosed herein, it is possible to select the sub-chip with the best performance in a quantum chip.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0024] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0025] Figure 1 This is a schematic diagram of a method for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of a first topological structure of a quantum chip according to an embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of a first topological structure of a quantum chip according to an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of determining candidate characterization patterns in the first topological structure diagram of a quantum chip according to an embodiment of the present disclosure;

[0029] Figure 5 This is a schematic diagram of determining candidate characterization patterns in the first topological structure diagram of a quantum chip according to an embodiment of the present disclosure;

[0030] Figure 6 This is a schematic diagram of determining candidate characterization patterns in the first topological structure diagram of a quantum chip according to an embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of a device for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure;

[0032] Figure 8 This is a block diagram of an electronic device used to implement the method for determining the sub-chip of a quantum chip according to embodiments of the present disclosure. Detailed Implementation

[0033] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0034] like Figure 1 As shown, this disclosure provides a method for determining a sub-chip of a quantum chip, including:

[0035] Step S101: Determine the first number of qubits required based on the computation task.

[0036] Step S102: Determine the initial configuration based on the first quantity and the pre-detailed pattern of the quantum chip. The pre-detailed pattern is a square tessellation configuration with a rectangular outline, and includes multiple first nodes corresponding one-to-one with the multiple qubits of the quantum chip.

[0037] Step S103: Based on the initial configuration, determine multiple candidate characterization patterns from the pre-characterization pattern. Each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip.

[0038] Step S104: Determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns.

[0039] as well as

[0040] Step S105: Determine the target sub-chip from multiple candidate sub-chips based on connectivity.

[0041] According to the embodiments of this disclosure, it should be noted that:

[0042] Computational tasks can be understood as tasks that require the use of quantum chips to perform calculations on specific data.

[0043] The first number of qubits can be understood as the number of qubits contained in the sub-chip to be determined from the quantum chip. That is to say, the number of second nodes containing qubits for characterizing the sub-chip in each candidate pattern is consistent with the first number.

[0044] A quantum subchip can be understood as a chip composed of a subset of the qubits of a quantum chip. In practical applications of quantum computers, not all the qubits on a quantum chip are necessarily used. Therefore, a subset of qubits can be selected from a given quantum chip, and a superconducting quantum subchip can be virtually constructed. This allows the qubits of the subchip to be used to perform corresponding computational tasks, saving the overall computational resources of the quantum chip.

[0045] A pre-detailed pattern can be understood as a first topological structure diagram containing distance weights, pre-detailed based on the chip information of a quantum chip. The structure of the first topological structure diagram depends on the number of qubits contained in the quantum chip and the communication relationships between them. Depending on the number of qubits and the different communication relationships between them, the first topological structure diagram of the quantum chip can be determined as follows: Figure 2 The rectangular tiling structure is shown. The first topological graph, containing distance weight information, can be understood as the distance weight between the qubits corresponding to the two nodes connected by the associated edges on each edge of the first topological graph. Chip information can be understood as information that can be directly read from the quantum chip, including but not limited to the number of qubits, quantum gate information, and the fidelity between each qubit. The distance weight between each qubit can be determined based on whether there is a communication relationship between the qubits and / or communication overhead.

[0046] The square tessellation of a rectangular outline can be understood as a tessellation formed by overlapping squares of equal side length, with each point and side overlapping the other. The rectangular outline itself can be understood as a rectangle cut from the tessellation, where each side of the rectangle has a square side parallel to it. An example of a square tessellation of a rectangular outline is shown below. Figure 2 As shown, it is specifically defined as:

[0047] Define the set of first nodes, i.e., the point set:

[0048] V m,n ={(j,k)|j=0,1,…,m-1,k=0,1,…,n-1}

[0049] Where j and k are the coordinates of the first node on the X and Y axes, m represents the number of columns of the square tessellation pattern of the rectangular outline, and n represents the number of rows of the square tessellation pattern of the rectangular outline.

[0050] Define the connecting edges between each first node, i.e., the set of undirected edges:

[0051]

[0052] Here, v1 and v2 represent any two first nodes, and E represents the edge connecting the two first nodes.

[0053] Based on V m,n and E m,n , constitute as Figure 2 The plan view G shown m,n =(V m,n E m,n This refers to a square tessellation pattern with m columns and n rows, possessing a rectangular outline, where m and n are both positive integers. It should be noted that... Figure 2 The dashed lines in the diagram represent several square structures omitted on the X and Y axes.

[0054] A candidate characterization can be understood as a configuration diagram obtained by transforming the initial configuration based on a traversal search of the pre-characterization diagram, and the number of second nodes contained therein is consistent with the first number of qubits required according to the computational task. For example, such as Figure 3 As shown, the quantum chip includes Q0 to Q10. 11 There are 12 fully functional qubits, corresponding to 12 nodes in the first topological diagram. Based on the quantum gate information in the quantum chip's chip information, it can be seen that Q0 communicates with Q1 and Q3; Q1 communicates with Q0, Q2, and Q4; Q2 communicates with Q1 and Q5; Q3 communicates with Q0, Q4, and Q6; Q4 communicates with Q1, Q3, Q5, and Q7; Q5 communicates with Q2, Q4, and Q8; Q6 communicates with Q3, Q7, and Q9; and Q7 communicates with Q4, Q6, Q8, and Q9. 10 There is a communication relationship between Q8 and Q5, Q7, and Q6. 11 There is a communication relationship between Q9 and Q6, Q 10 There is a communication relationship, Q 10 Compared with Q7, Q9, Q 11 There is a communication relationship, Q11 With Q8, Q 10 There is a communication relationship. When the number of qubits required for the computational task is determined to be six, then... Figure 3 The configuration of the target sub-chip consisting of six qubits is determined in the first topological structure diagram of the quantum chip.

[0055] Connectivity can be calculated using any method available in the prior art, and no specific limitation is made here.

[0056] The specific shape of the initial configuration can be selected and adjusted as needed. The initial configuration consists of multiple third nodes and edges connecting each third node. The second number of third nodes in the initial configuration can be greater than or less than the first number of qubits required by the sub-chip. Based on the second number of third nodes in the initial configuration, a candidate characterization pattern is formed. Since the number of second nodes in the candidate characterization pattern is the same as the first number, the shape of the candidate characterization pattern can be constructed by adding or removing nodes based on the initial configuration.

[0057] According to the technology of this disclosure, in quantum computers such as superconducting circuits, quantum dots, and NV (nitrogen-vacancy centers), due to topological constraints, two qubits may not necessarily interact through a two-qubit gate. Considering that in actual quantum circuit operation, it may not be necessary to use all the qubits on the quantum chip, a key issue is how to select suitable qubits on a given quantum chip to run the corresponding quantum circuit while ensuring optimal overall performance of the selected qubits. The method of this disclosure can effectively solve this problem. Using this method, several qubits conforming to the target configuration can be selected from a specific quantum chip to form a sub-chip, maximizing the overall performance of the sub-chip and meeting the requirements of the computational task. On a square tessellation, even with a specified number of qubits for the sub-chip, the corresponding candidate characterizations are exponentially numerous. The method of this disclosure first determines the initial configuration and then determines the candidate characterizations based on it, avoiding exponential traversal of candidate characterizations and efficiently determining the target sub-chip even when the target number of qubits t is relatively large. The method disclosed herein has a wide range of applications, suitable for determining sub-chips from quantum chips with different structures and technical approaches. The method is highly practical, as the selection of certain qubits is a practical issue of concern to the industry now and in the future. The method is computationally efficient; under applicable conditions, the sub-chip determination method proposed in this disclosure can efficiently calculate the optimal qubits constituting the sub-chip, with low computational complexity and high efficiency.

[0058] In one example, the method for determining the sub-chip of the quantum chip according to this disclosure embodiment includes steps S101 to S105, and further includes:

[0059] This includes information about the target sub-chip, the number of qubits contained in the target sub-chip, and the correlation information established between the qubits; and

[0060] Store the associated information.

[0061] According to the technology of the present disclosure embodiments, the number of repetitive calculations of the sub-chip can be reduced. When the same quantum circuit (quantum chip) is executed multiple times, that is, when the same number of qubits are used to perform calculations, it is not necessary to recalculate the qubits used by the sub-chip each time. Instead, the qubits can be stored locally or in the cloud in a certain data structure, and the associated information can be obtained directly from the local or cloud location, thereby quickly calling the sub-chip to perform calculation tasks.

[0062] In one embodiment, the method for determining the sub-chip of the quantum chip according to the present disclosure includes steps S101 to S105, and further includes:

[0063] Step S106: Based on the chip information of the quantum chip, determine the number of qubits and the quantum gate information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip.

[0064] Step S107 determines the first topological structure diagram of the quantum chip based on the quantity information and quantum gate information. The first topological structure diagram is composed of multiple first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.

[0065] Step S108: Determine the distance weights between each qubit based on the quantum gate information.

[0066] Step S109: Obtain the pre-printed pattern of the quantum chip based on the distance weight and the first topological structure diagram.

[0067] According to the embodiments of this disclosure, it should be noted that:

[0068] The quantum chip disclosed in this embodiment can be understood as a chip that has been manufactured but whose quantum chip layout is unknown. The quantum chip layout includes the arrangement and interconnection of each quantum bit. The required quantum chip can be manufactured based on the quantum chip layout.

[0069] Chip information can be understood as information that can be directly read from a quantum chip, including but not limited to information on the number of qubits, quantum gate information, and the fidelity between each qubit.

[0070] Quantitative information can characterize the total number of qubits contained in a quantum chip, or it can characterize the number of undamaged, intact qubits contained in a quantum chip.

[0071] Quantum gate information characterizes the communication relationship between the qubits of a quantum chip. It can be understood that quantum gate information can be used to know whether any two qubits are directly or indirectly connected.

[0072] The first topological structure graph is formed by multiple first nodes and edges connecting the first nodes. Here, a first node represents a qubit, and each first node can have corresponding coordinates in the coordinate system of the first topological structure graph (e.g., ...). Figure 3 (As shown). An edge connecting two adjacent first nodes indicates that the qubits corresponding to the first node have a communication relationship. When any two qubits are directly coupled, there is a communication relationship between them. When any two qubits are indirectly coupled through other qubits, there is a communication relationship between them and other qubits.

[0073] The distance weight between each qubit can be determined based on whether there is a communication relationship and / or communication overhead between the qubits.

[0074] The pre-detailed pattern of a quantum chip can be understood as the distance weight between the qubits corresponding to the two first nodes connected by the associated edges on each edge of the first topological structure graph.

[0075] Two directly adjacent qubits can be understood as being adjacent on a quantum chip when a two-qubit quantum gate is applied.

[0076] According to the technology of this disclosure, an efficient and systematic method for characterizing a quantum chip is provided. This method can graphically describe a pre-characterized pattern of a quantum chip using its chip information, even when the topological structure of a quantum chip already manufactured by another party is unknown. Furthermore, based on the pre-characterized pattern determined by a first topological structure and distance weights, the distance characteristics of the quantum chip can be quantitatively described, providing an operable method for efficiently drawing quantum chip topological structure diagrams. When the pre-characterized pattern of a manufactured quantum chip is unknown, it can be efficiently generated to facilitate subsequent computational tasks. In practical applications of quantum computers, not all qubits on a quantum chip are necessarily used. Therefore, how to select a portion of qubits on a given quantum chip and virtually construct a superconducting quantum sub-chip becomes a crucial issue. After generating the pre-characterized pattern of the quantum chip using the method of this disclosure, a second topological diagram of the desired sub-chip (composed of a portion of the qubits of the quantum chip) can be efficiently and systematically characterized based on the pre-characterized pattern, thereby enabling the selection of a portion of qubits on the quantum chip to form a sub-chip, which can then be used to perform subsequent computational tasks. The technology disclosed herein has a wide range of applications, applicable to quantum chips with different structures, and is not limited by the implementation method of quantum chips. The technology disclosed herein is highly systematic and architectural, capable of systematically characterizing quantum chips and quantum sub-chips, providing a system architecture for subsequent research. The technology disclosed herein is highly operable, enabling efficient and convenient drawing of topological structure diagrams of quantum chips with different structures, as well as the topological structure diagrams of their sub-chips. The technology disclosed herein is highly practical, helping researchers further study the optimal sub-chip problem on quantum chips and providing strong support for solving practical problems.

[0077] In one example, based on the quantity information in the quantum chip's chip information, it can be known that the quantum chip includes Q0 to Q... 11 There are 12 usable qubits. Based on the quantum gate information in the quantum chip's chip information, it can be seen that Q0 communicates with Q1 and Q3; Q1 communicates with Q0, Q2, and Q4; Q2 communicates with Q1 and Q5; Q3 communicates with Q0, Q4, and Q6; Q4 communicates with Q1, Q3, Q5, and Q7; Q5 communicates with Q2, Q4, and Q8; Q6 communicates with Q3, Q7, and Q9; and Q7 communicates with Q4, Q6, Q8, and Q9. 10 There is a communication relationship between Q8 and Q5, Q7, and Q6. 11 There is a communication relationship between Q9 and Q6, Q 10 There is a communication relationship, Q 10 Compared with Q7, Q9, Q 11 There is a communication relationship, Q 11 With Q8, Q10 There is a communication relationship. Based on the above information, a graph can be drawn in a custom coordinate system as follows. Figure 3 The first topological structure diagram is shown. Further, based on the quantum gate information, the distance weights between each qubit of the quantum chip are determined. Based on the distance weights and the first topological structure diagram, a pre-detailed pattern of the quantum chip is obtained.

[0078] In one example, the first topological graph consists of a set of points containing multiple first nodes and a set of edges containing multiple edges. The multiple first nodes correspond to multiple qubits of the quantum chip. The multiple edges correspond to the communication relationships between directly adjacent qubits. Specifically, a quantum chip C with N qubits has a set of points Q on its qubits. Using the qubits as the first nodes in the first topological graph, i.e., using Q as the set of points in the first topological graph, an undirected edge is connected between two qubits that can operate a two-bit quantum gate, i.e., using E = ... With Q j Using the set of undirected edges of a two-qubit gate as the topological graph, an undirected graph G = (Q, E) is constructed, which serves as the first topological graph of the quantum chip C. Specifically, when {Q... i Q j When}∈E, then the quantum bit Q can be... i Q j When a two-qubit quantum gate is applied, the quantum bit Q is called a quantum bit. i Q j They are adjacent on the quantum chip C.

[0079] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, wherein step S108: determining the distance weight between each qubit based on quantum gate information, including:

[0080] Based on quantum gate information, each pair of directly adjacent qubits in the quantum chip is determined.

[0081] Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits.

[0082] The distance weights between each quantum bit are determined based on the fidelity.

[0083] According to the embodiments of this disclosure, it should be noted that:

[0084] The method of calculating distance weights based on fidelity can be selected and adjusted as needed. For example, let Q... i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Qj It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:

[0085] d(Q i Q j )=1-F(Q i Q j ) or d(Q i Q j ) = -log a F(Q i Q j )

[0086] Among them, F(Q) i Q j ()∈[0,1], a is a fixed constant greater than 0 and not equal to 1. We can take a=e as a natural constant. The choice of a here will not make a practical difference to the scheme.

[0087] Determining the distance weights between each qubit can be understood as determining the distance weights between any two directly adjacent or indirectly adjacent qubits in a quantum chip.

[0088] According to the technology of this disclosure, the weight distance between any two directly adjacent qubits and the weight distance between any two indirectly adjacent qubits can be accurately calculated based on the fidelity of the two-qubit gates between directly adjacent qubits. This facilitates the planning of the target qubits required for the computational task based on the distance weights between each qubit.

[0089] In one example, the process of determining the distance weights includes:

[0090] Define the distance between adjacent qubits, and then define the distance between any two qubits based on this. Let Q be the distance between adjacent qubits. i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Q j It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:

[0091] d(Q i Q j )=1-F(Q i Qj ) or d(Q i , Q j ) = -log a F(Q i , Q j )

[0092] where F(Q i , Q j ) ∈ [0, 1], a is a fixed constant greater than 0 and not equal to 1, and a = e can be taken as the natural constant. The selection of a here will not make a practical difference to the scheme.

[0093] Furthermore, if each element in the quantum bit sequence is adjacent on the quantum chip C to the previous element (t, j are non - negative integers, j < t), and all elements are pairwise different, then the quantum bit sequence p is called a path connecting the quantum bits . The distance d(p) of the path p is defined as the sum of the distances between each two consecutive quantum bits in the quantum bit sequence p Thus, the distance between quantum bits can be extended to the non - adjacent case, that is, the distance between two non - directly adjacent quantum bits Q i , Q j is defined as the minimum value of the distances of the paths connecting these two quantum bits. In particular, when the path does not exist, the distance is defined as positive infinity.

[0094] d Q (Q i , Q j ) = min{d(p) | the path p ∈ Q t connects Q i and Q j , t is a non - negative integer}.

[0095] In one implementation, according to the fidelity, the distance weights between each quantum bit are determined, including:

[0096] According to the fidelity, the first distance weight between each two directly adjacent quantum bits is determined.

[0097] According to the first distance weight, the second distance weight between each two indirectly adjacent quantum bits is determined.

[0098] Based on the first distance weight and the second distance weight, the distance weights between each quantum bit are obtained.

[0099] According to the technology of this disclosure, the weight distance between any two directly adjacent qubits and the weight distance between any two indirectly adjacent qubits can be accurately calculated based on the fidelity of the two-qubit gates between directly adjacent qubits. This facilitates the planning of the target qubits required for the computational task based on the distance weights between each qubit.

[0100] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, wherein step S107: determining the first topological structure diagram of the quantum chip based on quantity information and quantum gate information, including:

[0101] The target drawing function is determined based on the quantitative information and the quantum gate information.

[0102] Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

[0103] According to the embodiments of this disclosure, it should be noted that:

[0104] The target drawing function can be understood as a drawing function that can draw the first topological structure diagram of the target structure shape. With the quantity and quantum gate information remaining constant, the target drawing function can also be different depending on the requirements. That is to say, even when the number of qubits and the communication relationships between them are fixed, different first topological structure diagrams can be obtained by adjusting the layout positions (coordinates) of the nodes corresponding to each qubit.

[0105] For example, quantum chips include Q0 to Q10. 11 There are 12 usable qubits. Based on the quantum gate information in the quantum chip's chip information, it can be seen that Q0 communicates with Q1 and Q3; Q1 communicates with Q0, Q2, and Q4; Q2 communicates with Q1 and Q5; Q3 communicates with Q0, Q4, and Q6; Q4 communicates with Q1, Q3, Q5, and Q7; Q5 communicates with Q2, Q4, and Q8; Q6 communicates with Q3, Q7, and Q9; and Q7 communicates with Q4, Q6, Q8, and Q9. 10 There is a communication relationship between Q8 and Q5, Q7, and Q6. 11 There is a communication relationship between Q9 and Q6, Q 10 There is a communication relationship, Q 10 Compared with Q7, Q9, Q 11 There is a communication relationship, Q 11 With Q8, Q 10 There is a communication relationship. Based on this, the target drawing function can be determined as a function capable of drawing the first topological structure diagram of the rectangular tiled structure, as needed.

[0106] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips is provided. This method can, even when the topological structure of a quantum chip already manufactured by another party is unknown, utilize the chip information of the quantum chip and a determined drawing function to graphically describe a first topological structure diagram of the quantum chip. Furthermore, based on a pre-characterized diagram determined by the first topological structure diagram and distance weights, the distance characteristics of the quantum chip can be quantitatively described, providing an operable method for efficiently drawing quantum chip topological structure diagrams. The technology of this disclosure is highly operable and can efficiently and easily draw topological structure diagrams of quantum chips with different structures, as well as the topological structure diagrams of their sub-chips.

[0107] In one implementation, the target drawing function is determined based on quantity information and quantum gate information, including:

[0108] Based on the quantity information and quantum gate information, multiple initial drawing functions are determined.

[0109] Based on preset characterization rules and multiple initial drawing functions, the target drawing function is determined.

[0110] According to the embodiments of this disclosure, it should be noted that:

[0111] With the quantity and gate information remaining constant, the drawing function can differ depending on the requirements. That is, even when the number of qubits and the communication relationships between them are fixed, multiple different initial drawing functions can be obtained by adjusting the layout positions (coordinates) of the nodes corresponding to each qubit. Each initial drawing function will produce a different first topological structure diagram.

[0112] Based on preset characterization rules, a target drawing function that meets the requirements can be selected from multiple initial drawing functions. These preset characterization rules can be selected and adjusted according to the computational task or design needs. For example, preset characterization rules may include: requiring the generated first topology graph to include intersecting edges; requiring the generated first topology graph to include intersecting edges; requiring the generated first topology to be a rectangular tiling structure; requiring the generated first topology to be a circular tiling structure; requiring the generated first topology to be arranged along the X-axis; requiring the generated first topology to be arranged along the Y-axis, etc.

[0113] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips and their sub-chips is provided. Based on a first topological structure diagram of the quantum chip, a distance weight is introduced to quantitatively describe the distance characteristics of the quantum chip and its sub-chips. Simultaneously, a drawing function is proposed, providing an operable method for efficiently drawing the topological structure diagram of the quantum chip and its sub-chips, and representing the relationship between the sub-chip's topological structure diagram and its parent chip. By combining the concepts of topological structure diagram and distance weight, and introducing a drawing function for the quantum chip, a novel characterization method for quantum chips is presented, and this method can be further extended to quantum sub-chips.

[0114] In one implementation, generating a first topological structure diagram of the target structure shape of the quantum chip according to a target drawing function includes:

[0115] Based on the point drawing function in the target drawing function, multiple first nodes representing each qubit are generated in the coordinate system, where each of the multiple first nodes contains corresponding coordinate information.

[0116] Based on the edge drawing function in the target drawing function, an edge is generated between the two first nodes corresponding to every two adjacent qubits, where the two first nodes belong to multiple first nodes.

[0117] Based on the positional relationships between multiple first nodes and edges, the correspondence information between multiple first nodes and multiple qubits of the quantum chip is determined.

[0118] Based on multiple first nodes, edges, and corresponding relationship information, a first topological structure diagram of the target structure shape of the quantum chip is generated.

[0119] According to the embodiments of this disclosure, it should be noted that:

[0120] The point drawing function is used to draw each first node in the first topology graph. Each first node drawn contains coordinate information.

[0121] The edge drawing function is used to draw the edges between qubits that have a communication relationship.

[0122] Determining the correspondence between multiple first nodes and multiple qubits of a quantum chip can be understood as mapping each first node to a specific qubit on the quantum chip. For example, as... Figure 3 As shown, the quantum chip includes Q0 to Q10. 11 There are a total of 12 fully functional qubits, corresponding to 12 first nodes drawn in the first topology diagram. Here, Q2: (0,2) represents the qubit Q2 associated with the quantum chip at this first node, and the coordinates of this first node are (0,2). Figure 2 The same applies to the other first nodes in the array, and will not be elaborated further here.

[0123] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips and their sub-chips is provided. Based on a first topological structure diagram of the quantum chip, a distance weight is introduced to quantitatively describe the distance characteristics of the quantum chip and its sub-chips. Simultaneously, a drawing function is proposed, providing an operable method for efficiently drawing the topological structure diagram of the quantum chip and its sub-chips, and representing the relationship between the sub-chip's topological structure diagram and its parent chip. By combining the concepts of topological structure diagram and distance weight, and introducing a drawing function for the quantum chip, a novel characterization method for quantum chips is presented, and this method can be further extended to quantum sub-chips.

[0124] In one implementation, the first topological graph consists of a set of points containing multiple first nodes and a set of edges containing multiple edges. The multiple first nodes correspond to multiple qubits of the quantum chip. The multiple edges correspond to the communication relationships between directly adjacent qubits. Specifically, for a quantum chip C with N qubits, the qubits on it are defined as forming a set of points Q. Using the qubits as the first nodes in the first topological graph, i.e., using Q as the set of points in the first topological graph, an undirected edge is connected between two qubits that can operate a two-bit quantum gate, i.e., an edge is defined as... With Q j Using the set of undirected edges of a two-qubit gate as the topological graph, an undirected graph G = (Q, E) is constructed, which serves as the first topological graph of the quantum chip C. Specifically, when {Q... i Q j When}∈E, then the quantum bit Q can be... i Q j When a two-qubit quantum gate is applied, the quantum bit Q is called a quantum bit. i Q j They are adjacent on the quantum chip C.

[0125] Define the distance between adjacent qubits, and then define the distance between any two qubits based on this. Let Q be the distance between adjacent qubits. i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Q j It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:

[0126] d(Q i Q j )=1-F(Q i Qj ) or d(Q i , Q j ) = -log a F(Q i , Q j )

[0127] where F(Q i , Q j ) ∈ [0, 1], a is a fixed constant greater than 0 and not equal to 1. We can take a = e as the natural constant. The selection of a here will not make a practical difference to the scheme.

[0128] Furthermore, if each element in the quantum bit sequence is adjacent to the previous element on the quantum chip C (t, j are non - negative integers, j < t), and all elements are pairwise different, then the quantum bit sequence p is called a path connecting the quantum bits . The distance d(p) of the path p is defined as the sum of the distances between each pair of consecutive quantum bits in the quantum bit sequence p Thus, the distance between quantum bits can be extended to the non - adjacent case, that is, the distance between two non - directly adjacent quantum bits Q i , Q j is defined as the minimum value of the distances of the paths connecting these two quantum bits. In particular, when the path does not exist, the distance is defined as positive infinity.

[0129] d Q (Q i , Q j ) = min{d(p)| the path p ∈ Q t connects Q i and Q j , t is a non - negative integer}.

[0130] When drawing the topological structure diagram of the quantum chip C on a plane, the quantum bit Q i can be drawn at the position g(Q i ) ∈ R 2 . If g: Q → R 2 is an injection, then it is called a drawing function of the quantum chip C, and its range is denoted as g(Q) = {g(Q i )|Q i ∈ Q}, where R is the set of real numbers. Based on g and g(Q), the inverse function g -1 : g(Q) → Q of g can be calculated. Here g -1 is a bijection, and further, the quantum bit Q i and its drawing function image g(Q i ) can be equated.

[0131] Furthermore, we can define the target drawing function g(G) = (g(Q), g(E)) for the first topological graph G = (Q, E), which is an undirected graph. The vertex set and edge set are represented by the vertex drawing function g(Q) and the edge drawing function g(E), respectively, where g(E) = {{g(Q)} i ),g(Q j )}|{Q i Q j}∈E}. Since graph G is isomorphic to graph g(G), the first topological graph G can also be equated with the target drawing function g(G) of the topological graph. Thus, a complete characterization of the quantum chip C can be obtained:

[0132] C=(Q,E,d Q ,g).

[0133] In one implementation, determining a target sub-chip from a plurality of candidate sub-chips based on connectivity includes:

[0134] Based on the distance weights between the qubits of the quantum chip, the distance weights between the qubits corresponding to each candidate pattern are determined.

[0135] Based on the distance weights between some qubits, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns is determined.

[0136] The target sub-chip is determined from multiple candidate sub-chips based on connectivity.

[0137] According to the technology of the embodiments of this disclosure, based on connectivity calculation, the most suitable sub-chip can be found quickly and accurately from the quantum chip.

[0138] In one example, based on the number of qubits required for the sub-chip, for the quantum chip C = (Q, E, d) Q Constructing a subset of qubits on g) Sub-chips can be defined similarly.

[0139] Where Q is the set of points of the quantum chip's qubits, E is the set of edges representing the communication relationships between the qubits of the quantum chip, and d Q Let be the distance weights between the qubits of the quantum chip, and g be the plotting function of the quantum chip. s The set of points representing the qubits of the sub-chip. Let d represent the set of edges that allow communication between the qubits of a sub-chip. s The distance weights between the qubits of the sub-chip. This is the function for drawing the sub-chip.

[0140] The point set Q of the sub-chip based on the point set Q of the quantum chip s We can define the first topological graph G = (Q, E) in Q. s The above restrictions, namely the second topology diagram This refers to the set of edges in the second topological graph.

[0141] Regarding d s There are several ways to define the choice: one is to choose d s =d Q One approach is to select all qubits on the quantum chip C when calculating the path; the other is based on d and Q. s ,definition Right now

[0142]

[0143] path Connect Q i and Q j ,t is a non-negative integer},

[0144] At this point, when calculating the path, only set Q can be selected. S The qubits in the array.

[0145] Drawing function That is, the function g in the set Q s The limitations on the above. Similarly, the topology diagram of the sub-chip can be... Rather than drawing function like Equivalent to. inverse mapping That is, g -1 In g(Q) s Restrictions on )

[0146] In one example, the method for drawing the first topological structure diagram of a quantum chip includes: given a quantum chip C = (Q, E, d... Q Establish a Cartesian coordinate system on the plane (g). Traverse the quantum bits Q. i ∈Q, in the rectangular coordinate system g(Q) i Plot the qubit Q at () i Then iterate through the edges {Q} i Q j}∈E, connecting qubit Q i Q j .

[0147] In one example, the method for drawing the second topological structure diagram of the sub-chip includes: given a quantum chip C = (Q, E, d... Q Sub-chips on g) Traversing the Q qubit i ∈Q s Q i Change to highlighting (visual display). Then traverse the edges. Connecting qubit Q i Q j The edge should be highlighted.

[0148] In one example, if quantum chip C m,n The topological structure graph and a square tessellation G with a rectangular outline m,n Isomorphism is called quantum chip C m,n It is a square tessellation pattern quantum chip with m columns and n rows and a rectangular outline. Let the isomorphic mapping be g:Q m,n →V m,n It can be used as a quantum chip C m,n The drawing function, where Q m,n It is a quantum chip C m,n The set consisting of all qubits. Based on this, let g be the set of all qubits. -1 (E m,n )={{g -1 (v1),g -1 (v2)}|{v1,v2}∈E m,n}, then quantum chip C m,n Can be characterized as C m,n =(Q m,n ,g -1 (E m,n ),d,g), there are no additional restrictions on d here.

[0149] For example, when g(Q) i )=(i / / n,i mod n), there is g -1 (j,k)=Q nj+k , where / / denotes the floor division rule, which is the largest integer not exceeding the quotient of the two numbers. For example... Figure 3 As shown, on a square tessellation pattern quantum chip with a rectangular outline of m=4 columns and n=3 rows, there is a diagram showing the correspondence between each qubit and its plotted function image.

[0150] In one example, after determining the quantum chip C m,n =(Q m,n ,g -1 (E m,n Given that the number of qubits required for the sub-chip is determined, d, g), d, g), and ... the number of qubits required for the sub-chip is determined.

[0151] Define the qubits of the sub-chip and In C m,n adjacent paths

[0152] Define the set of qubits of the sub-chip

[0153] Define edge set

[0154] Define the metric function d p (i.e., distance weight) is d p =d Q or

[0155]

[0156] Where 0≤k <j≤t-1。 That is, quantum chip C m,n A ring-shaped sub-chip.

[0157] For the ring-shaped sub-chip C p The connectivity α(C) p Modeling, such as or

[0158] Given a square tessellation patterned quantum chip C with a rectangular outline m,n =(Q m,n ,g -1 (E m,n Given the target number of qubits t∈[1,mn), find the qubits that satisfy d,g). and In C m,n adjacent paths This makes the circular sub-chip C p The connectivity α(C) p (As small as possible)

[0159] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, wherein step S102: determining the initial configuration based on a first quantity and a pre-detailed pattern of the quantum chip, including:

[0160] Step S1021: Based on the first quantity and the pre-printed pattern of the quantum chip, determine the second quantity of the third node contained in the initial configuration, wherein the second quantity is a perfect square number.

[0161] Step S1022: Based on the second quantity, determine the initial configuration, wherein the initial configuration is a square tessellation configuration.

[0162] According to the embodiments of this disclosure, it should be noted that:

[0163] A perfect square can be understood as an integer multiplied by itself, such as 1*1, 2*2, 3*3, and so on. If a number can be expressed as the square of some integer, then that number is called a perfect square. For example, Figure 4 The left side shows a schematic diagram of determining the initial configuration in the pre-characterized drawing. Figure 4 The right side shows a schematic diagram of the candidate characterization patterns determined based on the initial configuration, in which... Figure 4 The initial configuration shown on the left contains a second number of 3 third nodes. 2 That is, the perfect square of 3 with 9 third nodes. For example, Figure 5 The left side shows a schematic diagram of determining the initial configuration in the pre-characterized drawing. Figure 5 The right side shows a schematic diagram of the candidate characterization patterns determined based on the initial configuration, in which... Figure 5 The initial configuration shown on the left contains a second number of 4 third nodes. 2 That is, the perfect square of 4 with 16 third nodes. For example, Figure 6 The left side shows a schematic diagram of determining the initial configuration in the pre-characterized drawing. Figure 6 The right side shows a schematic diagram of the candidate characterization patterns determined based on the initial configuration, in which... Figure 6 The initial configuration shown on the left contains a second number of 3 third nodes. 2 That is, the perfect square of 3 with 9 third nodes.

[0164] A square tessellation pattern can be understood as a tessellation pattern formed by overlapping points and edges of squares with equal side lengths.

[0165] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0166] In one embodiment, the method for determining the sub-chips of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1021 and S1022, wherein step S1021: determining a second number of third nodes included in the initial configuration based on a first number and a pre-detailed pattern of the quantum chip, including:

[0167] Step S10211: If the boundary of the pre-drawing map is complete and the first quantity satisfies the first threshold, determine the second quantity of the third nodes contained in the initial configuration based on the first quantity.

[0168] The second quantity is less than the first quantity.

[0169] According to the embodiments of this disclosure, it should be noted that:

[0170] The pre-drawn pattern has complete boundaries, which can be understood as meaning that there is communication between the qubits at each edge position of the first topological structure diagram of the quantum chip. For example, as... Figure 4 and Figure 5 The pre-drawing pattern of the quantum chip shown is a complete pattern with no broken lines, meaning that there is no situation where any two adjacent qubits located at the edge do not have a communication relationship.

[0171] The first threshold can be set as needed and is not specifically limited here. For example, a relationship can be established between the first number of qubits required for the sub-chip and specific parameters, and the first threshold can be calculated using this relationship.

[0172] like Figure 4 As shown, under the condition that the boundary of the pre-characterized map is complete and the first quantity meets the first threshold, the following is determined: Figure 4 The second number of third nodes in the first configuration diagram corresponding to the initial configuration on the left is 9. Further performing steps S103a to S103d based on this will yield the following result. Figure 4 The candidate characterization shown on the right.

[0173] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0174] In one embodiment, the method for determining the sub-chips of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1021 and S1022, wherein step S1021: determining a second number of third nodes included in the initial configuration based on a first number and a pre-detailed pattern of the quantum chip, including:

[0175] Step S10212: If the boundary of the pre-drawing map is complete and the first quantity satisfies the second threshold, determine the second quantity of the third nodes contained in the initial configuration based on the first quantity.

[0176] The second quantity is greater than the first quantity.

[0177] According to the embodiments of this disclosure, it should be noted that:

[0178] The pre-drawn pattern has complete boundaries, which can be understood as meaning that there is communication between the qubits at each edge position of the first topological structure diagram of the quantum chip. For example, as... Figure 4 and Figure 5 The pre-drawing pattern of the quantum chip shown is a complete pattern with no broken lines, meaning that there is no situation where any two adjacent qubits located at the edge do not have a communication relationship.

[0179] The second threshold can be set as needed and is not specifically limited here. For example, a relationship can be established between the first number of qubits required for the sub-chip and specific parameters, and the second threshold can be calculated using this relationship.

[0180] like Figure 5 As shown, under the condition that the boundary of the pre-delineated map is complete and the first quantity satisfies the second threshold, the determination is made. Figure 5 The second number of third nodes in the first configuration diagram corresponding to the initial configuration on the left is 16. Further performing steps S103e to S103h based on this will yield the following result. Figure 5 The candidate characterization shown on the right.

[0181] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0182] In one embodiment, the method for determining the sub-chips of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1021 and S1022, wherein step S1021: determining a second number of third nodes included in the initial configuration based on a first number and a pre-detailed pattern of the quantum chip, including:

[0183] Step S10213: In the case that the boundary of the pre-drawing is incomplete, determine the second number of third nodes contained in the initial configuration based on the first number.

[0184] The second quantity is less than the first quantity.

[0185] According to the embodiments of this disclosure, it should be noted that:

[0186] The incomplete boundaries of the pre-delineated pattern, i.e., boundary degradation, can be understood as the fact that not all qubits at the edge positions of the first topological structure of the quantum chip have communication relationships. For example, as... Figure 6The pre-drawing pattern of the quantum chip shown has broken lines on both the right and bottom edges, meaning that there are cases where two adjacent qubits located on the right and bottom edges do not have a communication relationship.

[0187] like Figure 6 As shown, when the boundary of the pre-drawing map is incomplete, based on the first quantity, the second quantity of the third nodes contained in the first configuration map corresponding to the initial configuration is determined to be 9. Further performing steps S1031 to S1034 on this basis yields the following result. Figure 6 The candidate characterization shown on the right.

[0188] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0189] In one embodiment, the method for determining a sub-chip of a quantum chip according to this disclosure includes steps S101 to S105, and step S10211, wherein step S103: determining a plurality of candidate patterns from a pre-pattern based on an initial configuration, including:

[0190] Step S103a: In the pre-drawing diagram, determine a plurality of first configuration diagrams corresponding to the initial configuration.

[0191] Step S103b: Determine the outer boundaries of multiple first configuration diagrams.

[0192] Step S103c: Determine the fourth node on the outer boundary based on the first and second quantities.

[0193] Step S103d: Add a fourth node to multiple first configuration diagrams to generate multiple candidate characterization diagrams.

[0194] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0195] According to the embodiments of this disclosure, it should be noted that:

[0196] The first configuration diagram is a shape consistent with the initial configuration shape. For example... Figure 4 The first topological structure diagram of the quantum chip on the left shows a configuration with 9 nodes, which is the first configuration diagram corresponding to the initial configuration.

[0197] Based on the initial configuration, multiple first configuration graphs can be traversed in the first topological structure graph of the pre-determined graph. The number of multiple first configuration graphs can be adjusted as needed. For example, all first configuration graphs corresponding to the initial configuration in the pre-determined graph can be traversed exhaustively, which allows for more accurate determination of the target sub-chip with optimal connectivity based on all traversed first configuration graphs. Alternatively, traversal can be stopped after traversing a threshold number of first configuration graphs, which can improve traversal efficiency and further enhance the efficiency of determining the target sub-chip.

[0198] Determining the outer boundaries of multiple first configuration diagrams can be understood as determining the outer boundary of each first configuration diagram. The outer boundary of each first configuration diagram can be the boundary formed by expanding one or more qubits outward from any one or more sides of each first configuration diagram.

[0199] When the first configuration diagram is determined to include multiple outward boundaries, a fourth node can be determined on one or more outward boundaries of the first configuration diagram. The fourth node corresponds to a first node in the first topological structure diagram of the quantum chip; that is, the multiple first nodes include the fourth node.

[0200] Adding a fourth node to multiple first configuration diagrams can be understood as connecting the fourth node determined in each first configuration diagram to the existing nodes of that first configuration diagram, and connecting multiple fourth nodes to each other, thereby forming a candidate characterization diagram corresponding to that first configuration diagram. This candidate characterization diagram is used to represent a candidate sub-chip. It should be noted that the "connection" mentioned here refers to the association of the communication relationship between the fourth node and the existing nodes of the first configuration. The reason why the fourth node and the existing nodes of the first configuration can be associated is that the two already have a direct communication relationship in the quantum chip. Associating the communication relationship here is so that the corresponding sub-chip can use the communication relationship between the two to perform calculations.

[0201] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0202] In one example, based on the initial configuration, multiple candidate characterization maps are determined from the pre-characterization maps, including:

[0203] Given a parameter t, the algorithm will attempt to determine the shape of a sub-chip. This sub-chip shape may be square or nearly square, but in some cases a small number of nodes may be removed or added.

[0204] Step 1, calculate \(a\), which is the largest integer not exceeding \(\sqrt{t}\). This means that \(a\) is a number as large as possible such that its square is still less than \(t\).

[0205] Step 2, if \(t\lt a(a + 1)\), go to Step 2.1;

[0206] Step 2.1, some elements need to be selected from four specific sets. These sets are located on the four sides of the square. Select \(\delta=t - a\) 2 elements from each set and add them to the shape. This means adding nodes to the original square.

[0207] Step 3, return the list of shapes SHAPE as the final result.

[0208] Specifically, it can be transformed into the following process:

[0209] Input: the number of target qubits \(t\).

[0210] Output: a list of shapes SHAPE (multiple candidate characterization graphs) of the sub-chip with the number of qubits (the first number) \(t\) on the square tiling quantum chip.

[0211] Step 1, denote That is, the largest integer not exceeding ;

[0212] Step 2, if \(t\lt a(a + 1)\), go to Step 2.1;

[0213] Step 2.1, respectively select \(\delta=t - a\) 2 elements (nodes) from \(\{(z,a)|z = 0,1,\cdots,a - 1\}\), \(\{(a,z)|z = 0,1,\cdots,a - 1\}\), \(\{(-1,z)|z = 0,1,\cdots,a - 1\}\) and \(\{(z,-1)|z = 0,1,\cdots,a - 1\}\), and add them to the re-initialized shape sheape = \([(x,y)|x,y = 0,1,\cdots,a - 1]\) to obtain 4 updated shapes, and denote the shape list formed by them as SHAPE; when selecting here, the middle \(\delta\) consecutive ones can be selected, that is, \(z = z_0,z_0 + 1,\cdots,z_0+\delta - 1\), where the non-negative integer \(z_0\) satisfies \(|2z_0+\delta - a|\leq1\); go to Step 3;

[0214] Step 3, return SHAPE as the output result.

[0215] Among them, \(\{(z,a)\mid z = 0,1,\cdots,a - 1\}\): This is a set of points, where the \(y\)-coordinate is always \(a\), and the \(x\)-coordinate \(z\) ranges from \(0\) to \(a - 1\). This represents the upper boundary of the square. \(\{(a,z)\mid z = 0,1,\cdots,a - 1\}\): This is a set of points, where the \(x\)-coordinate is always \(a\), and the \(y\)-coordinate \(z\) ranges from \(0\) to \(a - 1\). This represents the right boundary of the square. \(\{(-1,z)\mid z = 0,1,\cdots,a - 1\}\): This is a set of points, where the \(x\)-coordinate is always \(-1\), and the \(y\)-coordinate \(z\) ranges from \(0\) to \(a - 1\). This represents the left boundary of the square. Here, \(-1\) indicates that the left boundary is outside the original square. \(\{(z, - 1)\mid z = 0,1,\cdots,a - 1\}\): This is a set of points, where the \(y\)-coordinate is always \(-1\), and the \(x\)-coordinate \(z\) ranges from \(0\) to \(a - 1\). This represents the lower boundary of the square. Similarly, \(-1\) indicates that the lower boundary is outside the original square.

[0216] In one embodiment, the method for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure includes steps S101 to S105, and step S10212. Among them, step S103: According to the initial configuration, determine a plurality of candidate carving graphs from the pre-carved graph, including:

[0217] Step S103e: In the pre-carved graph, determine a plurality of first configuration graphs corresponding to the initial configuration.

[0218] Step S103f: Determine the self-target boundaries of the plurality of first configuration graphs.

[0219] Step S103g: According to the first quantity and the second quantity, determine the fourth nodes on the self-target boundaries.

[0220] Step S103h: Delete the fourth nodes on the plurality of first configuration graphs to generate a plurality of candidate carving graphs.

[0221] Among them, the number of nodes included in each candidate carving graph is consistent with the first quantity.

[0222] According to an embodiment of the present disclosure, it should be noted that:

[0223] The first configuration graph is a shape consistent with the initial configuration. As Figure 4 Shown in the first topological structure diagram of the quantum chip on the left, the configuration including 9 nodes is the first configuration graph corresponding to the initial configuration.

[0224] Based on the initial configuration, multiple first configuration graphs can be traversed in the first topological structure graph of the pre-determined graph. The number of multiple first configuration graphs can be adjusted as needed. For example, all first configuration graphs corresponding to the initial configuration in the pre-determined graph can be traversed exhaustively, which allows for more accurate determination of the target sub-chip with optimal connectivity based on all traversed first configuration graphs. Alternatively, traversal can be stopped after traversing a threshold number of first configuration graphs, which can improve traversal efficiency and further enhance the efficiency of determining the target sub-chip.

[0225] Determining the self-target boundaries of multiple first configuration diagrams can be understood as determining the self-target boundary of each first configuration diagram. The self-target boundary of each first configuration diagram can be the boundary formed by any one or more sides of each first configuration diagram.

[0226] When it is determined that the first configuration diagram includes multiple self-target boundaries, a fourth node can be determined on one or more self-target boundaries of the first configuration diagram. The fourth node corresponds to a first node in the first topological structure diagram of the quantum chip; that is, the multiple first nodes include the fourth node.

[0227] Deleting the fourth node from multiple first configuration diagrams can be understood as deleting the fourth node determined by each first configuration diagram and canceling its connection with other nodes in that first configuration diagram, thereby forming a candidate characterization diagram corresponding to that first configuration diagram. This candidate characterization diagram is used to represent a candidate sub-chip. It should be noted that the "connection" mentioned here refers to the cancellation of the communication relationship between the fourth node and the original nodes of the first configuration. The reason why the fourth node and the original nodes of the first configuration could be associated is that they already had a direct communication relationship in the quantum chip. The purpose of canceling the communication relationship here is to prevent the corresponding sub-chip from using the communication relationship between the two when performing computational tasks.

[0228] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0229] In one example, based on the initial configuration, multiple candidate characterization maps are determined from the pre-characterization maps, including:

[0230] Given a parameter t, the algorithm will attempt to determine the shape of a sub-chip. This sub-chip shape may be square or nearly square, but in some cases a small number of nodes may be removed or added.

[0231] Step 1, calculate 'a', which is no more than 1 / 3. The largest integer t. This means that a is the largest possible number whose square is still less than t.

[0232] Step 2: If t ≥ a(a+1), proceed to step 2.2:

[0233] Step 2.2 requires selecting some elements from four specific sets and removing them from the shape. This means removing nodes from the original square.

[0234] Step 3: Return the list of shapes (SHAPE) as the final result.

[0235] Specifically, it can be transformed into the following process:

[0236] Input: The number of target qubits, t.

[0237] Output: A list of shapes (multiple candidate patterns) of sub-chips with a number of qubits (first count) of t on a square tessellation quantum chip.

[0238] Step 1, record That is, not exceeding The largest integer;

[0239] Step 2: If t >> a(a+1), proceed to step 2.2;

[0240] Step 2.2: Select σ = (a+1) from the following groups: {(z,a)|z=0,1,…,a}, {(a,z)|z=0,1,…,a}, {(0,z)|z=0,1,…,a}, and {(z,0)|z=0,1,…,a}. 2 -t elements (nodes) are removed from the reinitialized shape sheape = [(x,y)|x,y = 0,1,…,a] to obtain 4 updated shapes, which are denoted as the shape list SHAPE. When selecting, the two outermost σ elements can be chosen, i.e., z = 0,1,…,z1-1,a+z1-σ+1,a+z1-σ+2,…,a, where the non-negative integer z1 satisfies |2z1-σ|≤1; proceed to step 3;

[0241] Step 3: Return SHAPE as the output.

[0242] In one embodiment, the method for determining a sub-chip of a quantum chip according to this disclosure includes steps S101 to S105, and step S10213, wherein step S103: determining a plurality of candidate patterns from a pre-pattern based on an initial configuration, including:

[0243] Step S1031: In the pre-drawing diagram, determine a plurality of first configuration diagrams corresponding to the initial configuration.

[0244] Step S1032: Determine the outer boundaries of multiple first configuration diagrams in the pre-characterized diagram based on the number of rows and columns of the pre-characterized diagram.

[0245] Step S1033: Determine the fourth node on the outer boundary based on the first and second quantities.

[0246] Step S1034: Add a fourth node to multiple first configuration diagrams to generate multiple candidate characterization diagrams.

[0247] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0248] According to the embodiments of this disclosure, it should be noted that:

[0249] The first configuration diagram is a shape consistent with the initial configuration shape. For example... Figure 4 The first topological structure diagram of the quantum chip on the left shows a configuration with 9 nodes, which is the first configuration diagram corresponding to the initial configuration.

[0250] Based on the initial configuration, multiple first configuration graphs can be traversed in the first topological structure graph of the pre-determined graph. The number of multiple first configuration graphs can be adjusted as needed. For example, all first configuration graphs corresponding to the initial configuration in the pre-determined graph can be traversed exhaustively, which allows for more accurate determination of the target sub-chip with optimal connectivity based on all traversed first configuration graphs. Alternatively, traversal can be stopped after traversing a threshold number of first configuration graphs, which can improve traversal efficiency and further enhance the efficiency of determining the target sub-chip.

[0251] Determining the outer boundaries of multiple first configuration diagrams can be understood as determining the outer boundary of each first configuration diagram. The outer boundary of each first configuration diagram can be the boundary formed by expanding one or more qubits outward from any one or more sides of each first configuration diagram.

[0252] The outer boundary is determined based on the number of rows and columns of the pre-drawn image. This can be understood as follows: when the number of rows is greater than the number of columns, such as... Figure 6 As shown, the outer boundary is determined on the left and / or right side of the first configuration diagram. Alternatively, when the number of rows is less than the number of columns, the outer boundary is determined on the top and / or bottom side of the first configuration diagram. The left and right sides can be understood as the sides where the columns of the pre-characterized diagram are located, and the top and bottom sides can be understood as the sides where the edges of the pre-characterized diagram are located.

[0253] When the first configuration diagram is determined to include multiple outward boundaries, a fourth node can be determined on one or more outward boundaries of the first configuration diagram. The fourth node corresponds to a first node in the first topological structure diagram of the quantum chip; that is, the multiple first nodes include the fourth node.

[0254] Adding a fourth node to multiple first configuration diagrams can be understood as connecting the fourth node determined in each first configuration diagram to the existing nodes of that first configuration diagram, and connecting multiple fourth nodes to each other, thereby forming a candidate characterization diagram corresponding to that first configuration diagram. This candidate characterization diagram is used to represent a candidate sub-chip. It should be noted that the "connection" mentioned here refers to the association of the communication relationship between the fourth node and the existing nodes of the first configuration. The reason why the fourth node and the existing nodes of the first configuration can be associated is that the two already have a direct communication relationship in the quantum chip. Associating the communication relationship here is so that the corresponding sub-chip can use the communication relationship between the two to perform calculations.

[0255] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0256] In one example, based on the initial configuration, multiple candidate characterization maps are determined from the pre-characterization maps, including:

[0257] Input: A quantum chip with m columns and n rows, and the target number of qubits t.

[0258] Output: A list of shapes SHAPE for sub-chips with a total of t qubits on the quantum chip.

[0259] Step 1: This step determines whether the sub-chip shape is formed based on the chip's width (m) or height (n).

[0260] Step 1.1: If m is less than or equal to n, meaning the width of the chip is no greater than its height, then we will form a sub-chip shape with a width of m. Its basic shape consists of m columns and t / / m rows. To achieve the target number t, we may need to add some extra qubits to the left or right boundaries of the chip. The choice here is to ensure that the extra qubits are distributed on both sides of the sub-chip, thus maintaining the symmetry of the shape.

[0261] Step 1.2: If m is greater than n, meaning the width of the chip is greater than its height, then we will form a sub-chip shape with a height of n. Similarly, to achieve the target number t, we may need to add some additional qubits at the top or bottom boundary of the chip.

[0262] Step 2: Return the list of shapes (SHAPE) as the output.

[0263] The primary goal of this method is to form a sub-chip with an approximately square shape, but in this case, it is based on a quantum chip with a rectangular outline. To form an approximately square sub-chip on such a chip, some qubits need to be added or removed at the boundaries.

[0264] Specifically, it can be transformed into the following process:

[0265] Input: The number of columns m and rows n of a square tessellation quantum chip with a rectangular outline, and the number of target qubits (first count) t∈(min(m,n)). 2 ,mn].

[0266] Output: A list of shapes (SHAPE) of sub-chips with t qubits on a square tessellation quantum chip.

[0267] Step 1: If m≤n, proceed to step 1.1; otherwise, proceed to step 1.2.

[0268] Step 1.1: Select δ = t mod m elements (nodes) from {(m,z)|z=0,1,…,t / / m-1} and {(-1,z)|z=0,1,…,t / / m-1} respectively, and add them to the shape shape=[(x,y)|x=0,1,…,m-1,y=0,1,…,t / / m-1] to obtain two updated shapes, which constitute the shape list SHAPE; when selecting, you can choose the middle consecutive δ elements, i.e., z=z0,z0+1,…,z0+δ-1, where the non-negative integer z0 satisfies |2z0+δ-t / / m|≤1; proceed to step 2;

[0269] Step 1.2: Select δ = t mod n elements (nodes) from {(z,n)|z=0,1,…,t / / n-1} and {(z,-1)|z=0,1,…,t / / n-1} respectively, and add them to the shape shape=[(x,y)|x=0,1,…,t / / n-1,y=0,1,…,n-1] to obtain two updated shapes, which constitute the shape list SHAPE; when selecting, you can choose the middle consecutive δ elements, that is, z=z0,z0+1,…,z0+δ-1, where the non-negative integer z0 satisfies |2z0+δ-t / / n|≤1; proceed to step 2;

[0270] Step 2: Return SHAPE as the output.

[0271] In one implementation, such as Figure 6 As shown, the method for determining the sub-chip of the quantum chip in this embodiment includes steps S101 to S105, and steps S1031 to S1034, wherein step S1032: determining the outer boundary of a plurality of first configuration patterns in the pre-pattern based on the number of rows and columns of the pre-pattern, including:

[0272] When the number of rows in the pre-characterized pattern is greater than the number of columns, an outer expansion boundary is determined outside the target column of the plurality of first configuration patterns based on the pre-characterized pattern;

[0273] The target column is the outermost column located on both sides of the plurality of first configuration diagrams.

[0274] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0275] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1031 to S1034, wherein step S1032: determining the outer boundary of a plurality of first configuration patterns in the pre-pattern based on the number of rows and columns of the pre-pattern, including:

[0276] When the number of rows in the pre-characterized pattern is less than the number of columns, an outer expansion boundary is determined outside the target rows of the plurality of first configuration patterns based on the pre-characterized pattern;

[0277] The target behavior is located in the outermost rows on both sides of the plurality of first configuration diagrams.

[0278] According to the technology of the present disclosure, on a square tessellation, even if a first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0279] In one embodiment, the method for determining sub-chips of a quantum chip according to this disclosure includes steps S101 to S105, wherein step S104: determining the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns, including:

[0280] Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps is calculated based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps.

[0281] According to the embodiments of this disclosure, it should be noted that:

[0282] The connectivity algorithm can be any existing algorithm for calculating connectivity, and no specific limitation is made here.

[0283] The characterization path of a candidate characterization map can be understood as the connection line that links all the second nodes of the candidate characterization map.

[0284] Each candidate pattern represents a candidate sub-chip. The qubits corresponding to the second node in the candidate pattern and the communication relationships between these qubits can characterize the corresponding candidate sub-chip.

[0285] According to the steps of the embodiments of this disclosure, the connectivity of the candidate sub-chip corresponding to each candidate pattern can be calculated.

[0286] According to the technology of this disclosure, the connectivity calculation efficiency of the candidate sub-chip can be improved by using only the qubits corresponding to multiple second nodes on the characterization path of the candidate characterization map to calculate the connectivity of the corresponding candidate sub-chip.

[0287] In one implementation, a connectivity algorithm is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps, based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps. This includes:

[0288] Based on the qubits corresponding to the multiple second nodes on the characterization path of multiple candidate characterization maps, determine the qubits located at the two endpoints on the characterization path of multiple candidate characterization maps.

[0289] The first distance weight between qubits located at the two endpoints is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0290] Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps is calculated based on the first distance weight.

[0291] According to the embodiments of this disclosure, it should be noted that:

[0292] When the candidate characterization pattern corresponds to a loop configuration, any two second nodes in the loop configuration can be used as qubits located at the two endpoints on the characterization path of the candidate characterization pattern.

[0293] The characterization path of a candidate characterization map can be understood as the connection line that links all the second nodes of the candidate characterization map.

[0294] Each candidate pattern represents a candidate sub-chip. The qubits corresponding to the second node in the candidate pattern and the communication relationships between these qubits can characterize the corresponding candidate sub-chip.

[0295] According to the steps of the embodiments of this disclosure, the connectivity of the candidate sub-chip corresponding to each candidate pattern can be calculated.

[0296] According to the technology of this disclosure, by using the qubits corresponding to multiple first nodes (including the qubits corresponding to second nodes) on the pre-drawn pattern of the quantum chip to calculate the connectivity of the corresponding candidate sub-chip, the accuracy of the connectivity calculation of the candidate sub-chip can be improved, making the calculated connectivity of each candidate sub-chip more valuable for reference.

[0297] In one implementation, determining a first distance weight between qubits located at two endpoints based on distance weights between multiple qubits in a pre-defined pattern includes:

[0298] The second distance weight between each pair of adjacent qubits in the quantum chip is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0299] The first distance weight between the qubits located at the two endpoints is determined based on the second distance weight.

[0300] According to the embodiments of this disclosure, it should be noted that:

[0301] The distance weights can be obtained based on the information contained in the pre-detailed pattern. Specifically, the pre-detailed pattern contains information about the distance weights between any two qubits of the quantum chip.

[0302] According to the technology of this disclosure, by utilizing the numerical information of the distance weights of each qubit contained in the pre-pattern, the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns can be calculated quickly and accurately.

[0303] In one implementation, determining a first distance weight between qubits located at two endpoints based on distance weights between multiple qubits in a pre-defined pattern includes:

[0304] Based on the distance weights between multiple qubits in the pre-characterized pattern, a third distance weight is determined between every two adjacent qubits on the characterization path of multiple candidate characterization patterns.

[0305] The first distance weight between qubits located at the two endpoints is determined based on the third distance weight.

[0306] According to the embodiments of this disclosure, it should be noted that:

[0307] The characterization path of a candidate characterization map can be understood as the connection line that links all the second nodes of the candidate characterization map.

[0308] Each candidate pattern represents a candidate sub-chip. The qubits corresponding to the second node in the candidate pattern and the communication relationships between these qubits can characterize the corresponding candidate sub-chip.

[0309] The distance weights can be obtained based on the information contained in the pre-detailed pattern. Specifically, the pre-detailed pattern contains information about the distance weights between any two qubits of the quantum chip.

[0310] According to the technology of this disclosure, by utilizing the numerical information of the distance weights of each qubit contained in the pre-pattern, the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns can be calculated quickly and accurately.

[0311] In one implementation, a connectivity algorithm is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps, based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps. This includes:

[0312] Based on the distance weights between multiple qubits in the pre-characterized pattern, a third distance weight is determined between every two adjacent qubits on the characterization path of multiple candidate characterization patterns.

[0313] The average distance weight is determined based on the third distance weight.

[0314] Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps is calculated based on the average distance weight.

[0315] According to the technology of this disclosure, by utilizing the numerical information of the distance weights of each qubit contained in the pre-pattern, the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns can be calculated quickly and accurately.

[0316] In one implementation, determining a third distance weight between every two adjacent qubits on the characterization path of multiple candidate characterization maps, based on distance weights between multiple qubits in a pre-characterized map, includes:

[0317] The second distance weight between each pair of adjacent qubits in the quantum chip is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0318] Based on the second distance weight, a third distance weight is determined between every two adjacent qubits on the characterization path of multiple candidate characterization maps.

[0319] According to the technology of this disclosure, by utilizing the numerical information of the distance weights of each qubit contained in the pre-pattern, the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns can be calculated quickly and accurately.

[0320] In one example, the target sub-chip is determined from multiple candidate sub-chips based on connectivity, including:

[0321] Input: Quantum chip C m,n =(Q m,n ,g -1 (E m,n ),d,g), the number of target qubits is even t∈[4,mn), and the connectivity function is α.

[0322] Output: Optimal circular sub-chip

[0323] Step 1, Initialize the minimum connectivity α min =+∞;

[0324] Step 2, if t≤min(m,n) 2 If the target number of qubits is reached, then step S10211 or step S10212 is executed to obtain a list of sub-chip shapes; otherwise, step S10213 is executed to obtain a list of sub-chip shapes based on the number of columns and rows of the quantum chip and the target number of qubits.

[0325] Step 3, iterate through shapes ∈ SHAPE, and execute the following steps in sequence:

[0326] Step 3.1: Calculate or read from storage to obtain the minimum value x of the 0th element of all elements (nodes) of shape. min Maximum value x max The minimum value of the first element ymin Maximum value y max ;

[0327] Step 3.2, iterate through x = -x min ,-x min +1,…,m-1-x max Execute in sequence:

[0328] Step 3.2.1, iterate through y = -y min ,-y min +1,…,n-1-y max Execute in sequence:

[0329] Step 3.2.1.1. Let set Q be an example. p ={g -1 (shape[j]+(x,y))|j=0,1,…,t-1}, where shape[j] represents the j-th element of shape, and the numbering starts from 0;

[0330] Step 3.2.1.2, based on set Q p Calculate α(C) p If its value is less than α min Assign the value to α min and order Proceed to step 3.2.1.3; otherwise, proceed directly to step 3.2.1.3.

[0331] Step 3.2.1.3: After completing the traversal of Steps 3.2.1 and 3.2, proceed to Step 4;

[0332] Step 4, Return As an approximately optimal sub-chip.

[0333] It should be noted that in any embodiment of this disclosure, the parentheses () in the function represent an immutable tuple, [] represent a mutable list, and {} represent a set; the elements in the tuple and list are ordered and numbered starting from 0, while the elements in the set are unordered and non-repeating.

[0334] like Figure 7 As shown, this disclosure provides an apparatus for determining a sub-chip of a quantum chip, comprising:

[0335] The first determining module 701 is used to determine the first number of qubits to be used based on the computation task.

[0336] The second determining module 702 is used to determine the initial configuration based on the first quantity and the pre-detailed pattern of the quantum chip. The pre-detailed pattern is a square tessellation configuration with a rectangular outline, and includes multiple first nodes corresponding one-to-one with the multiple qubits of the quantum chip.

[0337] The third determining module 703 is used to determine multiple candidate characterization patterns from the pre-characterization pattern based on the initial configuration. Each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip.

[0338] The fourth determining module 704 is used to determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns.

[0339] The fifth determining module 705 is used to determine the target sub-chip from multiple candidate sub-chips based on connectivity.

[0340] In one implementation, the second determining module 702 includes:

[0341] The first determining submodule is used to determine the second number of third nodes included in the initial configuration based on the first number and the pre-detailed pattern of the quantum chip, wherein the second number is a perfect square number.

[0342] The second determining submodule is used to determine the initial configuration based on the second quantity, wherein the initial configuration is a square tessellation configuration.

[0343] In one implementation, the first determining submodule is used to:

[0344] If the boundaries of the pre-drawing map are complete and the first quantity satisfies the first threshold, the second quantity of the third nodes contained in the initial configuration is determined based on the first quantity.

[0345] The second quantity is less than the first quantity.

[0346] In one implementation, the first determining submodule is used to:

[0347] If the boundaries of the pre-drawing map are complete and the first quantity satisfies the second threshold, the second quantity of the third nodes contained in the initial configuration is determined based on the first quantity.

[0348] The second quantity is greater than the first quantity.

[0349] In one implementation, the first determining submodule is used to:

[0350] In the case where the boundaries of the pre-drawing are incomplete, the second number of third nodes contained in the initial configuration is determined based on the first number.

[0351] The second quantity is less than the first quantity.

[0352] In one implementation, the third determining module 703 is used to:

[0353] In the pre-delineation diagram, multiple first configuration diagrams corresponding to the initial configuration are determined.

[0354] Determine the outer boundaries of multiple first configuration diagrams.

[0355] Based on the first and second quantities, determine the fourth node on the outer boundary.

[0356] A fourth node is added to multiple first configuration diagrams to generate multiple candidate characterization diagrams.

[0357] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0358] In one implementation, the third determining module 703 is used to:

[0359] In the pre-delineation diagram, multiple first configuration diagrams corresponding to the initial configuration are determined.

[0360] Determine the self-target boundaries of multiple first configuration diagrams.

[0361] Based on the first and second quantities, determine the fourth node on its own target boundary.

[0362] The fourth node is deleted from multiple first configuration diagrams to generate multiple candidate characterization diagrams.

[0363] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0364] In one implementation, the third determining module 703 is used to:

[0365] The third determination submodule is used to determine multiple first configuration diagrams corresponding to the initial configuration in the pre-determined diagram.

[0366] The fourth determination submodule is used to determine the outer boundaries of multiple first configuration diagrams in the pre-characterized diagram based on the number of rows and columns of the pre-characterized diagram.

[0367] The fifth determination submodule is used to determine the fourth node on the outer boundary based on the first quantity and the second quantity.

[0368] The generation submodule is used to add a fourth node to multiple first configuration diagrams to generate multiple candidate characterization diagrams.

[0369] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0370] In one implementation, the fourth determining submodule is used to:

[0371] When the number of rows in the pre-delineated map is greater than the number of columns, an outer boundary is determined outside the target column of multiple first configuration maps based on the pre-delineated map.

[0372] The target column is the outermost column located on opposite sides of multiple first configuration diagrams.

[0373] In one implementation, the fourth determining submodule is used to:

[0374] When the number of rows in the pre-delineated map is less than the number of columns, an outer boundary is determined outside the target rows of multiple first configuration maps based on the pre-delineated map.

[0375] The target behavior is located in the outermost rows on both sides of multiple first configuration diagrams.

[0376] In one implementation, the fourth determining module 704 includes:

[0377] The computational submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps by using a connectivity algorithm, based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps.

[0378] In one implementation, the fourth determining module 704 includes:

[0379] The sixth determination submodule is used to determine the qubits located at both ends of the characterization path of multiple candidate characterization maps based on the qubits corresponding to the multiple second nodes on the characterization path of multiple candidate characterization maps.

[0380] The seventh determination submodule is used to determine the first distance weight between qubits located at two endpoints based on the distance weight between multiple qubits in the pre-determined pattern.

[0381] The first calculation submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps based on the first distance weight using a connectivity algorithm.

[0382] In one implementation, the seventh determining submodule is used for:

[0383] The second distance weight between each pair of adjacent qubits in the quantum chip is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0384] The first distance weight between the qubits located at the two endpoints is determined based on the second distance weight.

[0385] In one implementation, the seventh determining submodule is used for:

[0386] Based on the distance weights between multiple qubits in the pre-characterized pattern, a third distance weight is determined between every two adjacent qubits on the characterization path of multiple candidate characterization patterns.

[0387] The first distance weight between qubits located at the two endpoints is determined based on the third distance weight.

[0388] In one implementation, the fourth determining module 704 includes:

[0389] The eighth determination submodule is used to determine the third distance weight between every two adjacent qubits on the characterization path of multiple candidate characterization maps based on the distance weight between multiple qubits in the pre-characterization map.

[0390] The ninth determination submodule is used to determine the average distance weight based on the third distance weight.

[0391] The second calculation submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps based on the average distance weight using a connectivity algorithm.

[0392] In one implementation, the eighth determining submodule is used for:

[0393] The second distance weight between each pair of adjacent qubits in the quantum chip is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0394] Based on the second distance weight, a third distance weight is determined between every two adjacent qubits on the characterization path of multiple candidate characterization maps.

[0395] In one implementation, it further includes:

[0396] The sixth determining module is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip. The quantum gate information represents the communication relationship between the qubits of the quantum chip.

[0397] The seventh determining module is used to determine the first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information. The first topological structure diagram is composed of multiple first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.

[0398] The eighth determining module is used to determine the distance weights between each qubit based on the quantum gate information.

[0399] The generation module is used to obtain a pre-detailed pattern of the quantum chip based on the distance weights and the first topological structure diagram.

[0400] In one implementation, the eighth determining module is used to:

[0401] Based on quantum gate information, each pair of directly adjacent qubits in the quantum chip is determined.

[0402] Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits.

[0403] The distance weights between each quantum bit are determined based on the fidelity.

[0404] In one implementation, the seventh determining module is used to:

[0405] The target drawing function is determined based on the quantitative information and the quantum gate information.

[0406] Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

[0407] The specific functions and examples of each module and submodule of the apparatus in this disclosure can be found in the relevant descriptions of the corresponding steps in the above method embodiments, and will not be repeated here.

[0408] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0409] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0410] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0411] like Figure 8 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0412] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0413] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the method for determining sub-chips of a quantum chip. For example, in some embodiments, the method for determining sub-chips of a quantum chip can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the method for determining sub-chips of a quantum chip described above can be performed. Alternatively, in other embodiments, computing unit 801 may be configured by any other suitable means (e.g., by means of firmware) to perform a method for determining sub-chips of the quantum chip.

[0414] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0415] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0416] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0417] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0418] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0419] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0420] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0421] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for determining a sub-chip of a quantum chip, comprising: Determine the initial number of qubits required based on the computational task; Based on the first quantity and the pre-detailed pattern of the quantum chip, a second quantity of third nodes included in the initial configuration is determined, wherein the second quantity is a perfect square number; the pre-detailed pattern is a square tessellation configuration with a rectangular outline, and the pre-detailed pattern includes multiple first nodes corresponding one-to-one with multiple qubits of the quantum chip; Based on the second quantity, the initial configuration is determined, wherein the initial configuration is a square tessellation configuration; Based on the initial configuration, multiple candidate characterization patterns are determined from the pre-characterization pattern; wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip; wherein the number of nodes contained in each candidate characterization pattern is consistent with the first number; Determine the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns; and Based on the connectivity, a target sub-chip is determined from the plurality of candidate sub-chips; Specifically, based on the first quantity and the pre-detailed pattern of the quantum chip, determining the second quantity of the third node included in the initial configuration includes: If the boundary of the pre-delineated pattern is complete and the first quantity satisfies the first threshold, the second quantity of the third node included in the initial configuration is determined based on the first quantity. The second quantity is less than the first quantity.

2. The method of claim 1, wherein, Based on the first quantity and the pre-detailed pattern of the quantum chip, determining the second quantity of the third node included in the initial configuration further includes: If the boundary of the pre-delineated pattern is complete and the first quantity satisfies the second threshold, the second quantity of the third node included in the initial configuration is determined based on the first quantity. The second quantity is greater than the first quantity.

3. The method of claim 1, wherein, Based on the first quantity and the pre-detailed pattern of the quantum chip, determining the second quantity of the third node included in the initial configuration further includes: In the case that the boundary of the pre-drawing is incomplete, a second number of third nodes included in the initial configuration is determined based on the first number; The second quantity is less than the first quantity.

4. The method according to claim 1, wherein, Based on the initial configuration, a plurality of candidate characterization maps are determined from the pre-characterization maps, including: In the pre-characterized diagram, a plurality of first configuration diagrams corresponding to the initial configuration are determined; Determine the outer boundaries of the plurality of first configuration diagrams; Based on the first quantity and the second quantity, a fourth node is determined on the outer boundary; The fourth node is added to the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams.

5. The method according to claim 2, wherein, Based on the initial configuration, a plurality of candidate characterization maps are determined from the pre-characterization maps, including: In the pre-characterized diagram, a plurality of first configuration diagrams corresponding to the initial configuration are determined; Determine the self-target boundaries of the plurality of first configuration diagrams; Based on the first quantity and the second quantity, a fourth node is determined on the target boundary itself; The fourth node is deleted from the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams.

6. The method according to claim 3, wherein, Based on the initial configuration, a plurality of candidate characterization maps are determined from the pre-characterization maps, including: In the pre-characterized diagram, a plurality of first configuration diagrams corresponding to the initial configuration are determined; Based on the number of rows and columns of the pre-characterized pattern, the outer boundary of the plurality of first configuration patterns is determined in the pre-characterized pattern; Based on the first quantity and the second quantity, a fourth node is determined on the outer boundary; The fourth node is added to the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams.

7. The method according to claim 6, wherein, Based on the number of rows and columns of the pre-characterized pattern, the outer boundary of the plurality of first configuration patterns is determined in the pre-characterized pattern, including: When the number of rows in the pre-characterized pattern is greater than the number of columns, an outer expansion boundary is determined outside the target column of the plurality of first configuration patterns based on the pre-characterized pattern; The target column is the outermost column located on both sides of the plurality of first configuration diagrams.

8. The method according to claim 6, wherein, Based on the number of rows and columns of the pre-characterized pattern, the outer boundary of the plurality of first configuration patterns is determined in the pre-characterized pattern, including: When the number of rows in the pre-characterized pattern is less than the number of columns, an outer expansion boundary is determined outside the target rows of the plurality of first configuration patterns based on the pre-characterized pattern; The target behavior is located in the outermost rows on both sides of the plurality of first configuration diagrams.

9. The method according to claim 1, wherein, Determining the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns includes: Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated based on the qubits corresponding to the multiple second nodes on the characterization paths of the multiple candidate characterization maps.

10. The method according to claim 9, wherein, Using the connectivity algorithm, based on the qubits corresponding to the multiple second nodes on the characterization paths of the multiple candidate characterization maps, the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated, including: Based on the qubits corresponding to the multiple second nodes on the characterization path of the multiple candidate characterization patterns, determine the qubits located at both ends on the characterization path of the multiple candidate characterization patterns; Based on the distance weights between multiple qubits in the pre-etched pattern, the first distance weight between the qubits located at the two endpoints is determined; Using the connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated based on the first distance weight.

11. The method according to claim 10, wherein, Determining the first distance weight between the qubits located at the two endpoints based on the distance weight between multiple qubits in the pre-defined pattern includes: Based on the distance weights between multiple qubits in the pre-etched pattern, a second distance weight is determined between every two adjacent qubits of the quantum chip; The first distance weight between the qubits located at the two ends is determined based on the second distance weight.

12. The method according to claim 10, wherein, Determining the first distance weight between the qubits located at the two endpoints based on the distance weight between multiple qubits in the pre-defined pattern includes: Based on the distance weights between multiple qubits in the pre-characterized pattern, a third distance weight is determined between every two adjacent qubits on the characterization path of the multiple candidate characterization patterns. The first distance weight between the qubits located at the two endpoints is determined based on the third distance weight.

13. The method according to claim 9, wherein, Using the connectivity algorithm, based on the qubits corresponding to the multiple second nodes on the characterization paths of the multiple candidate characterization maps, the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated, including: Based on the distance weights between multiple qubits in the pre-characterized pattern, a third distance weight is determined between every two adjacent qubits on the characterization path of the multiple candidate characterization patterns. The average distance weight is determined based on the third distance weight. Using the connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated based on the average distance weight.

14. The method according to claim 13, wherein, Based on the distance weights between multiple qubits in the pre-delineated pattern, a third distance weight is determined between every two adjacent qubits on the marking path of the multiple candidate marking patterns, including: Based on the distance weights between multiple qubits in the pre-etched pattern, a second distance weight is determined between every two adjacent qubits of the quantum chip; Based on the second distance weight, a third distance weight is determined between each pair of adjacent qubits on the characterization path of the plurality of candidate characterization maps.

15. The method according to any one of claims 1 to 14, further comprising: Based on the chip information of the quantum chip, the number of qubits and the quantum gate information of the quantum chip are determined, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip; Based on the quantity information and the quantum gate information, a first topological structure diagram of the quantum chip is determined, wherein the first topological structure diagram is composed of a plurality of first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip; Based on the quantum gate information, determine the distance weights between each qubit; and Based on the distance weights and the first topological structure diagram, a pre-detailed pattern of the quantum chip is obtained.

16. The method according to claim 15, wherein, Based on the quantum gate information, the distance weights between each qubit are determined, including: Based on the quantum gate information, determine every two directly adjacent qubits in the quantum chip; Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits; Based on the fidelity, the distance weights between each quantum bit are determined.

17. The method according to claim 15, wherein, Based on the quantity information and the quantum gate information, the first topological structure diagram of the quantum chip is determined, including: Based on the quantity information and the quantum gate information, the target drawing function is determined; Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

18. A device for determining a sub-chip of a quantum chip, comprising: The first determining module is used to determine the first number of qubits to be used based on the computational task. The second determining module includes: a first determining submodule and a second determining submodule; wherein, the first determining submodule is used to determine a second number of third nodes included in the initial configuration based on the first number and the pre-etched pattern of the quantum chip, wherein the second number is a perfect square number; wherein, the pre-etched pattern is a square tessellation configuration with a rectangular outline, and the pre-etched pattern includes a plurality of first nodes corresponding one-to-one with a plurality of qubits of the quantum chip; the second determining submodule is used to determine the initial configuration based on the second number, wherein the initial configuration is a square tessellation configuration; The third determining module is used to determine multiple candidate characterization patterns from the pre-characterization pattern according to the initial configuration; wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip; wherein the number of nodes contained in each candidate characterization pattern is consistent with the first number; The fourth determining module is used to determine the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns; and The fifth determining module is used to determine the target sub-chip from the plurality of candidate sub-chips based on the connectivity. The first determining submodule is configured to: determine a second number of third nodes included in the initial configuration based on the first number, provided that the boundary of the pre-delineated map is complete and the first number satisfies the first threshold; wherein the second number is less than the first number.

19. The apparatus according to claim 18, wherein, The first determining submodule is further configured to: If the boundary of the pre-delineated pattern is complete and the first quantity satisfies the second threshold, the second quantity of the third node included in the initial configuration is determined based on the first quantity. The second quantity is greater than the first quantity.

20. The apparatus according to claim 18, wherein, The first determining submodule is further configured to: In the case that the boundary of the pre-drawing is incomplete, a second number of third nodes included in the initial configuration is determined based on the first number; The second quantity is less than the first quantity.

21. The apparatus according to claim 18, wherein, The third determining module is used for: In the pre-characterized diagram, a plurality of first configuration diagrams corresponding to the initial configuration are determined; Determine the outer boundaries of the plurality of first configuration diagrams; Based on the first quantity and the second quantity, a fourth node is determined on the outer boundary; The fourth node is added to the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams.

22. The apparatus according to claim 19, wherein, The third determining module is used for: In the pre-characterized diagram, a plurality of first configuration diagrams corresponding to the initial configuration are determined; Determine the self-target boundaries of the plurality of first configuration diagrams; Based on the first quantity and the second quantity, a fourth node is determined on the target boundary itself; The fourth node is deleted from the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams.

23. The apparatus according to claim 20, wherein, The third determining module is used for: The third determining submodule is used to determine a plurality of first configuration diagrams corresponding to the initial configuration in the pre-characterized diagram; The fourth determining submodule is used to determine the outer boundary of the plurality of first configuration patterns in the pre-characterized pattern based on the number of rows and columns of the pre-characterized pattern; The fifth determining submodule is used to determine the fourth node on the outer expansion boundary based on the first quantity and the second quantity; A generation submodule is used to add the fourth node to the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams.

24. The apparatus according to claim 23, wherein, The fourth determining submodule is used for: When the number of rows in the pre-characterized pattern is greater than the number of columns, an outer expansion boundary is determined outside the target column of the plurality of first configuration patterns based on the pre-characterized pattern; The target column is the outermost column located on both sides of the plurality of first configuration diagrams.

25. The apparatus according to claim 23, wherein, The fourth determining submodule is used for: When the number of rows in the pre-characterized pattern is less than the number of columns, an outer expansion boundary is determined outside the target rows of the plurality of first configuration patterns based on the pre-characterized pattern; The target behavior is located in the outermost rows on both sides of the plurality of first configuration diagrams.

26. The apparatus according to claim 18, wherein, The fourth determining module includes: The computational submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps by using a connectivity algorithm, based on the qubits corresponding to the multiple second nodes on the characterization path of the multiple candidate characterization maps.

27. The apparatus according to claim 26, wherein, The fourth determining module includes: The sixth determining submodule is used to determine the qubits located at both ends of the characterization path of the multiple candidate characterization patterns based on the qubits corresponding to the multiple second nodes on the characterization path of the multiple candidate characterization patterns. The seventh determining submodule is used to determine the first distance weight between the qubits located at the two endpoints based on the distance weight between the multiple qubits in the pre-etched pattern; The first calculation submodule is used to calculate the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization maps based on the first distance weight using the connectivity algorithm.

28. The apparatus according to claim 27, wherein, The seventh determining submodule is used for: Based on the distance weights between multiple qubits in the pre-etched pattern, a second distance weight is determined between every two adjacent qubits of the quantum chip; The first distance weight between the qubits located at the two ends is determined based on the second distance weight.

29. The apparatus according to claim 27, wherein, The seventh determining submodule is used for: Based on the distance weights between multiple qubits in the pre-characterized pattern, a third distance weight is determined between every two adjacent qubits on the characterization path of the multiple candidate characterization patterns. The first distance weight between the qubits located at the two endpoints is determined based on the third distance weight.

30. The apparatus according to claim 26, wherein, The fourth determining module includes: The eighth determining submodule is used to determine the third distance weight between every two adjacent qubits on the marking path of the multiple candidate marking maps based on the distance weight between multiple qubits of the pre-marking map; The ninth determining submodule is used to determine the average distance weight based on the third distance weight; The second calculation submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps based on the average distance weight using the connectivity algorithm.

31. The apparatus according to claim 30, wherein, The eighth determining submodule is used for: Based on the distance weights between multiple qubits in the pre-etched pattern, a second distance weight is determined between every two adjacent qubits of the quantum chip; Based on the second distance weight, a third distance weight is determined between each pair of adjacent qubits on the characterization path of the plurality of candidate characterization maps.

32. The apparatus according to any one of claims 18 to 31, further comprising: The sixth determining module is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip; The seventh determining module is used to determine a first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information, wherein the first topological structure diagram is composed of a plurality of first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip; The eighth determining module is used to determine the distance weights between the qubits based on the quantum gate information; and A generation module is used to obtain a pre-detailed pattern of the quantum chip based on the distance weights and the first topology diagram.

33. The apparatus according to claim 32, wherein, The eighth determining module is used for: Based on the quantum gate information, determine every two directly adjacent qubits in the quantum chip; Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits; Based on the fidelity, the distance weights between each quantum bit are determined.

34. The apparatus according to claim 32, wherein, The seventh determining module is used for: Based on the quantity information and the quantum gate information, the target drawing function is determined; Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

35. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 17.

36. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 17.

37. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 17.

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