Wafer map real-time drawing and updating method based on GPU acceleration and layered rendering

Abstract

This invention discloses a method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering, belonging to the field of semiconductor packaging equipment technology. Addressing the problem of insufficient traditional CPU rendering performance due to the massive number of large-size wafer chips, this method constructs a layered rendering architecture including wafer layers, crosshair layers, reference point layers, and path point layers. It starts an independent background rendering thread, controls thread execution through thread synchronization events, and utilizes GPU hardware acceleration to achieve asynchronous rendering and updating of layers. It introduces a graphics rendering volume control strategy, reducing the rendering burden through data extraction and region coverage. A dirty region update mechanism is adopted, redrawing only minor areas that have changed. Simultaneously, a local magnification window is provided for detailed observation. This invention achieves smooth, real-time display of wafer images with millions of data points under high-speed production conditions, effectively avoiding software interface lag and ensuring high equipment throughput.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging equipment technology, and more specifically to a method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering. Background Technology

[0002] With the development of the semiconductor industry, wafer sizes have gradually increased from 6 inches and 8 inches to the mainstream 12 inches. This increase in wafer size means a dramatic increase in the number of chips that can be diced from a single wafer, with low-end equipment reaching over 500,000 chips and high-end equipment exceeding 600,000 chips. This represents an order-of-magnitude change compared to the few thousand chips handled by traditional soldering equipment. This growth poses a significant challenge to the data processing capabilities and graphics display speed of die bonder software. Driven by the industry trend of pursuing higher output per hour (UPH), the equipment software must be able to respond quickly and update the wafer image status in real time. Existing technologies primarily rely on CPUs for 2D graphics rendering, but their computing power is already overwhelmed when handling the real-time rendering of millions of chip elements, easily leading to sluggish software interface responses, which in turn affects equipment production speed and operator monitoring efficiency. Although GPU technology is becoming increasingly mature, how to effectively utilize its parallel computing capabilities and design corresponding data scheduling and update strategies to overcome the bottleneck of real-time display of massive amounts of data in the specific application scenario of wafer image rendering remains a pressing technical problem.

[0003] To address the aforementioned issues, there is an urgent need for a real-time wafer image rendering and updating method based on GPU acceleration and layered rendering to solve the problems existing in traditional methods. Summary of the Invention

[0004] The purpose of this invention is to provide a method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering, which enables smooth and real-time display of wafer images with millions of data points under high-speed production conditions, effectively avoiding software interface lag and ensuring high output of the equipment.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering includes: Step 1: Construct a layered drawing architecture, creating multiple independent logical layers for the wafer image, with each logical layer having its own dedicated pixel image storage area in memory; Step 2: Start the background rendering thread, control the runtime of the thread through the thread synchronization event mechanism, and monitor the state changes of each logical layer; Step 3: Asynchronous layer update and pixel map drawing. When any logical layer changes, the background rendering thread is activated to redraw the pixel map information corresponding to the changed logical layer in memory. Step 4: The main software thread renders and updates. After the background rendering thread completes the pixel map drawing, it notifies the main software thread. The main thread then loads the updated pixel maps of each layer into the drawing board control for composite display. Step 5: Implement graphics drawing optimization. For the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, selectively extract the chip elements that need to be drawn, skip the drawing of some chips, and expand the drawing area by the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips. Step 6: Incremental update of dirty areas. When the chip state of a specific area changes, the area is marked as a dirty area. The background rendering thread updates the pixel map of the corresponding logical layer for the tiny area corresponding to the dirty area. Step 7: Provide a magnified view. Open a magnified window on the interface to display the chip status within a specified range around the current operating area.

[0006] Further, in step 1, the logical layer includes at least a wafer layer for displaying the chip array, a crosshair layer for displaying the selected points, a reference point layer for displaying the positioning reference, and a path point layer for displaying the picking path.

[0007] Furthermore, in step 2, the thread synchronization event mechanism creates synchronization events and passes them to the class corresponding to each logical layer. When a logical layer changes, it sends an instruction to control the background rendering thread to execute once. After execution, it blocks and waits for the next execution instruction.

[0008] Furthermore, the thread synchronization event is implemented using the AutoResetEvent class, and the on / off state of the background rendering thread is controlled by the WaitOne method in the AutoResetEvent class.

[0009] Furthermore, in step 3, the redrawing process utilizes the graphics library to call the GPU for hardware acceleration.

[0010] Furthermore, in step 5, the graphics drawing volume is optimized. For the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, the chip elements that need to be drawn are selectively extracted, skipping the drawing of some chips, and the drawing area is expanded by the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips. Specifically: Based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chip, the theoretical pixel size of a single chip on the drawing is calculated. When the theoretical pixel size is less than the visual threshold, the chip elements to be drawn are selectively extracted according to preset rules, that is, some chips are skipped and their adjacent, drawn chip elements expand the drawing area to cover the visual area of ​​the skipped chips, thereby reducing the number of graphic elements that actually need to be rendered.

[0011] Furthermore, the selective extraction is achieved by calculating the sampling step size. The number of rows and columns to be extracted is determined based on the difference between the total number of chips and a preset threshold. During cyclic drawing, the remainder between the row and column numbers and the sampling step size determines whether to skip the drawing.

[0012] Furthermore, in step 7, the local magnified window displays the chip status within a specified range around the current operating area and highlights the currently picked chip.

[0013] In summary, the present invention has the following beneficial technical effects: This invention successfully solves the industry challenge of real-time display of large-volume wafer images by introducing a series of techniques, including GPU acceleration, layered asynchronous rendering, rendering volume optimization, dirty area updating, and local magnification. This method significantly reduces the software's CPU resource consumption, decreasing CPU utilization from approximately 30% during full rendering to 10%, while maintaining GPU utilization at a low level (approximately 5%), ensuring high smoothness and responsiveness of the software under high production cycles. This results in no perceptible lag in the user interface when the equipment is operating at high speeds (producing 15,000 to 20,000 chips per hour). Ultimately, this method directly supports a significant increase in equipment throughput per hour (UPH), for example, from 4,000 chips / hour to 6,000 chips / hour for soldering equipment, from 10,000 chips / hour to 15,000 chips / hour for silver paste bonding equipment, and from 12,000 chips / hour to 20,000 chips / hour for eutectic bonding equipment. Simultaneously, mounting accuracy is also significantly improved, meeting the dual high standards of efficiency and precision required by modern semiconductor manufacturing. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the method flow of the present invention; Figure 2 A schematic diagram of the layer classification process; Figure 3 This is a flowchart illustrating the thread synchronization event mechanism. Figure 4 A schematic diagram illustrating the asynchronous layer update and pixel map drawing process; Figure 5 A schematic diagram of the drawn graphic elements; Figure 6Diagram of the dirty area; Figure 7 This is a schematic diagram of the production process; Figure 8 This is a schematic diagram of the manual operation process for wafer imaging. Figure 9 This is a diagram illustrating the calibration process for reference. Figure 10 This is a schematic diagram of the initial chip calibration process; Figure 11 This is a schematic diagram of the wafer image guidance device pickup process. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0016] like Figure 1 As shown, this invention provides a method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering, including: Step 1: Construct a layered drawing architecture, creating multiple independent logical layers for the wafer image, with each logical layer having its own dedicated pixel image storage area in memory; Step 2: Start the background rendering thread, control the runtime of the thread through the thread synchronization event mechanism, and monitor the state changes of each logical layer; Step 3: Asynchronous layer update and pixel map drawing. When any logical layer changes, the background rendering thread is activated to redraw the pixel map information corresponding to the changed logical layer in memory. Step 4: The main software thread renders and updates. After the background rendering thread completes the pixel map drawing, it notifies the main software thread. The main thread then loads the updated pixel maps of each layer into the drawing board control for composite display. Step 5: Implement graphics drawing optimization. For the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, selectively extract the chip elements that need to be drawn, skip the drawing of some chips, and expand the drawing area by the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips. Step 6: Incremental update of dirty areas. When the chip state of a specific area changes, the area is marked as a dirty area. The background rendering thread updates the pixel map of the corresponding logical layer for the tiny area corresponding to the dirty area. Step 7: Provide a magnified view. Open a magnified window on the interface to display the chip status within a specified range around the current operating area.

[0017] It should be noted that the main software thread is a single process that is only responsible for UI rendering and does not require manual control. Within the main software process, a background rendering thread is defined. The background rendering thread is a long-running thread that determines whether to draw layers by using a thread switch. When the various graphics rendering controllers mentioned later need to redraw graphics, they notify the background rendering thread to turn on the switch. The background rendering thread draws the layer's Bitmap in memory and notifies the main software thread to draw the Bitmap onto the controls and display it to the user.

[0018] In step 1, a layered drawing architecture is constructed, creating multiple independent logical layers for the wafer image. Each logical layer has its own dedicated pixel image storage area in memory, specifically: The logical layer includes at least a wafer layer for displaying the chip array, a crosshair layer for displaying the selection points, a reference point layer for displaying the positioning reference, and a path point layer for displaying the picking path. Different information is drawn using multiple logical images. The background rendering thread monitors the changes in each layer. If any layer changes, the corresponding layer's information is immediately drawn in memory into the dedicated pixel image for that layer. The main thread is then notified that the graphic information has changed. The main thread loads the pixel image drawn by the background rendering thread into the drawing board. The entire process takes approximately 2 milliseconds. In high-speed production (15,000-20,000 units per hour), this process does not cause any software lag or affect the equipment's output.

[0019] This invention provides a specific embodiment, such as... Figure 2 As shown, layer categorization is implemented as follows: First, this invention provides a specific system framework, including: The viewport controller is responsible for defining the map's size information, the spacing / scaling scale of each chip on the screen, defining the position of the top-left corner of the world coordinate system on the screen, responding to left-click dragging, mouse wheel zooming, and resetting the map boundaries when the window size changes.

[0020] The wafer mesh controller is responsible for drawing the wafer data model into a wafer mesh diagram according to the current viewport parameters, triggering redrawing when the data changes, calculating the visible area under the current viewport, and drawing the character information of the chip category.

[0021] Select the indicator box controller, calculate the current die based on the mouse click / scroll wheel position, draw a crosshair passing through the center of the die on the interface, and highlight the selected package with a marker box.

[0022] The scale controller is responsible for creating horizontal / vertical scales to display the row and column coordinates of the wafer map.

[0023] The marker point controller is responsible for drawing the starting point chip, reference point chip, and current point chip indicator box.

[0024] A simplified map controller is responsible for drawing a small map display of 100 chips around the current chip on the wafer.

[0025] This invention employs a layer rendering controller and a 2D viewport controller to classify layers. The layer rendering controller acts as the overall controller for layers, receiving drawing notifications and sequentially implementing interaction (2D viewport controller), rendering parameters (reference chip and current chip starting chip layers), base map (wafer image), overlay layers (crosshair and selection indicator), and composite output. The layer rendering controller is an object that oversees all layers, acting as a unified controller above all other layer controllers. Whenever a layer controller issues a redraw request, it checks the request status of each controller, identifying layers that require redrawing. The 2D viewport controller is the viewport layer controller, and its core managed states include: 1. The offset of the top left corner when world coordinates are mapped to the screen; 2. Screen spacing / span of each die (determines the scaling level); 3. Draw the dimensions of the die's appearance; 4. Allows for fine-tuning (relative offset) by dragging the mouse while following the current die; 5. Control center point, used to place a die in the center when Auto / Focus.

[0026] When displaying the crosshair on the crosshair layer and selecting the indicator box layer, the specific steps include the following: 1. When a user clicks on a location in the main view, the corresponding row / column is calculated, and finally the chip is located and set as the current die.

[0027] 2. If the current die is within the visible area, draw a horizontal line and a vertical line (i.e., a crosshair) on the screen, passing through the center of the die.

[0028] When clicking on the reference chip and the current chip, the starting chip indicator layer includes the following steps: When the user sets the reference chip, start chip, and current chip, an internal timer is enabled to periodically draw a slightly wider rectangle along the perimeter of the chip to indicate the chip's location.

[0029] The application of wafer layers is as follows: 1. Responsible for drawing each die in the Wafer. 2. If the number of dies in the visible area exceeds 40,000, skip some rows and columns in the rendering loop by using the modulus (sampling) to avoid freezing.

[0030] Application of path point layers: When a wafer platform needs to move from one chip to another, arrowed line segments are drawn to indicate the direction of movement.

[0031] Finally, the layers are combined into a bitmap using the layer rendering controller.

[0032] In step 2, a background rendering thread is started, and its runtime is controlled through a thread synchronization event mechanism to monitor the state changes of each logical layer. Specifically: Based on the layered architecture in step 1, the system starts an independent background drawing thread. This thread is responsible for monitoring the state changes of each layer. The runtime of this thread is controlled by the thread synchronization event mechanism. When all layers are unchanged, the thread is in a blocked state to save system resources. To control the background drawing thread from running without restriction, a switch is used to control its execution time. Through thread synchronization events, the software creates a synchronization event when the background rendering thread starts and passes this event to the class corresponding to each layer via the constructor. When a layer changes, a Reset command is sent to control the background rendering thread to execute once. After execution, it blocks and waits for the next execution command. This method can greatly reduce the resource waste caused by thread execution. Figure 3 As shown, the thread synchronization event mechanism of this invention uses the AutoResetEvent class provided by Microsoft C#. This class provides the WaitOne method, which is equivalent to a switch. Each execution waits for the next signal.

[0033] In step 3, asynchronous layer updates and pixel map drawing occur when any logical layer changes. The background rendering thread is activated to redraw the pixel map information corresponding to the changed logical layer in memory. Specifically: When any layer changes due to device operation (such as chip pickup), the background drawing thread is activated. This thread immediately redraws the pixel map information corresponding to the changed layer in memory, while the pixel maps of other unchanged layers remain unchanged. This drawing process utilizes graphics libraries such as OpenGL to call the GPU for hardware acceleration. The specific process is as follows: like Figure 4 As shown, when a device state changes (e.g., a chip is picked up), causing a change in the data of a certain layer, the control system notifies the host computer, which then forwards the changed data (e.g., row and column numbers) to the background drawing thread. Once awakened, the background drawing thread recalculates and draws its dedicated pixel map in memory, only for the specific layer that has changed. The drawing process utilizes the OpenGL 4.6 API to call the GPU for hardware acceleration.

[0034] In step 4, the main thread renders and updates. After the background drawing thread completes the pixel map drawing, it notifies the main thread. The main thread then loads the updated pixel maps of each layer into the drawing board control for composite display. Specifically: Based on step 3, after the background drawing thread completes the pixel image drawing, it immediately notifies the main thread of the software. Upon receiving the notification, the main thread loads the updated pixel images of each layer from the background drawing thread into the drawing board control of the graphical user interface for composite display. The entire processing cycle from layer change to interface update is controlled within a few milliseconds. The background rendering process will be described in detail below: When the background rendering thread sends a drawing command, it posts a redraw request (WM_PAINT) to the window message queue. WinForms only triggers the actual drawing process of the OpenGL control when the main thread is idle and processes the message, and the control's drawing command is then called back. Its safety stems from its UI thread affinity and message queue serialization.

[0035] In step 5, the graphics drawing volume is optimized. For the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, the chip elements that need to be drawn are selectively extracted, skipping the drawing of some chips. The drawing area is then expanded by the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips. Specifically: In the drawing process of step 3, for the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, the theoretical pixel size of a single chip on the drawing is calculated. When this size is less than the visual threshold, the system selectively extracts the chip elements to be drawn according to preset rules, that is, skips the drawing of some chips, and expands the drawing area of ​​the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips, thereby reducing the actual number of graphic elements to be rendered by about half, significantly reducing the computing load of the CPU and GPU. A specific embodiment will be used to illustrate this: like Figure 5 As shown, the actual number of graphic elements to be drawn is approximately 500,000. The drawing board control has a pixel size of 600×600, and the graphic has 840 rows and 670 columns. The calculated size of a single pixel element in each row and column is approximately 0.75×0.89 pixels. For an operator standing one meter away, such small pixels are beyond the range of human perception. Therefore, the software does not need to draw all elements when displaying the overall graphic. This invention extracts the data that does not need to be drawn according to rows and columns and a certain rule, using adjacent elements to expand the drawing area and cover the area of ​​the extracted elements, reducing the number of drawings by half. This means a reduction in the drawing workload of the CPU and GPU, and a corresponding reduction in performance pressure. GPU utilization is approximately 5%, and CPU utilization decreases from 30% of full drawing to 10%.

[0036] It's important to note here that if the number of chips exceeds 40,000, the sampling step size (mod) is calculated to determine which rows / columns are not drawn in subsequent loops. The number of chips is subtracted from 40,000, and the excess is divided by 2 to obtain the number of rows and columns to be removed. The row and column numbers of the chips in the two-dimensional array are looped through. The remainder between the row or column number and the calculated sampling step size (mod) is taken; if the remainder is 0, it means that this row or column will not be drawn.

[0037] In step 6, the dirty region is incrementally updated. When the chip state of a specific area changes, that area is marked as dirty. The background rendering thread then updates the pixel map of the corresponding logical layer for the tiny area corresponding to that dirty region. Specifically: During continuous operation of the device, based on step 3, when a chip in a specific row or column is picked up, that location is marked as a dirty area. The background drawing thread only updates the pixel map of the wafer layer for the tiny area corresponding to this dirty area, rather than redrawing the entire wafer layer. Then, it notifies the main thread again to perform a local update, thereby achieving fast incremental refresh. The specific process is as follows: During the die bonding process, each time a chip is picked up, the corresponding row and column positions on the wafer image should change accordingly. The area that needs to be changed is called the dirty region. The control system notifies the host computer of the number of rows and columns picked up and the picking result. The host computer forwards the data to the background drawing thread. The background rendering thread updates the corresponding row and column areas based on the data and then notifies the main thread to load the drawn image into the drawing board. Because the update area of ​​a single chip is very small, the entire processing time is very short, about 1-2 milliseconds. The GPU handles such a small area without any pressure, and the operator does not feel any software lag.

[0038] When the user clicks the left mouse button on the view, the offset value mapped to the screen is calculated by subtracting the X position of the grid world coordinate origin from the current pixel coordinate X position of the mouse on the control, and dividing by the width of the chip, to get the column number. Similarly, the row number is calculated.

[0039] Using the calculated row and column numbers, in the two-dimensional array of chip row and column information stored in memory, move 5 chips to the left and 5 chips up to obtain the starting chip for the magnified partial image. From the starting chip, find 10 columns to the right and 10 rows down to obtain the total number of chips required to draw the magnified partial image. Specifically, as follows... Figure 6 As shown.

[0040] In step 7, a magnified view is provided. A magnified window is opened on the interface to display the chip status within a specified range around the current operating area. Specifically: Based on the picking operation in step 6, the system simultaneously opens a local magnification window on the interface. This window displays the chip status within a specified range (e.g., 10×10) around the currently picked chip and highlights the current chip. Since this window only needs to draw a small number of chips (e.g., 100), its rendering speed is extremely fast, providing the operator with a detailed view while avoiding the huge performance overhead caused by full-image magnification.

[0041] During production, operators need to simultaneously observe the overall wafer pickup status and the pickup status of the current pickup area. Enlarging the entire wafer image would require drawing hundreds of thousands of elements simultaneously within a very short time, placing a heavy burden on the CPU and GPU, and causing software lag and interface stuttering. Therefore, the software is designed with a small window that magnifies a local area. It displays 100 chips within a 10×10 area around the currently picked chip, indicated by a marker. Drawing these 100 chips takes approximately 1 millisecond. This allows users to observe the current chip pickup status without causing software lag. A detailed illustration is shown below. Figure 7 As shown.

[0042] Next, the present invention will provide a detailed description of the manual operation process for wafer imaging using a specific embodiment: like Figure 8 As shown, the operator finds an unexposed, unetched chip on the wafer as a reference chip, moves this chip to the center of the camera, finds the corresponding chip on the wafer image, and marks this chip as a reference point. A maximum of 4 reference points can be marked. The user creates a chip template through a vision recognition system and uses the chip spacing measurement function to measure the center distance between two adjacent chips in the horizontal and vertical directions. The user uses the calibration mapping function to move from the first reference point to the last reference point in sequence. Each time the reference point is moved, the motion control system records the axis position of this reference point. The software internally calculates the position information of each row and column: Assume the row and column numbers of the first reference chip are a and b, and its axis coordinates are x and y. The row and column coordinates of the second reference chip are a1 and b1, and its axis coordinates are x1 and y1.

[0043] Chip pitch r; Then calculate the difference in the number of rows = |a-a1|, the difference in the number of columns = |y-y1|, the difference in row spacing = |x-x1|, and the difference in column spacing = |y-y1|. Row spacing difference / number of rows difference = row interval; column spacing difference / number of columns difference = column spacing. Compare row spacing with visual Y-axis spacing, and column spacing with visual X-axis spacing, accurate to 3 decimal places.

[0044] Calculate the coordinates of the entire two-dimensional array.

[0045] From row 0, column 0 to the last row, column 1, the calculation method can be based on the spacing and number of rows and columns given by the vision. The row number of the first reference chip - row 0 = number of rows, and the position of row 0, column 0 = (reference chip position XX spacing * number of columns, reference chip position YY spacing * number of rows). The calculation of other row and column positions is similar.

[0046] The operator sets the starting chip, the host computer records the row and column number of the starting chip, and sends it to the PLC. The PLC wafer moves to the position of the starting chip, and the actual position is checked to see if it matches the calculated position. The error range should be within 0.01 mm.

[0047] Two tolerance levels are set: Angle error tolerance: Maximum angle tolerance error. If the angle recognized by the vision system exceeds this error, the Wafer Table needs to compensate for the error, and the PRS will then perform a search before picking.

[0048] Angle recovery tolerance: Set a recovery angle compensation value for the wafer ring. If the recovery angle exceeds the set tolerance, the wafer ring should rotate to 0 degrees.

[0049] The following describes the positioning reference calibration process: Figure 9 As shown, the initial chip calibration process is as follows: Figure 10 As shown, the wafer image boot device pick-up process is as follows: Figure 11 As shown.

[0050] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0051] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0052] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0053] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0054] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering, characterized in that, include: Step 1: Construct a layered drawing architecture, creating multiple independent logical layers for the wafer image, with each logical layer having its own dedicated pixel image storage area in memory; Step 2: Start the background rendering thread, control the runtime of the thread through the thread synchronization event mechanism, and monitor the state changes of each logical layer; Step 3: Asynchronous layer update and pixel map drawing. When any logical layer changes, the background rendering thread is activated to redraw the pixel map information corresponding to the changed logical layer in memory. Step 4: Main thread renders and updates. After the background rendering thread completes the pixel map drawing, it notifies the main thread of the software. The main thread of the software loads the updated pixel maps of each layer into the drawing board control for composite display. Step 5: Implement graphics drawing optimization. For the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, selectively extract the chip elements that need to be drawn, skip the drawing of some chips, and expand the drawing area by the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips. Step 6: Incremental update of dirty areas. When the chip state of a specific area changes, the area is marked as a dirty area. The background rendering thread updates the pixel map of the corresponding logical layer for the tiny area corresponding to the dirty area. Step 7: Provide a magnified view. Open a magnified window on the interface to display the chip status within a specified range around the current operating area.

2. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 1, characterized in that, In step 1, the logic layer includes at least a wafer layer for displaying the chip array, a crosshair layer for displaying the selected points, a reference point layer for displaying the positioning reference, and a path point layer for displaying the picking path.

3. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 1, characterized in that, In step 2, the thread synchronization event mechanism creates synchronization events and passes them to the class corresponding to each logical layer. When a logical layer changes, it sends an instruction to control the background rendering thread to execute once. After execution, it blocks and waits for the next execution instruction.

4. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 2, characterized in that, The thread synchronization event is implemented using the AutoResetEvent class, and the on / off state of the background rendering thread is controlled by the WaitOne method in the AutoResetEvent class.

5. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 1, characterized in that, In step 3, the redrawing process utilizes the graphics library to call the GPU for hardware acceleration.

6. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 1, characterized in that, In step 5, the graphics drawing volume is optimized. For the wafer layer, based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chips, the chip elements that need to be drawn are selectively extracted, skipping the drawing of some chips. The drawing area is then expanded by the adjacent, drawn chip elements to cover the visual area of ​​the skipped chips. Specifically: Based on the actual pixel size of the drawing board control and the total number of rows and columns of the wafer chip, the theoretical pixel size of a single chip on the drawing is calculated. When the theoretical pixel size is less than the visual threshold, the chip elements to be drawn are selectively extracted according to preset rules, that is, some chips are skipped and their adjacent, drawn chip elements expand the drawing area to cover the visual area of ​​the skipped chips, thereby reducing the number of graphic elements that actually need to be rendered.

7. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 1, characterized in that, The selective extraction is achieved by calculating the sampling step size. The number of rows and columns to be extracted is determined based on the difference between the total number of chips and a preset threshold. During cyclic drawing, the remainder between the row and column numbers and the sampling step size determines whether to skip the drawing.

8. The method for real-time rendering and updating of wafer images based on GPU acceleration and layered rendering according to claim 1, characterized in that, In step 7, the local magnification window displays the chip status within a specified range around the current operating area and highlights the currently picked chip.

Images