Display panel, test method thereof and display device

Abstract

This disclosure provides a display panel and its testing method and display device, belonging to the field of display technology. The display panel of this disclosure includes: a substrate, a plurality of signal lines to be tested located on the substrate and extending from the display area to the peripheral area, and a plurality of test pads disposed in the peripheral area; the signal lines to be tested are correspondingly connected to the test pads; the display panel further includes: a switching unit located on the substrate and disposed in the peripheral area, a switching control signal line, and a switching control pad; the switching unit is connected to at least two of the plurality of signal lines to be tested, and is connected to the switching control pad through the switching control signal line; the switching unit is configured to control the on / off state of at least two of the plurality of signal lines to be tested in response to a switching control signal applied by the switching control pad.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and its testing method, and a display device. Background Technology

[0002] In the manufacturing process of display panels, to ensure the reliability and stability of products during long-term use, aging tests are typically required for the signal lines in the display panel. By simulating extreme stress conditions such as high temperature, high current, or high voltage, aging tests can effectively expose potential weaknesses in the manufacturing or materials of the signal lines, such as electromigration, overheating burns, partial open circuits, or impedance abnormalities. This allows for the elimination of defective products with a high risk of early failure before shipment. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display panel and its testing method and display device.

[0004] In a first aspect, embodiments of this disclosure provide a display panel having a display area and a peripheral area disposed on at least one side of the display area. The display panel includes: a substrate, a plurality of signal lines to be tested located on the substrate and extending from the display area to the peripheral area, and a plurality of test pads disposed in the peripheral area; the signal lines to be tested are correspondingly connected to the test pads; the display panel further includes: a switching unit located on the substrate and disposed in the peripheral area, a switching control signal line, and a switching control pad;

[0005] The switching unit is connected to at least two of the plurality of signal lines under test, and is connected to the switching control pad via the switching control signal line; the switching unit is configured to control the on / off state of at least two of the plurality of signal lines under test in response to a switching control signal applied by the switching control pad.

[0006] In some embodiments, the signal line to be tested includes at least two of the following: a power signal line, an initialization signal line, a data signal line, and a scan signal line.

[0007] In some embodiments, the display panel further includes: a lamp testing circuit located on the substrate and disposed in the peripheral area; the lamp testing circuit is connected to the data signal line;

[0008] The switching unit is arranged adjacent to the lighting test circuit.

[0009] In some embodiments, the data signal line is connected to the test pad via the lamp testing circuit.

[0010] In some embodiments, the switching unit includes: at least one switching transistor;

[0011] The control electrode of the switching transistor is connected to the switching control signal line, the first electrode is connected to one of the signal lines to be tested, and the second electrode is connected to another signal line to be tested.

[0012] In some embodiments, when there are multiple switching transistors, the first terminal of each switching transistor is connected to the same test signal line, and the second terminal is connected to different test signal lines.

[0013] In some embodiments, the display panel further includes: a lamp test pad located on the substrate and disposed in the peripheral area;

[0014] The light-up test pad is reused as the test pad.

[0015] In some embodiments, the display panel further includes: module pads located on the substrate and disposed in the peripheral region;

[0016] The module pads are reused as the test pads.

[0017] Secondly, embodiments of this disclosure provide a display device, the display device including a display panel as provided in the first aspect.

[0018] Thirdly, embodiments of this disclosure provide a method for testing a display panel, used to test the display panel as provided in the first aspect, the method comprising:

[0019] In the first testing phase, a shutdown signal is input to the switch unit through the switch control pad and the switch control signal line to control the switch unit to shut down, thereby disconnecting each of the signal lines to be tested. At the same time, different test signals are input to each of the signal lines to be tested through the test pad.

[0020] In the second testing phase, a conduction signal is input to the switch unit through the switch control pad and the switch control signal line to control the switch unit to conduct, thereby connecting at least two of the multiple test signal lines. At the same time, the same test signal is input to at least two of the multiple test signal lines through the test pad. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure.

[0022] Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present disclosure.

[0023] Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure.

[0024] Figure 4 This is a schematic diagram of an exemplary pixel circuit.

[0025] Figure 5 This is a schematic diagram of the structure of a switch unit in a display panel provided in an embodiment of the present disclosure.

[0026] Figure 6 This is a flowchart illustrating a testing method for a display panel provided in an embodiment of the present disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. Without conflict, the various embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0029] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0030] It should be noted that the transistors in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0031] It should be noted that thin-film transistors (TFTs) can be either N-type or P-type. An N-type TFT refers to a TFT with N-type ion doping in its active layer, while a P-type TFT refers to a TFT with P-type ion doping in its active layer. The operating voltage level of an N-type TFT is high; that is, when a high-level signal is input to the gate, the source and drain are connected. The operating voltage level of a P-type TFT is low; that is, when a low-level signal is input to the gate, the source and drain are connected.

[0032] Display panels typically include multiple signal lines with different functions, such as power signal lines, initialization signal lines, data signal lines, and scan signal lines. Among these, the power signal lines carry the largest current and experience the highest voltage stress, thus requiring the most aging tests to verify their resistance to burn-in. Accordingly, existing aging test equipment generally only has an output channel for the power signal lines, allowing the necessary test current or voltage to be applied independently to them. For other signal lines, such as initialization signal lines, data signal lines, and scan signal lines, these devices lack dedicated drive channels and cannot directly provide the high current or high voltage stress required for aging tests.

[0033] To perform burn-resistance aging tests on initialization signal lines, data signal lines, and scan signal lines individually, theoretically, a high-current source would be required, along with a separate test channel for each signal line under test. This would significantly increase the hardware cost and upgrade complexity of the aging test equipment, extend test time, and reduce production efficiency. Furthermore, the display panel contains a large number of signal lines, making it difficult to implement a separate test channel for each line in terms of both cost and space. Therefore, how to achieve simultaneous aging tests on multiple signal lines (especially those other than power signal lines) without significantly modifying existing aging test equipment or incurring excessive additional costs has become a pressing technical problem in this field.

[0034] To at least solve one of the aforementioned technical problems, this disclosure provides a display panel and its detection method and display device. The display panel and its detection method and display device provided in this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] In a first aspect, embodiments of this disclosure provide a display panel, Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure. Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure, as shown below. Figures 1 to 3 As shown, the display panel has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. The display panel includes: a substrate 101, a plurality of test signal lines 102 located on the substrate 101 and extending from the display area AA to the peripheral area BB, and a plurality of test pads 103 disposed on the peripheral area BB; the test signal lines 102 are correspondingly connected to the test pads 103; the display panel also includes: a switch unit 104 located on the substrate 101 and disposed on the peripheral area BB, a switch control signal line 105, and a switch control pad 106; the switch unit 104 is connected to at least two of the plurality of test signal lines 102, and is connected to the switch control pad 106 through the switch control signal line 105; the switch unit 104 is configured to control the on / off state of at least two of the plurality of test signal lines 102 in response to a switch control signal applied by the switch control pad 106.

[0036] The substrate 101 can be made of rigid materials such as glass. Glass substrates have high elastic modulus and excellent structural stability, which can effectively improve the load-bearing capacity of the upper functional film layers and ensure the stability and reliability of the overall display panel structure. Especially in large-size or high-precision display panels, rigid substrates can reduce deformation during the manufacturing process, which is beneficial to ensuring the alignment accuracy between film layers. At the same time, the substrate 101 can also be made of flexible polymer materials such as polyimide (PI). These materials give the display panel good flexibility and resistance to mechanical stress, which can significantly reduce the risk of substrate breakage caused by stress concentration during bending, stretching or twisting, and also help reduce the probability of signal line breakage, thereby improving the service life of flexible display products. In practical engineering applications, the material type of the substrate 101 can be reasonably selected according to the specific application scenario, mechanical environment requirements and optoelectronic performance requirements. For example, for wearable devices and foldable screen phones that require frequent bending or curved surface bonding, flexible substrates are preferred; while for televisions, monitors, industrial control panels and other applications with high requirements for structural rigidity, glass substrates can be used.

[0037] Multiple test signal lines 102 are provided on the substrate 101, extending from the display area AA to the peripheral area BB. Specifically, the test signal lines 102 may be power signal lines VDD, initialization signal lines Vinit, data signal lines Data, and scan signal lines (not shown in the figure). The power signal line VDD primarily provides a stable operating voltage to the pixel circuits within the display area AA and carries a large operating current, making it the most important power transmission line in the display panel. The initialization signal line Vinit, data signal line Data, and scan signal line are responsible for initialization signal transmission, data voltage writing, and scan signal transmission, respectively. These test signal lines 102 all extend outward from the display area AA into the peripheral area BB for connection to external test equipment or drive circuits.

[0038] Figure 4 This is a schematic diagram of an exemplary pixel circuit, such as... Figure 4 As shown, the pixel circuit includes: a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a storage capacitor C. All transistors are P-type transistors.

[0039] The gate of driving transistor T3 is connected to the first node N1, the source to the second node N2, and the drain to the third node N3. The gate of the first reset transistor T1 is connected to the reset signal line Reset, the source to the initialization signal line Vinit, and the drain to the third node N3. The gate of the threshold compensation transistor T2 is connected to the scan signal line Gate, the source to the third node N3, and the drain to the first node N1. The gate of the data write transistor T4 is connected to the scan signal line Gate, the source to the data signal line Data, and the drain to the second node N2. The gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, the source to the first power supply signal line VDD, and the drain to the second node N2. The gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM, the source to the third node N3, and the drain to the fourth node N4. The gate of the second reset transistor T7 is connected to the reset signal line Reset, the source to the initialization signal line Vinit, and the drain to the fourth node N4. The anode of the OLED light-emitting device is connected to the fourth node N4, and the cathode is connected to the second power signal line VSS. One end of the storage capacitor C is connected to the first node N1, and the other end is connected to the first power signal line VDD.

[0040] It should be noted that in the following description, the power signal line VDD is the same signal line as the first power signal line VDD mentioned above. The different names are only to distinguish it from the second power signal line VSS involved in the pixel circuit.

[0041] The test pads 103 are typically patterned from a conductive metal layer deposited on the substrate 101. For example, single-layer metals such as aluminum, copper, or molybdenum, or their stacked structures, can be used, thus providing good conductivity. The test pads 103 have a relatively large planar area and can be designed as rectangular, square, or other easily aligned block pads. This facilitates precise contact and stable abutment of external test probes and effectively reduces contact resistance, ensuring smooth and reliable injection of electrical signals into the panel. Each test signal line 102 extending from the display area AA to the peripheral area BB is electrically connected to its corresponding test pad 103, establishing a conductive path so that the required test signals can be applied to each test signal line 102 through the test pads 103 during subsequent testing.

[0042] The switching unit 104 is electrically connected to at least two of the plurality of test signal lines 102, and is electrically connected to the switching control pad 106 via the switching control signal line 105. With the above configuration, the switching unit 104 can control the on / off state of at least two of the plurality of test signal lines 102 in response to a switching control signal applied via the switching control pad 106.

[0043] Specifically, when a conduction control signal, such as a high-level signal, is input to the switch control pad 106, the switch unit 104 switches to the off state, restoring the electrical isolation between the previously connected signal lines 102 to be tested. At this time, different test signals or drive signals can be independently applied to each signal line 102 to be tested. When an off control signal, such as a low-level signal, is input to the switch control pad 106 via an external test probe or test fixture, this control signal is transmitted to the switch unit 104 via the switch control signal line 105, causing the switch unit 104 to switch to the on state. This electrically connects the connected signal lines 102 to be tested, forming a conductive path. At this time, the same test signal can be applied synchronously to these signal lines 102 to be tested.

[0044] Thus, by setting up a switch unit 104, a switch control signal line 105, and a switch control pad 106 in the peripheral area BB, and uniformly regulating them with the switch control signal, the connection relationship between multiple test signal lines 102 can be flexibly changed without the need for additional external switching circuits, making it easy to complete the configuration switching, thereby effectively simplifying the test operation process of the display panel and improving test efficiency and test flexibility.

[0045] In the display panel provided in this embodiment, when aging tests are required, a conduction control signal can be applied to the switching unit 104 via the switch control pad 106, electrically connecting the originally independent multiple test signal lines 102 to each other, thereby connecting at least two test signal lines 102 in parallel. At this time, only the output channel of the existing aging test equipment is needed to synchronously apply high current or high voltage stress to these parallel test signal lines 102, without needing to configure a dedicated drive channel or add an extra high current source for each test signal line 102. Thus, without significant hardware modifications to the existing aging test equipment or a significant increase in testing costs, the coverage of aging tests can be expanded from a single type of test signal line 102 to multiple different types of test signal lines 102, allowing these test signal lines 102 to undergo aging verification for burn resistance. Simultaneously, since multiple test signal lines 102 can be simultaneously subjected to the same test stress, the testing time is significantly shortened, significantly improving the efficiency and productivity of aging tests. Furthermore, when the aging test is completed and other types of tests (such as lamp lighting tests) are required, a shutdown control signal can be applied to the switch unit 104 through the switch control pad 106, so that each signal line 102 under test is restored to an independent state. This ensures that each signal line 102 under test can be given a different test signal in the subsequent test stage, and there will be no signal crosstalk or mutual interference due to interconnection, thereby further saving test costs.

[0046] In some embodiments, the signal line to be tested 102 includes at least two of the following: a power signal line VDD, an initialization signal line Vinit, a data signal line Data, and a scan signal line.

[0047] As one exemplary configuration, the test signal line 102 may include a power signal line VDD and an initialization signal line Vinit, which are responsible for providing drive power and initialization reset voltage, respectively. As another exemplary configuration, the test signal line 102 may also include a power signal line VDD and a data signal line Data, which are responsible for providing drive power and write data voltage, respectively. Similarly, the test signal line 102 may also include a power signal line VDD and a scan signal line, which are responsible for providing drive power and scan drive signal, respectively. Furthermore, all four types of functional signal lines—power signal line VDD, initialization signal line Vinit, data signal line Data, and scan signal line—may be included within the scope of the test signal line 102.

[0048] Among them, the power signal line VDD is used to transmit the DC power supply voltage required to drive the light emission of each pixel circuit in the display area AA. Its trace width is usually wide to carry a large current. The initialization signal line Vinit is used to provide initialization voltage to perform periodic reset operations on specific internal nodes in the pixel circuit to ensure the uniformity and stability of the display image. The data signal line Data is used to write the analog data voltage signal corresponding to each gray level into each pixel circuit column by column. It is a key signal line that determines the display content. The scan signal line is used to provide scan drive pulse signal line by line to control the turn-on and turn-off timing of each switching transistor in the pixel circuit to realize the line-by-line selection function.

[0049] In one specific implementation, Figure 1 In the display panel shown, the signal line 102 under test includes both the power signal line VDD and the data signal line Data.

[0050] In the first testing phase, a shutdown control signal, such as a low-level signal, is input to the switching unit 104 via the switch control pad 106 and the switch control signal line 105, causing the switching transistor in the switching unit 104 to be in the off state. At this time, the power signal line VDD and the data signal line Data are electrically isolated from each other and are not connected. Next, test probes are used to contact the test pads 103 corresponding to the power signal line VDD and the data signal line Data, respectively, to input the DC power supply voltage signal required for normal operation to the power signal line VDD, and simultaneously input the analog data voltage signal corresponding to a specific grayscale to the data signal line Data. Since the two signal lines are independent of each other, the signals they carry will not interfere with each other, so the voltage transmission characteristics on the power signal line VDD and the data writing function on the data signal line Data can be accurately tested separately.

[0051] In the second testing phase, a conduction control signal, such as a high-level signal, is input to the switching unit 104 via the switch control pad 106 and the switch control signal line 105, causing the switching transistor in the switching unit 104 to switch to the conducting state. At this time, the power signal line VDD and the data signal line Data are electrically connected to each other via the conducting switching transistor, forming a parallel connection. Subsequently, only the power signal line output channel of the existing aging test equipment is needed to apply the large current or high voltage stress required for the aging test through the test pad 103 corresponding to the power signal line VDD. Since the two test signal lines 102 are connected in parallel by the switching unit 104, the large current or high voltage stress will flow synchronously through the power signal line VDD and the data signal line Data, thereby achieving simultaneous aging test of these two test signal lines 102 without the need to configure a dedicated high-current drive channel for the data signal line Data.

[0052] In one specific implementation, Figure 2 In the display panel shown, the signal line 102 under test includes both the power signal line VDD and the initialization signal line Vinit.

[0053] In the first testing phase, a shutdown control signal, such as a low-level signal, is input to the switching unit 104 via the switch control pad 106 and the switch control signal line 105, causing the switching transistor in the switching unit 104 to be in the off state. At this time, the power signal line VDD and the initialization signal line Vinit are electrically isolated from each other and not connected. Next, test probes are used to contact the test pads 103 connected to the power signal line VDD and Vinit respectively, inputting the DC power supply voltage signal required for normal operation to the power signal line VDD, and simultaneously inputting an initialization signal to the initialization signal line Vinit to prevent residual voltage in the pixel circuit from affecting the display of the current frame. Since the two signal lines are independent of each other, the signals they carry will not interfere with each other, so the voltage transmission characteristics on the power signal line VDD and the initialization signal writing function on the initialization signal line Vinit can be accurately tested separately.

[0054] In the second testing phase, a conduction control signal, such as a high-level signal, is input to the switching unit 104 via the switch control pad 106 and the switch control signal line 105, causing the switching transistor in the switching unit 104 to switch to the conducting state. At this time, the power signal line VDD and the initialization signal line Vinit are electrically connected to each other via the conducting switching transistor, forming a parallel connection. Subsequently, only the power signal line output channel of the existing aging test equipment is needed to apply the large current or high voltage stress required for the aging test through the test pad 103 corresponding to the power signal line VDD. Since the two test signal lines 102 are connected in parallel by the switching unit 104, the large current or high voltage stress will flow synchronously through the power signal line VDD and the initialization signal line Vinit, thereby achieving simultaneous aging test of these two test signal lines 102 without the need to configure a dedicated high-current drive channel for the initialization signal line Vinit.

[0055] In one specific implementation, Figure 3 In the display panel shown, the signal line 102 under test simultaneously includes a power signal line VDD, a data signal line Data, and an initialization signal line Vinit. Its implementation principle is similar to that of the two specific implementation methods described above, and will not be detailed here.

[0056] In some embodiments, such as Figure 1As shown, the display panel also includes: a lamp testing circuit CT located on the substrate 101 and disposed in the peripheral area BB; the lamp testing circuit CT is connected to the data signal line Data; and the switch unit 104 is disposed adjacent to the lamp testing circuit CT.

[0057] The LED lighting test circuit CT is electrically connected to multiple data signal lines Data extending from the display area AA. Its main function is to input corresponding LED lighting test signals, such as data voltages corresponding to different gray levels, to each data signal line Data during the intermediate process stage after the display panel has completed the cell assembly process but before the driver chip has been bonded to the display panel. This drives the display panel to light up the entire screen or illuminate specific areas, thereby screening and judging various display defects such as uniform light emission, bright spots, dark spots, and line defects in the display panel at an early stage. This allows for the timely removal of defective panels before entering the subsequent module bonding process, avoiding unnecessary subsequent processing of defective products and effectively reducing the overall manufacturing cost.

[0058] The switching unit 104 and the lamp-lighting test circuit CT are configured to be adjacent to each other, and the switching unit 104 and the lamp-lighting test circuit CT are arranged adjacently on the layout. Since there is an exchange of control signals or test signals between the switching unit 104 and the lamp-lighting test circuit CT during operation, their adjacent arrangement can significantly shorten the signal transmission path length in the peripheral area BB, reduce the parasitic resistance and capacitance of the traces themselves, thereby reducing signal delay and signal attenuation, and improving the quality and reliability of signal transmission. On the other hand, the adjacent layout can also make the functional circuit modules in the peripheral area BB more compact and orderly, reduce the additional trace crossing and winding areas caused by the scattered layout, thereby effectively reducing the bezel area occupied by the peripheral area BB, which is conducive to realizing the narrow bezel design of the display panel and meeting consumers' demand for high screen-to-body ratio display products.

[0059] In some embodiments, such as Figure 1 and Figure 2 As shown, the data signal line Data is connected to the test pad 103 through the lamp test circuit CT.

[0060] In this embodiment, the data signal lines Data are not directly connected to the test pads 103, but are indirectly connected to the test pads 103 via the LED lighting test circuit CT. Specifically, the end of each data signal line Data is first connected to the input terminal of the LED lighting test circuit CT. The LED lighting test circuit CT has corresponding switching elements or signal distribution networks. After the test signal is distributed, buffered, or selected within the LED lighting test circuit CT, it is then led out from the output terminal of the LED lighting test circuit CT and connected to the corresponding test pad 103. Using this connection method, when the display panel needs to be subjected to aging tests via the test pads 103, the aging test signal emitted by the external test equipment first enters the LED lighting test circuit CT via the test pads 103, and then the LED lighting test circuit CT distributes and drives the signal to each data signal line Data according to the test timing, thereby testing the data signal lines Data in the display panel. This effectively avoids the risk of electrostatic damage that may be caused by direct exposure of the data signal lines Data, and also facilitates flexible switching of the signal paths required for the aging test function and subsequent module binding stages.

[0061] Figure 5 This is a schematic diagram of the structure of a switch unit in a display panel provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the switching unit 104 includes: at least one switching transistor TFT; the gate of the switching transistor TFT is connected to the switching control signal line 105, the source is connected to one test signal line 102, and the other terminal is connected to another test signal line 102.

[0062] In the circuit structure, the switching transistor TFT is connected in series between two different test signal lines 102, forming a controllable conductive bridge branch. When the switch control signal line 105 applies a conduction signal to the gate of the switching transistor TFT, the switching transistor TFT turns on, forming a low-impedance conductive channel between its source and drain, thereby electrically connecting the two test signal lines 102 connected to it. When the switch control signal line 105 applies a turn-off signal to the gate of the switching transistor TFT, the switching transistor TFT turns off, and its source and drain are in a high-impedance state, restoring electrical isolation between the two test signal lines 102. By implementing the circuit structure of the switching unit 104 with at least one switching transistor TFT, it has advantages such as fewer components, simpler control logic, and faster response speed. It can be manufactured simultaneously using the existing thin-film transistor process of the display panel without the need for additional process steps or masks, which helps to reduce manufacturing costs.

[0063] In specific embodiments of this disclosure, Figure 1 and Figure 2 The switch unit 104 shown may contain a switching transistor TFT. Figure 3 The switch unit 104 shown can contain two switching transistors (TFTs). It is understood that the number of switching transistors (TFTs) in the switch unit 104 is not limited to the example above. In actual design, it can be adjusted and set according to the specific number and type of the signal lines 102 to be tested. This application will not list them one by one here.

[0064] Specifically, when the switching unit 104 includes multiple switching transistors (TFTs), the sources of each TFT are all connected to the same test signal line 102. For example, this test signal line 102 can be a power signal line VDD. The drains of each TFT are connected to different test signal lines 102. For example, these different test signal lines 102 can be an initialization signal line Vinit, a data signal line Data, and a scan signal line, respectively. Through this connection method, multiple TFTs, using the common test signal line 102 (power signal line VDD) as a common node, establish controllable electrical connections with multiple other test signal lines 102 in a star topology. Therefore, by controlling the on and off states of each TFT, parallel connections between the common test signal line 102 and any one or more other test signal lines 102 can be flexibly achieved.

[0065] In some embodiments, such as Figures 1 to 3 As shown, the display panel also includes: an illumination test pad ET Pad located on the substrate 101 and disposed in the peripheral area BB; the illumination test pad ET Pad is reused as a test pad 103.

[0066] The LED lighting test pad ET Pad is physically reused as test pad 103. Specifically, this pad performs different test functions in different test phases. For example, in the LED lighting test phase, this pad acts as the LED lighting test pad ET Pad, receiving external LED lighting test signals to drive the display panel for light emission function verification. In the signal line aging test or other electrical test phases, this pad acts as test pad 103, used to receive and transmit corresponding test signals to the signal line 102 under test. By reusing the LED lighting test pad ET Pad as test pad 103, the total number of pads required in the peripheral area BB can be effectively reduced, simplifying the layout of the pad area, saving bezel space, which is beneficial for the narrow bezel design of the display panel. At the same time, it can also reduce the parasitic effects and signal interference risks that may be introduced due to an excessive number of pads.

[0067] In some embodiments, such as Figures 1 to 3As shown, the display panel also includes: a module pad MDL Pad located on the substrate 101 and disposed in the peripheral area BB; the module pad MDL Pad is reused as a test pad 103.

[0068] The module pad MDL Pad is directly reused as the test pad 103 in physical structure. Specifically, the pad undertakes different electrical functions in different working stages. For example, after the display panel completes all testing procedures and enters the module bonding stage, the pad, as the module pad MDL Pad, is used to press and bond with the output bump of the driver chip or the corresponding pin of the flexible circuit board to receive the display driving signal provided by the driver chip or the flexible circuit board, thereby driving the display panel to perform normal image display. When the display panel is in the testing stage, the pad serves as the test pad 103, which is used to contact external test probes or test fixtures to receive the detection signal or aging test signal applied by the test equipment and transmit these signals to the corresponding test signal line 102. By reusing the module pad MDL Pad as the test pad 103, the total number of pads required in the peripheral area BB can be effectively reduced, simplifying the layout of the pad area and reducing the overall size of the peripheral area BB. This is beneficial for achieving a narrow bezel design for the display panel. At the same time, due to the reduction in the number of pads, the risk of signal crosstalk and parasitic capacitance effects caused by excessively close spacing between pads can also be reduced, improving the integrity and reliability of signal transmission.

[0069] It should be noted here that, as Figures 1 to 3 As shown, a driver chip IC can also be disposed in the display panel. This driver chip IC can be packaged in the peripheral area BB of the display panel using a COP (Chip On Pi) method. Specifically, in the COP packaging method, the driver chip IC is not directly bonded to the substrate 101, but is first bonded to the corresponding pins of the flexible polyimide (PI) film substrate by pressing its output bumps together, and then the flexible film substrate is bent to the back side of the display panel. This allows the driver chip IC to be disposed within the flexible film bending area, transferring the driver chip IC, which originally needed to occupy the bezel area of ​​the substrate 101, to the back side of the panel or the bent portion, thereby significantly reducing the width of the front bezel of the display panel. This facilitates the realization of narrow bezel or even bezel-less display panel designs, improving the screen-to-body ratio. The specific placement of the driver chip IC in the peripheral area BB and its corresponding connection relationship with the module pad MDL Pad can be flexibly configured according to the actual packaging architecture and wiring layout requirements of the display panel; this embodiment does not impose specific limitations on this.

[0070] Secondly, this disclosure further provides a display device. This display device includes the display panel provided in any of the above embodiments. Specifically, the display device can encompass various products or components with display functions, including but not limited to: monitors, tablet computers, laptops, digital photo frames, navigators, smartphones, smart wearable devices, virtual reality or augmented reality display devices, in-vehicle central control screens, televisions, advertising screens, industrial control panels, etc. Any electronic device that needs to present information visually can use the display device provided in this disclosure. The basic principle by which this display device achieves its display function is the same as the basic principle of the aforementioned display panel. To avoid repetition, this embodiment will not elaborate on the same technical principles; please refer to the preceding description of the display panel for relevant details.

[0071] Thirdly, this disclosure provides a method for testing a display panel, used to test the display panel provided in any of the above embodiments. Figure 6 This is a flowchart illustrating a testing method for a display panel provided in an embodiment of this disclosure, as shown below. Figure 6 As shown, the testing method for the display panel includes the following steps S601 to S602.

[0072] In the first test phase, S601 inputs a shutdown signal to the switch unit through the switch control pad and the switch control signal line to control the switch unit to shut down, thereby disconnecting the signal lines to be tested. At the same time, different test signals are input to each signal line to be tested through the test pad.

[0073] In step S601 above, during the first test phase, a shutdown control signal is applied to the switching unit 104 via the switch control pad 106 and the switch control signal line 105, causing all the switching transistors (TFTs) in the switching unit 104 to be in the off state. At this time, each signal line 102 under test is electrically isolated from each other and does not conduct. In this state, an external test device is used to independently input different test signals to each connected signal line 102 under test through each test pad 103. For example, a DC power supply voltage signal is input to the power signal line VDD, an initialization reset voltage signal is input to the initialization signal line Vinit, a data voltage signal corresponding to different gray levels is input to the data signal line Data, and a scan drive pulse signal is input to the scan signal line, etc., so as to perform independent electrical performance testing on each signal line 102 under test, such as detecting whether there are defects such as open circuits, short circuits, or impedance abnormalities in each signal line.

[0074] S602, in the second test phase, a conduction signal is input to the switch unit through the switch control pad and the switch control signal line to control the switch unit to conduct, so that at least two of the multiple test signal lines are connected. At the same time, the same test signal is input to at least two of the multiple test signal lines through the test pad.

[0075] In step S602 above, during the second testing phase, a conduction control signal is applied to the switching unit 104 via the switch control pad 106 and the switch control signal line 105, causing all the switching transistors (TFTs) in the switching unit 104 to switch to the conducting state. At this time, at least two signal lines 102 to be tested are electrically connected to each other via the conducting switching transistors (TFTs), forming a parallel conductive path. In this state, an external testing device is used to input the same test signal to the at least two signal lines 102 to be tested through the test pad 103. This same test signal can be a high-current stress signal or a high-voltage stress signal required for aging testing, so as to synchronously apply the same electrical stress to these signal lines 102 to be tested, thereby simultaneously completing the burn resistance verification of multiple signal lines 102 to be tested in one test operation, significantly shortening the total time required for aging testing, and improving testing efficiency and production capacity.

[0076] It should be noted that, for clarity of illustration, the dimensions of layers and regions may be appropriately exaggerated in the accompanying drawings to facilitate a visual understanding of the structural features. Furthermore, it should be understood that when an element or layer is referred to as being "above" another element or layer, it may be directly above that other element or layer, or there may be intermediate layers between them. Similarly, when an element or layer is referred to as being "below" another element or layer, it may be directly below that other element or layer, or there may be one or more intermediate layers or elements. It should also be understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer or element between them, or there may be one or more intermediate layers or elements. Similar reference numerals used throughout this specification are used to indicate similar elements.

[0077] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in many other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the positional relationships of the components illustrated or described represent only a logical functional relative position. In actual implementation, different positional arrangements can be adopted according to specific design requirements, and should not be regarded as a limitation on the scope of protection of this disclosure.

[0078] In this disclosure, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to descriptions in connection with that embodiment or example, indicating that the specific feature, structure, material, or characteristic described is included in at least one embodiment or example of this specification. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined with each other in any suitable manner in one or more embodiments or examples. Moreover, without creating contradictions, those skilled in the art can combine or merge the different embodiments or examples described in this specification, as well as the features in different embodiments or examples.

[0079] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements should also be considered within the scope of protection of this disclosure.

Claims

1. A display panel having a display area and a peripheral area disposed on at least one side of the display area, characterized in that, The display panel includes: a substrate, multiple signal lines to be tested located on the substrate and extending from the display area to the peripheral area, and multiple test pads disposed in the peripheral area; the signal lines to be tested are correspondingly connected to the test pads; the display panel further includes: a switching unit, a switching control signal line, and a switching control pad located on the substrate and disposed in the peripheral area; The switching unit is connected to at least two of the plurality of signal lines under test, and is connected to the switching control pad via the switching control signal line; the switching unit is configured to control the on / off state of at least two of the plurality of signal lines under test in response to a switching control signal applied by the switching control pad.

2. The display panel according to claim 1, characterized in that, The signal lines to be tested include at least two of the following: power signal lines, initialization signal lines, data signal lines, and scan signal lines.

3. The display panel according to claim 2, characterized in that, The display panel further includes: a lamp testing circuit located on the substrate and disposed in the peripheral area; the lamp testing circuit is connected to the data signal line; The switching unit is arranged adjacent to the lighting test circuit.

4. The display panel according to claim 3, characterized in that, The data signal line is connected to the test pad through the lamp testing circuit.

5. The display panel according to claim 1, characterized in that, The switching unit includes: at least one switching transistor; The control electrode of the switching transistor is connected to the switching control signal line, the first electrode is connected to one of the signal lines to be tested, and the second electrode is connected to another signal line to be tested.

6. The display panel according to claim 5, characterized in that, When there are multiple switching transistors, the first terminal of each switching transistor is connected to the same test signal line, and the second terminal is connected to different test signal lines respectively.

7. The display panel according to claim 1, characterized in that, The display panel further includes: a lamp test pad located on the substrate and disposed in the peripheral area; The light-up test pad is reused as the test pad.

8. The display panel according to claim 1, characterized in that, The display panel further includes: module pads located on the substrate and disposed in the peripheral area; The module pads are reused as the test pads.

9. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 8.

10. A method for testing a display panel, used to test the display panel as described in any one of claims 1 to 8, characterized in that, The testing method for the display panel includes: In the first testing phase, a shutdown signal is input to the switch unit through the switch control pad and the switch control signal line to control the switch unit to shut down, thereby disconnecting each of the signal lines to be tested. At the same time, different test signals are input to each of the signal lines to be tested through the test pad. In the second testing phase, a conduction signal is input to the switch unit through the switch control pad and the switch control signal line to control the switch unit to conduct, thereby connecting at least two of the multiple test signal lines. At the same time, the same test signal is input to at least two of the multiple test signal lines through the test pad.

Images