Display device

Abstract

A display device includes: a display panel having a display area and a non-display area adjacent to the display area; a plurality of signal lines spaced apart from each other in the non-display area; a first planarization layer below the plurality of signal lines; and a second planarization layer on the plurality of signal lines, wherein the non-display area includes a scribing area from which the first planarization layer and the second planarization layer have been removed, and wherein the ends of the first planarization layer and the ends of the second planarization layer are disposed at different positions.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device capable of reducing or minimizing electrical short circuits between signal lines. Background Technology

[0002] Recently, various flat panel display devices, such as liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), and field emission displays (FEDs), which have excellent properties such as thinness, light weight, and low power consumption, have been developed and applied in various fields.

[0003] The display device includes multiple signal lines in the non-display area for transmitting power voltages such as reference signals, high-level signals and low-level signals, as well as drive signals such as start signals and clock signals, and the multiple signal lines are typically arranged between a first planarization layer and a second planarization layer with relatively large thicknesses.

[0004] The descriptions provided in this Background section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0005] To facilitate substrate cutting, a relatively thick first and second planarization layers are removed in the scribe area. The inventors of this disclosure have newly recognized that, because subsequent metal layers are not completely removed and remain at the step difference between the first and second planarization layers, electrical short circuits between multiple signal lines may occur.

[0006] Therefore, this disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0007] More specifically, this disclosure relates to a display device in which short circuits between multiple signal lines due to residual metal layers are prevented or reduced by positioning the ends of a first planarization layer and a second planarization layer at different locations.

[0008] Furthermore, this disclosure relates to a display device in which short circuits between multiple signal lines due to residual metal layers are prevented or reduced by forming the ends of a first planarization layer in a sawtooth shape.

[0009] Additional features and advantages of this disclosure will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained through the written description and claims, and the structures particularly pointed out in the drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of this disclosure, as implemented and broadly described herein, a display device includes: a display panel having a display area and a non-display area adjacent to the display area; a plurality of signal lines spaced apart from each other in the non-display area; a first planarization layer below the plurality of signal lines; and a second planarization layer on the plurality of signal lines, wherein the non-display area includes a scribing area in which the first planarization layer and the second planarization layer have been removed, and wherein the ends of the first planarization layer and the ends of the second planarization layer are disposed at different locations.

[0011] In another aspect, a display device may include: a substrate having a display area and a non-display area adjacent to the display area; a plurality of signal lines spaced apart from each other in the non-display area; a first planarization layer below the plurality of signal lines; and a second planarization layer on the plurality of signal lines, wherein in the non-display area, the ends of the first planarization layer and the ends of the second planarization layer are disposed at different locations, and the plurality of signal lines extend beyond the ends of the first planarization layer and the ends of the second planarization layer.

[0012] According to embodiments of this disclosure, since the ends of the first planarization layer and the second planarization layer are located at different positions, electrical short circuits between multiple signal lines caused by residual metal layers are minimized, reduced, and / or prevented.

[0013] It should be understood that both the foregoing general description and the following detailed description are interpretive and intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and form part of the specification. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0015] In the attached diagram:

[0016] Figure 1 This is a diagram illustrating a display device according to one or more exemplary embodiments of the present disclosure;

[0017] Figure 2 This is a circuit diagram illustrating a sub-pixel of a display device according to one or more exemplary embodiments of the present disclosure;

[0018] Figure 3 This is a cross-sectional view showing the sub-pixels of the display panel of a display device according to one or more exemplary embodiments of the present disclosure;

[0019] Figure 4This is a plan view showing the scribbled area of ​​a display device according to one or more exemplary embodiments of the present disclosure;

[0020] Figure 5A , Figure 5B , Figure 5C and Figure 5D They are respectively along Figure 4 Example cross-sectional views of lines Va-Va, Vb-Vb, Vc-Vc, and Vd-Vd;

[0021] Figure 6 This is a plan view showing the scribbled area of ​​a display device according to one or more exemplary embodiments of the present disclosure;

[0022] Figure 7A , Figure 7B , Figure 7C and Figure 7D They are respectively along Figure 6 Example cross-sectional views taken from lines VIIa-VIIa, VIIb-VIIb, VIIc-VIIc, and VIId-VIId; and

[0023] Figure 8 This is a cross-sectional view showing the residue of the metal layer in the scribing area of ​​a display device according to one or more exemplary embodiments of the present disclosure.

[0024] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and illustrations of these elements may be exaggerated. Detailed Implementation

[0025] Descriptions of embodiments of this disclosure will now be given in detail, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where it is determined that such descriptions unnecessarily obscure the gist of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that need to occur in a specific order. Similar reference numerals refer to similar elements throughout. The names of corresponding elements used in the following description may be chosen solely for ease of writing and therefore may differ from the names used in actual products.

[0026] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following exemplary aspects described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the appended claims.

[0027] The shapes, dimensions, scales, angles, quantities, etc., illustrated in the accompanying drawings for the purpose of describing various exemplary aspects of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Unless otherwise specified, similar reference numerals throughout the specification refer to similar elements.

[0028] In the following description, when a detailed description of a known function or configuration may unnecessarily obscure a feature or aspect of this disclosure, a detailed description of such known function or configuration may be omitted, or a brief description may be provided.

[0029] When using terms such as “including,” “having,” or “containing,” one or more additional elements may be added unless a more restrictive term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise. Any implementation described herein as an “example” is not necessarily to be construed as being better or more advantageous than other implementations.

[0030] When interpreting components, even if no explicit description of the error or tolerance range is provided, the component should be interpreted as including the error or tolerance range.

[0031] When describing positional relationships, for example, when using terms such as "above," "over," "below," "above," "below," "under," "near," "adjacent," "next to," "beside," or "adjoining" to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being "above," "over," "below," "above," "below," "near," "adjacent," "next to," "beside," or "adjoining" another structure, this description should be interpreted to include situations where these structures are in contact with each other and situations where a third structure is positioned or inserted between them. Furthermore, the terms "left side," "right side," "top," "bottom," "downward," "upward," "upper part," "lower part," etc., refer to any frame of reference. For example, when an element or layer is positioned "above" another element or layer, a third layer or element may be inserted between them.

[0032] When describing temporal relationships, such as when time priority is described as “after,” “next,” “before,” “next,” etc., discontinuous situations may be included unless more restrictive terms such as “only,” “directly,” or “immediately” are used.

[0033] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to refer to various elements, these elements should not be construed as being limited by these terms, as they are not intended to define a particular order or priority. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0034] The term "at least one" should be understood to include all combinations of one or more of the relevant elements. For example, the term "at least one of the first element, the second element, and the third element" can include all combinations of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0035] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and shall not be interpreted as having an overly idealized or overly formal meaning, unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0036] The term "display device" can include, in a narrow sense, display devices such as liquid crystal modules (LCMs), organic light-emitting diode (OLED) modules, and quantum dot (QD) modules, which include a display panel and driving units for driving the display panel. Furthermore, the term "display device" can include complete products (or final products) such as notebook computers, televisions, computer monitors, equipment display devices including automotive displays or other forms of display devices besides vehicles, and mobile electronic devices such as smartphones or tablets, which include LCMs, OLED modules, and QD modules.

[0037] Therefore, the display devices disclosed herein may include assemblies of application products or end-user devices that include LCM, OLED modules and QD modules, as well as display devices in the narrow sense such as LCM, OLED modules and QD modules.

[0038] Depending on the context, an LCM, OLED, and QD module having a display panel and a driving unit can be referred to as a "display device," and an electronic device comprising a complete product including an LCM, OLED, and QD module can be referred to as a "complete assembly." For example, a display device in a narrow sense may include a liquid crystal, organic light-emitting diode, and quantum dot display panel and a source printed circuit board (PCB) for a control unit for driving the display panel, and a complete assembly may further include a complete PCB of a complete control unit electrically connected to the source PCB for controlling the entire assembly.

[0039] The display panel disclosed herein may include various display panels, such as liquid crystal display panels, organic light-emitting diode (OLED) display panels, quantum dot display panels, and electroluminescent display panels. The display panel disclosed herein is not limited to a specific display panel having a curved bezel with a flexible substrate for an OLED display panel and a lower backplate support. The shape or size of the display panel of the display device disclosed herein is not limited thereto.

[0040] For example, when the display panel is an organic light-emitting diode (OLED) display panel, the display panel may include multiple gate lines, multiple data lines, and sub-pixels in the intersection areas of the multiple gate lines and multiple data lines. The display panel may include an array of thin-film transistors having elements for selectively applying voltage to each sub-pixel, a light-emitting element layer on the array, and an encapsulation substrate or encapsulation component covering the light-emitting element layer. The encapsulation component can protect the thin-film transistors and the light-emitting element layer from external impacts and can prevent or at least reduce the penetration of moisture or oxygen into the light-emitting element layer. Furthermore, the light-emitting element layer on the array may include an inorganic light-emitting layer, such as a nanoscale material layer or quantum dots.

[0041] The thin-film transistors disclosed herein may include one of oxide thin-film transistors, amorphous silicon thin-film transistors, and low-temperature polycrystalline silicon thin-film transistors.

[0042] Features of the various embodiments of this disclosure may be partially or wholly interconnected or combined. They may be technically linked and operated in various ways, as will be fully understood by those skilled in the art. These aspects may be implemented independently or in conjunction with each other in various combinations.

[0043] In the following, a display device according to various exemplary embodiments of the present disclosure, wherein electrical short circuits between multiple signal lines due to residual metal layers are minimized, reduced, and / or prevented, will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 This is a diagram illustrating a display device according to one or more exemplary embodiments (e.g., a first embodiment) of the present disclosure. While the display device may be an organic light-emitting diode (OLED) display device, it is not limited thereto. For example, the display device may be a quantum dot display device, a micro light-emitting diode (LED) display device, or a miniature light-emitting diode (LED) display device.

[0045] exist Figure 1 In this embodiment, the display device 110 according to one or more exemplary embodiments of the present disclosure includes a timing control unit (e.g., circuit) 120, a data driving unit (e.g., circuit) 122, a gating driving unit (e.g., but not limited to, a first gating driving unit (e.g., circuit) 124 and a second gating driving unit (e.g., circuit) 126) and a display panel 128.

[0046] The timing control unit 120 uses image signals sent from an external system such as a graphics card or television system, as well as multiple timing signals such as a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, to generate image data RGB, a data control signal DCS, and a gating control signal GCS. The timing control unit 120 sends the image data RGB and the data control signal DCS to the data drive unit 122, and sends the gating control signal GCS to the first gating drive unit 124 and the second gating drive unit 126.

[0047] Data drive unit 122 uses image data RGB and data control signal DCS sent from timing control unit 120 to generate data signal (data voltage) Vda (see Figure 2 The data signal Vda is applied to the data line DL of the display panel 128.

[0048] The first gating drive unit 124 and the second gating drive unit 126 use the gating control signal GCS sent from the timing control unit 120 to generate gating signals (gating voltages) Vsc and Vse (see Figure 2 The strobe signals Vsc and Vse are applied to the strobe line GL of the display panel 128.

[0049] The first gating drive unit 124 and the second gating drive unit 126 may have an in-panel gating (GIP) type to be formed in the non-display area NDA of the substrate of the display panel 128 having gating lines GL, data lines DL and pixels P, but this disclosure is not limited thereto. Alternatively, the gating drive unit may be manufactured as a drive chip encapsulated in a flexible film and attached to the non-display area of ​​the display panel by a tape-on-adhesion (TAB) method.

[0050] Despite Figure 1 In one or more example embodiments, the first gating drive unit 124 and the second gating drive unit 126 are disposed on two sides of the display panel 128, but in another embodiment, a gating drive unit may be disposed on one side of the display panel 128.

[0051] Display panel 128 includes a display area DA in its central portion and a non-display area NDA surrounding the display area DA. In another example, the non-display area NDA may be configured to be adjacent to the display area DA. Display panel 128 displays an image using gating signals Vsc and Vse and a data signal Vda. To display the image, display panel 128 includes multiple pixels P, multiple gating lines GL, and multiple data lines DL in the display area DA.

[0052] Each of the plurality of pixels P may include one or more of a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4, and the gate line GL and the data line DL intersect each other to define the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4. Each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may correspond to a first color, a second color, a third color, and a fourth color, respectively, and the first color, the second color, the third color, and the fourth color may be red, green, blue, and white, respectively.

[0053] Each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may include, for example, a switching transistor Tsw (see...). Figure 2 ), drive transistor Tdr (see Figure 2 ) and sensing transistor Tse (see Figure 2 Multiple transistors such as ) and storage capacitors Cst (see Figure 2 ) and LED Del (see Figure 2 ).

[0054] Figure 2 This is a circuit diagram illustrating a sub-pixel of a display device according to one or more exemplary embodiments of the present disclosure.

[0055] exist Figure 2In the display panel 128 of the display device 110 according to one or more exemplary embodiments of the present disclosure, each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 includes a switching transistor Tsw, a driving transistor Tdr, a sensing transistor Tse, a storage capacitor Cst, and a light-emitting diode Del.

[0056] Despite Figure 2 In the example, each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 has a 3T1C structure comprising three transistors and one storage capacitor. However, in another embodiment, each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may have one of a 6T1C structure comprising six transistors and one storage capacitor, a 7T1C structure comprising seven transistors and one storage capacitor, and an 8T1C structure comprising eight transistors and one storage capacitor. In other words, more or fewer transistors and more or fewer capacitors may be included in the sub-pixels of this disclosure.

[0057] Despite Figure 2 In the example, the switching transistor Tsw, the driving transistor Tdr, and the sensing transistor Tse can be N-type, but in another embodiment, at least one of the switching transistor Tsw, the driving transistor Tdr, and the sensing transistor Tse can be P-type. For example, each of the switching transistor Tsw, the driving transistor Tdr, and the sensing transistor Tse can be composed of one or a combination of P-type and N-type transistors.

[0058] The switching transistor Tsw switches on and off according to the scan signal Vsc to send the data signal Vda to the first node N1.

[0059] The gate electrode of the switching transistor Tsw is connected to the gating line GL to receive the scan signal Vsc, the drain electrode of the switching transistor Tsw is connected to the data line DL to receive the data signal Vda, and the source electrode of the switching transistor Tsw is connected to the first node N1. However, since the source and drain electrodes can change according to the applied voltage, the source and drain electrodes of the transistor are not fixed.

[0060] The driving transistor Tdr switches according to the voltage of the first node N1 to send a high-level signal (high-level voltage) Vdd to the second node N2.

[0061] The gate electrode of the driving transistor Tdr is connected to the first node N1, the drain electrode of the driving transistor Tdr is connected to the high-level power line to receive the high-level signal Vdd, and the source electrode of the driving transistor Tdr is connected to the second node N2.

[0062] The sensing transistor Tse switches according to the sensing signal (sensing voltage) Vse to send the reference signal (reference voltage) Vre to the second node N2, or to send the voltage of the second node N2 to the reference line.

[0063] The gate electrode of the sensing transistor Tse is connected to the gate line GL to receive the sensing signal Vse, the drain electrode of the sensing transistor Tse is connected to the reference line to receive the reference signal Vre or to send the voltage of the second node N2 to the reference line, and the source electrode of the sensing transistor Tse is connected to the second node N2.

[0064] The storage capacitor Cst holds the data signal Vda provided to the first node N1 for one frame and stores the threshold voltage (Vth) of the driving transistor Tdr, so that the change of the threshold voltage (Vth) of the driving transistor Tdr can be compensated during the display period.

[0065] The first capacitor electrode of the storage capacitor Cst is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cst is connected to the second node N2.

[0066] The light-emitting diode Del emits light with a brightness proportional to the current driving the transistor Tdr.

[0067] The anode of LED Del is connected to the second node N2, and the cathode of LED Del is connected to the low-level power line to receive the low-level signal (low-level voltage) Vss.

[0068] The source electrode of the switching transistor Tsw, the gate electrode of the driving transistor Tdr, and the first capacitor electrode of the storage capacitor Cst can be connected to form a first node N1, and the source electrode of the driving transistor Tdr, the source electrode of the sensing transistor Tse, the second capacitor electrode of the storage capacitor Cst, and the anode of the light-emitting diode Del can be connected to form a second node N2.

[0069] The light-emitting diode Del can display an image with brightness corresponding to the RGB of the image data, based on the driving of the sub-pixel circuits of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4.

[0070] The cross-sectional structure of each sub-pixel SP1, SP2, SP3 and SP4 of the display panel 128 of the display device 110 will be illustrated with reference to the accompanying drawings.

[0071] Figure 3 This is a cross-sectional view showing the sub-pixels of the display panel of a display device according to one or more exemplary embodiments of the present disclosure.

[0072] exist Figure 3 In the first light-shielding pattern 132, a first light-shielding pattern 132 is disposed on the substrate 130 in each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3 and the fourth sub-pixel SP4, and a first buffer layer 134 is disposed on the first light-shielding pattern 132 over the entire substrate 130.

[0073] The first light-shielding pattern 132 can block light incident from the lower part of the substrate 130. For example, the first light-shielding pattern 132 can have a single layer or multiple layers of metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0074] The first buffer layer 134 can block moisture or oxygen from penetrating from the outside. For example, the first buffer layer 134 can be a single layer or multiple layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0075] The first semiconductor layer 136 is disposed on the first buffer layer 134 corresponding to the first light-shielding pattern 132, and the first gate insulating layer 138 is disposed on the first semiconductor layer 136 over the entire substrate 130.

[0076] The first semiconductor layer 136 includes an undoped first channel region 136a at its central portion, and doped first source regions 136b and first drain regions 136c at two sides of the first channel region 136a. For example, the first semiconductor layer 136 may include a polycrystalline semiconductor material such as polycrystalline silicon.

[0077] For example, the first gate insulating layer 138 may have a single layer or multiple layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0078] The first gate electrode 140 is disposed on the first gate insulating layer 138 corresponding to the first channel region 136a of the first semiconductor layer 136, and the first capacitor electrode 142, which is separated from the first gate electrode 140, is disposed on the first gate insulating layer 138. The first interlayer insulating layer 144 is disposed on the first gate electrode 140 and the first capacitor electrode 142.

[0079] The first gate electrode 140 and the first capacitor electrode 142 may have the same layers and the same materials. For example, the first gate electrode 140 and the first capacitor electrode 142 may have a single layer or multiple layers of metal materials and their alloys, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0080] For example, the first interlayer insulation layer 144 may be a single layer or multiple layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0081] The second capacitor electrode 146 is disposed on the first interlayer insulating layer 144 corresponding to the first capacitor electrode 142, and the second light-shielding pattern 148, which is separate from the second capacitor electrode 146, is disposed on the first interlayer insulating layer 144. The second buffer layer 150 is disposed on the second capacitor electrode 146 and the second light-shielding pattern 148 over the entire substrate 130.

[0082] The second capacitor electrode 146 and the second light-shielding pattern 148 may have the same layers and the same materials. For example, the second capacitor electrode 146 and the second light-shielding pattern 148 may have a single layer or multiple layers of metallic materials and their alloys, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0083] The first capacitor electrode 142, the first interlayer insulating layer 144, and the second capacitor electrode 146 can constitute a storage capacitor Cst.

[0084] The second buffer layer 150 can block moisture or oxygen from penetrating from the outside. For example, the second buffer layer 150 can be a single layer or multiple layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0085] The second semiconductor layer 152 is disposed on the second buffer layer 150 corresponding to the second light-shielding pattern 148, and the second gate insulating layer 154 is disposed on the second semiconductor layer 152 over the entire substrate 130.

[0086] The second semiconductor layer 152 includes a non-conductive second channel region 152a at its central portion, and a conductive second source region 152b and a second drain region 152c at two sides of the second channel region 152a. For example, the second semiconductor layer 152 may include oxide semiconductor materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0087] For example, the second gate insulating layer 154 may have a single layer or multiple layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0088] The second gate electrode 156 is disposed on the second gate insulating layer 154 corresponding to the second channel region 152a of the second semiconductor layer 152, and the second interlayer insulating layer 158 is disposed on the second gate electrode 156 over the entire substrate 130.

[0089] For example, the second gate electrode 156 may have a single layer or multiple layers of metallic materials and their alloys, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0090] For example, the second interlayer insulation layer 158 may be a single layer or multiple layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0091] A first source electrode 160, a first drain electrode 162, a second source electrode 164, and a second drain electrode 166, spaced apart from each other, are disposed on a second interlayer insulating layer 158, and a first planarization layer 168 is disposed on the first source electrode 160, the first drain electrode 162, the second source electrode 164, and the second drain electrode 166 over the entire substrate 130.

[0092] The first source electrode 160 and the first drain electrode 162 are connected to the first source region 136b and the first drain region 136c of the first semiconductor layer 136 through contact holes in the second interlayer insulating layer 158, the second gate insulating layer 154, the second buffer layer 150, the first interlayer insulating layer 144, and the first gate insulating layer 138, respectively. The first source electrode 160 is connected to the second capacitor electrode 146 through contact holes in the second interlayer insulating layer 158, the second gate insulating layer 154, and the second buffer layer 150.

[0093] The second source electrode 164 and the second drain electrode 166 are respectively connected to the second source region 152b and the second drain region 152c of the second semiconductor layer 152 through contact holes in the second interlayer insulating layer 158 and the second gate insulating layer 154.

[0094] The first source electrode 160, the first drain electrode 162, the second source electrode 164, and the second drain electrode 166 may have the same layers and the same materials. For example, the first source electrode 160, the first drain electrode 162, the second source electrode 164, and the second drain electrode 166 may have a single layer or multiple layers of metallic materials and their alloys, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0095] For example, the first planarization layer 168 may have a single or multiple layers of organic insulating materials such as photoacrylic acid and benzocyclobutene (BCB).

[0096] The first semiconductor layer 136, the first gate electrode 140, the first source electrode 160, and the first drain electrode 162 can form a driving transistor Tdr, and the second semiconductor layer 152, the second gate electrode 156, the second source electrode 164, and the second drain electrode 166 can form a switching transistor Tsw.

[0097] The connecting electrode 170 is disposed on the first planarization layer 168 corresponding to the first source electrode 160, and the second planarization layer 172 is disposed on the connecting electrode 170 over the entire substrate 130.

[0098] The connecting electrode 170 is connected to the first source electrode 160 through a contact hole in the first planarization layer 168.

[0099] For example, the connecting electrode 170 may have three layers of metallic materials such as aluminum (Al) and titanium (Ti).

[0100] For example, the second planarization layer 172 may have a single layer or multiple layers of organic insulating materials such as photoacrylic acid and benzocyclobutene (BCB).

[0101] The first electrode 174 is disposed on the second planarization layer 172 corresponding to the connecting electrode 170, and the embankment layer 176 is disposed on the first electrode 174.

[0102] The first electrode 174 is connected to the connecting electrode 170 through a contact hole in the second planarization layer 172.

[0103] For example, the first electrode 174 may be an anode and may have one or more layers of transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), or one or more layers of opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and their alloys.

[0104] The embankment 176 covers the edge portion of the first electrode 174 and has an opening that exposes the central portion of the first electrode 174.

[0105] For example, the dam layer 176 can have a single or multiple layers of organic insulating materials such as photoacrylic acid and benzocyclobutene (BCB).

[0106] Although not shown, when the display device 110 has a top-emitting type, a metal layer for reflecting light emitted downward from the light-emitting layer 180 upward may be further disposed between the second planarization layer 172 and the first electrode 174.

[0107] For example, the metal layer can include metallic materials and can be electrical lines.

[0108] Spacer 178 is disposed on dam layer 176, light-emitting layer 180 is disposed on spacer 178 above the entire substrate 130, and second electrode 182 is disposed on light-emitting layer 180 above the entire substrate 130.

[0109] For example, spacer 178 may have a single layer or multiple layers of organic insulating materials such as photoacrylic acid and benzocyclobutene (BCB).

[0110] The light-emitting layer 180 contacts the first electrode 174 exposed through the opening of the dam 176, the sidewall of the opening of the dam 176, the top surface of the dam 176, and the side and top surfaces of the spacer 178.

[0111] The light-emitting layer 180 may include a hole-assisted layer such as a hole injection layer and a hole transport layer, a light-emitting material layer, and an electron-assisted layer such as an electron transport layer and an electron injection layer.

[0112] For example, the second electrode 182 may be a cathode and may have one or more layers of transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), or one or more layers of semi-transparent or opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and their alloys.

[0113] The first electrode 174, the light-emitting layer 180, and the second electrode 182 can form a light-emitting diode (LED) Del.

[0114] An encapsulation layer 184 for preventing or reducing moisture penetration is disposed on the second electrode 182 over the entire substrate 130. The encapsulation layer 184 includes a first encapsulation layer 184a, a second encapsulation layer 184b, and a third encapsulation layer 184c sequentially disposed on the second electrode 182.

[0115] For example, the first encapsulation layer 184a and the third encapsulation layer 184c may have one or more layers of inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), and the second encapsulation layer 184b may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0116] Although not shown, a metal layer, a third buffer layer, a plurality of spaced-apart bridging patterns, a third interlayer insulating layer, a plurality of spaced-apart sensor patterns, and a protective layer can be disposed on the encapsulation layer 184 over the entire substrate 130. Multiple bridging patterns and multiple sensor patterns can be used to sense a user's touch. Furthermore, Figure 3The specific structures of subpixels SP1 to SP4 shown are described by way of example only, and this disclosure is not limited thereto, and the subpixels may have various other structures when needed.

[0117] In the display device 110, multiple signal lines SL (see [link to display device]) are used to transmit power voltages such as reference signal Vre, high-level signal Vdd, and low-level signal Vss, as well as drive signals such as start signal and clock signal from the first gating drive unit 124 and the second gating drive unit 126. Figure 4 The signal lines SL are located in the non-display area NDA of the display panel 128. Multiple signal lines SL may have the same layer and material as the connection electrode 170 between the first planarization layer 168 and the second planarization layer 172.

[0118] In the display device 110, pads for connection to the data driving unit 122 are provided in the non-display area NDA of the display panel 128, and discharge patterns for preventing or reducing electrostatic discharge are provided on the outside of the pads to connect to them. After the display panel 128 is manufactured, the discharge patterns are removed from the pads by a scribing process.

[0119] For the scribing process to be successful, the scribing area SA (see...) must be removed. Figure 4 The first planarization layer 168 and the second planarization layer 172 have relatively large thicknesses. As a result, a relatively large step difference is formed at the ends of the first planarization layer 168 and the second planarization layer 172 that constitute the boundary of the scribing region SA, and multiple signal lines SL are exposed in the scribing region SA.

[0120] When a metal layer is formed on the second planarization layer 172, the metal layer is not completely removed at the step difference between the first planarization layer 168 and the second planarization layer 172, and metal layer residue is formed. As a result, electrical short circuits may occur between multiple signal lines SL due to the metal layer residue.

[0121] In the display device 110 according to one or more exemplary embodiments of the present disclosure, electrical short circuits are minimized, reduced, and / or prevented because the ends of the first planarization layer 168 and the second planarization layer 172 are located at different positions. The positions of the ends are not limited to the positions of the ends of the first planarization layer 168 and the second planarization layer 172. The positions of the ends can be applied to planarization layers on signal lines in the area where the driving unit is connected to the display device.

[0122] Figure 4 This is a plan view showing the scribbled area of ​​a display device according to one or more exemplary embodiments of the present disclosure, and Figure 5A , Figure 5B , Figure 5C and Figure 5D They are respectively along Figure 4 The cross-sectional views of lines Va-Va, Vb-Vb, Vc-Vc, and Vd-Vd.

[0123] exist Figure 4 In the non-display area NDA of the display panel 128 of the display device 110 according to one or more exemplary embodiments of the present disclosure, a plurality of signal lines SL spaced apart from each other are provided.

[0124] The non-display area NDA includes a scribing area SA corresponding to the cutting lines of the substrate 130, and the first planarization layer 168 and the second planarization layer 172 are removed in the scribing area SA to expose multiple signal lines SL.

[0125] In the non-display area NDA above and below the lined area SA, the ends of the first planarization layer 168 and the second planarization layer 172 are located at different positions.

[0126] In the non-display area NDA above the scribing area SA, the end of the first planarization layer 168 is disposed below the end of the second planarization layer 172, and in the non-display area NDA below the scribing area SA, the end of the first planarization layer 168 is disposed above the end of the second planarization layer 172.

[0127] The end of the first planarization layer 168 protrudes from the end of the second planarization layer 172 toward the scribing region SA, and the step difference between the first planarization layer 168 and the second planarization layer 172 is dispersed into a stepped shape. As a result, metal layer residues in subsequent steps of forming the metal layer are minimized, reduced, or prevented.

[0128] exist Figure 5A In the non-display area NDA above and below the scribe area SA protruding from the end of the first planarization layer 168, a first buffer layer 134, a first gate insulating layer 138, a first interlayer insulating layer 144, a second buffer layer 150, a second gate insulating layer 154, and a second interlayer insulating layer 158 are sequentially disposed on the substrate 130. The first planarization layer 168 is disposed on the second interlayer insulating layer 158, and multiple signal lines SL are disposed on the first planarization layer 168.

[0129] exist Figure 5B In the scribed region SA, a first buffer layer 134, a first gate insulating layer 138, a first interlayer insulating layer 144, a second buffer layer 150, a second gate insulating layer 154, and a second interlayer insulating layer 158 are sequentially disposed on the substrate 130. Multiple signal lines SL are disposed on the second interlayer insulating layer 158.

[0130] Since the relatively thick first planarization layer 168 and second planarization layer 172 are removed in the scribing area SA, the substrate 130 can be easily cut.

[0131] exist Figure 5C In this structure, a first buffer layer 134, a first gate insulating layer 138, a first interlayer insulating layer 144, a second buffer layer 150, a second gate insulating layer 154, and a second interlayer insulating layer 158 are sequentially disposed on a substrate 130. A first planarization layer 168 is disposed in the non-display area NDA above and below the scribe region SA. Multiple signal lines SL are disposed on the first planarization layer 168 in the non-display area NDA, and a second planarization layer 172 is disposed on the multiple signal lines SL in the non-display area NDA above and below the scribe region SA.

[0132] In the non-display area NDA, at the top and bottom of the scribing area SA, the end of the first planarization layer 168 protrudes from the end of the second planarization layer 172 toward the scribing area SA.

[0133] When the ends of the first planarization layer 168 and the second planarization layer 172 are positioned at the same location and the first planarization layer 168 and the second planarization layer 172 form a relatively large step difference portion, a residue of a metal layer is formed along the step difference portion with a relatively large thickness. As a result, adjacent signal lines SL may be electrically connected to each other, leading to an electrical short circuit.

[0134] In a display device 110 according to one or more exemplary embodiments of the present disclosure, wherein the ends of the first planarization layer 168 and the second planarization layer 172 are disposed at different locations and the step difference portions of the first planarization layer 168 and the second planarization layer 172 are dispersed, the residual thickness of the metal layer is formed or not formed along the step difference portions having a relatively small thickness. As a result, electrical short circuits between adjacent signal lines SL are minimized, reduced, or prevented.

[0135] exist Figure 5D In this structure, a first buffer layer 134, a first gate insulating layer 138, a first interlayer insulating layer 144, a second buffer layer 150, a second gate insulating layer 154, and a second interlayer insulating layer 158 are sequentially disposed on a substrate 130. A first planarization layer 168 is disposed on the second interlayer insulating layer 158 in the non-display areas NDA above and below the scribe region SA, and a second planarization layer 172 is disposed on the first planarization layer 168 in the non-display areas NDA above and below the scribe region SA.

[0136] In the display device 110 according to one or more exemplary embodiments of the present disclosure, since the ends of the first planarization layer 168 and the second planarization layer 172 adjacent to the scribe area SA are located at different positions, the step difference portions of the first planarization layer 168 and the second planarization layer 172 are dispersed, and metal layer residues are formed or not formed along the step difference portions having relatively small thicknesses. As a result, electrical short circuits between adjacent signal lines SL are minimized, reduced, or prevented.

[0137] In another embodiment, the ends of the first planarization layer and the second planarization layer are located at different positions, and the end of the first planarization layer is formed in a zigzag shape to minimize, reduce or prevent electrical short circuits.

[0138] Figure 6 This is a plan view showing the scribbled area of ​​a display device according to one or more exemplary embodiments of the present disclosure, and Figure 7A , Figure 7B , Figure 7C and Figure 7D They are respectively along Figure 6 The cross-sectional views taken from lines VIIa-VIIa, VIIb-VIIb, VIIc-VIIc and VIId-VIId in the diagram.

[0139] exist Figure 6 In the present disclosure, a plurality of signal lines SL spaced apart from each other are provided in the non-display area NDA of the display panel of a display device according to one or more exemplary embodiments of the present disclosure.

[0140] The non-display area NDA includes a scribing area SA corresponding to the cutting lines of the substrate 230, and the first planarization layer 268 and the second planarization layer 272 are removed in the scribing area SA to expose multiple signal lines SL.

[0141] In the non-display area NDA above and below the lined area SA, the ends of the first planarization layer 268 and the second planarization layer 272 are located at different positions.

[0142] In the non-display area NDA above the scribing area SA, the end of the first planarization layer 268 is disposed below the end of the second planarization layer 272, and in the non-display area NDA below the scribing area SA, the end of the first planarization layer 268 is disposed above the end of the second planarization layer 272.

[0143] The end of the first planarization layer 268 protrudes from the end of the second planarization layer 272 toward the scribing region SA, and the step difference between the first planarization layer 268 and the step difference between the second planarization layer 272 is dispersed into a stepped shape. As a result, metal layer residues in subsequent steps of forming the metal layer are minimized, reduced, or prevented.

[0144] In addition, the ends of the first planarization layer 268 have a serrated shape.

[0145] The portion of the first planarization layer 268 of the non-display area NDA at the upper part of the scribbled area SA protrudes downward between adjacent signal lines SL, and the portion of the first planarization layer 268 of the non-display area NDA at the lower part of the scribbled area SA protrudes upward between adjacent signal lines SL.

[0146] The portion of the end of the first planarization layer 268 corresponding to the space between adjacent signal lines SL protrudes from another portion of the end of the first planarization layer 268 toward the scribing region SA, and the length of the end of the first planarization layer 268 is increased. As a result, the connection of the metal layer residue in subsequent steps is minimized, reduced, or prevented.

[0147] exist Figure 7A In the protruding region at the end of the first planarization layer 268 in the scribed region SA, a first buffer layer 234, a first gate insulating layer 238, a first interlayer insulating layer 244, a second buffer layer 250, a second gate insulating layer 254, and a second interlayer insulating layer 258 are sequentially disposed on the substrate 230. The protruding portions of the first planarization layers 268, spaced apart from each other, are disposed on the second interlayer insulating layer 258, and multiple signal lines SL are respectively disposed on the second interlayer insulating layer 258 between the protruding portions of the first planarization layers 268.

[0148] The thickness of the first planarization layer 268 can be greater than the thickness of the signal lines SL, and each of the multiple signal lines SL can be positioned between protrusions of the first planarization layer 268. Therefore, even if metal layer residues are formed in subsequent steps, the metal layer residues on one signal line SL do not directly connect to the metal layer residues on adjacent signal lines SL. Thus, electrical short circuits between adjacent signal lines SL caused by metal layer residues are minimized, reduced, and prevented.

[0149] Reference Figure 8 This example illustrates an electrical short circuit.

[0150] exist Figure 7BIn the scribed region SA, a first buffer layer 234, a first gate insulating layer 238, a first interlayer insulating layer 244, a second buffer layer 250, a second gate insulating layer 254, and a second interlayer insulating layer 258 are sequentially disposed on the substrate 230. Multiple signal lines SL are disposed on the second interlayer insulating layer 258.

[0151] Since the relatively thick first planarization layer 268 and second planarization layer 272 are removed in the scribing area SA, the substrate 230 can be easily cut.

[0152] exist Figure 7C In this structure, a first buffer layer 234, a first gate insulating layer 238, a first interlayer insulating layer 244, a second buffer layer 250, a second gate insulating layer 254, and a second interlayer insulating layer 258 are sequentially disposed on a substrate 230. A first planarization layer 268 is disposed in the non-display area NDA above and below the scribe region SA. Multiple signal lines SL are disposed on the first planarization layer 268 in the non-display area NDA, and a second planarization layer 272 is disposed on the multiple signal lines SL in the non-display area NDA above and below the scribe region SA.

[0153] In the non-display area NDA above and below the scribe area SA, the end of the first planarization layer 268 protrudes from the end of the second planarization layer 272 toward the scribe area SA.

[0154] When the ends of the first planarization layer 268 and the second planarization layer 272 are positioned at the same location and the first planarization layer 268 and the second planarization layer 272 form a relatively large step difference portion, metal layer residue will form along the step difference portion with a relatively large thickness. As a result, adjacent signal lines SL may be electrically connected to each other, causing an electrical short circuit.

[0155] In a display device according to one or more exemplary embodiments of the present disclosure, wherein the ends of the first planarization layer 268 and the second planarization layer 272 are disposed at different locations and the step difference portions of the first planarization layer 268 and the second planarization layer 272 are dispersed, the residual thickness of the metal layer is formed or not formed along the step difference portions having a relatively small thickness. As a result, electrical short circuits between adjacent signal lines SL are minimized, reduced, or prevented.

[0156] exist Figure 7DIn this structure, a first buffer layer 234, a first gate insulating layer 238, a first interlayer insulating layer 244, a second buffer layer 250, a second gate insulating layer 254, and a second interlayer insulating layer 258 are sequentially disposed on a substrate 230. A first planarization layer 268 is disposed on the second interlayer insulating layer 258 in the non-display area NDA above and below the scribe region SA, and a second planarization layer 272 is disposed on the first planarization layer 268 in the non-display area NDA above and below the scribe region SA.

[0157] Figure 8 This is a cross-sectional view showing the residue of the metal layer in the scribing area of ​​a display device according to one or more exemplary embodiments of the present disclosure.

[0158] exist Figure 8 In the protruding region at the end of the first planarization layer 268 in the scribed region SA, a first buffer layer 234, a first gate insulating layer 238, a first interlayer insulating layer 244, a second buffer layer 250, a second gate insulating layer 254, and a second interlayer insulating layer 258 are sequentially disposed on the substrate 230. The protruding portions of the first planarization layers 268, spaced apart from each other, are disposed on the second interlayer insulating layer 258, and multiple signal lines SL are respectively disposed on the second interlayer insulating layer 258 between the protruding portions of the first planarization layers 268.

[0159] In subsequent steps of forming the metal layer, a metal layer residue MR is formed along the step difference between the first planarization layer 268 and the second planarization layer 272. The metal layer residue MR may be disposed on the signal line SL between the protrusions of the first planarization layer 268.

[0160] However, since the protruding portion of the first planarization layer 268, which is thicker than the signal line SL, is disposed between adjacent signal lines SL, the metal layer residue MR on one signal line SL will not be directly connected to the metal layer residue MR on the adjacent signal line SL.

[0161] Furthermore, because the ends of the first planarization layer 268 have a serrated shape and the length of the step difference portion of the first planarization layer 268 is increased, the possibility of residual MR connections in the metal layer is reduced. As a result, electrical short circuits between adjacent signal lines SL caused by residual MR in the metal layer are minimized, reduced, or prevented.

[0162] In a display device according to one or more exemplary embodiments of the present disclosure, since the ends of the first planarization layer 268 and the second planarization layer 272 of the non-display area NDA adjacent to the scribbled area SA are located at different positions, the step difference portion of the first planarization layer 268 and the second planarization layer 272 is dispersed, and metal layer residues are formed or not formed along the relatively thin step difference portion. As a result, electrical short circuits between adjacent signal lines SL are minimized, reduced, or prevented.

[0163] Furthermore, the end of the first planarization layer 268 of the non-display area NDA adjacent to the scribing area SA has a serrated shape, and the length of the step difference portion of the first planarization layer 268 is increased. As a result, the possibility of residual MR connections in the metal layer is reduced, and electrical short circuits between adjacent signal lines SL caused by residual MR in the metal layer are further minimized, reduced, or prevented. In addition, process optimization is achieved.

[0164] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

[0165] Cross-reference to related applications

[0166] This application claims the benefit and priority of Korean Patent Application No. 10-2024-0188193, filed on December 17, 2024, the entire disclosure of which is expressly incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: A display panel having a display area and a non-display area adjacent to the display area; Multiple signal lines, which are spaced apart from each other in the non-display area; A first planarization layer is located beneath the plurality of signal lines; as well as A second planarization layer is applied to the multiple signal lines. The non-display area includes the scribing area where the first planarization layer and the second planarization layer have been removed, and The ends of the first planarization layer and the ends of the second planarization layer are located at different positions.

2. The display device according to claim 1, wherein, The end of the first planarization layer protrudes from the end of the second planarization layer toward the scribing area.

3. The display device according to claim 1, wherein, Each of the first planarization layer and the second planarization layer has one of a single layer of organic insulating material and a multilayer of organic insulating material.

4. The display device according to claim 1, wherein, The ends of the first planarization layer have a serrated shape.

5. The display device according to claim 4, wherein, The portion of the end of the first planarization layer between the plurality of signal lines protrudes from another portion of the end of the first planarization layer toward the scribing area.

6. The display device according to claim 5, further comprising a metal layer on the second planarization layer, in, The residue of the metal layer is disposed on the plurality of signal lines between the protruding portions at the ends of the first planarization layer.

7. The display device according to claim 4, wherein, The end of the first planarization layer includes a protrusion that extends from other portions of the end of the first planarization layer into the scribing region.

8. The display device according to claim 7, wherein, Each of the protruding portions at the end of the first planarization layer is disposed between two adjacent signal lines among the plurality of signal lines.

9. The display device according to claim 1, wherein, The multiple signal lines are positioned in the scribed area between two opposite ends of the first planarization layer.

10. The display device according to claim 1, wherein, The thickness of the first planarization layer is greater than the thickness of the plurality of signal lines.

11. The display device according to claim 1, wherein, The step difference of the first planarization layer and the step difference of the second planarization layer are dispersed in a stepped shape.

12. The display device according to claim 1, further comprising: Multiple gate lines and multiple data lines in the display area intersect each other to define multiple sub-pixels; as well as Pixel circuit unit in each of the plurality of sub-pixels.

13. The display device according to claim 12, wherein, The pixel circuit unit includes at least one thin-film transistor and a light-emitting diode. The at least one thin-film transistor includes a semiconductor layer, a gate insulating layer on the semiconductor layer, a gate electrode located on the gate insulating layer corresponding to the semiconductor layer, an interlayer insulating layer on the gate electrode, a source electrode and a drain electrode on the interlayer insulating layer, and... The light-emitting diode includes a first electrode, a diaphragm layer on the first electrode, a light-emitting layer on the diaphragm layer, and a second electrode on the light-emitting layer.

14. The display device according to claim 13, wherein, The first planarization layer is disposed on the source electrode and the drain electrode. The connection electrode connecting the first electrode and the source electrode or the drain electrode of the at least one thin-film transistor is disposed on the first planarization layer, and The second planarization layer is disposed on the connecting electrode.

15. The display device according to claim 14, wherein, A metal layer is disposed between the second planarization layer and the first electrode.

16. The display device according to claim 13, wherein, A first encapsulation layer of inorganic insulating material, a second encapsulation layer of organic insulating material, and a third encapsulation layer of inorganic insulating material are sequentially disposed on the second electrode.

17. The display device according to claim 13, wherein, The interlayer insulating layer and the gate insulating layer are sequentially disposed below the plurality of signal lines.

18. A display device, the display device comprising: A substrate having a display area and a non-display area adjacent to the display area; Multiple signal lines, which are spaced apart from each other in the non-display area; A first planarization layer is located beneath the plurality of signal lines; as well as A second planarization layer is applied to the multiple signal lines. In the non-display area, the ends of the first planarization layer and the second planarization layer are located at different positions, and the multiple signal lines extend beyond the ends of the first planarization layer and the second planarization layer.

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