A phase-locked loop based on a dual-frequency adaptive third-order generalized integrator and a moving average compensation filter

Abstract

This invention discloses a phase-locked loop (PLL) based on a dual-frequency adaptive third-order generalized integrator and a moving average compensation filter (DFTOGI-FMAF-PLL), belonging to the field of power electronic grid-connected control and grid synchronization technology. Addressing the problems of large phase errors, poor dynamic response, and insufficient adaptability to fixed parameters in traditional PLLs under complex operating conditions such as weak grids, voltage imbalances, DC offset, and harmonic distortion, this invention proposes a hybrid PLL architecture and an adaptive parameter design method. This architecture includes a coordinate transformation module, a dual-frequency adaptive third-order integrator (DFTOGI) module, a positive-sequence calculation module, a compensation filter (FMAF) module, a phase-locked loop module, a frequency feedback module, and a parameter adaptive module. Specifically, the DFTOGI module suppresses DC offset, negative-sequence components, and harmonic distortion; the FMAF module achieves high-frequency harmonic suppression and phase compensation; and the parameter adaptive module uses a dual-branch decoupled inner-loop recurrent neural network (DBDILRNN) to tune the filter and controller parameters online. This invention can improve the accuracy of phase and frequency estimation under complex grid environments, enhance system stability margin and disturbance rejection robustness, and is suitable for grid-connected synchronization control under weak / distorted grid conditions.

Description

Technical Field

[0001] This invention relates to the field of power electronic grid-connected control and grid synchronization technology, and particularly to a filter / phase-locked loop hybrid architecture and its adaptive phase-locked loop control method for weak grid / distorted grid conditions. Specifically, it involves a phase-locked loop topology that considers DFTOGI pre-filtering and FMAF compensation filtering, as well as online parameter updates based on neural networks. Background Technology

[0002] Phase-locked loops (PLLs), as the core component of power grid synchronization, typically consist of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). In grid-connected inverters or static var generators, PLLs are used to lock the grid phase and frequency in real time, synchronizing the output current with the grid voltage. However, under conditions of increased grid impedance, weak grids, or even extremely weak grids, voltage imbalance, DC offset, and harmonic distortion can lead to increased PLL phase errors, thereby inducing system instability. Traditional PLL structures struggle to meet the demands for higher accuracy and stability under complex grid conditions, necessitating enhancement through pre-filtering and loop filtering, and further adaptive parameter adjustment based on operating conditions. Therefore, improving existing PLL structures to enhance synchronization accuracy under weak grids and unbalanced conditions, while addressing the shortcomings of traditional methods, remains a major technological challenge. In view of this, this application is proposed to reduce PLL phase errors under conditions of weak grids, voltage imbalance, DC offset, and harmonic distortion. Summary of the Invention

[0003] This invention addresses numerous technical bottlenecks of existing phase-locked loops (PLLs) under complex operating conditions such as DC offset, harmonic distortion, three-phase imbalance, and weak power grids. It proposes an innovative hybrid PLL architecture and its adaptive parameter design method. Existing technologies face three main challenges: First, the traditional orthogonal signal generation stage lacks sufficient suppression of DC components, leading to steady-state errors in the PLL results and severely impacting phase detection accuracy. Second, the introduction of a moving average filter to enhance harmonic suppression inevitably introduces a fixed phase delay, further deteriorating dynamic response performance and detection accuracy. Third, fixed controller parameters struggle to adapt to power grid strength fluctuations caused by changes in the short-circuit ratio, resulting in insufficient stability margin under weak power grid conditions and a susceptibility to oscillations and instability. To address this, this invention proposes a phase-locked loop (PLL) based on a dual-frequency adaptive third-order generalized integrator-filtered moving average filter (DFTOGI-FMAF-PLL), and provides a corresponding adaptive parameter adjustment strategy to achieve robust adaptive PLL in complex power grid environments. This invention is achieved through the following technical solution:

[0004] This invention proposes a phase-locked loop based on a dual-frequency adaptive third-order generalized integrator and a moving average compensation filter, comprising:

[0005] Coordinate transformation module: used to transform the three-phase power grid to the αβ stationary coordinate system and the dq rotating coordinate system, or to perform the inverse transformation;

[0006] Dual-frequency adaptive third-order integrator module (DFTOGI): used to pre-filter the αβ voltage signal to suppress negative sequence components and harmonic distortion caused by faults such as DC offset and three-phase imbalance, and to receive the grid angular frequency estimate to improve the adaptability to grid frequency fluctuations.

[0007] Positive sequence calculation module: used to extract the fundamental positive sequence synchronization component from the DFTOGI output and send it into the phase-locked loop control loop;

[0008] The compensation filter module (FMAF) is used to perform high-frequency harmonic suppression and phase compensation on the input of the phase-locked loop before the positive sequence component is phase-locked.

[0009] Phase-locked module: Based on a synchronous rotating coordinate system phase-locked loop (PLL), it outputs phase angle estimates and grid angular frequency estimates;

[0010] Frequency feedback module: used to feed back the estimated grid angular frequency to DFTOGI, enabling its filter to have frequency adaptive capability;

[0011] Parameter Adaptive Module: A dual-branch decoupled inner-loop recurrent neural network (DBDILRNN) is used to adaptively tune the DFTOGI filter parameters, FMAF phase compensation parameters, FMAF window length, and PI control parameters online, so as to maintain synchronization accuracy and closed-loop stability when the power grid operating conditions fluctuate over a wide range.

[0012] The overall workflow of the DFTOGI-FMAF-PLL proposed in this invention is as follows: The grid voltage is transformed by Clark to obtain the voltage components in the αβ stationary coordinate system. u α and u β First, the signal is preprocessed by a DFTOGI filter to remove DC bias, fundamental negative-sequence components, and some harmonic disturbances. The output signal of DFTOGI is then processed by a positive-sequence calculation unit to extract the fundamental positive-sequence synchronous component. The resulting FFPS component is fed into the FMAF stage, and then a PLL is used to perform real-time estimation of the fundamental grid voltage phase angle, frequency, and amplitude. Simultaneously, the estimated grid angular frequency is also calculated. ω c The filters fed back into the DTOGI module enable them to adapt to different frequencies.

[0013] The transfer function of the DFTOGI module is as follows:

[0014]

[0015] in, R F ( s ) represents the in-phase transfer function of DFTOGI. Q F ( s ) represents the orthogonal transfer function of DFTOGI. ω c The phase-locked loop estimates the grid angular frequency in real time. k 1. k 2 represents the filter gain parameter. s For the Laplace operator;

[0016] The transfer function of the FMAF module satisfies:

[0017]

[0018] in, G FMAF ( s () represents the transfer function of the FMAF module.G MAF ( s () represents the forward pass function to the MAF module. H c ( s () represents the transfer function of the phase compensation stage. r ∈[0,1), where is the attenuation factor. k =(1- r N ) / (1- r ), for normalized gain, N = T ω / T s , which is the number of sampling points within the filtering window, T ω For the length of the sliding window, T s For time delay;

[0019] Under the αβ framework R F ( s ), Q F ( s Convert to the equivalent form under the dq framework. H dq-DFTOGI ( s ), further obtained H dq-DFTOGI ( s )and G MAF ( s The transfer function of the combined filter composed of ) is:

[0020]

[0021] The open-loop transfer function of the phase-locked loop containing the combined filter G ol ( s )for:

[0022]

[0023] in, H DFTOGI ( s ) for H dq-DFTOGI ( s The simplified format after ignoring higher-order terms is as follows:

[0024]

[0025] The parameter adaptive module uses a dual-inner-loop recurrent neural network to adaptively adjust the parameters. Training can minimize the error between the actual system output and the neural network output. The input vector U in ( k )satisfy:

[0026]

[0027] in e θ ( k ), Δ ω ( k ), u d ( k ), u q ( k SCR ( k ), THD k ), ε unb ( k ), ε dc ( k These refer to phase error, frequency deviation, dq-axis voltage, short-circuit ratio, total harmonic distortion of voltage, unbalance, and DC voltage offset, respectively. k Represents discrete time points;

[0028] Training output filter parameter vector O1( k ), controller parameter vector O2( k )satisfy:

[0029]

[0030] The training objective is to minimize the PLL phase tracking error, and the loss function is... J ( k ) is defined as:

[0031]

[0032] Compared to existing technologies, this invention employs a DFTOGI-FMAF hybrid phase-locked loop architecture. While retaining the dynamic response of the phase-locked loop, it significantly enhances the suppression capability of DC offset and unbalance / distortion components through the improvement of the DFTOGI positive traffic channel. Furthermore, it utilizes FMAF to effectively filter high-frequency harmonics under the condition of satisfying the fundamental amplitude constraint and phase compensation, thereby improving the accuracy of phase and frequency estimation. In addition, a dual-loop neural network is introduced, using operating parameters such as phase error, frequency error, dq voltage, and short-circuit ratio as inputs, to achieve online adaptive adjustment of DFTOGI and phase-locked loop parameters. This allows the system to maintain better stability margin and engineering feasibility even under weak power grid and parameter disturbance conditions. Attached Figure Description

[0033] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0034] Figure 1 This invention proposes a phase-locked loop architecture based on a dual-frequency adaptive third-order generalized integrator-filtered moving average filter.

[0035] Figure 2 This is a schematic diagram of the DFTOGI integrator in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the FMAF structure in an embodiment of the present invention;

[0037] Figure 4 This is a single-phase waveform of the power grid voltage under extreme conditions of multiple disturbances superimposed in an embodiment of the present invention;

[0038] Figure 5 The waveforms for angular frequency tracking of each phase-locked loop under extreme conditions of multiple disturbances in the embodiments of the present invention are shown.

[0039] Figure 6 This invention presents a comparison of the grid synchronization performance of the adaptive parameter DFTOGI-FMAF-PLL and the fixed parameter DFTOGI-FMAF-PLL under extreme conditions of multiple disturbances in this embodiment of the invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0041] Example 1

[0042] The overall workflow of the DFTOGI-MAF-PLL proposed in this invention is as follows: The grid voltage is transformed by Clark to obtain the voltage components in the αβ stationary coordinate system. u α and u β First, the signal is preprocessed by a DFTOGI filter to remove DC bias, fundamental negative-sequence components, and some harmonic disturbances. The output signal of DFTOGI is then processed by a positive-sequence calculation unit to extract the fundamental positive-sequence synchronous component. The resulting FFPS component is fed into the FMAF stage, and then a PLL is used to perform real-time estimation of the fundamental grid voltage phase angle, frequency, and amplitude. Simultaneously, the estimated grid angular frequency is also calculated. ω c The filters fed back into the DTOGI module enable them to adapt to different frequencies.

[0043] The transfer function of the DFTOGI module is as follows:

[0044]

[0045] in, R F ( s ) represents the in-phase transfer function of DFTOGI. Q F ( s ) represents the orthogonal transfer function of DFTOGI. ω c The phase-locked loop estimates the grid angular frequency in real time. k 1. k 2 represents the filter gain parameter. s For the Laplace operator;

[0046] The transfer function of the FMAF module satisfies:

[0047]

[0048] in, G FMAF ( s () represents the transfer function of the FMAF module. G MAF ( s () represents the forward pass function to the MAF module. H c ( s () represents the transfer function of the phase compensation stage. r ∈[0,1), where is the attenuation factor. k =(1- r N ) / (1- r ), for normalized gain,N = T ω / T s , which is the number of sampling points within the filtering window, T ω For the length of the sliding window, T s For time delay;

[0049] Under the αβ framework R F ( s ), Q F ( s Convert to the equivalent form under the dq framework. H dq-DFTOGI ( s ), further obtained H dq-DFTOGI ( s )and G MAF ( s The transfer function of the combined filter composed of ) is:

[0050]

[0051] The open-loop transfer function of the phase-locked loop containing the combined filter G ol ( s )for:

[0052]

[0053] in, H DFTOGI ( s ) for H dq-DFTOGI ( s The simplified format after ignoring higher-order terms is as follows:

[0054]

[0055] The parameter adaptive module uses a dual-inner-loop recurrent neural network to adaptively adjust the parameters. Training can minimize the error between the actual system output and the neural network output. The input vector U in ( k )satisfy:

[0056]

[0057] in e θ ( k ), Δ ω (k ), u d ( k ), u q ( k SCR ( k ), THD k ), ε unb ( k ), ε dc ( k These refer to phase error, frequency deviation, dq-axis voltage, short-circuit ratio, total harmonic distortion of voltage, unbalance, and DC voltage offset, respectively. k Represents discrete time points;

[0058] Training output filter parameter vector O1( k ), controller parameter vector O2( k )satisfy:

[0059]

[0060] The training objective is to minimize the PLL phase tracking error, and the loss function is... J ( k ) is defined as:

[0061]

[0062] To fully verify the effectiveness of the novel phase-locked loop (PLL) architecture proposed in this invention, this embodiment builds a system simulation model based on the MATLAB / Simulink simulation platform to conduct comprehensive testing on the synchronization performance of the PLL. This simulation sets up an extreme and complex operating condition with multiple types of disturbances superimposed, comparing and testing four topologies: the proposed adaptive DFTOGI-FMAF-PLL, the fixed-parameter DFTOGI-FMAF-PLL, and the traditional DFTOGI-PLL and DSOGI-PLL. The system evaluates the differences in dynamic response characteristics, steady-state tracking accuracy, and disturbance robustness of different PLLs. The fixed-parameter DFTOGI-FMAF-PLL adopts... k 1 = 4.18 k 2=3.1; The adaptive DFTOGI-FMAF-PLL achieves online adaptive adjustment of parameters based on the neural network strategy proposed in this invention, and the bandwidth design of the PI controller of all topologies maintains a unified benchmark.

[0063] The simulation lasted 1.5 seconds. During the simulation, four types of disturbances—DC offset, grid voltage imbalance, harmonic interference, and frequency drop—were superimposed in an extreme condition. At 0.5 seconds, a DC offset component was injected into the grid; at 0.75 seconds, a three-phase voltage imbalance disturbance was introduced; and at 1.0 seconds, the 5th, 7th, 11th, and 13th harmonics were injected. The simulated grid voltage waveform under this extreme condition with multiple disturbances is shown in the attached figure. Figure 4 As shown;

[0064] Furthermore, based on Figure 4 Regarding voltage disturbances, the simulation waveforms of angular frequency tracking of each phase-locked loop under extreme conditions of multiple disturbance superposition in this embodiment of the invention are as follows: Figure 5 As shown, simulation results demonstrate significant performance differences under identical PI controller parameters: While both DSOGI-PLL and DETOGI-PLL can suppress some disturbances, DSOGI-PLL's overall suppression of DC offset and DETOGI-PLL harmonic distortion is insufficient, resulting in noticeable oscillations in the tracking output. Furthermore, in the frequency drop phase with multiple disturbances, DSOGI-PLL's settling time is significantly longer than in the single frequency drop condition, with a substantial increase in overshoot and severely deteriorated dynamic performance. The DFTOGI-FMAF-PLL proposed in this invention still exhibits excellent overall performance under this extremely complex condition. Although a very small frequency fluctuation occurs after multiple disturbances are continuously superimposed, compared to the other three types of phase-locked loops, its tracking overshoot is extremely small, its transient adjustment time is shorter, and there are no large oscillations throughout the entire process. With the synergistic effect of the pre-filter and phase compensator, its dynamic response speed is better than DFTOGI-PLL, demonstrating strong anti-disturbance robustness and adaptability to complex conditions.

[0065] Finally, a comparison of the grid synchronization performance of the adaptive parameter DFTOGI-FMAF-PLL and the fixed parameter DFTOGI-FMAF-PLL under extreme conditions of multiple disturbances in this embodiment of the invention is attached. Figure 6 As shown in the figure. Simulation results show that, compared with the fixed parameter scheme, the adaptive phase-locked loop based on DBDILRNN reduces transient overshoot by more than 20% and shortens transient settling time by more than 10% during angular frequency and phase tracking. It outperforms the fixed parameter phase-locked loop in terms of steady-state tracking accuracy, disturbance rejection robustness, and dynamic response speed, fully verifying the effectiveness and superiority of the adaptive strategy proposed in this invention.

[0066] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A phase-locked loop (DFTOGI-FMAF-PLL) based on a dual-frequency adaptive third-order generalized integrator-filtered moving average filter, characterized in that, include: Coordinate transformation module: used to transform the three-phase power grid to the αβ stationary coordinate system and the dq rotating coordinate system, or to perform the inverse transformation; Dual-frequency adaptive third-order integrator module (DFTOGI): used to pre-filter the αβ voltage signal to suppress negative sequence components and harmonic distortion caused by faults such as DC offset and three-phase imbalance, and to receive the grid angular frequency estimate to improve the adaptability to grid frequency fluctuations. Positive sequence calculation module: used to extract the fundamental positive sequence synchronization component from the DFTOGI output and send it into the phase-locked loop control loop; The compensation filter module (FMAF) is used to perform high-frequency harmonic suppression and phase compensation on the input of the phase-locked loop before phase-locking the positive sequence component; Phase-locked module: Based on a synchronous rotating coordinate system phase-locked loop (PLL), it outputs phase angle estimates and grid angular frequency estimates; Frequency feedback module: used to feed back the estimated grid angular frequency to DFTOGI, enabling its filter to have frequency adaptive capability; Parameter Adaptive Module: A dual-branch decoupled inner-loop recurrent neural network (DBDILRNN) is used to adaptively tune the DFTOGI filter parameters, FMAF phase compensation parameters, FMAF window length, and PI control parameters online, so as to maintain synchronization accuracy and closed-loop stability when the power grid operating conditions fluctuate over a wide range.

2. A phase-locked loop based on a dual-frequency adaptive third-order generalized integrator and a moving average compensation filter according to claim 1, characterized in that, The transfer function of the DFTOGI module is as follows: in, R F ( s ) represents the in-phase transfer function of DFTOGI. Q F ( s ) represents the orthogonal transfer function of DFTOGI. ω c The phase-locked loop estimates the grid angular frequency in real time. k 1. k 2 represents the filter gain parameter. s For the Laplace operator; The transfer function of the FMAF module satisfies: in, G FMAF ( s () represents the transfer function of the FMAF module. G MAF ( s () represents the forward pass function to the MAF module. H c ( s () represents the transfer function of the phase compensation stage. r ∈[0,1), where is the attenuation factor. k =(1- r N ) / (1- r ), for normalized gain, N = T ω / T s , which is the number of sampling points within the filtering window, T ω For the length of the sliding window, T s For time delay; Under the αβ framework R F ( s ), Q F ( s Convert to the equivalent form under the dq framework. H dq-DFTOGI ( s ), further obtained H dq-DFTOGI ( s )and G MAF ( s The transfer function of the combined filter composed of ) is: 。 3. A phase-locked loop based on a dual-frequency adaptive third-order generalized integrator and a moving average compensation filter according to claim 1, characterized in that, The open-loop transfer function of the phase-locked loop containing the combined filter G ol ( s )for: in, H DFTOGI ( s ) for H dq-DFTOGI ( s The simplified format after ignoring higher-order terms is as follows: 。 4. A phase-locked loop based on a dual-frequency adaptive third-order generalized integrator and a moving average compensation filter according to claim 1, characterized in that, The parameter adaptive module uses a dual-inner-loop recurrent neural network to adaptively adjust the parameters. Training can minimize the error between the actual system output and the neural network output. The input vector U in ( k )satisfy: in e θ ( k ), Δ ω ( k ), u d ( k ), u q ( k SCR ( k ), THD k ), ε unb ( k ), ε dc ( k These refer to phase error, frequency deviation, dq-axis voltage, short-circuit ratio, total harmonic distortion of voltage, unbalance, and DC voltage offset, respectively. k Represents discrete time points; Training output filter parameter vector O1( k ), controller parameter vector O2 ( k )satisfy: The training objective is to minimize the PLL phase tracking error, and the loss function is... J ( k ) is defined as: 。

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