Wide input coreless power supply for wide bandgap devices

Abstract

A power supply device includes a secondary inductor (Ls) configured to form a transformer with a primary inductor (Lp). A first terminal of the secondary inductor is electrically connected to a second terminal of the secondary inductor via a second capacitor (C2), an inductor (Lc), and a third capacitor (C3) connected in series. The two terminals of the third capacitor (C3) are electrically connected to corresponding output terminals to provide an output voltage (Vout). The two terminals of the third capacitor (C3) are also electrically connected to the corresponding output terminals via an electronic network including a plurality of diodes (D1, D2) and a plurality of additional capacitors (C4, C5, Cout). The power supply device can be implemented on a single chip or a dual-chip architecture.

Description

Technical Field

[0001] This disclosure relates to a power supply device. Background Technology

[0002] Wide bandgap devices are suitable for use in electric vehicles due to their relatively low switching losses and relatively high operating temperatures. However, their fast switching speed results in a high dv / dt during the switching process. This high dv / dt can lead to common-mode current. A considerable common-mode current can distort the gating signal.

[0003] To keep the common-mode current as small as possible, it is desirable to design low pseudo-capacitance for both the gate driver IC and the gate driver power supply. For example, it is known to use an isolated power supply to achieve a small pseudo-capacitance. Figure 2 A typical gate driver power supply using a flyback based on a high-frequency transformer is shown.

[0004] In traditional isolated power supply designs, high-frequency transformers are designed to have a small coupling coefficient between the primary and secondary sides, which contributes to small pseudo-capacitance. Such design considerations may result in relatively large magnetic cores, large air gap designs, or specific winding arrangements.

[0005] However, the power supply is advantageously designed with a relatively high coupling factor between the primary and secondary windings to achieve good output voltage quality. Therefore, a low pseudo-capacitor value will not only affect the power supply's output voltage quality but also result in a large power supply size, which is not vibration-friendly.

[0006] In summary, conventional power supply designs may suffer from one or more drawbacks. For example, low pseudo-capacitance and common-mode current can lead to a large power supply size. High dv / dt immunity can also result in a large power supply size. A proper balance between output voltage quality, pseudo-capacitance value, and winding input voltage design can only be achieved through specific core selection and windings. A voltage feedback loop with high insulation capability from the high-voltage side may be required to control the output voltage.

[0007] The background section is intended only to provide a contextual overview of some current problems and is not intended to be exhaustive. Further contextual information will become apparent to those skilled in the art after reading the following detailed description. Summary of the Invention

[0008] According to one embodiment, the power supply device may include:

[0009] A secondary inductor, configured to form a transformer with the primary inductor.

[0010] The first terminal of the secondary inductor is electrically connected to the second terminal of the secondary inductor via a second capacitor, an inductor, and a third capacitor connected in series.

[0011] The two terminals of the third capacitor are electrically connected to the corresponding output terminals to provide an output voltage.

[0012] Surprisingly, the network on the secondary inductor side helps reduce the pseudo-capacitance between the primary and secondary inductors, thereby reducing the common-mode current.

[0013] The two terminals of the third capacitor can be electrically connected to the corresponding output terminals via an electronic network comprising multiple diodes and multiple additional capacitors. This further improves the electrical characteristics of the power supply device.

[0014] The electronic network may include a first diode having a first terminal and a second terminal; a second diode having a first terminal and a second terminal; a fourth capacitor having a first terminal and a second terminal; and a fifth capacitor having a first terminal and a second terminal, wherein the first terminal of the first diode is electrically connected in parallel to the first terminal of the third capacitor and the second terminal of the second diode, wherein the second terminal of the first diode is electrically connected in parallel to the respective output terminals of the first terminal of the fourth capacitor and the first terminal of the third capacitor, and wherein the second terminal of the third capacitor is electrically connected in parallel to the second terminal of the fourth capacitor and the second terminal of the fifth capacitor, and wherein the first terminal of the second diode is electrically connected to the first terminal of the fifth capacitor and the respective output terminal of the third capacitor. This can further help reduce spurious capacitance and / or common-mode current.

[0015] The power supply device may further include the primary inductor, wherein two terminals of the primary inductor are electrically connected to corresponding input terminals to receive an input voltage. This provides a compact, integrated power supply device.

[0016] At least one of the two terminals of the primary inductor can be electrically connected to its corresponding input terminal via a capacitor. This further enhances the electrical characteristics of the power supply device.

[0017] The two terminals of the primary inductor can be electrically connected to the corresponding input terminals via a switching network. This further improves the electrical characteristics of the power supply device.

[0018] The secondary inductor can be integrated into a chip that does not include the primary inductor. This provides greater flexibility in design. Furthermore, by arranging the primary inductor relative to the secondary inductor as needed, freedom can be provided to configure pseudo-capacitance and / or common-mode current.

[0019] The power supply device may include a printed circuit board, a first chip, and a second chip, wherein a primary inductor is implemented in the first chip and a secondary inductor is implemented in the second chip, and wherein the first chip and the second chip are mounted on the printed circuit board, with the primary inductor of the first chip facing the secondary inductor of the second chip. This allows the distance between the primary and secondary inductors to be selected during assembly.

[0020] Primary and secondary inductors can be integrated into a single chip. This provides a compact power supply device with pre-configured properties.

[0021] The primary and secondary inductors can be coreless transformer inductors. This allows for a smaller power supply unit size. Power supply unit designs as described in this article can allow for the omission of the inductor core while still providing sufficient mass.

[0022] Those skilled in the art will understand that the above features can be combined in any way that they deem useful. Attached Figure Description

[0023] This disclosure will be described in more detail below with reference to the accompanying drawings. Throughout the drawings, similar items may be indicated by the same reference numerals. The drawings are schematic and may not be drawn to scale.

[0024] Figure 1 A perspective view of the power supply device is shown.

[0025] Figure 2 The circuit diagram of the power supply device is shown.

[0026] Figure 3 A top view of a power supply device with two chips is shown.

[0027] Figure 4 A circuit diagram of a power supply device with two chips is shown.

[0028] Figure 5 A top view of a power supply device with a single chip is shown.

[0029] Figure 6 A circuit diagram of a power supply device with a single chip is shown.

[0030] Figure 7A -K shows a graph illustrating the electrical characteristics of the power supply device.

[0031] Figure 8 An example of pseudocapacitance as a function of distance is shown.

[0032] Figure 9 An example of common-mode current as a function of switching speed is shown.

[0033] Figure 10 An example of how the output voltage changes over time is shown. Detailed Implementation

[0034] Certain exemplary embodiments will be described in more detail with reference to the accompanying drawings. The disclosures in the specification, such as detailed constructions and elements, are provided to aid in a comprehensive understanding of the exemplary embodiments. Therefore, it will be apparent that the exemplary embodiments can be performed without those specific limitations. Furthermore, well-known operations or structures are not described in detail, as this would obscure them with unnecessarily detailed descriptions.

[0035] Figure 1 A power supply device 100 is shown, which includes circuitry with an internal inductor and a wide-bandgap device. The wide-bandgap device has a relatively fast switching speed. This results in a rapid transition between on and off states, as well as high peak values ​​for voltage increases and / or decreases. Therefore, the voltage increase (or decrease) divided by the duration (dV / dt) when switched on or off can have a large absolute value. This is because the power supply device inherently possesses a pseudo-capacitance C. PS Therefore, it may lead to common-mode current I CM .

[0036] Figure 2 A circuit diagram of power supply device 100 is shown. Power supply device 100 may show a power supply using a flyback gate driver based on a high-frequency transformer. When switch S is closed, AC voltage source Vi generates voltage V1 across primary inductor L1. Secondary inductor L2 obtains voltage V2 from primary inductor V1. One end of L2 is connected to the first output terminal T1 via rectifier diode D. The other end of inductor L2 is connected to the second output terminal T2. Output terminals T1 and T2 are electrically connected to each other via a capacitor C and a resistor R arranged in parallel. To maintain the current-mode current (I0)... CM The goal is to design low pseudo-capacitance C for both the gate driver IC and the gate driver power supply, ideally as small as possible. PS For example, a smaller C can be achieved using an isolated power supply. PS .

[0037] Figure 3 A two-chip implementation of a power device is shown. The primary-side chip 301 includes a primary inductor Lp, and the secondary-side chip 302 includes a secondary inductor Ls. As shown, the distance d between the two chips 301 and 302 defines the distance between the primary inductor Lp and the secondary inductor Ls. PSThis refers to a pseudo-capacitor, which is not a separate component but an inherent capacitance present between the primary and secondary inductors. As shown, the primary-side chip 301 and the secondary-side chip 302 can be placed in a circuit that includes several other components. This circuit can be implemented, for example, on a printed circuit board. For example, suitable terminals of the primary-side chip can be connected to the input voltage Vin, the capacitance Cin, and the resistance R. C1 The secondary-side chip 302 may have an output voltage terminal Vout that can be connected to a capacitive load Cout.

[0038] Both chips 301 and 302 can have separate chip packages 304 and 305. The primary-side chip 301 can be packaged in the first package 304, and the secondary-side chip 302 can be packaged in the second package 305. These packages 304 and 305 can be molded or manufactured in any other suitable manner. Packages 304 and 305 may have pins 306 extending from them for external connections to circuitry within the respective chips 301 and 302. For example, these pins 306 can be soldered onto a PCB.

[0039] For example, such as Figure 3 As shown, a primary-side package 304 with a primary-side chip 301 and a secondary-side package 305 with a secondary-side chip 302 can be soldered to the same side of a PCB 303. Alternatively, the primary-side package 304 and the secondary-side package 305 can be soldered to opposite sides of a PCB (not shown). Other mounting methods can be considered instead of soldering. For example, Figure 4 The components of the primary-side chip 301 shown may be partially separate components, for example, included in a package 304. Similarly, the secondary-side components may be packaged in a package 305.

[0040] Figure 4 The circuitry of the dual-chip implementation is shown in more detail. The figure illustrates the input capacitor C. IN Output capacitor C OUT Primary side resonant capacitor C1, C2, C3, L (from the equivalent diagram) C The components shown are the secondary resonant components, boost capacitors C4 and C5, boost diodes D1 and D2, and the primary inductor L of the coreless transformer. P and the secondary inductor L of the coreless transformer S .

[0041] Switches S1-S4 form a full bridge. This full bridge can be connected as is known in the prior art. Switches S1 to S4 can be wide-bandgap devices. Capacitor C1 and inductor L... p This forms a primary-side resonant circuit, while the inductor L... s Capacitor C2, Inductor L CIt forms a secondary side circuit with conductor C3.

[0042] Conductors C4 and C5, along with diodes D1 and D2, can be used to double the voltage across C3, making the output voltage Vout greater than the voltage across C3.

[0043] Control can be implemented in the primary-side circuit using controller 401, peak detector 402, and pulse width modulator 403. For this purpose, the end-peak detector 402 can be configured to detect the flow through L. p The peak current. Resistor R C R C1 and capacitor C C It can be used to set control parameters to achieve current peak control. Controller 401 can be any digital or analog signal processor, such as a computer processor. Controller 401 controls pulse width modulator 403 based on the signal received from peak detector 402.

[0044] Parameters (C1, C2, C3, Lp, Ls, and Lc) can be selected to ensure that the circuit formed by C1, C2, C3, Lp, Ls, and Lc has the same or similar resonant frequency as the switching frequencies of S1-S4. Examples are listed below:

[0045] Primary side resonant capacitor – C1: 5.1nF

[0046] Secondary resonant components – C2: 5.1nF; C3: 51nF; L C 0.5nH

[0047] Coreless transformer primary side inductor – L P 4.967nH

[0048] Coreless transformer secondary side inductor – L S 4.967nH

[0049] The turns ratio of Lp to Ls can be 10:16.

[0050] The testing process with the above values ​​is shown in Figure 7. Here, the x-axis represents time in seconds, and the y-axis shows arbitrary units. Figure 7A The curve 701 shows the state of switch S1, that is, the gate of S1 (1 = open, 2 = closed). Figure 7B Graph 702 shows the gate of switch S2. Figure 7C Graph 403 shows the gate of switch S3. Figure 7D Graph 704 shows the gate of switch S4. Figure 7E Graph 705 shows the current through capacitor C1 and primary inductor Lp. Figure 7FThe curve 706 shows the voltage across the secondary inductor Ls. Figure 7G Graph 707 shows the current flowing through capacitor C2, inductor Lc, and secondary inductor Ls. Figure 7H The curve 708 shows the voltage of capacitor C3. Figure 7I The curve 709 shows the voltage of capacitor C4. Figure 7J The curve 710 shows the voltage of capacitor C5. Figure 7K The curve 711 shows the output voltage Cout.

[0051] As shown, switches S1 and S3 can share the same gate signal. Switches S2 and S4 can also share the same gate signal. Furthermore, in the illustrated example, the switching frequency of S1-S4 is 1 MHz, which means t3-t1 = 1 / 1 MHz (megahertz) = 1 μs (microsecond). The switching pattern between t1 and t3 can be continuously repeated during use. The switching cycle can have a first portion of approximately 0.9 μs from t1 to t2 and a second portion of approximately 0.1 μs from t2 to t3.

[0052] The values ​​of capacitors C1, C2, and C3, as well as inductors Lp, Ls, and Lc, can be chosen to make the current and voltage in the circuit follow the resonant frequency. Figure 7 shows a resonant frequency of 1 MHz as an example. However, any other suitable resonant frequency can be configured. It can be seen that the currents through capacitors C1 and C2, and inductors Lp and Ls, are sinusoidal. Furthermore, in the example shown, the voltages across these components are also sinusoidal. This sinusoidal shape indicates that the circuit is successfully operating in a resonant manner.

[0053] As mentioned above, Figure 3 and Figure 4 A dual-chip solution is shown. The primary-side inductor L of the transformer... p and the secondary side inductor L of the transformer s A coreless transformer is formed. Switches S1-S4 can be implemented as, for example, Si MOSFETs, SiC MOSFETs, or GaN. Such components can support high-frequency switching speeds, such as 500 kHz. Peak detector 402 can be used to detect the current flowing through the primary-side inductor L. p The peak current. Resistance R C1 Used to set the control reference for the current controller. R C1 The controller 401 is connected to ground via its resistor. Meanwhile, resistor R... C and capacitor C C It can be used to form a typical proportional-integral (PI) controller to control the flow through the primary-side inductor L. p The current. In addition, the input capacitor CIN and output capacitor C OUT It can be used to form typical input and output capacitors.

[0054] Figure 3 and Figure 4 The illustrated implementation includes two chips: a primary-side chip 301 that receives an input voltage Vin for power supply and performs current control; and a secondary-side chip 302 that receives induced energy from the primary-side chip 301 and is configured to transfer energy from the input side to establish an output voltage Vout.

[0055] Throughout the attached diagram, d represents the primary-side inductor L. p and secondary side inductor L s The distance between them. This distance d can be correlated with the control parameter (R). C R C1 C C Together, they can be flexibly adjusted to configure the output voltage (V). OUT )quality.

[0056] Figure 5 The implementation of a single chip 501 in a single package 502 is shown. Figure 6 It shows Figure 5 Electrical diagram of a single-chip implementation. Chip 501 includes a primary inductor L. p and secondary side inductor L s Both. Therefore, the primary inductor L p and secondary side inductor L s The distance between them is fixed. The electrical diagram can also be the same as the one shown and described for a two-chip solution. For example... Figure 5 As shown, the pseudo capacitor C PS It is generated internally within the single-chip 501. Otherwise, the connecting component C IN R C R C1 C C and C OUT It can be similar to the implementation described above for dual-chip implementations.

[0057] like Figure 6 As shown, the circuit implemented with a single chip includes the transformer primary-side inductor L. p and transformer secondary side inductor L s These inductors, Lp and Ls, form a coreless transformer, and it is implemented within a single chip. With the help of packaging materials, the distance d between the primary-side inductor Lp and the secondary-side inductor Ls can be minimized as much as possible (or as little as possible what is required for the desired quality). Figure 3 and Figure 4Compared to the dual-chip implementation shown, this provides a more integrated and compact implementation. All other functions and components are identical for both implementations. Therefore, the electronic circuitry and components of both the primary chip 301 and the secondary chip 302 can be integrated into a single chip 501.

[0058] Chip 501 may have a chip package 502. Chip 501 may be packaged in package 502. Package 502 may be molded or manufactured in any other suitable manner. Package 502 may have pins 503 extending therefrom for external connections to circuitry within chip 501. For example, these pins 503 may be soldered onto a PCB.

[0059] Instead of welding, other fixing methods can be considered. For example, Figure 6 The components of the chip 501 shown may be, for example, partially separate components included in a package 502.

[0060] It should be understood that the inductor described herein can be implemented as, for example, a coil.

[0061] generally, Figures 3 to 6 The two embodiments shown illustrate various aspects of a power supply device, which can be implemented in a single-chip or dual-chip manner. Generally, the power supply device includes a secondary inductor Ls configured to form a transformer with the primary inductor Lp, wherein the first terminal of the secondary inductor is electrically connected to the second terminal of the secondary inductor via a second capacitor C2, an inductor Lc, and a third capacitor C3 connected in series. The two terminals of the third capacitor C3 are electrically connected to corresponding output terminals to provide an output voltage Vout. The two terminals of the third capacitor C3 may be electrically connected to the corresponding output terminals via an electronic network including multiple diodes D1, D2 and multiple additional capacitors C4, C5, Cout.

[0062] As shown in the figure, the electronic network of power supply devices 300 and 501 may include: a first diode D1 having a first terminal and a second terminal; a second diode D2 having a first terminal and a second terminal; a fourth capacitor C4 having a first terminal and a second terminal; and a fifth capacitor C5 having a first terminal and a second terminal.

[0063] The first terminal of the first diode D1 can be connected in parallel to the first terminal of the third capacitor C3 and the second terminal of the second diode D2. The second terminal of the first diode D1 can be connected in parallel to the corresponding output terminals of the first terminals of the fourth capacitor C4 and the third capacitor C3. The second terminal of the third capacitor C3 can be connected in parallel to the second terminals of the fourth capacitor C4 and the fifth capacitor C5. The first terminal of the second diode D2 can be connected in parallel to the first terminal of the fifth capacitor C5 and the corresponding output terminal of the third capacitor C3.

[0064] The two terminals of the primary inductor Lp can be electrically connected to the corresponding input terminals to receive the input voltage Vin. At least one of the two terminals of the primary inductor Lp can be electrically connected to its corresponding input terminal via capacitor C1. The two terminals of the primary inductor Lp can be electrically connected to the corresponding input terminals via a network of switches S1, S2, S3, and S4.

[0065] The secondary inductor Ls can be integrated into chip 302, which does not include the primary inductor Lp, such as... Figure 3 and Figure 4 As illustrated in the diagram, the primary inductor Lp can be included in another separate chip 301. Chips 301 and 302 can be connected to electronic circuitry, for example, mounted on a printed circuit board. In this case, chips 301 and 302 can be fixed relative to each other such that the primary inductor Lp of the first chip 301 faces the secondary inductor Ls of the second chip 302. This allows a distance d to be configured between the primary inductor Lp and the secondary inductor Ls.

[0066] Or, such as Figure 5 and Figure 6 As shown, the primary inductor Lp and the secondary inductor Ls can be integrated into a single chip.

[0067] In any case, the primary and secondary inductors can be coreless transformer inductors, especially coreless coils.

[0068] The distance between Lp and Ls affects the pseudo-capacitance. The greater the distance between Lp and Ls, the smaller the pseudo-capacitance. In a dual-package configuration, the distance can be increased to reduce the pseudo-capacitance.

[0069] Both dual-chip and single-chip implementations have advantages, such as the small pseudo-capacitance C between the primary inductor Lp and the secondary inductor Ls. PS Value. For example, if implemented using a single chip, C can be implemented. PS < 1.5 pF. A dual-chip implementation can provide the possibility of further reducing pseudo-capacitance, for example, C PS < 0.5 pF.

[0070] exist Figure 8 In the graph, curve I shows Figure 5 and Figure 6 The performance of the dual-chip implementation is shown in curve II. Figure 3 and Figure 4 The performance of the single-chip implementation. Specifically, Figure 8 The pseudo-capacitance value C in pF is shown as a function of distance d in mm. PS The result obtained indicates that this value is lower than that in other solutions.

[0071] Figure 9 The common-mode current I in pA is shown as a function of the switching speed dV / dt in kV / μs. CM The result obtained indicates that this value is lower than that in other solutions.

[0072] Figure 10 An example is shown of the results obtained for a given input voltage shape Vin, with the output voltage behavior Vout (on the vertical axis) over time in seconds (on the horizontal axis). It demonstrates that the output voltage remains constant regardless of how the input voltage changes.

[0073] The techniques disclosed in this paper can help solve at least some of the problems of traditional isolated power supplies. For example, C PS It can be reduced to less than 1.5 pF (picofarad) without affecting the power supply size. CM The voltage can be reduced to less than 0.5 pA without affecting the power supply size. This circuit can be designed to support broadband switching applications with dv / dt values ​​up to, for example, 300 kV / μs. Furthermore, stable output voltage control can be achieved over a wide input voltage range even without a feedback loop from the high-voltage side.

[0074] While this disclosure has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes can be made and elements can be substituted with equivalents without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of this disclosure without departing from its essential scope. Therefore, it is intended that this disclosure be limited to the specific embodiments disclosed, but rather that it encompass all embodiments falling within the scope of the appended claims.

Claims

1. A power supply device, comprising: The secondary inductor (Ls) is configured to form a transformer with the primary inductor (Lp). The first terminal of the secondary inductor is electrically connected to the second terminal of the secondary inductor via a second capacitor (C2), an inductor (Lc), and a third capacitor (C3) connected in series. The two terminals of the third capacitor (C3) are electrically connected to the corresponding output terminals to provide the output voltage (Vout).

2. The power supply device according to claim 1, wherein, The two terminals of the third capacitor (C3) are electrically connected to the corresponding output terminals via an electronic network comprising multiple diodes (D1, D2) and multiple additional capacitors (C4, C5, Cout).

3. The power supply device according to claim 2, wherein, The electronic network includes: A first diode (D1) having a first terminal and a second terminal; A second diode (D2) having a first terminal and a second terminal; A fourth capacitor (C4) having a first terminal and a second terminal; and A fifth capacitor (C5) having a first terminal and a second terminal. The first terminal of the first diode (D1) is connected in parallel to the first terminal of the third capacitor (C3) and the second terminal of the second diode (D2). The second terminal of the first diode (D1) is connected in parallel to the corresponding output terminals of the first terminal of the fourth capacitor (C4) and the first terminal of the third capacitor (C3), and The second terminal of the third capacitor (C3) is connected in parallel to the second terminal of the fourth capacitor (C4) and the second terminal of the fifth capacitor (C5), and The first terminal of the second diode (D2) is electrically connected to the first terminal of the fifth capacitor (C5) and the corresponding output terminal of the third capacitor (C3).

4. The power supply device according to claim 1, further comprising the primary inductor (Lp). The two terminals of the primary inductor (Lp) are electrically connected to the corresponding input terminals to receive the input voltage (Vin).

5. The power supply device according to claim 4, wherein at least one of the two terminals of the primary inductor (Lp) is electrically connected to its respective input terminal via a capacitor (C1).

6. The power supply device according to claim 4, wherein the two terminals of the primary inductor (Lp) are electrically connected to the respective input terminals via a network of switches (S1, S2, S3, S4).

7. The power supply device according to claim 1, wherein the secondary inductor (Ls) is integrated in a chip (302) that does not include the primary inductor (Lp).

8. The power supply device according to claim 1, It includes a printed circuit board (303), a first chip (301), and a second chip (302). The primary inductor (Lp) is implemented in the first chip (301), and the secondary inductor (Ls) is implemented in the second chip (302). in, The first chip (301) and the second chip (302) are mounted on the printed circuit board (303). The primary inductor (Lp) of the first chip (301) faces the secondary inductor (Ls) of the second chip (302).

9. The power supply device according to claim 1, wherein the primary inductor (Lp) and the secondary inductor (Ls) are integrated in a single chip (501).

10. The power supply device according to any one of the preceding claims, wherein the primary inductor (Lp) and the secondary inductor (Ls) are coreless transformer inductors.

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