Power drive chip, motor drive device and direct current asynchronous motor

Abstract

This application discloses a power drive chip, a motor drive device, and a DC asynchronous motor. Relating to the field of motor drive technology, the power drive chip includes a chip carrier, N inverter circuits, and logic circuits. The chip carrier has a power input terminal and N sets of signal output terminals, each set of output terminals being used to connect to a stator winding. The N inverter circuits are integrated on the chip carrier, with the midpoint of their bridge arms connected to the corresponding signal output terminal. The logic circuits generate N modulation signals with a preset phase difference. Each modulation signal contains two alternately operating drive signals to drive the inverter circuit bridge arms. During the high-level period, the duty cycle of the drive signal changes from 0 to a peak value and then back to 0. This effectively simplifies the motor drive control.

Description

Technical Field

[0001] This application relates to the field of motor drive technology, and in particular to a power drive chip, a motor drive device, and a DC asynchronous motor. Background Technology

[0002] In the existing technology, the drive control of DC asynchronous motors, especially non-magnetic rotor motors, usually adopts a coupling architecture with star or delta connection of stator windings. This results in strong electrical coupling between each phase winding, making it difficult to achieve independent and precise adjustment of the current in each phase, thus increasing the complexity of the control algorithm. Summary of the Invention

[0003] The main objective of this application is to propose a power drive chip, a motor drive device, and a DC asynchronous motor, which aims to simplify the drive control of the motor.

[0004] To achieve the above objectives, the power drive chip proposed in this application is applied to a DC asynchronous motor, wherein the DC asynchronous motor includes a stator and a non-magnetic rotor, the stator includes a stator core and N independently arranged stator windings, where N is greater than 1; the power drive chip includes:

[0005] A chip carrier is provided with a power input terminal and N sets of signal output terminals. Each set of signal output terminals includes a first output terminal and a second output terminal. The first and second output terminals of each signal output terminal are used to connect to the two ends of a stator winding, respectively. N inverter circuits are disposed on the chip carrier. The power supply terminals of the N inverter circuits are connected to the power input terminal. Each inverter circuit has a first bridge arm and a second bridge arm. The midpoint of the first bridge arm and the midpoint of the second bridge arm of each inverter circuit are respectively connected to the first output terminal and the second output terminal of a corresponding set of signal output terminals. A logic circuit is disposed on the chip carrier. The logic circuit is connected to the power input terminal and N inverter circuits. The logic circuit is used to generate N first modulation signals. The phase difference between each adjacent pair of the N first modulation signals is preset. Each first modulation signal includes a first driving signal and a second driving signal, which are used to drive the first bridge arm and the second bridge arm of the corresponding inverter circuit, respectively. The first driving signal and the second driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the first driving signal and the second driving signal alternate. The duty cycle of the first driving signal and the second driving signal during the high-level period changes as follows: gradually rising from 0 to a preset peak value, and then gradually returning from the preset peak value to 0.

[0006] In one embodiment, the phase difference between the first and Xth of the N first modulation signals is within a preset phase difference interval, and the minimum value of the preset phase difference interval is: The maximum value of the preset phase difference interval is: The phase difference between the first and the Xth is greater than the phase difference between the first and the (X-1)th, where X is greater than 1 and not greater than N.

[0007] In one embodiment, the first bridge arm of each inverter circuit includes a first switch and a second switch, and the second bridge arm of each inverter circuit includes a third switch and a fourth switch. The first terminal of the first switch is connected to the power input terminal, the second terminal of the first switch is connected to the first terminal of the second switch, and the second terminal of the second switch is grounded. The first terminal of the third switch is connected to the power input terminal, the second terminal of the third switch is connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is grounded. The connection point between the first and second switching transistors is the midpoint of the first bridge arm, and the connection point between the third and fourth switching transistors is the midpoint of the second bridge arm. The first drive signal of each first modulation signal is used to drive the first switch of the corresponding inverter circuit, and the second drive signal of each first modulation signal is used to drive the third switch of the corresponding inverter circuit.

[0008] In one embodiment, the chip carrier is further provided with N sets of switch control terminals, each set of switch control terminals including a first control terminal and a second control terminal, the first control terminal being used to connect to a third driving signal, and the second control terminal being used to connect to a fourth driving signal; The second and fourth switching transistors are used to connect to the third and fourth driving signals respectively through the first and second control terminals of the set of switching control terminals, wherein the second switching transistor is connected to the third driving signal and the fourth switching transistor is connected to the fourth driving signal. The third driving signal and the fourth driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the third driving signal and the fourth driving signal alternate. The duty cycle of the third driving signal and the fourth driving signal during the high-level period is 1, and the duty cycle of the third driving signal and the fourth driving signal during the low-level period is 0. The high-level period of the first driving signal is synchronized with the high-level period of the fourth driving signal in terms of timing, and the high-level period of the second driving signal is synchronized with the high-level period of the third driving signal in terms of timing.

[0009] In one embodiment, the logic circuit is further configured to generate a second modulation signal, the second modulation signal including a third driving signal and a fourth driving signal; The third drive signal of each of the second modulation signals is used to drive the second switch of an inverter circuit, and the fourth drive signal of each of the second modulation signals is used to drive the fourth switch of an inverter circuit. The third driving signal and the fourth driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the third driving signal and the fourth driving signal alternate. The duty cycle of the third driving signal and the fourth driving signal during the high-level period is 1, and the duty cycle of the third driving signal and the fourth driving signal during the low-level period is 0. The high-level period of the first driving signal is synchronized with the high-level period of the fourth driving signal in terms of timing, and the high-level period of the second driving signal is synchronized with the high-level period of the third driving signal in terms of timing.

[0010] In one embodiment, the first and third switching transistors are N-type transistors, and the second and fourth switching transistors are bipolar transistors. The power drive chip further includes a pre-drive circuit disposed on the chip carrier. The pre-drive circuit includes N pre-drive modules. The input terminal of each pre-drive module is used to receive a first modulation signal. The output terminal of each pre-drive module is respectively connected to the gate of the first switch and the gate of the third switch of the corresponding inverter circuit, and is used to convert the first drive signal and the second drive signal of the received first modulation signal into corresponding first gate drive signal and second gate drive signal, so as to drive the first switch and the third switch to turn on and off respectively.

[0011] In one embodiment, the logic circuitry includes a processor, a memory, and a pulse width modulation generator; The memory stores a preset sine wave lookup table or a sine wave calculation program; The processor is configured to invoke the quasi-sine wave lookup table or execute the quasi-sine wave calculation program to determine the target duty cycle of the first drive signal and the second drive signal in each working cycle. The pulse width modulation generator is used to generate N first modulation signals according to the target duty cycle output by the processor.

[0012] In one embodiment, the logic circuit includes a modulation wave generation analog circuit and a pulse width modulation generator; The modulation wave generation simulation circuit is used to generate a simulated sinusoidal modulation wave, and the amplitude change of the simulated sinusoidal modulation wave corresponds to the duty cycle change of the first driving signal and the second driving signal. The pulse width modulation generator is connected to the modulation wave generation analog circuit, and is used to receive the analog sinusoidal modulation wave and convert the instantaneous amplitude of the analog sinusoidal modulation wave into a switching signal with a corresponding pulse width to generate N first modulation signals.

[0013] In one embodiment, the power drive chip further includes: A rectifier circuit is disposed on the chip carrier. The input terminal of the rectifier circuit is connected to the power input terminal. The rectifier circuit is used to convert the external AC power input through the power input terminal into a first DC power. The output terminal of the rectifier circuit is connected to N inverter circuits to output the first DC power to the N inverter circuits. A conversion circuit is disposed on the chip carrier. The input terminal of the conversion circuit is connected to the output terminal of the rectifier circuit, and the output terminal of the conversion circuit is connected to the logic circuit. The conversion circuit is used to step down the first DC power supply output by the rectifier circuit and convert it into a second DC power supply, and then output it to the logic circuit.

[0014] In one embodiment, the chip carrier is further provided with a signal acquisition terminal, which is used to receive an acquisition signal, and the acquisition signal is the working signal of the target load connected to N groups of first signal output terminals; The logic circuit is connected to the signal acquisition terminal, and the logic circuit is also used to adjust the duty cycle of the N first modulation signals according to the received working signal.

[0015] This application also provides a motor drive device, which includes the power drive chip as described above.

[0016] This application also provides a DC asynchronous motor, the DC asynchronous motor comprising: Non-magnetic rotor; The stator includes a stator core and N independently configured stator windings, where N is greater than 1; The motor drive device described above.

[0017] In one embodiment, the non-magnetic rotor includes a rotor core and a conductor disposed on the rotor core; The conductor includes a conductive bar embedded in the rotor core, or a conductive coil wound around the rotor core.

[0018] In summary, the power drive chip, motor drive device, and DC asynchronous motor provided in this application generate N first modulation signals and control their phase difference and duty cycle changes to achieve independent driving of N inverter circuits, so that the N inverter circuits output corresponding N alternating voltages to drive the DC asynchronous motor. This has the beneficial effects of realizing independent adjustment of the current of each phase, reducing electrical coupling effects, simplifying the control algorithm, and making motor control simpler. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a first embodiment of the power drive chip provided in this application; Figure 2 A schematic diagram of a second embodiment of the power drive chip provided in this application; Figure 3 A schematic diagram of a third embodiment of the power drive chip provided in this application; Figure 4 This is a waveform diagram of an embodiment of the first modulation signal in this application; Figure 5 This is a waveform diagram of an embodiment of the second modulation signal in this application; Figure 6 A waveform diagram of an embodiment of the output voltage of the inverter circuit provided in this application; Figure 7 A waveform diagram of another embodiment of the inverter circuit output voltage provided in this application; Figure 8 Waveform diagram of an embodiment of the inverter circuit provided in this application; Figure 9 This is a structural diagram of an embodiment of the DC asynchronous motor provided in this application.

[0021] Explanation of icon numbers: 10. Power drive chip; 100. Chip carrier; 200. Inverter circuit; 300. Logic circuit; 400. Stator winding; 510. Rectifier circuit; 520. Conversion circuit.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0024] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0025] In existing technologies, the stator windings of DC asynchronous motors generally adopt a star (Y-type) or delta connection architecture. This results in inherent physical coupling between the three-phase windings in the electrical circuit. For example, in a star connection, the sum of the three-phase currents is constrained by Kirchhoff's laws to be zero, meaning that adjusting the current in any one phase will inevitably cause a coordinated change in the currents of the other phases. This strong electrical coupling between the phase windings means that the control system cannot directly and independently adjust the current or voltage of a single phase. This leads to the motor drive system exhibiting complex characteristics of multivariables, strong coupling, and nonlinearity, complicating the motor's drive control.

[0026] To simplify motor drive control, this application provides a power drive chip. In one embodiment, the power drive chip includes a chip carrier, N inverter circuits, and logic circuits.

[0027] Optionally, the power drive chip 10 is applied to a DC asynchronous motor, which includes a stator and a non-magnetic rotor. The stator includes a stator core and N independently configured stator windings, where N is greater than 1.

[0028] This DC asynchronous motor breaks the traditional separation between the motor and driver, achieving an integrated design of drive control and electromechanical energy conversion. Regarding the stator structure, the stator core is embedded with N independently configured stator windings 400. Unlike traditional motor windings that use star or delta connections, the N stator windings 400 in this application are electrically isolated from each other, do not share a common ground, and have no common neutral point. This motor integrates the aforementioned motor drive device, establishing a one-to-one direct drive connection between its internal N inverter circuits 200 and these N independent windings, thereby constructing a multi-parallel independent drive architecture. Figure 9 As shown, the N stator windings 400 wound on the stator core of the DC asynchronous motor are electrically completely independent, meaning there is no common neutral point connection or end-to-end loop between the windings. Correspondingly, the power drive chip 10 is equipped with N independent inverter circuits 200. In terms of connection, a one-to-one direct drive method is adopted: the two output terminals of the first inverter circuit 200 (i.e., the midpoints of the first and second bridge arms) are connected to the two ends of the first stator winding 400, and so on, with the two output terminals of the Nth inverter circuit 200 connected to the two ends of the Nth stator winding 400. Regarding the rotor structure, the non-magnetic rotor does not contain rare-earth permanent magnets or DC excitation windings, but rather a salient pole structure or squirrel-cage structure made of high-permeability soft magnetic materials (such as laminated silicon steel sheets). This non-magnetic rotor does not possess a constant magnetic polarity.

[0029] In this embodiment, as Figure 1As shown, the chip carrier 100 is provided with a power input terminal and N sets of signal output terminals. Each set of signal output terminals includes a first output terminal and a second output terminal. The first and second output terminals of each signal output terminal are respectively connected to the two ends of a stator winding. N inverter circuits 200 are disposed on the chip carrier 100. The power supply terminals of the N inverter circuits 200 are connected to the power input terminal. Each inverter circuit 200 has a first bridge arm and a second bridge arm. The midpoint of the first bridge arm and the midpoint of the second bridge arm of each inverter circuit 200 are respectively connected to the first and second output terminals of the corresponding set of signal output terminals. A logic circuit 300 is disposed on the chip carrier 100. The logic circuit 300 is connected to the power input terminal and N inverter circuits 200. It is used to generate N first modulation signals. The phase difference between each adjacent pair of the N first modulation signals is a preset phase difference. Each first modulation signal includes a first driving signal and a second driving signal, which are used to drive the first bridge arm and the second bridge arm of the corresponding inverter circuit 200, respectively. The first driving signal and the second driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the first driving signal and the second driving signal alternate. The duty cycle of the first driving signal and the second driving signal during the high-level period changes from 0 to a preset peak value and then from the preset peak value back to 0.

[0030] The chip carrier 100 serves as the physical substrate of the power driver chip 10, housing the internal circuit modules. The chip carrier 100 has a power input terminal and N sets of first signal output terminals. The power input terminal is configured to receive external power, while the N sets of first signal output terminals are used to output drive signals. Each set of first signal output terminals typically includes a first output terminal and a second output terminal to transmit a pair of drive signals respectively. For example, the chip carrier 100 can be in a QFN package or an SOP package, and the aforementioned power input terminal and N sets of first signal output terminals are its pins.

[0031] In one feasible implementation, the logic circuit 300 is configured to output N sets of first modulation signals. These N sets of first modulation signals can be generated by a microcontroller with multiple pulse width modulation output channels, and the output timing and waveform of each channel can be programmed. Alternatively, multiple independent oscillators and phase-shifting circuits can be used to generate drive signals with specific phase relationships. The first modulation signals include a first drive signal and a second drive signal, both configured as high-frequency modulation signals. Each operating cycle has a high-level period (i.e., the operating period) and a low-level period (i.e., the cutoff period). The first and second drive signals operate alternately in timing; that is, when the first drive signal is high-level, the second drive signal is low-level, and vice versa. During the high-level period, the duty cycle of the first and second drive signals exhibits a pattern of gradually increasing from zero to a preset peak value, and then gradually decreasing back to zero. Here, the frequency of duty cycle changes is not limited and can be adjusted according to actual accuracy requirements. For example, the first and second drive signals can contain 256 discrete duty cycle changes, or 1024, or any other number of modulations during a high-level period. Of course, the preset peak value is also not limited here; it depends on the rated voltage or power requirements of the target load. Alternatively, the amplitude of the first and second drive signals may be 0 during the low-level period. It should be noted that a working cycle is defined as the time length for the first or second drive signal to complete one full electrical cycle, which includes a high-level period and a low-level period in timing.

[0032] The inverter circuit 200 converts the power received from the power input terminal into an alternating voltage. The inverter circuit 200 can be constructed from a bridge structure composed of switching transistors, such as an H-bridge full-bridge topology composed of four power switching devices, such as MOSFETs, IGBTs and transistors.

[0033] In the N inverter circuits 200, each inverter circuit 200 includes a first bridge arm and a second bridge arm. Each inverter circuit 200 is configured to receive a set of first modulation signals. Specifically, the first bridge arm is controlled by a first drive signal, and the second bridge arm is controlled by a second drive signal. Since the first drive signal and the second drive signal are distributed alternately in time, the first bridge arm and the second bridge arm alternately perform high-frequency chopping or conduction under the action of the first drive signal and the second drive signal. This action causes the potential difference between the midpoint of the first bridge arm and the midpoint of the second bridge arm to undergo periodic polarity reversal, thereby outputting a sinusoidal alternating voltage at the output terminal, which has a complete positive half-cycle and a negative half-cycle. Furthermore, since a precise preset phase difference is set between the first modulation signals input to the N inverter circuits 200, the N alternating voltages output by the N inverter circuits 200 also strictly maintain the corresponding phase relationship. When these N voltages are applied to N spatially independent stator windings, the magnetic fields generated by each winding are superimposed in the air gap to form a rotating magnetic field with constant amplitude, which efficiently drives the poleless rotor to rotate.

[0034] It is understood that in some embodiments, the first and second bridge arms also need to be connected to a third and a fourth driving signal to drive the switching transistors other than those driven by the first and second driving signals, so as to realize the power frequency commutation logic.

[0035] It is understandable that this power driver chip 10 has a highly integrated signal generation capability. After receiving external power through the power input terminal, its internal logic circuit 300 can directly generate and output N sets of first modulation signals through N sets of first signal output terminals. N inverter circuits 200 receive N sets of first modulation signals to output N independent alternating voltages, each of which can be applied to an independent stator winding. In this way, the ease of use and integration of the system are improved, realizing a "single-chip drive" solution. That is, users do not need to configure complex external controllers; they only need to use this power driver chip 10 to directly obtain power for driving DC asynchronous motors while completing power acquisition, thereby greatly simplifying the peripheral circuit design.

[0036] like Figure 1 As shown, the first output terminal a and the second output terminal a form a set of first signal output terminals, and the first output terminal b and the second output terminal b form another set of first signal output terminals, used to output two alternating voltages respectively. The first drive signal a and the second drive signal a form a set of first modulation signals, and the first drive signal b and the second drive signal b form another set of first modulation signals.

[0037] Optionally, the voltage value corresponding to each group of first modulation signals can be 12V, 24V, 42V, or even higher values ​​such as 310V and 400V. The specific value depends on the actual application scenario and is not limited here.

[0038] In summary, the power drive chip 10, motor drive device, and DC asynchronous motor provided in this application generate N first modulation signals and control their phase difference and duty cycle changes to achieve independent driving of N inverter circuits 200, so that the N inverter circuits 200 output corresponding N alternating voltages to drive the DC asynchronous motor. This has the beneficial effects of realizing independent adjustment of the current of each phase, reducing electrical coupling effects, simplifying the control algorithm, and making motor control simpler.

[0039] In one embodiment, such as Figure 4 As shown, the phase difference between the first and Xth of the N first modulation signals takes values ​​within a preset phase difference interval, and the minimum value of the preset phase difference interval is: The maximum value of the preset phase difference interval is: The phase difference between the first and the Xth is greater than the phase difference between the first and the (X-1)th, where X is greater than 1 and not greater than N.

[0040] For example, assuming N is 3, when X=2, that is, the phase difference between the first and second first modulation signals: Its minimum value is: Spend; Its maximum value is: Spend; That is, the phase difference interval between the second and the first is... Within this range, as a preferred implementation, a second lag of 60 degrees can be set after the first.

[0041] When X=3, that is, calculate the phase difference between the first and third first modulation signals: Its minimum value is: Spend; Its maximum value is: Spend; That is, the phase difference interval between the third and the first is... Within this range, as a preferred implementation, a third lag of 120 degrees can be set.

[0042] By analogy, the orderly distribution of each first modulation signal within a preset range is achieved.

[0043] like Figure 4 As shown, Figure 4The first driving signal a and the second driving signal a in the first modulation signal group labeled "a", and the first driving signal b and the second driving signal b in the first modulation signal group labeled "b" appear alternately in time, and there is a 90-degree phase difference between the two groups of first modulation signals (that is, "first driving signal b" lags behind "first driving signal a" by 1 / 4 cycle), which are used to generate alternating voltages of phase A and phase B, respectively.

[0044] In one embodiment, such as Figure 8 As shown, the first bridge arm of each inverter circuit 200 includes a first switch Q1 and a second switch Q2, and the second bridge arm of each inverter circuit 200 includes a third switch Q3 and a fourth switch Q4. The first end of the first switch Q1 is connected to the power input terminal, the second end of the first switch Q1 is connected to the first end of the second switch Q2, and the second end of the second switch Q2 is grounded. The first end of the third switch Q3 is connected to the power input terminal, the second end of the third switch Q3 is connected to the first end of the fourth switch Q4, and the second end of the fourth switch Q4 is grounded. The connection point between the first switch Q1 and the second switch Q2 is the midpoint of the first bridge arm, and the connection point between the third switch Q3 and the fourth switch Q4 is the midpoint of the second bridge arm. The first driving signal of each first modulation signal is used to drive the first switch Q1 of the corresponding inverter circuit 200, and the second driving signal of each first modulation signal is used to drive the third switch Q3 of the corresponding inverter circuit 200.

[0045] In this embodiment, the inverter circuit 200 consists of two parallel half-bridge arms. The first switch Q1 (upper switch) and the second switch Q2 (lower switch) are connected in series to form the first bridge arm, and the third switch Q3 (upper switch) and the fourth switch Q4 (lower switch) are connected in series to form the second bridge arm. The upper ends of both bridge arms are connected to the power input terminal to access DC high voltage, and the lower ends are grounded. The common connection point of the first switch Q1 and the second switch Q2 is defined as the midpoint of the first bridge arm, and the common connection point of the third switch Q3 and the fourth switch Q4 is defined as the midpoint of the second bridge arm. These two midpoints constitute the AC output port of the inverter circuit 200, used to connect to the target load (such as the stator winding of a motor). At the control logic level, this embodiment clearly defines the driving object of each component in the first modulation signal and adopts a "self-driving upper bridge arm" control strategy. Specifically, the first driving signal in the first modulation signal is used to drive the upper switch (first switch Q1) of the first bridge arm, while the second driving signal is used to drive the upper switch (third switch Q3) of the second bridge arm.

[0046] Of course, the lower transistor of the first bridge arm (the second switch Q2) and the lower transistor of the second bridge arm (the fourth switch Q4) are respectively acted upon by the third drive signal and the fourth drive signal. Thus, by controlling the alternating conduction of these two upper bridge arm switches at different timings (and with the assistance of the lower transistor at the diagonal position), the power supply voltage can be controlled to be applied to both ends of the load in turn, thereby causing the potential difference between the midpoint of the first bridge arm and the midpoint of the second bridge arm to undergo periodic positive and negative polarity reversals, and finally synthesizing the required sinusoidal AC voltage on the load.

[0047] In one embodiment, the chip carrier 100 is further provided with N sets of switch control terminals. Each set of switch control terminals includes a first control terminal and a second control terminal. The first control terminal is used to connect to a third driving signal, and the second control terminal is used to connect to a fourth driving signal. The second switch Q2 and the fourth switch Q4 are connected to the third driving signal and the fourth driving signal respectively through the first control terminal and the second control terminal of the set of switch control terminals. The second switch Q2 is connected to the third driving signal, and the fourth switch Q4 is connected to the fourth driving signal. The third driving signal and the fourth driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the third driving signal and the fourth driving signal alternate. The duty cycle of the third driving signal and the fourth driving signal during the high-level period is 1, and the duty cycle of the third driving signal and the fourth driving signal during the low-level period is 0. The high-level period of the first driving signal is synchronized with the high-level period of the fourth driving signal, and the high-level period of the second driving signal is synchronized with the high-level period of the third driving signal.

[0048] In this embodiment, the corresponding third and fourth drive signals are generated by external circuitry. This means the logic circuit 300 only needs to output the first and second drive signals and can connect the received third and fourth drive signals to the corresponding bridge arm switches. This forms a collaborative drive architecture of "internal high-frequency modulation + external power frequency commutation." Thus, while reducing the chip's computing power burden, it retains the ability of the external system to directly intervene in the motor commutation logic.

[0049] The first control terminal and the second control terminal are pins.

[0050] In one embodiment, such as Figure 2As shown, the logic circuit 300 is further used to generate a second modulation signal, which includes a third driving signal and a fourth driving signal; the third driving signal of each second modulation signal is used to drive a second switch Q2 of an inverter circuit 200, and the fourth driving signal of each second modulation signal is used to drive a fourth switch Q4 of an inverter circuit 200; the third driving signal and the fourth driving signal have a high-level period and a low-level period in each working cycle, the high-level periods of the third driving signal and the fourth driving signal alternate, the duty cycle of the third driving signal and the fourth driving signal during the high-level period is 1, and the duty cycle of the third driving signal and the fourth driving signal during the low-level period is 0; wherein, the high-level period of the first driving signal is synchronized with the high-level period of the fourth driving signal in timing, and the high-level period of the second driving signal is synchronized with the high-level period of the third driving signal in timing.

[0051] In this embodiment, the logic circuit 300 can also directly generate a second modulation signal, which includes a third drive signal and a fourth drive signal. This eliminates the need for external signals; the power drive chip 10 can output the alternating voltage for driving the motor, thus achieving a fully integrated "single-chip full-bridge drive" solution. In this mode, the internal logic circuit 300 manages the switching timing of all bridge arms, ensuring strict clock synchronization between the high-frequency chopping signal (first / second drive signal) and the power frequency commutation signal (fourth / third drive signal), effectively eliminating drive logic confusion caused by external signal transmission delays. This not only greatly simplifies the peripheral circuit design and reduces the number of components but also ensures a smoother and more accurate voltage waveform output to the motor stator windings, improving the overall reliability of the drive system.

[0052] Figure 5 The middle section displays either the third or fourth drive signal, which is a square-wave normally-on signal. It can be understood that the third and fourth drive signals maintain a continuous high level (i.e., a 100% duty cycle) during the high-level period to drive the corresponding switch to remain on, forming a complete current loop with the high-frequency switch on the diagonal. During the low-level period, they maintain a continuous zero level (i.e., logic low) to control the corresponding switch to be completely off. The third and fourth drive signals are mutually exclusive in timing, such as... Figure 2 As shown, during the period when the first driving signal is at a high level (corresponding to the positive half-cycle), the fourth driving signal is at a high level, while the third driving signal is at a low level; conversely, during the period when the second driving signal is at a high level (corresponding to the negative half-cycle), the third driving signal flips to a high level, while the fourth driving signal flips to a low level.

[0053] N inverter circuits 200 are used to convert the input DC power supply into N independent alternating voltages according to N sets of power drive signals. It is understood that during the high-level period of the first drive signal, the diagonally opposite fourth drive signal remains at a constant high level (duty cycle of 1), the first switch Q1 and the fourth switch Q4 are turned on, and current flows from the power input terminal through the first switch Q1 into the load and back to ground through the fourth switch Q4, making the midpoint voltage of the first bridge arm higher than the midpoint voltage of the second bridge arm, forming a positive output voltage. Similarly, during the high-level period of the second drive signal, the diagonally opposite third drive signal remains at a constant high level, the third switch Q3 and the second switch Q2 are turned on, and current flows from the power input terminal through the third switch Q3 into the load and back to ground through the second switch Q2, making the midpoint voltage of the second bridge arm higher than the midpoint voltage of the first bridge arm, forming a reverse output voltage. Thus, through the above hybrid driving strategy, the potential difference between the midpoints of the two bridge arms periodically reverses polarity with time, thereby achieving precise generation and modulation of the AC output waveform (i.e., alternating voltage).

[0054] like Figure 6 and Figure 7 As shown, the timing diagrams of the voltage waveforms output by the inverter circuit 200 after the first and second modulation signals output by the power driver chip 10 under different driving configurations are sent to the inverter circuit 200 are presented intuitively. Figure 6 For applications with N=2 (i.e., two-phase drive), it can be seen that "A-path alternating voltage" and "B-path alternating voltage" are two independent paths with a specific phase difference (e.g., 90 degrees, reflected in...). The sequentially lagging sinusoidal wave, the A-path alternating voltage and the B-path alternating voltage are the two voltages output by the two inverter circuits 200 respectively, and the two work together to drive the synthesis of a rotating magnetic field. Figure 7 The embodiment corresponding to N=3 (i.e., three-phase drive) demonstrates that the three alternating voltages A, B, and C output by the three inverter circuits 200 exhibit a uniform phase change relationship on the time axis (reflected in...). (The voltages are sequentially delayed), and a preset phase difference (e.g., 60 degrees) is maintained between adjacent voltages, thereby driving three independent stator windings 400 to generate a continuous and smooth rotating magnetic field. Figure 7 and Figure 8 This clearly verifies the logic of this application to independently and accurately modulate multiple alternating voltages through the timing of control signals.

[0055] Thus, after N stator windings receive N alternating voltages, alternating currents with corresponding phase differences flow through each stator winding, thereby generating pulsating magnetomotive forces. Since these N stator windings are spatially independent (e.g., at specific angles to each other on a circle), and the driving currents have corresponding precise phase differences in time, the magnetic fields generated by each winding undergo vector synthesis in the motor's air gap, constructing a stable and continuously rotating circular magnetic field. This rotating magnetic field moves relative to the poleless rotor and cuts the conductors on the rotor, inducing a current in the rotor according to the law of electromagnetic induction. This induced current further interacts with the rotating magnetic field to generate an electromagnetic force, ultimately forming an electromagnetic torque that drives the rotor to rotate, thus pulling the poleless rotor to follow the rotating magnetic field, achieving smooth and efficient driving of the DC asynchronous motor.

[0056] In one embodiment, the first switch Q1 and the third switch Q3 are N-type transistors, and the second switch Q2 and the fourth switch Q4 are bipolar transistors. The power drive chip 10 further includes a pre-drive circuit disposed on the chip carrier 100. The pre-drive circuit includes N pre-drive modules. The input terminal of each pre-drive module is used to receive a first modulation signal, and the output terminal of each pre-drive module is respectively connected to the gate of the first switch Q1 and the gate of the third switch Q3 of the corresponding inverter circuit 200. The pre-drive module is used to convert the first drive signal and the second drive signal of the received first modulation signal into corresponding first gate drive signal and second gate drive signal, so as to drive the first switch Q1 and the third switch Q3 to switch on and off respectively.

[0057] It is understandable that N-type transistors require pre-drive because their source potential fluctuates to the power supply voltage along with the output voltage when they are turned on. This causes the low-voltage signal output by logic circuit 300 to fail to provide a sufficient gate-source voltage difference to turn them on. For example, without a pre-drive module, logic circuit 300 outputs 3V to the control terminal of the switching transistor, while with a pre-drive module, it can output 12V to the control terminal of the switching transistor. Therefore, a pre-drive circuit is needed for level shifting and voltage boosting. Optionally, each pre-drive module has two independent pre-drive circuits: one receives the first drive signal, and the other receives the second drive signal, to generate corresponding first and second gate drive signals, which are then sent to the gates of the first switching transistor Q1 and the third switching transistor Q3, respectively. The two pre-drive circuits of each pre-drive module can adopt the same topology, both including a bootstrap diode, a bootstrap capacitor, and a level shifting unit. The energy storage effect of the bootstrap capacitor is used to boost the gate drive voltage to a level higher than the power supply input, thereby ensuring that the N-type transistor can reliably saturate and conduct.

[0058] In addition, since the second switch Q2 and the fourth switch Q4 are transistors with their emitters directly grounded, they are current-controlled devices with low turn-on threshold voltages (usually only requiring a base-emitter voltage Vbe of about 0.7V). Therefore, they do not require a complex floating high-voltage pre-drive circuit like the upper bridge arm.

[0059] In one embodiment, the logic circuit 300 includes a processor, a memory, and a pulse width modulation generator; the memory stores a preset sine wave lookup table or a sine wave calculation program; the processor is configured to call the sine wave lookup table or execute the sine wave calculation program to determine the target duty cycle of the first driving signal and the second driving signal in each working cycle; the pulse width modulation generator is used to generate N first modulation signals according to the target duty cycle output by the processor.

[0060] The processor can be a microcontroller (MCU), digital signal processor (DSP), or programmable logic device (FPGA), etc., and is responsible for executing instructions and processing data. In this embodiment, the processor is mainly used to calculate and determine the target duty cycle of the required first and second drive signals in each working cycle according to a preset algorithm or data. The memory can be a read-only memory (ROM), random access memory (RAM), flash memory, etc., used to store the program code and data required for processor execution. Here, the memory is used to store a preset sine wave lookup table or a sine wave calculation program. The sine wave lookup table is a set of pre-calculated duty cycle numerical sequences, which can accurately describe the duty cycle change curve of the first and second drive signals from 0 to a preset peak value and then back to 0. The sine wave calculation program is a piece of algorithm code, which the processor can use to calculate the required duty cycle value at the current moment in real time. The pulse width modulation generator is a circuit module used to generate pulse width modulation signals, which can be a PWM peripheral integrated into the processor or a separate PWM controller. Its function is to receive the target duty cycle value output by the processor and convert it into a high-frequency switching signal with a corresponding pulse width, namely N first modulation signals.

[0061] Optionally, when using a lookup-based method, the memory pre-stores, for example, 256 (or 1024, etc.) discrete duty cycle values. This value sequence corresponds to the amplitude change trajectory of a sine wave within half an electrical cycle (i.e., phase from 0 to π). The processor uses the current timing progress as an index to quickly read the corresponding values ​​from the table as the target duty cycle. This method has low computational complexity and fast response speed. When using a real-time calculation-based method, the processor uses the formula... Perform the calculation; where y is the target duty cycle at the current moment, and A is the target amplitude (i.e., the preset peak value mentioned above, also known as the modulation index). The real-time phase angle increases linearly with time. The processor updates the phase angle in each carrier cycle. It then performs trigonometric function calculations to obtain the precise target duty cycle at the current moment. This method can flexibly adjust parameters... To adjust the amplitude and frequency of the output voltage in real time.

[0062] In one embodiment, the logic circuit 300 includes a modulation wave generation analog circuit and a pulse width modulation generator; the modulation wave generation analog circuit is used to generate an analog sinusoidal modulation wave, the amplitude change of the analog sinusoidal modulation wave corresponding to the duty cycle change of the first driving signal and the second driving signal; the pulse width modulation generator is connected to the modulation wave generation analog circuit, and is used to receive the analog sinusoidal modulation wave and convert the instantaneous amplitude of the analog sinusoidal modulation wave into a switching signal with a corresponding pulse width to generate N first modulation signals.

[0063] The modulation wave generation analog circuit is designed to generate continuous analog signals. Its core function is to generate an analog sinusoidal modulated wave, the amplitude of which directly corresponds to the duty cycle changes required by the first and second drive signals. For example, when the duty cycle of the required output drive signal is 0, the amplitude of the analog sinusoidal modulated wave is also 0; when the duty cycle reaches a preset peak value, the amplitude of the analog sinusoidal modulated wave reaches its maximum value. This modulation wave generation analog circuit can be implemented using various analog circuit topologies. For example, it can be based on a low-frequency oscillator (such as a Wien bridge oscillator or a phase-shift oscillator) built with operational amplifiers, whose output is shaped and amplitude adjusted to accurately simulate a sinusoidal waveform. By adjusting the circuit parameters, the frequency and amplitude of the analog sinusoidal modulated wave can be controlled, thereby precisely controlling the working period and maximum duty cycle of the output drive signal. This analog method provides smooth and continuous waveform changes, avoiding the step effect caused by digital quantization.

[0064] The pulse width modulation (PWM) generator is a circuit that converts an analog input signal into a pulse width modulated signal. Its function is to receive an analog sinusoidal modulated wave output from a modulation wave generation analog circuit, and generate switching signals corresponding to the pulse width, i.e., N first modulation signals, based on the instantaneous amplitude of the analog waveform. Specifically, the PWM generator can include a comparator and a high-frequency carrier generator, such as a triangular wave or sawtooth wave generator. The comparator compares the instantaneous amplitude of the analog sinusoidal modulated wave with the carrier signal. When the amplitude of the analog sinusoidal modulated wave is higher than that of the carrier signal, the comparator outputs a high level; otherwise, it outputs a low level. Through this comparison, the width of the output pulse will be proportional to the instantaneous amplitude of the analog sinusoidal modulated wave, thereby achieving duty cycle modulation.

[0065] In summary, the generation of the first modulated signal can be achieved in three ways in this application. These include: first, a digital control method based on memory lookup tables; second, a digital control method based on real-time processor computation; and third, a modulation method based on purely analog circuits. The specific method used in practical applications is not limited here.

[0066] In one embodiment, such as Figure 3 As shown, the power drive chip 10 further includes a rectifier circuit 510 and a conversion circuit 520. The rectifier circuit 510 is disposed on the chip carrier 100, and its input terminal is connected to the power input terminal. The rectifier circuit 510 is used to convert the external AC power input via the power input terminal into a first DC power supply. The output terminal of the rectifier circuit 510 is connected to N inverter circuits 200 to output the first DC power supply to the N inverter circuits 200. The conversion circuit 520 is disposed on the chip carrier 100, and its input terminal is connected to the output terminal of the rectifier circuit 510. The output terminal of the conversion circuit 520 is connected to the logic circuit 300. The conversion circuit 520 is used to step down the first DC power supply output by the rectifier circuit 510 and convert it into a second DC power supply before outputting it to the logic circuit 300.

[0067] The rectifier circuit 510 converts externally supplied AC power into DC power. The input terminal of the rectifier circuit 510 is connected to the power input terminal to receive external AC power. The rectifier circuit 510 can be implemented in various ways. For example, it can be a full-bridge rectifier composed of four diodes to convert AC power into pulsating DC power; or, to improve the power factor and reduce harmonics, an active power factor correction (PFC) rectifier circuit 510 can be used, which can convert AC power into stable DC power and ensure that the input current waveform is in phase with the voltage waveform. The output terminal of the rectifier circuit 510 is then connected to the power supply terminals of N inverter circuits 200, thereby providing the first DC power required for the operation of these inverter circuits 200.

[0068] The conversion circuit 520 steps down the first DC power supply output from the rectifier circuit 510 and converts it into a second DC power supply for use by the logic circuit 300. Since the logic circuit 300 typically operates at a lower DC voltage, while the first DC power supply output from the rectifier circuit 510 may have a higher voltage, the conversion circuit 520 is needed for voltage conversion. The input terminal of the conversion circuit 520 is connected to the output terminal of the rectifier circuit 510, receiving the first DC power supply. The conversion circuit 520 can be a step-down DC-DC converter, such as a pulse-width modulation (PWM) controlled switching power supply, which converts high-voltage DC to low-voltage DC through efficient switching operations; alternatively, in scenarios where efficiency requirements are less stringent, a linear regulator (LDO) can be used. The output terminal of the conversion circuit 520 is connected to the power supply terminal of the logic circuit 300, ensuring that the logic circuit 300 receives a stable second DC power supply that meets its operating voltage requirements.

[0069] Through the above technical solution, the power drive chip 10 integrates a rectifier circuit 510 and a conversion circuit 520, enabling the power drive chip 10 to directly receive external AC power. The rectifier circuit 510 directly supplies N inverter circuits 200, and the conversion circuit 520 directly supplies the logic circuit 300, thereby simplifying the external power supply design and reducing the dependence on external rectifier modules.

[0070] In one embodiment, the chip carrier 100 is further provided with a signal acquisition terminal, which is used to receive acquisition signals, the acquisition signals being the working signals of the target load connected to N groups of first signal output terminals; the logic circuit 300 is connected to the signal acquisition terminal, and the logic circuit 300 is further used to adjust the duty cycle of the N first modulation signals according to the received working signals.

[0071] The signal acquisition terminal is one or more physical interfaces disposed on the chip carrier 100, capable of receiving real-time operating signals from external target loads. This signal acquisition terminal can be designed as an analog input port, for example, converting analog signals into digital signals via an on-chip analog-to-digital converter for processing by the logic circuit 300; or it can be designed as a digital input port to directly receive digitized operating signals.

[0072] The acquired signal is an electrical signal reflecting the current operating state of the target load connected to the first signal output terminals of N groups. The type of the acquired signal depends on the nature of the target load and the parameters to be monitored. For example, when the target load is a motor, the acquired signal can be the current signal flowing through the motor windings, the voltage signal across the motor terminals, the motor speed signal, or the position signal. These signals are usually acquired by external sensors (such as current sensors, voltage sensors, Hall sensors, encoders, etc.) and, after appropriate preprocessing, are connected to the signal acquisition terminal of the power drive chip 10.

[0073] After receiving the real-time operating signal from the signal acquisition terminal, the logic circuit 300 dynamically adjusts the duty cycle of N first modulation signals. Optionally, the logic circuit 300 can have a built-in control algorithm, such as a proportional-integral-derivative (PID) controller. The logic circuit 300 compares the acquired signal with a preset target value and calculates the required duty cycle and / or frequency adjustment based on the error between the two. Alternatively, the logic circuit 300 can also optimize the duty cycle and / or frequency of the first modulation signals in real time based on the changing trend and current state of the acquired signal using a lookup table method or a model-based predictive control method.

[0074] Optionally, when the load is a DC asynchronous motor, the DC asynchronous motor has N independent stator windings 400, and the acquired signal can be an electrical parameter sampling signal associated with each of the N windings, such as a phase current sampling signal or a terminal voltage sampling signal.

[0075] This application also provides a motor drive device, which includes the power drive chip 10 as described above.

[0076] It should be noted that since this motor drive device includes a power drive chip 10, and the power drive chip 10 adopts all the technical solutions of all the above embodiments, this motor drive device has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0077] This application also provides a DC asynchronous motor, which includes a motor drive device, a non-magnetic rotor, and a stator. The stator includes a stator core and N independently arranged stator windings, where N is greater than 1.

[0078] In one embodiment, the non-magnetic rotor includes a rotor core and a conductor disposed on the rotor core; the conductor includes a conductive bar embedded in the rotor core or a conductive coil wound on the rotor core.

[0079] The squirrel-cage structure utilizes conductive bars (such as copper or cast aluminum) embedded in the iron core slots, forming a closed loop through end rings. The wound structure uses insulated wire wound into coils around the iron core. During operation, these conductors act as carriers of induced current. When the rotating magnetic field generated by the stator cuts these closed conductive bars or coils, an induced electromotive force and induced current are generated inside the conductors according to Faraday's law of electromagnetic induction. This current is further subjected to the Ampere force (Lorentz force) in the magnetic field, thereby generating electromagnetic torque to drive the rotor to rotate. This design eliminates expensive rare-earth permanent magnets, reducing manufacturing costs, and also endows the rotor with extremely high high-temperature resistance and mechanical strength.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no technical conflict, the various technical features mentioned in the various embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A power drive chip, characterized in that, This is applied to a DC asynchronous motor, which includes a stator and a non-magnetic rotor. The stator includes a stator core and N independently configured stator windings, where N is greater than 1. The power drive chip includes: A chip carrier is provided with a power input terminal and N sets of signal output terminals. Each set of signal output terminals includes a first output terminal and a second output terminal. The first and second output terminals of each signal output terminal are used to connect to the two ends of a stator winding, respectively. N inverter circuits are disposed on the chip carrier. The power supply terminals of the N inverter circuits are connected to the power input terminal. Each inverter circuit has a first bridge arm and a second bridge arm. The midpoint of the first bridge arm and the midpoint of the second bridge arm of each inverter circuit are respectively connected to the first output terminal and the second output terminal of a corresponding set of signal output terminals. A logic circuit is disposed on the chip carrier. The logic circuit is connected to the power input terminal and N inverter circuits. The logic circuit is used to generate N first modulation signals. The phase difference between each adjacent pair of the N first modulation signals is preset. Each first modulation signal includes a first driving signal and a second driving signal, which are used to drive the first bridge arm and the second bridge arm of the corresponding inverter circuit, respectively. The first driving signal and the second driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the first driving signal and the second driving signal alternate. The duty cycle of the first driving signal and the second driving signal during the high-level period changes as follows: gradually rising from 0 to a preset peak value, and then gradually returning from the preset peak value to 0.

2. The power drive chip as described in claim 1, characterized in that, The phase difference between the first and Xth of the N first modulation signals takes values ​​within a preset phase difference interval, where the minimum value of the preset phase difference interval is: The maximum value of the preset phase difference interval is: The phase difference between the first and the Xth is greater than the phase difference between the first and the (X-1)th, where X is greater than 1 and not greater than N.

3. The power drive chip as described in claim 2, characterized in that, Each inverter circuit's first bridge arm includes a first switch and a second switch, and each inverter circuit's second bridge arm includes a third switch and a fourth switch. The first terminal of the first switch is connected to the power input terminal, the second terminal of the first switch is connected to the first terminal of the second switch, and the second terminal of the second switch is grounded. The first terminal of the third switch is connected to the power input terminal, the second terminal of the third switch is connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is grounded. The connection point between the first and second switching transistors is the midpoint of the first bridge arm, and the connection point between the third and fourth switching transistors is the midpoint of the second bridge arm. The first drive signal of each first modulation signal is used to drive the first switch of the corresponding inverter circuit, and the second drive signal of each first modulation signal is used to drive the third switch of the corresponding inverter circuit.

4. The power drive chip as described in claim 3, characterized in that, The chip carrier is also provided with N sets of switch control terminals. Each set of switch control terminals includes a first control terminal and a second control terminal. The first control terminal is used to connect to a third driving signal, and the second control terminal is used to connect to a fourth driving signal. The second and fourth switching transistors are used to connect to the third and fourth driving signals respectively through the first and second control terminals of the set of switching control terminals, wherein the second switching transistor is connected to the third driving signal and the fourth switching transistor is connected to the fourth driving signal. The third driving signal and the fourth driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the third driving signal and the fourth driving signal alternate. The duty cycle of the third driving signal and the fourth driving signal during the high-level period is 1, and the duty cycle of the third driving signal and the fourth driving signal during the low-level period is 0. The high-level period of the first driving signal is synchronized with the high-level period of the fourth driving signal in terms of timing, and the high-level period of the second driving signal is synchronized with the high-level period of the third driving signal in terms of timing.

5. The power drive chip as described in claim 3, characterized in that, The logic circuit is also used to generate a second modulation signal, the second modulation signal including a third driving signal and a fourth driving signal; The third drive signal of each of the second modulation signals is used to drive the second switch of an inverter circuit, and the fourth drive signal of each of the second modulation signals is used to drive the fourth switch of an inverter circuit. The third driving signal and the fourth driving signal have a high-level period and a low-level period in each working cycle. The high-level periods of the third driving signal and the fourth driving signal alternate. The duty cycle of the third driving signal and the fourth driving signal during the high-level period is 1, and the duty cycle of the third driving signal and the fourth driving signal during the low-level period is 0. The high-level period of the first driving signal is synchronized with the high-level period of the fourth driving signal in terms of timing, and the high-level period of the second driving signal is synchronized with the high-level period of the third driving signal in terms of timing.

6. The power drive chip according to any one of claims 3 to 5, characterized in that, The first and third switching transistors are N-type transistors, and the second and fourth switching transistors are triodes. The power drive chip further includes a pre-drive circuit disposed on the chip carrier. The pre-drive circuit includes N pre-drive modules. The input terminal of each pre-drive module is used to receive a first modulation signal. The output terminal of each pre-drive module is respectively connected to the gate of the first switch and the gate of the third switch of the corresponding inverter circuit, and is used to convert the first drive signal and the second drive signal of the received first modulation signal into corresponding first gate drive signal and second gate drive signal, so as to drive the first switch and the third switch to turn on and off respectively.

7. The power drive chip as described in claim 1, characterized in that, The logic circuit includes a processor, a memory, and a pulse width modulation generator; The memory stores a preset sine wave lookup table or a sine wave calculation program; The processor is configured to invoke the quasi-sine wave lookup table or execute the quasi-sine wave calculation program to determine the target duty cycle of the first drive signal and the second drive signal in each working cycle. The pulse width modulation generator is used to generate N first modulation signals according to the target duty cycle output by the processor.

8. The power drive chip as described in claim 1, characterized in that, The logic circuit includes a modulation wave generation analog circuit and a pulse width modulation generator; The modulation wave generation simulation circuit is used to generate a simulated sinusoidal modulation wave, and the amplitude change of the simulated sinusoidal modulation wave corresponds to the duty cycle change of the first driving signal and the second driving signal. The pulse width modulation generator is connected to the modulation wave generation analog circuit, and is used to receive the analog sinusoidal modulation wave and convert the instantaneous amplitude of the analog sinusoidal modulation wave into a switching signal with a corresponding pulse width to generate N first modulation signals.

9. The power drive chip as described in claim 1, characterized in that, The power drive chip also includes: A rectifier circuit is disposed on the chip carrier. The input terminal of the rectifier circuit is connected to the power input terminal. The rectifier circuit is used to convert the external AC power input through the power input terminal into a first DC power. The output terminal of the rectifier circuit is connected to N inverter circuits to output the first DC power to the N inverter circuits. A conversion circuit is disposed on the chip carrier. The input terminal of the conversion circuit is connected to the output terminal of the rectifier circuit, and the output terminal of the conversion circuit is connected to the logic circuit. The conversion circuit is used to step down the first DC power supply output by the rectifier circuit and convert it into a second DC power supply, and then output it to the logic circuit.

10. The power drive chip as described in claim 1, characterized in that, The chip carrier is also provided with a signal acquisition terminal, which is used to receive acquisition signals. The acquisition signals are the working signals of the target load connected to the N groups of first signal output terminals. The logic circuit is connected to the signal acquisition terminal, and the logic circuit is also used to adjust the duty cycle of the N first modulation signals according to the received working signal.

11. A motor drive device, characterized in that, The motor drive device includes the power drive chip as described in any one of claims 1 to 10.

12. A DC asynchronous motor, characterized in that, The DC asynchronous motor includes: Non-magnetic rotor; The stator includes a stator core and N independently configured stator windings, where N is greater than 1; The motor drive device as described in claim 11.

13. The DC asynchronous motor as described in claim 12, characterized in that, The non-magnetic rotor includes a rotor core and a conductive body disposed on the rotor core; The conductor includes a conductive bar embedded in the rotor core, or a conductive coil wound around the rotor core.

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