Transient enhanced class-ab buffer circuit, control method, electronic device, and storage medium
By designing a transient enhancement-type Class-AB buffer circuit, differential voltage conversion and gate static bias are used to suppress channel length modulation effect and capture output voltage changes. This solves the problem of insufficient transient response of traditional Class-AB operational amplifiers when driving capacitive loads, improves the conversion rate and accuracy of the ADC, and reduces power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 广东芯赛威科技有限公司
- Filing Date
- 2026-05-14
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional Class-AB operational amplifiers have insufficient transient response when driving capacitive loads, resulting in output voltage overshoot/undershoot and a long settling time, which limits the conversion rate and accuracy of the ADC and increases power consumption.
A transient enhancement Class-AB buffer circuit is designed, which includes a VI conversion circuit, an IV conversion circuit, a floating voltage source, a MOSFET, and a transient response enhancement circuit. Through differential voltage conversion, high output impedance, and static gate bias, the channel length modulation effect is suppressed. The undershoot/overshoot suppression circuit captures voltage changes and intervenes in the MOSFET gate voltage change in advance to reduce static power consumption.
It improves the transient response of the buffer circuit, reduces output voltage fluctuations, lowers static power consumption, avoids output crossover distortion, and improves the conversion rate and accuracy of the ADC.
Smart Images
Figure CN122247357A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic circuit technology, and relates to a buffer circuit, and more particularly to a transient enhancement type Class-AB buffer circuit, control method, electronic device and storage medium. Background Technology
[0002] Traditional Class-AB operational amplifiers have inherent limitations in transient response when driving capacitive loads. In high-speed, high-precision ADCs, Class-AB operational amplifiers are often used as unity-gain buffers.
[0003] For example, when the CDAC capacitor array switches during successive comparisons in a SAR ADC, it is equivalent to introducing a step load current at the op-amp output. The limited static bias current of traditional op-amps prevents them from providing sufficient charging and discharging current instantaneously, resulting in large output voltage overshoot / undershoot and long settling time.
[0004] Existing solutions not only limit the overall conversion rate of the ADC, but may also introduce nonlinear errors due to incomplete setup, reducing conversion accuracy. Although the slew rate and gain-bandwidth product can be improved by simply increasing the op-amp's quiescent current, this will lead to increased power consumption.
[0005] In view of this, there is an urgent need to design a new buffer circuit in order to overcome at least some of the aforementioned defects of existing buffer circuits. Summary of the Invention
[0006] This invention provides a transient-enhanced Class-AB buffer circuit, a control method, an electronic device, and a storage medium, which can improve the transient response of the buffer circuit.
[0007] To solve the above-mentioned technical problems, according to one aspect of the present invention, the following technical solution is adopted: A transient enhancement type Class-AB buffer circuit, comprising: a VI conversion circuit, a first IV conversion circuit, a second IV conversion circuit, a floating voltage source, a second MOSFET, a second second MOSFET, and a transient response enhancement circuit; The VI conversion circuit is connected to the first IV conversion circuit and the second IV conversion circuit respectively; the floating voltage source is connected to the first IV conversion circuit and the second IV conversion circuit respectively; The first IV conversion circuit is connected to the gate of the second MOSFET and the transient response enhancement circuit, respectively; the second IV conversion circuit is connected to the gate of the second MOSFET and the transient response enhancement circuit, respectively. The source of the second MOSFET is connected to the power supply voltage, the drain of the second MOSFET is connected to the drain of the second MOSFET, and the source of the second MOSFET is grounded; the drains of the second MOSFET and the second MOSFET are connected to the output voltage VOUT. The VI conversion circuit is used to receive the input voltage VIN and the reference voltage VIP, form a differential voltage, and realize the linear conversion from differential voltage to differential current. The first IV conversion circuit is used to provide high output impedance, completely suppress the channel length modulation effect, and realize the conversion of input current to output voltage; The second IV conversion circuit is used to provide high output impedance, completely suppress the channel length modulation effect, and realize the conversion of input current to output voltage; The floating voltage source module is used to provide a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, set the static operating current of the output stage, ensure that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, reduce static power consumption, avoid output crossover distortion, and realize Class-AB working mode. The second MOSFET is used to charge the load capacitor; the second MOSFET is used to discharge the load capacitor. The transient response enhancement circuit is used to capture the undershoot / overshoot voltage of the output voltage VOUT and directly inject the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
[0008] In one embodiment of the present invention, the transient response enhancement circuit includes an undershoot suppression circuit and an overshoot suppression circuit; the undershoot suppression circuit is connected to the gate of the first IV conversion circuit and the gate of the second MOS transistor, respectively, and the overshoot suppression circuit is connected to the gate of the second IV conversion circuit and the gate of the second MOS transistor, respectively. The undershoot suppression circuit is used to suppress the undershoot voltage when the output voltage VOUT of the buffer circuit undershoots; the overshoot suppression circuit is used to suppress the overshoot voltage when the output voltage VOUT of the buffer circuit overshoots. The floating voltage source module is also used to isolate the large signal swing between the input stage and the output stage, prevent large fluctuations in the output voltage from causing the static bias current of the output stage to run away from control, and stabilize the circuit operating point; the floating voltage source module is also used to cooperate with the output current of the VI conversion circuit to complete the current-voltage conversion and realize linear control of the gate voltage of the output power transistor.
[0009] As one embodiment of the present invention, the undershoot suppression circuit includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a first zero MOSFET M10, a first capacitor C1, a second capacitor C2, and a first resistor R1. The first power supply voltage is connected to the source of the second MOSFET M2, the source of the third MOSFET M3, the source of the sixth MOSFET M6, and the source of the ninth MOSFET M9, respectively; the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are respectively connected to the voltage output terminal VOUT of the undershoot suppression circuit. The gate of the first MOSFET M1 is connected to the second voltage VBN, and the drain of the first MOSFET M1 is connected to the second terminal of the first capacitor C1, the drain of the second MOSFET M2, the gate of the second MOSFET M2, and the gate of the third MOSFET; the source of the first MOSFET M1 is grounded. The drain of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4, and the gate of the seventh MOS transistor M7, respectively. The source of the fourth MOS transistor M4 is connected to the second terminal of the first resistor R1, the drain of the fifth MOS transistor M5, and the gate of the eighth MOS transistor M8, respectively. The gate of the fifth MOS transistor M5 is connected to the second terminal of the second capacitor C2 and the first terminal of the first resistor R1, respectively; the source of the fifth MOS transistor M5 is grounded. The drain of the sixth MOSFET M6 is connected to the third voltage VP and the drain of the seventh MOSFET M7, respectively; the source of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8; and the source of the eighth MOSFET M8 is grounded. The gate of the sixth MOS transistor M6 is connected to the gate of the ninth MOS transistor M9, the drain of the ninth MOS transistor M9, and the drain of the first zero MOS transistor M10, respectively; the gate of the first zero MOS transistor M10 is connected to the second power supply voltage VBN, and the source of the first zero MOS transistor M10 is grounded.
[0010] In one embodiment of the present invention, the second MOS transistor is a PMOS transistor, and the second and second MOS transistors are NMOS transistors; the operation of the undershoot suppression circuit includes: When the output of the buffer circuit undershoots, the first capacitor C1 detects the voltage change of VOUT. Since the voltage across the first capacitor C1 cannot change abruptly, the gate potential of the second MOSFET M2 is suddenly pulled low, and the drain output current of the second MOSFET M2 becomes high. The first MOSFET M1 acts as a current source, providing static bias, and VBN is provided by another bias circuit. At this time, the current in the branch of the third MOSFET M3 becomes the sum of the static bias current IB and the current change ΔI caused by the change of VOUT. One end of the second capacitor C2 is connected to VOUT. The second capacitor C2 detects the undershoot voltage. Due to the characteristic that the voltage across the second capacitor C2 cannot change abruptly, the gate of the fifth MOSFET M5 is pulled low, and the current that can flow through the fifth MOSFET M5 decreases. At this time, part of the current flowing out of the third MOSFET M3 passes through the first resistor R1 and charges the second capacitor C2. The current ΔI caused by the change in VOUT is converted into a voltage through the first resistor R1 and then amplified by the eighth MOSFET M8. The current flowing through the eighth MOSFET M8 increases, and the sixth MOSFET M6 outputs a static bias current. Current is drawn from VP and flows to the eighth MOSFET M8. Since VP is connected to a Class-AB PMOS transistor, the outflowing current causes the gate voltage of the PMOS transistor to drop rapidly, thereby reducing the undershoot voltage of VOUT.
[0011] In one embodiment of the present invention, the overshoot suppression circuit includes a first MOSFET M11, a first second MOSFET M12, a first third MOSFET M13, a first fourth MOSFET M14, a first fifth MOSFET M15, a first sixth MOSFET M16, a first seventh MOSFET M17, a first eighth MOSFET M18, a first ninth MOSFET M19, a second zero MOSFET M20, a third capacitor C3, a fourth capacitor C4, and a second resistor R2; The first power supply voltage is connected to the source of the first MOSFET M11, the source of the first MOSFET M13, the source of the first MOSFET M16, and the source of the first MOSFET M19, respectively; the second terminal of the third capacitor C3 and the second terminal of the fourth capacitor C4 are respectively connected to the voltage output terminal of the overshoot suppression circuit. The gate of the first MOSFET M11 is connected to the second power supply voltage VBN. The drain of the first MOSFET M11 is connected to the first terminal of the fourth capacitor C4, the drain of the first MOSFET M12, the gate of the first MOSFET M12, and the gate of the first MOSFET M15. The source of the first MOSFET M12 is grounded. The drain of the first three MOSFET M13 is connected to the source of the first four MOSFET M14, the gate of the first six MOSFET M16, and the first terminal of the second resistor R2, respectively; the gate of the first three MOSFET M13 is connected to the first terminal of the third capacitor C3 and the second terminal of the second resistor R2, respectively. The drain of the first four MOSFET M14 is connected to the gate of the first four MOSFET M14, the drain of the first five MOSFET M15, and the gate of the first seven MOSFET M17, respectively; the source of the first five MOSFET M15 is grounded. The drain of the first sixth MOSFET M16 is connected to the source of the first seventh MOSFET M17; the drain of the first seventh MOSFET M17 is connected to the fourth voltage VN and the drain of the first eighth MOSFET M18 respectively; the source of the first eighth MOSFET M18 is grounded. The gate of the first nine-MOSFET M19 is connected to the sixth voltage VBP; the drain of the first nine-MOSFET M19 is connected to the drain of the second zero-MOSFET M20 and the gate of the second zero-MOSFET M20 respectively; the source of the second zero-MOSFET M20 is grounded.
[0012] In one embodiment of the present invention, the second MOS transistor is a PMOS transistor, and the second and second MOS transistors are NMOS transistors; the operation of the overshoot suppression circuit includes: When an overshoot occurs at the output of the buffer circuit, the fourth capacitor C4 detects a change in the voltage of VOUT. Since the voltage across the fourth capacitor C4 cannot change abruptly, the gate potential of the first two MOSFETs M12 is suddenly pulled low, and the drain output current of the first two MOSFETs M12 becomes high. The first MOSFET M11 acts as a current source, providing static bias, and VBP is provided by another bias circuit. At this time, the current in the branch of the first five MOSFET M15 becomes the sum of the static bias current IB' and the current change ΔI' caused by the change in VOUT. One end of the third capacitor C3 is connected to VOUT. The third capacitor C3 detects the overshoot voltage. Due to the characteristic that the voltage across the third capacitor C3 cannot change abruptly, the gate of the first three-MOSFET M13 is pulled low, and the current that can flow through the first three-MOSFET M13 decreases. At this time, part of the current flowing out of the first five-MOSFET M15 passes through the second resistor R2 and charges the third capacitor C3. The current change ΔI' caused by the change in VOUT is converted into voltage through the second resistor R2 and then amplified by the first six-MOSFET M16. The current flowing through the first six-MOSFET M16 increases, and the first eight-MOSFET M18 outputs static bias current, drawing current from VN and flowing to the first six-MOSFET M16. Since VN is connected to the Class-AB NMOS transistor, the outflowing current causes the gate voltage of the NMOS transistor to drop rapidly, thereby reducing the overshoot voltage of VOUT.
[0013] According to another aspect of the present invention, the following technical solution is adopted: a control method for the above-mentioned transient enhancement-type Class-AB buffer circuit, the control method comprising: The VI conversion circuit receives the input voltage VIN and the reference voltage VIP, forms a differential voltage, and realizes a linear conversion from differential voltage to differential current. The first IV conversion circuit and the second IV conversion circuit provide high output impedance, completely suppressing the channel length modulation effect and realizing the conversion from input current to output voltage; The floating voltage source module provides a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, sets the static operating current of the output stage, and ensures that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, thereby reducing static power consumption, avoiding output crossover distortion, and realizing Class-AB operating mode; the second MOSFET is used to charge the load capacitor, and the second MOSFET is used to discharge the load capacitor. The transient response enhancement circuit captures the undershoot / overshoot voltage of the output voltage VOUT and directly injects the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
[0014] As one embodiment of the present invention, the control method specifically includes: Under unity-gain negative feedback, the input voltage VIN equals the output voltage VOUT. The differential input voltage of the input differential pair of the VI conversion circuit is 0, and the output has a fixed static bias current. Through a floating voltage source, a stable gate bias is provided for the second MOSFET MP and the second MOSFET MN, so that the second MOSFET MP and the second MOSFET MN operate simultaneously in the weak conduction Class-AB state. The static current is maintained at the designed low value to ensure extremely low static power consumption and avoid output crossover distortion. At this time, the output stage provides only a very small static current to maintain the stability of the load capacitor voltage, and the output voltage VOUT will follow the reference voltage VIP. When the reference voltage VIP undergoes a step change, the voltage across the capacitive load CL cannot change abruptly and remains at the value before the step change of the reference voltage VIP. At this time, the voltage values at the input terminals of the Class-AB buffer circuit are different, and the error voltage is converted into a differential input current. The first IV conversion circuit and the second IV conversion circuit convert the error differential input current into the gate voltage of the power transistor. The quiescent current on this branch determines the rate of change of the output power transistor's gate voltage. Finally, the op-amp charges the load capacitor CL, and the rate of increase of the output voltage VOUT is determined by the op-amp's slew rate, resulting in a linear increase in the output voltage VOUT. When the output voltage VOUT rises to a certain value, the op-amp re-establishes its operating point, and the negative feedback loop regains its control capability. The Class-AB buffer circuit has limited bandwidth and inherent phase delay. When the output voltage VOUT reaches the voltage of the reference voltage VIP after the step change, the gate voltage of the second MOSFET and / or the second MOSFET does not immediately return to its normal value. At this moment, the output voltage VOUT experiences undershoot / overshoot. After the undershoot / overshoot occurs, the loop itself will gradually converge to the correct output voltage VOUT value.
[0015] According to another aspect of the present invention, the following technical solution is adopted: an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above method.
[0016] According to another aspect of the present invention, the following technical solution is adopted: a storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the above-described method.
[0017] The beneficial effects of the present invention are as follows: The transient enhancement-type Class-AB buffer circuit, control method, electronic device and storage medium proposed in the present invention use capacitive coupling technology to detect the voltage change at the output terminal of the operational amplifier, and couple the voltage change into the fast loop through the capacitor, thereby accelerating the change of the gate voltage of the Class-AB MOS transistor, thereby improving the transient response of the buffer circuit. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the transient enhancement-type Class-AB buffer circuit in one embodiment of the present invention.
[0019] Figure 2 This is a circuit diagram of an undershoot suppression circuit in one embodiment of the present invention.
[0020] Figure 3 This is a circuit diagram of an overshoot suppression circuit in one embodiment of the present invention.
[0021] Figure 4This is a simulation diagram of the undershoot suppression circuit in one embodiment of the present invention.
[0022] Figure 5 This is a schematic diagram of the composition of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0023] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0024] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.
[0025] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Substitution of identical or similar prior art methods with some technical features in the embodiments is also within the scope of the description and protection of this invention.
[0026] The steps described in the various embodiments in the specification are for illustrative purposes only, and the implementation of this application is not limited by the order of the steps.
[0027] The term "coupled" or "connected" in the specification includes both direct and indirect connections, such as connections made through active devices, passive devices, or electrical conduction media; it may also include connections made by other active or passive devices that are known to those skilled in the art and can achieve the same or similar functional purpose, such as connections made through circuits or components such as switches or follower circuits.
[0028] This invention discloses a transient enhancement-type Class-AB buffer circuit. Figure 1 This is a schematic diagram of the transient enhancement-type Class-AB buffer circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 1 The transient enhancement Class-AB buffer circuit includes: a VI conversion circuit 1, a first IV conversion circuit 2, a second IV conversion circuit 3, a floating voltage source 4, a second MOSFET 7, a second MOSFET 8, and a transient response enhancement circuit.
[0029] The VI conversion circuit 1 is connected to the first IV conversion circuit 2 and the second IV conversion circuit 3, respectively; the floating voltage source 4 is connected to the first IV conversion circuit 2 and the second IV conversion circuit 3, respectively. The first IV conversion circuit 2 is connected to the gate of the second MOSFET 7 and the transient response enhancement circuit, respectively; the second IV conversion circuit 3 is connected to the gate of the second MOSFET 8 and the transient response enhancement circuit, respectively. The source of the second MOSFET 7 is connected to the power supply voltage, the drain of the second MOSFET 7 is connected to the drain of the second MOSFET 8, and the source of the second MOSFET 8 is grounded; the drains of the second MOSFET 7 and the drains of the second MOSFET 8 are connected to the output voltage VOUT.
[0030] The VI conversion circuit 1 receives the input voltage VIN and the reference voltage VIP, forms a differential voltage, and realizes a linear conversion from differential voltage to differential current. The first IV conversion circuit 2 provides high output impedance to completely suppress the channel length modulation effect and realize the conversion from input current to output voltage; the second IV conversion circuit 3 provides high output impedance to completely suppress the channel length modulation effect and realize the conversion from input current to output voltage.
[0031] The floating voltage source module 4 provides a stable gate static bias voltage difference for the second MOSFET 7 and the second MOSFET 8 in the output stage, sets the static operating current of the output stage, and ensures that the second MOSFET 7 and the second MOSFET 8 are simultaneously in a weak conduction state in the static state, reducing static power consumption, avoiding output crossover distortion, and realizing the Class-AB operating mode. The second MOSFET 7 is responsible for charging the load capacitor; the second MOSFET 8 is responsible for discharging the load capacitor.
[0032] The transient response enhancement circuit is used to capture the undershoot / overshoot voltage of the output voltage VOUT and directly inject the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
[0033] In one embodiment of the present invention, the transient response enhancement circuit includes an undershoot suppression circuit 5 and an overshoot suppression circuit 6. The undershoot suppression circuit 5 is connected to the gates of the first IV conversion circuit 2 and the second MOSFET 7, respectively, and the overshoot suppression circuit 6 is connected to the gates of the second IV conversion circuit 3 and the second MOSFET 8, respectively. The undershoot suppression circuit 5 is used to suppress the undershoot voltage when the output voltage VOUT of the buffer circuit undershoots; the overshoot suppression circuit 6 is used to suppress the overshoot voltage when the output voltage VOUT of the buffer circuit overshoots.
[0034] The floating voltage source module 4 is also used to isolate the large signal swing between the input stage and the output stage, prevent the output voltage from fluctuating greatly and causing the static bias current of the output stage to run away from control, and stabilize the circuit operating point; the floating voltage source module 4 is also used to cooperate with the output current of the VI conversion circuit to complete the current-voltage conversion and realize the linear control of the gate voltage of the output power transistor.
[0035] Figure 2 This is a circuit diagram of an undershoot suppression circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 2 In one embodiment of the present invention, the undershoot suppression circuit includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a first zero MOSFET M10, a first capacitor C1, a second capacitor C2, and a first resistor R1.
[0036] The first power supply voltage is connected to the source of the second MOSFET M2, the source of the third MOSFET M3, the source of the sixth MOSFET M6, and the source of the ninth MOSFET M9, respectively; the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are respectively connected to the voltage output terminal VOUT of the undershoot suppression circuit.
[0037] The gate of the first MOSFET M1 is connected to the second voltage VBN, and the drain of the first MOSFET M1 is connected to the second terminal of the first capacitor C1, the drain of the second MOSFET M2, the gate of the second MOSFET M2, and the gate of the third MOSFET. The source of the first MOSFET M1 is grounded.
[0038] The drain of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4, the gate of the fourth MOSFET M4, and the gate of the seventh MOSFET M7. The source of the fourth MOSFET M4 is connected to the second terminal of the first resistor R1, the drain of the fifth MOSFET M5, and the gate of the eighth MOSFET M8. The gate of the fifth MOSFET M5 is connected to the second terminal of the second capacitor C2 and the first terminal of the first resistor R1. The source of the fifth MOSFET M5 is grounded. The drain of the sixth MOSFET M6 is connected to the third voltage VP and the drain of the seventh MOSFET M7. The source of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8. The source of the eighth MOSFET M8 is grounded. The gate of the sixth MOSFET M6 is connected to the gate of the ninth MOSFET M9, the drain of the ninth MOSFET M9, and the drain of the first zero MOSFET M10. The gate of the first zero MOSFET M10 is connected to the second power supply voltage VBN, and the source of the first zero MOSFET M10 is grounded.
[0039] In one embodiment of the present invention, the second MOS transistor is a PMOS transistor, and the second and second MOS transistors are NMOS transistors; the operation of the undershoot suppression circuit includes: When the output of the buffer circuit undershoots, the first capacitor C1 detects the voltage change of VOUT. Since the voltage across the first capacitor C1 cannot change abruptly, the gate potential of the second MOSFET M2 is suddenly pulled low, and the drain output current of the second MOSFET M2 becomes high. The first MOSFET M1 acts as a current source, providing static bias, and VBN is provided by another bias circuit. At this time, the current in the branch of the third MOSFET M3 becomes the sum of the static bias current IB and the current change ΔI caused by the change of VOUT.
[0040] One end of the second capacitor C2 is connected to VOUT. The second capacitor C2 detects the undershoot voltage. Due to the characteristic that the voltage across the second capacitor C2 cannot change abruptly, the gate of the fifth MOSFET M5 is pulled low, and the current that can flow through the fifth MOSFET M5 decreases. At this time, part of the current flowing out of the third MOSFET M3 passes through the first resistor R1 and charges the second capacitor C2. The current ΔI caused by the change in VOUT is converted into a voltage through the first resistor R1 and then amplified by the eighth MOSFET M8. The current flowing through the eighth MOSFET M8 increases, and the sixth MOSFET M6 outputs a static bias current. Current is drawn from VP and flows to the eighth MOSFET M8. Since VP is connected to a Class-AB PMOS transistor, the outflowing current causes the gate voltage of the PMOS transistor to drop rapidly, thereby reducing the undershoot voltage of VOUT.
[0041] Figure 3 This is a circuit diagram of an overshoot suppression circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 3 In one embodiment of the present invention, the overshoot suppression circuit includes a first MOSFET M11, a first second MOSFET M12, a first third MOSFET M13, a first fourth MOSFET M14, a first fifth MOSFET M15, a first sixth MOSFET M16, a first seventh MOSFET M17, a first eighth MOSFET M18, a first ninth MOSFET M19, a second zeroth MOSFET M20, a third capacitor C3, a fourth capacitor C4, and a second resistor R2.
[0042] The first power supply voltage is connected to the source of the first MOSFET M11, the source of the first MOSFET M13, the source of the first MOSFET M16, and the source of the first MOSFET M19, respectively; the second terminal of the third capacitor C3 and the second terminal of the fourth capacitor C4 are respectively connected to the voltage output terminal of the overshoot suppression circuit.
[0043] The gate of the first MOSFET M11 is connected to the second power supply voltage VBN. The drain of the first MOSFET M11 is connected to the first terminal of the fourth capacitor C4, the drain of the first second MOSFET M12, the gate of the first second MOSFET M12, and the gate of the first fifth MOSFET M15. The source of the first second MOSFET M12 is grounded.
[0044] The drain of the first three-MOSFET M13 is connected to the source of the first four-MOSFET M14, the gate of the first six-MOSFET M16, and the first terminal of the second resistor R2, respectively. The gate of the first three-MOSFET M13 is connected to the first terminal of the third capacitor C3 and the second terminal of the second resistor R2, respectively. The drain of the first four-MOSFET M14 is connected to the gate of the first four-MOSFET M14, the drain of the first five-MOSFET M15, and the gate of the first seven-MOSFET M17, respectively. The source of the first five-MOSFET M15 is grounded. The drain of the first six-MOSFET M16 is connected to the source of the first seven-MOSFET M17, respectively. The drain of the first seven-MOSFET M17 is connected to the fourth voltage VN and the drain of the first eight-MOSFET M18, respectively. The source of the first eight-MOSFET M18 is grounded. The gate of the first nine-MOSFET M19 is connected to the sixth voltage VBP; the drain of the first nine-MOSFET M19 is connected to the drain of the second zero-MOSFET M20 and the gate of the second zero-MOSFET M20 respectively; the source of the second zero-MOSFET M20 is grounded.
[0045] In one embodiment of the present invention, the second MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor; the operation of the overshoot suppression circuit includes: When an overshoot occurs at the output of the buffer circuit, the fourth capacitor C4 detects a change in the voltage of VOUT. Since the voltage across the fourth capacitor C4 cannot change abruptly, the gate potential of the first two MOSFETs M12 is suddenly pulled low, and the drain output current of the first two MOSFETs M12 becomes high. The first MOSFET M11 acts as a current source, providing static bias, and VBP is provided by another bias circuit. At this time, the current in the branch of the first five MOSFET M15 becomes the sum of the static bias current IB' and the current change ΔI' caused by the change in VOUT.
[0046] One end of the third capacitor C3 is connected to VOUT. The third capacitor C3 detects the overshoot voltage. Due to the characteristic that the voltage across the third capacitor C3 cannot change abruptly, the gate of the first three-MOSFET M13 is pulled low, and the current that can flow through the first three-MOSFET M13 decreases. At this time, part of the current flowing out of the first five-MOSFET M15 passes through the second resistor R2 and charges the third capacitor C3. The current change ΔI' caused by the change in VOUT is converted into voltage through the second resistor R2 and then amplified by the first six-MOSFET M16. The current flowing through the first six-MOSFET M16 increases, and the first eight-MOSFET M18 outputs static bias current, drawing current from VN and flowing to the first six-MOSFET M16. Since VN is connected to the Class-AB NMOS transistor, the outflowing current causes the gate voltage of the NMOS transistor to drop rapidly, thereby reducing the overshoot voltage of VOUT.
[0047] This invention further discloses a control method for the above-mentioned transient enhancement-type Class-AB buffer circuit, the control method comprising: The VI conversion circuit receives the input voltage VIN and the reference voltage VIP, forms a differential voltage, and realizes a linear conversion from differential voltage to differential current. The first IV conversion circuit and the second IV conversion circuit provide high output impedance, completely suppressing the channel length modulation effect and realizing the conversion from input current to output voltage; The floating voltage source module provides a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, sets the static operating current of the output stage, and ensures that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, thereby reducing static power consumption, avoiding output crossover distortion, and realizing Class-AB operating mode; the second MOSFET is used to charge the load capacitor, and the second MOSFET is used to discharge the load capacitor. The transient response enhancement circuit captures the undershoot / overshoot voltage of the output voltage VOUT and directly injects the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
[0048] Connect the input terminal VIN of the Class-AB operational amplifier to the output terminal VOUT, so that the Class-AB operational amplifier is configured in a unity-gain negative feedback form, thus obtaining the Class-AB buffer circuit (Class-AB buffer).
[0049] In one embodiment of the present invention, the control method specifically includes: Under unity-gain negative feedback, the input voltage VIN equals the output voltage VOUT. The differential input voltage of the input differential pair in the VI conversion circuit is 0, and the output has a fixed static bias current. This current provides a stable gate bias for the second MOSFET MP and the second MOSFET MN through a floating voltage source, allowing both MOSFETs MP and MN to operate simultaneously in a weakly conducting Class-AB state. The static current is maintained at the designed low value, ensuring extremely low static power consumption and avoiding output crossover distortion. At this time, the output stage provides only a very small static current to maintain a stable load capacitor voltage, and the output voltage VOUT will follow the reference voltage VIP. When the reference voltage VIP undergoes a step change, the voltage across the capacitive load CL cannot change abruptly and remains at the value before the step change of the reference voltage VIP. At this time, the voltage values at the input terminals of the op-amp are different, and the error voltage is converted into a differential input current. The first IV conversion circuit and the second IV conversion circuit convert the error differential input current into the gate voltage of the power transistor. The quiescent current on this branch determines the rate of change of the gate voltage of the output power transistor. Finally, the op-amp charges the load capacitor CL, and the rate of increase of the output voltage VOUT is determined by the slew rate of the op-amp, and the output voltage VOUT increases linearly. When the output voltage VOUT rises to a certain value, the op-amp re-establishes its operating point, and the negative feedback loop recovers its control capability. Due to the limited bandwidth of the op-amp, there is an inherent phase delay. Therefore, when the output voltage VOUT reaches the voltage of the reference voltage VIP after the step change, the gate voltage of the second MOSFET and / or the second MOSFET does not immediately return to the normal voltage value. At this moment, the output voltage VOUT experiences undershoot / overshoot. After the undershoot / overshoot occurs, the loop itself will gradually converge to the correct output voltage VOUT value.
[0050] This invention also discloses an electronic device, Figure 5 This is a schematic diagram of the composition of an electronic device according to an embodiment of the present invention; please refer to [link / reference]. Figure 5 At the hardware level, the electronic device includes a memory, a processor, and at least one communication interface; the processor may be a microprocessor, and the memory may include main memory, such as random access memory (RAM) or non-volatile memory. Of course, the electronic device may also include other hardware as needed.
[0051] The processor, communication interface, and memory can be interconnected via an internal bus. The memory stores programs (including operating system programs and application programs); the programs may include program code, which may include computer operation instructions. The memory may include main memory and non-volatile memory, and provides instructions and data to the processor.
[0052] In one embodiment, the processor can read the corresponding program from non-volatile memory into memory and then run it; the processor can execute the program stored in memory and specifically perform the following operations: The VI conversion circuit receives the input voltage VIN and the reference voltage VIP, forms a differential voltage, and realizes a linear conversion from differential voltage to differential current. The first IV conversion circuit and the second IV conversion circuit provide high output impedance, completely suppressing the channel length modulation effect and realizing the conversion from input current to output voltage; The floating voltage source module provides a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, sets the static operating current of the output stage, and ensures that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, thereby reducing static power consumption, avoiding output crossover distortion, and realizing Class-AB operating mode; the second MOSFET is used to charge the load capacitor, and the second MOSFET is used to discharge the load capacitor. The transient response enhancement circuit captures the undershoot / overshoot voltage of the output voltage VOUT and directly injects the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
[0053] In one embodiment of the present invention, the processor can execute a program stored in the memory, and specifically performs the following operations: Connect the input terminal VIN of the Class-AB operational amplifier to the output terminal VOUT, so that the Class-AB operational amplifier is configured in a unity-gain negative feedback form, thus obtaining the Class-AB buffer circuit (Class-AB buffer). Under unity-gain negative feedback, the input voltage VIN equals the output voltage VOUT. The differential input voltage of the input differential pair of the VI conversion circuit is 0, and the output has a fixed static bias current. Through a floating voltage source, a stable gate bias is provided for the second MOSFET MP and the second MOSFET MN, so that the second MOSFET MP and the second MOSFET MN operate simultaneously in the weak conduction Class-AB state. The static current is maintained at the designed low value to ensure extremely low static power consumption and avoid output crossover distortion. At this time, the output stage provides only a very small static current to maintain the stability of the load capacitor voltage, and the output voltage VOUT will follow the reference voltage VIP. When the reference voltage VIP undergoes a step change, the voltage across the capacitive load CL cannot change abruptly and remains at the value before the step change of the reference voltage VIP. At this time, the voltage values at the input terminals of the Class-AB buffer circuit are different, and the error voltage is converted into a differential input current. The first IV conversion circuit and the second IV conversion circuit convert the error differential input current into the gate voltage of the power transistor. The quiescent current on this branch determines the rate of change of the output power transistor's gate voltage. Finally, the op-amp charges the load capacitor CL, and the rate of increase of the output voltage VOUT is determined by the op-amp's slew rate, resulting in a linear increase in the output voltage VOUT. When the output voltage VOUT rises to a certain value, the op-amp re-establishes its operating point, and the negative feedback loop regains its control capability. The Class-AB buffer circuit has limited bandwidth and inherent phase delay. When the output voltage VOUT reaches the voltage of the reference voltage VIP after the step change, the gate voltage of the second MOSFET and / or the second MOSFET does not immediately return to its normal value. At this moment, the output voltage VOUT experiences undershoot / overshoot. After the undershoot / overshoot occurs, the loop itself will gradually converge to the correct output voltage VOUT value.
[0054] The present invention further discloses a storage medium storing computer program instructions thereon, which, when executed by a processor, implement the following steps of the method of the present invention: The VI conversion circuit receives the input voltage VIN and the reference voltage VIP, forms a differential voltage, and realizes a linear conversion from differential voltage to differential current. The first IV conversion circuit and the second IV conversion circuit provide high output impedance, completely suppressing the channel length modulation effect and realizing the conversion from input current to output voltage; The floating voltage source module provides a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, sets the static operating current of the output stage, and ensures that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, thereby reducing static power consumption, avoiding output crossover distortion, and realizing Class-AB operating mode; the second MOSFET is used to charge the load capacitor, and the second MOSFET is used to discharge the load capacitor. The transient response enhancement circuit captures the undershoot / overshoot voltage of the output voltage VOUT and directly injects the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
[0055] In one embodiment of the present invention, when the computer program instructions are executed by the processor, the following steps of the method of the present invention are implemented: Connect the input terminal VIN of the Class-AB operational amplifier to the output terminal VOUT, so that the Class-AB operational amplifier is configured in a unity-gain negative feedback form, thus obtaining a Class-AB buffer circuit (or Class-AB buffer). Under unity-gain negative feedback, the input voltage VIN equals the output voltage VOUT. The differential input voltage of the input differential pair in the VI conversion circuit is 0, and the output has a fixed static bias current. This current provides a stable gate bias for the second MOSFET MP and the second MOSFET MN through a floating voltage source, allowing both MOSFETs MP and MN to operate simultaneously in a weakly conducting Class-AB state. The static current is maintained at the designed low value, ensuring extremely low static power consumption and avoiding output crossover distortion. At this time, the output stage provides only a very small static current to maintain a stable load capacitor voltage, and the output voltage VOUT will follow the reference voltage VIP. When the reference voltage VIP undergoes a step change, the voltage across the capacitive load CL cannot change abruptly and remains at the value before the step change of the reference voltage VIP. At this time, the voltage values at the input terminals of the op-amp are different, and the error voltage is converted into a differential input current. The first IV conversion circuit and the second IV conversion circuit convert the error differential input current into the gate voltage of the power transistor. The quiescent current on this branch determines the rate of change of the gate voltage of the output power transistor. Finally, the op-amp charges the load capacitor CL, and the rate of increase of the output voltage VOUT is determined by the slew rate of the op-amp, and the output voltage VOUT increases linearly. When the output voltage VOUT rises to a certain value, the op-amp re-establishes its operating point, and the negative feedback loop recovers its control capability. Due to the limited bandwidth of the op-amp, there is an inherent phase delay. Therefore, when the output voltage VOUT reaches the voltage of the reference voltage VIP after the step change, the gate voltage of the second MOSFET and / or the second MOSFET does not immediately return to the normal voltage value. At this moment, the output voltage VOUT experiences undershoot / overshoot. After the undershoot / overshoot occurs, the loop itself will gradually converge to the correct output voltage VOUT value.
[0056] In summary, the transient enhancement-type Class-AB buffer circuit, control method, electronic device, and storage medium proposed in this invention use capacitive coupling technology to detect voltage changes at the output of the operational amplifier. The voltage changes are coupled into the fast loop through the capacitor, thereby accelerating the change of the gate voltage of the Class-AB MOS transistor and thus improving the transient response of the buffer.
[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0058] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. Effects or advantages involved in the embodiments may not be apparent due to various factors, and the description of effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be apparent to those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.
Claims
1. A transient enhancement-type Class-AB buffer circuit, characterized in that, The transient-enhanced Class-AB buffer circuit includes: a VI conversion circuit, a first IV conversion circuit, a second IV conversion circuit, a floating voltage source, a second MOSFET, a second second MOSFET, and a transient response enhancement circuit; The VI conversion circuit is connected to the first IV conversion circuit and the second IV conversion circuit respectively; the floating voltage source is connected to the first IV conversion circuit and the second IV conversion circuit respectively; The first IV conversion circuit is connected to the gate of the second MOSFET and the transient response enhancement circuit, respectively; the second IV conversion circuit is connected to the gate of the second MOSFET and the transient response enhancement circuit, respectively. The source of the second MOSFET is connected to the power supply voltage, the drain of the second MOSFET is connected to the drain of the second MOSFET, and the source of the second MOSFET is grounded; the drains of the second MOSFET and the second MOSFET are connected to the output voltage VOUT. The VI conversion circuit is used to receive the input voltage VIN and the reference voltage VIP, form a differential voltage, and realize the linear conversion from differential voltage to differential current. The first IV conversion circuit is used to provide high output impedance, completely suppress the channel length modulation effect, and realize the conversion of input current to output voltage; The second IV conversion circuit is used to provide high output impedance, completely suppress the channel length modulation effect, and realize the conversion of input current to output voltage; The floating voltage source module is used to provide a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, set the static operating current of the output stage, ensure that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, reduce static power consumption, avoid output crossover distortion, and realize Class-AB working mode. The second MOSFET is used to charge the load capacitor; the second MOSFET is used to discharge the load capacitor. The transient response enhancement circuit is used to capture the undershoot / overshoot voltage of the output voltage VOUT and directly inject the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
2. The transient enhancement-type Class-AB buffer circuit according to claim 1, characterized in that: The transient response enhancement circuit includes an undershoot suppression circuit and an overshoot suppression circuit; the undershoot suppression circuit is connected to the gate of the first IV conversion circuit and the gate of the second MOS transistor, respectively, and the overshoot suppression circuit is connected to the gate of the second IV conversion circuit and the gate of the second MOS transistor, respectively. The undershoot suppression circuit is used to suppress the undershoot voltage when the output voltage VOUT of the buffer circuit undershoots; the overshoot suppression circuit is used to suppress the overshoot voltage when the output voltage VOUT of the buffer circuit overshoots. The floating voltage source module is also used to isolate the large signal swing between the input stage and the output stage, prevent large fluctuations in the output voltage from causing the static bias current of the output stage to run away from control, and stabilize the circuit operating point; the floating voltage source module is also used to cooperate with the output current of the VI conversion circuit to complete the current-voltage conversion and realize linear control of the gate voltage of the output power transistor.
3. The transient enhancement-type Class-AB buffer circuit according to claim 2, characterized in that: The undershoot suppression circuit includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a first zero MOSFET M10, a first capacitor C1, a second capacitor C2, and a first resistor R1. The first power supply voltage is connected to the source of the second MOSFET M2, the source of the third MOSFET M3, the source of the sixth MOSFET M6, and the source of the ninth MOSFET M9, respectively; the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are respectively connected to the voltage output terminal of the undershoot suppression circuit. The gate of the first MOSFET M1 is connected to the second voltage VBN, and the drain of the first MOSFET M1 is connected to the second terminal of the first capacitor C1, the drain of the second MOSFET M2, the gate of the second MOSFET M2, and the gate of the third MOSFET; the source of the first MOSFET M1 is grounded. The drain of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4, and the gate of the seventh MOS transistor M7, respectively. The source of the fourth MOS transistor M4 is connected to the second terminal of the first resistor R1, the drain of the fifth MOS transistor M5, and the gate of the eighth MOS transistor M8, respectively. The gate of the fifth MOS transistor M5 is connected to the second terminal of the second capacitor C2 and the first terminal of the first resistor R1; the source of the fifth MOS transistor M5 is grounded. The drain of the sixth MOSFET M6 is connected to the third voltage VP and the drain of the seventh MOSFET M7, respectively; the source of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8; and the source of the eighth MOSFET M8 is grounded. The gate of the sixth MOS transistor M6 is connected to the gate of the ninth MOS transistor M9, the drain of the ninth MOS transistor M9, and the drain of the first zero MOS transistor M10, respectively; the gate of the first zero MOS transistor M10 is connected to the second power supply voltage VBN, and the source of the first zero MOS transistor M10 is grounded.
4. The transient enhancement-type Class-AB buffer circuit according to claim 3, characterized in that: The second MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor; the operation of the undershoot suppression circuit includes: When the output of the buffer circuit undershoots, the first capacitor C1 detects the voltage change of the output voltage VOUT. Since the voltage across the first capacitor C1 cannot change abruptly, the gate potential of the second MOSFET M2 is suddenly pulled low, and the drain output current of the second MOSFET M2 becomes high. The first MOSFET M1 acts as a current source, providing static bias, and the second voltage VBN is provided by another bias circuit. At this time, the current in the branch of the third MOSFET M3 becomes the sum of the static bias current IB and the current change ΔI caused by the change in the output voltage VOUT. One end of the second capacitor C2 is connected to the output voltage VOUT. The second capacitor C2 detects the undershoot voltage. Due to the characteristic that the voltage across the second capacitor C2 cannot change abruptly, the gate of the fifth MOSFET M5 is pulled low, and the current that can flow through the fifth MOSFET M5 decreases. At this time, part of the current flowing out of the third MOSFET M3 passes through the first resistor R1 and charges the second capacitor C2. The current ΔI caused by the change in the output voltage VOUT is converted into a voltage through the first resistor R1 and then amplified by the eighth MOSFET M8. The current flowing through the eighth MOSFET M8 increases, and the sixth MOSFET M6 outputs a static bias current. It draws current from the third voltage VP and flows to the eighth MOSFET M8. The third voltage VP is connected to the PMOS transistor of the Class-AB buffer circuit. The current flowing out causes the gate voltage of the PMOS transistor of the Class-AB buffer circuit to drop rapidly, thereby reducing the undershoot voltage of the output voltage VOUT.
5. The transient enhancement-type Class-AB buffer circuit according to claim 2, characterized in that: The overshoot suppression circuit includes a first MOSFET M11, a second MOSFET M12, a third MOSFET M13, a fourth MOSFET M14, a fifth MOSFET M15, a sixth MOSFET M16, a seventh MOSFET M17, an eighth MOSFET M18, a ninth MOSFET M19, a ninth MOSFET M20, a third capacitor C3, a fourth capacitor C4, and a second resistor R2. The first power supply voltage is connected to the source of the first MOSFET M11, the source of the first MOSFET M13, the source of the first MOSFET M16, and the source of the first MOSFET M19, respectively; the second terminal of the third capacitor C3 and the second terminal of the fourth capacitor C4 are respectively connected to the voltage output terminal of the overshoot suppression circuit. The gate of the first MOSFET M11 is connected to the second power supply voltage VBN. The drain of the first MOSFET M11 is connected to the first terminal of the fourth capacitor C4, the drain of the first MOSFET M12, the gate of the first MOSFET M12, and the gate of the first MOSFET M15. The source of the first MOSFET M12 is grounded. The drain of the first three MOSFET M13 is connected to the source of the first four MOSFET M14, the gate of the first six MOSFET M16, and the first terminal of the second resistor R2, respectively; the gate of the first three MOSFET M13 is connected to the first terminal of the third capacitor C3 and the second terminal of the second resistor R2, respectively. The drain of the first four MOSFET M14 is connected to the gate of the first four MOSFET M14, the drain of the first five MOSFET M15, and the gate of the first seven MOSFET M17, respectively; the source of the first five MOSFET M15 is grounded. The drain of the first sixth MOSFET M16 is connected to the source of the first seventh MOSFET M17; the drain of the first seventh MOSFET M17 is connected to the fourth voltage VN and the drain of the first eighth MOSFET M18 respectively; the source of the first eighth MOSFET M18 is grounded. The gate of the first nine-MOSFET M19 is connected to the sixth voltage VBP; the drain of the first nine-MOSFET M19 is connected to the drain and gate of the second zero-MOSFET M20, respectively. The source of the second zero MOSFET M20 is grounded.
6. The transient enhancement-type Class-AB buffer circuit according to claim 5, characterized in that: The second MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor; the operation of the overshoot suppression circuit includes: When an overshoot occurs at the output of the buffer circuit, the fourth capacitor C4 detects a change in the output voltage VOUT. Since the voltage across the fourth capacitor C4 cannot change abruptly, the gate potential of the first two MOSFETs M12 is suddenly pulled low, and the drain output current of the first two MOSFETs M12 becomes high. The first MOSFET M11 acts as a current source, providing static bias, and the sixth voltage VBP is provided by another bias circuit. At this time, the current in the branch of the first five MOSFET M15 becomes the sum of the static bias current IB' and the current change ΔI' caused by the change in output voltage VOUT. One end of the third capacitor C3 is connected to the output voltage VOUT. The third capacitor C3 detects the overshoot voltage. Due to the characteristic that the voltage across the third capacitor C3 cannot change abruptly, the gate of the first three-MOSFET M13 is pulled low, and the current that can flow through the first three-MOSFET M13 decreases. At this time, part of the current flowing out of the first five-MOSFET M15 passes through the second resistor R2 and charges the third capacitor C3. The current change ΔI' caused by the change in output voltage VOUT is converted into voltage through the second resistor R2 and then amplified by the first six-MOSFET M16. The current flowing through the first six-MOSFET M16 increases, and the first eight-MOSFET M18 outputs static bias current. Current is drawn from the fourth voltage VN and flows to the first six-MOSFET M16. The fourth voltage VN is connected to the NMOS transistor of the Class-AB buffer circuit. The current flowing out causes the gate voltage of the NMOS transistor of the Class-AB buffer circuit to drop rapidly, thereby reducing the overshoot voltage of the output voltage VOUT.
7. A control method for the transient enhancement-type Class-AB buffer circuit according to any one of claims 1 to 6, characterized in that... Control methods include: The VI conversion circuit receives the input voltage VIN and the reference voltage VIP, forms a differential voltage, and realizes a linear conversion from differential voltage to differential current. The first IV conversion circuit and the second IV conversion circuit provide high output impedance, completely suppressing the channel length modulation effect and realizing the conversion from input current to output voltage; The floating voltage source module provides a stable gate static bias voltage difference for the second MOSFET and the second MOSFET of the output stage, sets the static operating current of the output stage, and ensures that the second MOSFET and the second MOSFET are simultaneously in a weak conduction state when static, thereby reducing static power consumption, avoiding output crossover distortion, and realizing Class-AB working mode; the second MOSFET is responsible for charging the load capacitor, and the second MOSFET is responsible for discharging the load capacitor. The transient response enhancement circuit captures the undershoot / overshoot voltage of the output voltage VOUT and directly injects the change in output voltage VOUT into the gate of the second MOSFET and / or the gate of the second MOSFET. The transient response enhancement circuit responds before the loop, thereby intervening in the gate voltage change of the second MOSFET and / or the gate voltage change of the second MOSFET in advance and suppressing the change in output voltage VOUT.
8. The control method according to claim 7, characterized in that: The control method specifically includes: Under unity-gain negative feedback, the input voltage VIN equals the output voltage VOUT. The differential input voltage of the input differential pair of the VI conversion circuit is 0, and the output has a fixed static bias current. Through a floating voltage source, a stable gate bias is provided for the second MOSFET MP and the second MOSFET MN, so that the second MOSFET MP and the second MOSFET MN operate simultaneously in the weak conduction Class-AB state. The static current is maintained at the designed low value to ensure extremely low static power consumption and avoid output crossover distortion. At this time, the output stage provides only a very small static current to maintain the stability of the load capacitor voltage, and the output voltage VOUT will follow the reference voltage VIP. When the reference voltage VIP undergoes a step change, the voltage across the capacitive load cannot change abruptly and remains at the voltage value before the step change of the reference voltage VIP. At this time, the voltage values at the input terminals of the Class-AB buffer circuit are different, and the error voltage is converted into a differential input current. The first IV conversion circuit and the second IV conversion circuit convert the error differential input current into the gate voltage of the power transistor. The quiescent current on this branch determines the rate of change of the output power transistor's gate voltage. Finally, the op-amp charges the load capacitor CL, and the rate of increase of the output voltage VOUT is determined by the op-amp's slew rate, resulting in a linear increase in the output voltage VOUT. When the output voltage VOUT rises to a certain value, the op-amp re-establishes its operating point, and the negative feedback loop regains its control capability. The Class-AB buffer circuit has limited bandwidth and inherent phase delay. When the output voltage VOUT reaches the voltage of the reference voltage VIP after the step change, the gate voltage of the second MOSFET and / or the second MOSFET does not immediately return to its normal value. At this moment, the output voltage VOUT experiences undershoot / overshoot. After the undershoot / overshoot occurs, the loop itself will gradually converge to the correct output voltage VOUT value.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 7 to 8.
10. A storage medium storing computer program instructions thereon, characterized in that, When executed by a processor, the computer program instructions implement the steps of the method according to any one of claims 7 to 8.