Voltage comparison circuit, related integrated circuit and method

Abstract

This disclosure relates to voltage comparison circuits, related integrated circuits, and methods. According to an embodiment, a voltage comparison circuit includes terminals for receiving an input voltage and a supply voltage. A measurement circuit generates a measurement signal and includes a first resistor and a second resistor coupled in series. An n-channel field-effect transistor is coupled in series with the first resistor and has a gate terminal coupled to a bias voltage source. The collectors of a first NPN bipolar transistor and a second NPN bipolar transistor are coupled to the supply voltage terminal, and their bases are coupled to a node between the resistors. A third resistor is coupled between the emitter of the first NPN bipolar transistor and ground, and a fourth resistor is coupled between the emitters of the transistors. A comparison circuit determines whether a first current through the first NPN bipolar transistor exceeds a second current through the second NPN bipolar transistor and asserts the comparison signal accordingly. The n-channel field-effect transistor limits the measurement signal.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Italian patent application No. 102024000028974, filed on December 18, 2024, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments described herein relate to a voltage comparison circuit. Background Technology

[0004] In many applications, it may be necessary to determine whether the voltage exceeds a given threshold. For example, Figure 1 A typical system is shown in which circuit 10 includes two power supply terminals 100 and 102 configured to receive an input voltage VIN. For example, terminal 102 (negative) can represent ground (GND). For example, circuit 10 can implement a power management unit (PMU). For example, circuit 10 can perform one or more of the following functions: DC-DC conversion, battery charging, power selection, voltage scaling, etc.

[0005] In the considered example, circuit 10 includes detection circuit 12 configured to monitor the input voltage VIN and generate a signal PG indicating whether VIN exceeds a given threshold. For example, Figure 2 The detection circuit 12 is shown. Specifically, in the example considered, the detection circuit 12 includes a measurement circuit 120 configured to generate a measurement signal VS indicating a voltage VIN (e.g., proportional to the voltage VIN) and a comparison circuit 122 configured to assert or deassert a comparison signal PG based on the signal VS and a threshold signal VTH.

[0006] For example, in the considered example, the measurement circuit 120 includes a voltage divider comprising two resistors RA and RB connected in series between terminals 100 and 102, wherein the signal VS corresponds to the voltage at resistor RB.

[0007] In many applications, to indicate the logic level of the comparison signal PG, the comparison signal PG is either set to 0V (ground) or set to voltage VDD. For example, this can be achieved by supplying voltage VDD to the comparison circuit 122. Such a detection circuit 12 is disclosed, for example, in Chinese Patent CN 101557215 B, which is incorporated herein by reference. Summary of the Invention

[0008] In view of the foregoing, one objective of the various embodiments is to provide an improved solution for voltage comparison circuits.

[0009] According to one or more embodiments, one or more of the above-described objectives are achieved by a voltage comparison circuit having the distinguishing elements specifically set forth in the appended claims. Furthermore, the embodiments also relate to related integrated circuits and methods.

[0010] The scope of protection is defined in the appended claims, which form part of the technical teachings described herein.

[0011] As mentioned above, various embodiments of this disclosure relate to a voltage comparison circuit configured to assert a comparison signal in response to determining that an input voltage exceeds a given threshold voltage. This voltage comparison circuit, such as a voltage comparison circuit integrated into an integrated circuit, includes a first terminal and a second terminal configured to receive an input voltage, and an additional terminal configured to receive a supply voltage.

[0012] In various embodiments, the measurement circuit is configured to generate a measurement signal indicating an input voltage, wherein the measurement circuit includes a first resistor coupled between a first terminal and a first node, and a second resistor coupled between the first node and a second terminal, wherein the measurement signal corresponds to the voltage at the second resistor.

[0013] In various embodiments, the collectors of the first and second NPN bipolar transistors are coupled to the additional terminal configured to receive a supply voltage, and the bases of the first and second NPN bipolar transistors are coupled to a first node. Specifically, the emitter area of ​​the second bipolar transistor is larger than that of the first bipolar transistor. A third resistor is coupled between the emitter of the first NPN bipolar transistor and the second terminal, and a fourth resistor is coupled between the emitter of the second NPN bipolar transistor and the emitter of the first NPN bipolar transistor.

[0014] In various embodiments, the comparator circuit is configured to determine whether a first current flowing through the collector of a first NPN bipolar transistor is greater than a second current flowing through the collector of a second NPN bipolar transistor. In response to determining that the first current is greater than the second current, the comparator circuit asserts a comparison signal. Conversely, in response to determining that the first current is less than the second current, the comparator circuit deasserts the comparison signal.

[0015] According to a first aspect of this disclosure, the measurement circuit includes an n-channel field-effect transistor (FET), wherein the n-channel FET and a first resistor are coupled in series between a first terminal and a first node, and wherein the gate terminal of the n-channel FET is coupled to a bias voltage source. In various embodiments, the gate terminal of the n-channel FET is coupled to said additional terminal configured to receive a supply voltage.

[0016] For example, in various embodiments, the drain of the n-channel field-effect transistor is coupled to a first terminal, and the source of the n-channel field-effect transistor is coupled to a first node via a first resistor. Alternatively, the source of the n-channel field-effect transistor is coupled to a first node, and the drain of the n-channel field-effect transistor is coupled to a first terminal via a first resistor.

[0017] In various embodiments, the voltage comparison circuit includes hysteresis. For this purpose, the second resistor may be a resistor switchable between a first resistance value and a second resistance value based on a comparison signal. For example, for this purpose, the second resistor may include two resistors coupled in series between the first node and the second terminal, and an electronic switch configured to short-circuit one of the two resistors when the comparison signal is de-asserted.

[0018] According to a second aspect of this disclosure, the comparison circuit includes a first transistor of a first current mirror connected between the collector of a first NPN bipolar transistor and the other terminal configured to receive a supply voltage. A second transistor of the first current mirror is coupled between the collector of a second NPN bipolar transistor and the other terminal configured to receive a supply voltage. Furthermore, a third transistor and a pull-down resistor are coupled between the other terminal configured to receive the supply voltage and the second terminal, wherein a control terminal of the third transistor is coupled to the collector of the first NPN bipolar transistor. In this configuration, a comparison signal can be determined based on the voltage at the pull-down resistor.

[0019] According to a third aspect of this disclosure, the comparator circuit includes a fifth resistor coupled between the collector of the first NPN bipolar transistor and the additional terminal configured to receive a supply voltage, and a sixth resistor coupled between the collector of the second NPN bipolar transistor and the additional terminal configured to receive a supply voltage. The operational amplifier has a first input terminal coupled to the collector of the first NPN bipolar transistor and a second input terminal coupled to the collector of the second NPN bipolar transistor. In this case, the comparator signal is determined based on the voltage at the output of the operational amplifier.

[0020] For example, in various embodiments, the operational amplifier includes a fourth transistor and a fifth transistor, such as a p-channel FET, wherein the control terminals of the fourth and fifth transistors are coupled to the collectors of a first NPN bipolar transistor and a second NPN bipolar transistor, respectively. The second current mirror may include a sixth transistor and a seventh transistor, the sixth transistor being coupled to the current path of the fourth transistor between the additional terminal configured to receive the supply voltage and the second terminal, and the seventh transistor being coupled to the current path of the fifth transistor between the additional terminal configured to receive the supply voltage and the second terminal. Furthermore, an eighth transistor and a pull-up resistor may be coupled between the additional terminal configured to receive the supply voltage and the second terminal, wherein the control terminal of the eighth transistor is coupled to an intermediate node between the sixth and fourth transistors. In this case, the comparison signal can be determined based on the voltage at the intermediate node.

[0021] In various embodiments, the fifth and sixth resistors (and similar other resistors) can be implemented using corresponding FETs configured to receive bias voltages at their respective gate terminals. Attached Figure Description

[0022] Embodiments of this disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only and in the drawings:

[0023] The features and advantages of the present invention will become clear from the following detailed description of practical embodiments thereof, which are illustrated by way of non-limiting example in the accompanying drawings, wherein:

[0024] Figure 1 An electronic system including a voltage comparison circuit is shown;

[0025] Figure 2 A voltage comparison circuit is shown;

[0026] Figure 3 The voltage measurement circuit is shown;

[0027] Figure 4 A voltage comparison circuit is shown;

[0028] Figure 5 It shows in Figure 4 The waveform of the current flowing in the voltage comparator circuit; and

[0029] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 A voltage comparison circuit is shown. Detailed Implementation

[0030] This disclosure provides numerous applicable inventive concepts that can be implemented in a wide variety of specific contexts. Specific embodiments are merely illustrative of particular configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form other embodiments. Various embodiments are illustrated in the accompanying drawings, wherein identical components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0031] The variations or modifications described in one embodiment may also be applied to other embodiments. Furthermore, various changes, substitutions, and alterations may be made to this document without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0032] In the following description, various specific details are set forth to enable a thorough understanding of the embodiments. Embodiments may be provided without one or more of these specific details, or may be provided using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail so as not to obscure various aspects of the embodiments.

[0033] References to “embodiment” or “one embodiment” within the framework of this description are intended to indicate that a particular configuration, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear in various places within this description do not necessarily refer to the same embodiment. Furthermore, specific constructions, structures, or features may be combined in any suitable manner in one or more embodiments.

[0034] The reference numerals used herein are provided for convenience only and therefore do not define the scope of protection or the scope of embodiments.

[0035] The following description Figures 3 to 12 In the middle, it has been referenced Figure 1 and Figure 2 The described parts, elements, or components are designated by the same reference numerals used previously in these figures. Descriptions of these elements have already been made and will not be repeated below to avoid burdening this detailed description.

[0036] As mentioned above, various embodiments of this disclosure relate to a detection circuit configured to assert a comparison signal PG in response to determining that a voltage VIN is greater than a given threshold.

[0037] Figure 3 An embodiment of a measurement circuit 20 configured to generate a signal VS indicating voltage VIN is shown. For example, with Figure 2The circuit shown is similar. In the considered embodiment, the measurement circuit 20 includes a voltage divider comprising (at least) a first resistor RA and a second resistor RB coupled in series between the voltage VIN and ground, wherein the measurement signal VS corresponds to the voltage at resistor RB (i.e., the voltage at the intermediate node A of the voltage divider). For example, in the considered embodiment, the first terminal of resistor RA is coupled to terminal 100, the second terminal of resistor RA is coupled to the first terminal of resistor RB (representing node A), and the second terminal of resistor RB is coupled to terminal 102 / ground.

[0038] Figure 4 An embodiment of the comparator circuit 30 is shown. Essentially, in the considered embodiment, the comparator circuit 30 is implemented around the Brokaw bandgap reference. For example, in this context, Paul Brokaw's article "A Simple Three-Terminal IC Bandgap Reference," IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974, pp. 388-393, is incorporated herein by reference.

[0039] Specifically, in the considered embodiment, the comparator circuit 30 includes a first NPN bipolar transistor Q1 and a second NPN bipolar transistor Q2. In the considered embodiment, the emitter of transistor Q1 is coupled (e.g., directly coupled) to node B, and its collector is coupled to the supply voltage VDD. Furthermore, in the considered embodiment, the emitter of transistor Q2 is coupled (e.g., directly coupled) to node B via resistor R2, and the collector of transistor Q2 is coupled to the supply voltage VDD. In the considered embodiment, node B is coupled (e.g., directly coupled) to ground via a resistor. Specifically, as explained below, the term "connection" does not mean that the collector terminal is directly connected to the voltage VDD.

[0040] Specifically, in the considered embodiment, the base terminal of transistor Q1 is coupled (e.g., directly coupled) to the base terminal of transistor Q2, wherein the base terminal receives the measured voltage VS.

[0041] Specifically, in various embodiments, the emitter area of ​​transistor Q2 is N times the emitter area of ​​transistor Q1. For example, in various embodiments, N is greater than four. Therefore, the larger transistor Q2 will achieve a given current at a lower base-emitter voltage VBE than the smaller transistor Q1. Accordingly, since transistor Q2 has an emitter area that is N times the emitter area of ​​transistor Q1, the base-emitter voltage VBE2 of transistor Q2 will be lower than the base-emitter voltage VBE1 of transistor Q1 by the following amounts:

[0042] (1)

[0043] Where VT corresponds to the thermal voltage (kT / q). For example, in many embodiments, N equals 8 because ln(N) is approximately 2.

[0044] Specifically, such as Figure 5 As shown, transistors Q1 and Q2 turn on once the voltage VS exceeds the lower threshold voltage VL. Specifically, when the voltage VS is below the threshold voltage VTH, the current IQ1 through transistor Q1 is lower than the current IQ2 through transistor Q2 (due to the lower base-emitter voltage). Conversely, when the voltage VS is above the threshold voltage VTH, the current IQ1 flowing through transistor Q1 is greater than the current IQ2 flowing through transistor Q2.

[0045] Specifically, the threshold voltage VTH corresponds to the point where currents IQ1 and IQ2 are equal (i.e., IQ1 = IQ2). In this case, the voltage difference... VBE is applied to resistor R2, and resistor R1 is connected to 2 The current corresponding to IQ2 flows through it, that is, the following voltage V1 is generated at resistor R1:

[0046] (2)

[0047] Therefore, the threshold voltage VTH corresponds to the sum of the voltage drop V1 and the base-emitter voltage VBE1 of transistor Q1, that is:

[0048] (3)

[0049] Specifically, according to the Brokaw bandgap reference, the threshold VTH remains essentially constant with temperature.

[0050] Accordingly, by also considering the voltage dividers RA and RB, the threshold voltage VIN_TH of the input voltage VIN can be calculated as:

[0051] (4)

[0052] Accordingly, in the considered embodiment, the circuit is configured to compare the collector current IQ1 of transistor Q1 with the collector current IQ2 of transistor Q2. For example, in the considered embodiment, the collector of transistor Q1 is coupled (e.g., directly coupled) to voltage VDD via a first current measurement circuit 32, and the collector of transistor Q2 is coupled (e.g., directly coupled) to voltage VDD via a second current measurement circuit 34. Furthermore, the comparison circuit 36 ​​is configured to generate a signal PG based on the signals provided by the current measurement circuits 32 and 34.

[0053] Accordingly, in the considered embodiment, the measurement voltage VS is applied directly to the base terminals of transistors Q1 and Q2. Specifically, the use of voltage dividers RA and RB within the measurement circuit 20 allows monitoring of a voltage VIN greater than the voltage VDD. Accordingly, the comparator circuit 30 can be in a low-voltage domain. For example, the voltage VDD can be selected in the range of 1-5V (e.g., 2.5-3V). The voltage VIN (when supplied to terminals 100 and 102) can be greater than the voltage VDD; for example, VIN can be greater than 5V, for example, between 9V and 24V. The low-voltage comparator circuit 30 also has several advantages. First, the comparator circuit 30 already provides a binary comparator signal PG in the low-voltage domain, which is typically used by other digital processing circuitry (e.g., within circuit 10), thereby avoiding additional level-shifting circuitry. Moreover, low-voltage components (such as transistors and resistors) generally exhibit better matching and accuracy, for example, relative to process, voltage, and temperature (PVT) variations. Furthermore, the area of ​​low-voltage components is generally smaller than that of corresponding high-voltage components.

[0054] However, if the input voltage VIN changes, the measured voltage VS may exceed VDD, potentially damaging circuit 30. Therefore, the measured voltage VS should be limited to VDD or lower. This can be achieved, for example, by limiting the voltage VS via a Zener diode. However, such a Zener diode will generate electrical losses based on the current flowing through resistor RA. Therefore, to reduce the power consumption of the detection circuit 20, resistors RA and RB should be large.

[0055] However, as Figure 4 As shown, the actual given base current Ib will flow through the bases of transistors Q1 and Q2, which generates an additional voltage drop at resistor RA. That is, the actual threshold voltage corresponds to the following equation:

[0056] (5)

[0057] Among them, EIB = RA Ib corresponds to the error.

[0058] However, this means that the EIB error also increases with RA. Therefore, the following section describes a solution for limiting current consumption at high VIN voltages while minimizing the error EIB to improve the accuracy of the threshold VIN_TH.

[0059] Figure 6 An embodiment of a voltage comparison circuit according to the present disclosure is shown. Specifically, in the considered embodiment, the measurement circuit 20 now includes a clamping circuit implemented with an n-channel field-effect transistor (FET) M0.

[0060] Specifically, in the considered embodiment, the current path of FET M0 is coupled (e.g., directly coupled) between resistor RA and terminal 100, which is configured to receive voltage VIN. Specifically, in the considered embodiment, the drain terminal of FET M0 is coupled (e.g., directly coupled) to terminal 100, and the source terminal of FET M0 is coupled (e.g., directly coupled) to ground via voltage dividers RA and RB, i.e., terminal 102. Specifically, in the considered embodiment, a first terminal of resistor RA is coupled to the source terminal of FET M0, a second terminal of resistor RA is coupled to a first terminal of resistor RB, and a second terminal of resistor RB is coupled to terminal 102, wherein an intermediate node A between resistors RA and RB is coupled to the base terminals of transistors Q1 and Q2.

[0061] Specifically, in various embodiments, the gate terminal of FET M0 is coupled to a bias voltage VB, which indicates the maximum value to which the voltage at the source terminal of FET M0 should be limited. For example, in the considered embodiment, the gate terminal is coupled (e.g., directly coupled) to a voltage VDD, i.e., VB = VDD.

[0062] Accordingly, in the considered embodiment, when the voltage VIN is less than the threshold voltage corresponding to VB - VT (where VT corresponds to the threshold voltage of FET M0), FET M0 is in the triode region, that is, the voltage at the source terminal of FET M0 approximately corresponds to VIN. Conversely, when the voltage VIN is greater than VB - VT, FET M0 is in saturation, that is, the voltage at its source terminal is approximately VB - VT.

[0063] Accordingly, in the considered embodiment, when VIN > VB - VT, the clamping circuit M0 limits the current through the voltage dividers RA and RB. Therefore, the values ​​of resistors RA and RB can be smaller, thereby reducing the error EIB.

[0064] Figure 6An embodiment of circuit 30 is also shown. Specifically, in the considered embodiment, current measurement circuits 32 and 34 are implemented with an active load. Specifically, in the considered embodiment, circuit 30 includes a first p-channel FET QB1, wherein the source terminal of FET QB1 is coupled (e.g., directly coupled) to voltage VDD, and the drain terminal of FET QB1 is coupled (e.g., directly coupled) to the collector terminal of transistor Q1, which represents node C. Similarly, in the considered embodiment, circuit 30 includes a second p-channel FET QB2, wherein the source terminal of FET QB2 is coupled (e.g., directly coupled) to voltage VDD, and the drain terminal of FET QB2 is coupled (e.g., directly coupled) to the collector terminal of transistor Q2. Specifically, in the considered embodiment, the gate terminal of FET QB1 is coupled (e.g., directly coupled) to the gate terminal of FET QB2, which in turn is coupled (e.g., directly coupled) to the drain terminal of FET QB2. Accordingly, in the considered embodiment, FETs QB1 and QB2 substantially implement current mirrors.

[0065] Therefore, once current IQ1 exceeds current IQ2, the voltage at the collector of node C / transistor Q1 drops. Accordingly, in the considered embodiment, comparator circuit 36 ​​is configured to generate a comparator signal PG based on the voltage at node C. For example, in the considered embodiment, comparator circuit 36 ​​includes a p-channel FET Q3 having a source terminal coupled (e.g., directly coupled) to voltage VDD, a drain terminal coupled to node D, and a gate terminal coupled to node C, whereby transistor Q3 closes when current IQ1 exceeds current IQ2. In various embodiments, node D is coupled to ground via pull-down resistor R3.

[0066] In various embodiments, p-channel FETs QB1, QB2, and Q3 can also be replaced by corresponding pnp bipolar transistors, wherein the source terminal of the FET is replaced by the emitter terminal of the corresponding bipolar transistor, the drain terminal of the FET is replaced by the collector terminal of the corresponding bipolar transistor, and the gate terminal of the FET is replaced by the base terminal of the corresponding bipolar transistor.

[0067] Accordingly, in the considered embodiment, the voltage at node B is high when current IQ1 exceeds current IQ2. Accordingly, the signal PG can correspond to the voltage at node B (i.e., the voltage at resistor R3), or the signal PG can be generated using an even number of logic inverters (powered by voltage VDD) based on the voltage at node B. For example, in the considered embodiment, two inverters 362 and 364 are cascaded and coupled between node B and the terminal providing the signal PG.

[0068] Figure 7 An embodiment of a voltage comparator circuit with hysteresis is shown. Specifically, in the considered embodiment, resistor RB can be switched between two resistance values. For example, in the considered embodiment, resistor RB comprises two resistors RB1 and RB2 coupled in series between node A and ground. Moreover, an electronic switch MH is used to selectively short-circuit resistor RB2. For example, in the considered embodiment, resistor RB2 is coupled to ground. For example, the electronic switch MH can be an n-channel FET. For example, in the considered embodiment, the source terminal of FET MH is coupled to ground, and its drain terminal is coupled to an intermediate node between resistors RB1 and RB2.

[0069] Accordingly, when the electronic switch MH is closed, the detection circuit has the following (rising) threshold for the input voltage VIN:

[0070] (6)

[0071] Conversely, when the electronic switch MH is open, the detection circuit has the following (falling) threshold for the input voltage VIN:

[0072] (7)

[0073] Accordingly, to implement a comparator with hysteresis, the electronic switch MH can initially be closed, thereby setting the threshold voltage VTH to voltage VIN_TH_H. Next, once the signal PG is asserted, the electronic switch MH is opened, thereby setting the threshold voltage VTH to VIN_TH_L. Accordingly, in various embodiments, the electronic switch MH can be configured to short-circuit resistor RB2 in response to determining that the signal PG is low / deasserted. For example, in the considered embodiment, the gate terminal of FET MH is coupled to the output of inverter 362 to receive the inverted version PGN of the signal PG.

[0074] The use of a switchable voltage divider also has the advantage of reducing the current consumption of the measurement circuit 20 once the signal PG is asserted.

[0075] Figure 8 An alternative embodiment of the measurement circuit 20 is shown, wherein the clamping FET M0 is not coupled between the voltage VIN and the voltage dividers RA, RB, but rather between the resistor RA and node A. Specifically, the first terminal of the resistor RA is coupled (e.g., directly coupled) to terminal 100, and the second terminal of the resistor RA is coupled (e.g., directly coupled) to the drain terminal of the FET M0. The source terminal of the FET M0 is coupled (e.g., directly coupled) to node A, and the gate terminal of the FET M0 is coupled to the bias voltage VB, e.g., VDD. Accordingly, in the considered embodiment, the voltage VS is clamped / limited to the voltage VB - VT.

[0076] In various embodiments, the measurement circuit 20 may also include a switchable resistor RB, for example, the switchable resistor RB may be implemented using resistors RB1 and RB2 and an electronic switch MH.

[0077] Accordingly, Figure 8 The solution shown allows for a direct limitation of the voltage VS, which allows for a wider range of selection of the threshold voltage VTH of circuit 30. However, Figure 8 The solution shown has higher current consumption because the voltage VS may be higher, thus generating a higher current through the resistor RB (or equivalently RB1 + RB2).

[0078] In the following sections, alternative embodiments of the current measurement circuits 32 and 34 and the comparison circuit 36 ​​will be described. Generally, these circuits can be used with… Figure 3 , Figure 6 , Figure 7 and Figure 8 Any of the measurement circuits 20 shown will be used together. For example, in the considered embodiment, the following will be used: Figure 7 The measurement circuit 20 shown is general in nature.

[0079] Figure 9 One embodiment is shown in which current measurement circuits 32 and 34 are implemented using resistors RM1 and RM2, i.e., the collector of transistor Q1 is coupled (e.g., directly coupled) to voltage VDD via resistor RM1, and the collector of transistor Q2 is coupled (e.g., directly coupled) to voltage VDD via resistor RM2. Specifically, in various embodiments, resistors RM1 and RM2 are equal.

[0080] Accordingly, in the considered embodiment, the voltage at resistor RM1 is proportional to the current IQ1, and the voltage at resistor RM2 is proportional to the current IQ2. Accordingly, in the considered embodiment, the voltages CL1 and CL2 at the collector terminals of transistors Q1 and Q2 are respectively provided to comparator / operational amplifier 366, i.e., the first input terminal (e.g., the negative / inverting input terminal) of operational amplifier 366 is coupled (e.g., directly coupled) to the collector of transistor Q1, and the second input terminal (e.g., the positive / non-inverting input terminal) of operational amplifier 366 is coupled (e.g., directly coupled) to the collector of transistor Q2. Accordingly, based on the connections to the input terminals of operational amplifier 366, the output terminal of operational amplifier 366 can provide a signal PG or PGN.

[0081] For example, in the considered embodiment, the operational amplifier output is high when the voltage CL1 at transistor Q1 is lower than the voltage CL2 at transistor Q2 (indicating that current IQ1 is greater than current IQ2). Accordingly, in this case, the signal PG can correspond to the signal at the output of operational amplifier 366, or an even number of inverters (e.g., two inverters 362 and 364) can generate the signal PG based on that signal.

[0082] For example, using inverters 362 and 364, the PGN signal used by the electronic switch MH can correspond to the output of inverter 362.

[0083] However, through the input terminal of the inverting operational amplifier 366, the signal at the output terminal of the operational amplifier 366 can correspond to the signal PGN, and the inverter 362 can be omitted.

[0084] Figure 10 An embodiment of operational amplifier 366 is shown. Specifically, in the considered embodiment, the collector of transistor Q1 is coupled (e.g., directly coupled) to the gate of a first p-channel FET M1, i.e., the gate of FET M1 receives voltage CL1, and the collector of transistor Q2 is coupled (e.g., directly coupled) to the gate of a second p-channel FET M2, i.e., the gate of FET M2 receives voltage CL2.

[0085] Furthermore, in the considered embodiment, the source terminals of FETs M1 and M2 are coupled (e.g., directly coupled) to voltage VDD, and the drain terminals of FETs M1 and M2 are coupled to a current mirror comprising two n-channel FETs M3 and M4. Specifically, in the considered embodiment, the drain terminal of FET M3 is coupled (e.g., directly coupled) to the drain terminal of FET M1, the source terminal of FET M3 is coupled (e.g., directly coupled) to ground, the drain terminal of FET M4 is coupled (e.g., directly coupled) to the drain terminal of FET M2, and the source terminal of FET M4 is coupled (e.g., directly coupled) to ground. Moreover, the gate terminal of FET M3 is coupled (e.g., directly coupled) to the gate terminal of FET M4, which in turn is coupled (e.g., directly coupled) to the drain terminal of FET M4.

[0086] Accordingly, such as regarding Figure 6As described, in the considered embodiment, transistors M3 and M4 act as current sensors. Accordingly, in the considered embodiment, circuit 30 can be configured to generate a signal PG based on the voltage at the drain terminal of FET M3 (also indicated as node E). For example, in the considered embodiment, the voltage at the drain terminal of FET M3 drives the gate of n-channel FET M5; that is, the gate of FET M5 is coupled to node E. Specifically, FET M5 is coupled between node F and ground. In this case, pull-up resistor R4 can be coupled between node F and voltage VDD. Accordingly, in the considered embodiment, when current IQ1 is greater than current IQ2, voltage CL1 is lower than voltage CL2, thereby closing FET M5. Accordingly, in the considered embodiment, signal PGN can correspond to the voltage at node F, and an additional inverter 364 can be used to generate signal PG based on the voltage at node F.

[0087] In various embodiments, the gate terminal of transistor M1 may alternatively be coupled to the collector of transistor Q2, and the gate terminal of transistor M2 may be coupled to the collector of transistor Q1. In this case, the voltage at node F exhibits opposite behavior, and an additional inverter 362 can be used to generate a PGN signal based on the voltage at node F.

[0088] Moreover, with Figure 6 Similar to the discussion, FETs M3, M4, and M5 can be replaced by corresponding bipolar transistors, where the source terminal of the FET is replaced by the emitter terminal of the corresponding bipolar transistor, the drain terminal of the FET is replaced by the collector terminal of the corresponding bipolar transistor, and the gate terminal of the FET is replaced by the base terminal of the corresponding bipolar transistor.

[0089] Figure 11 and Figure 12 Alternative embodiments are shown, wherein Figure 9 and Figure 11 Resistors RM1 and RM2 have been replaced with p-channel FETs MM1 and MM2.

[0090] Specifically, in the considered embodiment, the collector of transistor Q1 is coupled (e.g., directly coupled) to the drain of FET MM1, and the source of FET MM1 is coupled (e.g., directly coupled) to the supply voltage VDD. Similarly, the collector of transistor Q2 is coupled (e.g., directly coupled) to the drain of FET MM2, and the source of FET MM2 is coupled (e.g., directly coupled) to the supply voltage VDD. Furthermore, the gate terminals of FETs MM1 and MM2 are coupled to the bias voltage VBIAS. To achieve the same resistance (for a given bias voltage), MM1 and MM2 have the same characteristics. Moreover, in many embodiments, MM1 and MM2 are not connected in a diode configuration.

[0091] For the rest, Figure 11 and Figure 12 The circuit shown is in accordance with the following Figure 9 and Figure 10 The embodiments discussed are operational, and the corresponding descriptions apply in general.

[0092] Accordingly, Figures 3 to 12 The various resistors shown can be implemented using discrete resistors, or via resistors in an integrated circuit of a sensing circuit (e.g., a track of a given length), or, as... Figure 11 and Figure 12 As shown, this is achieved by replacing the resistor with a properly biased FET.

[0093] Of course, without departing from the principles of the invention, the details of the construction and embodiments may be varied extensively with respect to the descriptions and illustrations herein which are merely examples, without departing from the scope of the invention as defined by the appended claims.

[0094] While this description has been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Identical elements are designated by the same reference numerals in the various figures. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as those skilled in the art will clearly recognize from this disclosure that existing or later-developed processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps within their scope.

[0095] Accordingly, the specification and drawings should be regarded as merely an illustration of this disclosure as defined by the appended claims, and are intended to cover any and all modifications, alterations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A voltage comparison circuit configured to assert a comparison signal in response to determining that an input voltage exceeds a given threshold voltage, the voltage comparison circuit comprising: First terminal and second terminal, the first terminal and second terminal being configured to receive input voltage; The third terminal is configured to receive the supply voltage; A measurement circuit configured to generate a measurement signal indicating an input voltage, wherein the measurement circuit includes a first resistor coupled between a first terminal and a first node, and a second resistor coupled between the first node and a second terminal, wherein the measurement signal corresponds to the voltage at the second resistor; A first NPN bipolar transistor and a second NPN bipolar transistor, each having a collector terminal, an emitter terminal, and a base terminal, wherein the collector terminals of the first and second NPN bipolar transistors are coupled to a third terminal, and the base terminals of the first and second NPN bipolar transistors are coupled to a first node, wherein the emitter area of ​​the second NPN bipolar transistor is larger than that of the first NPN bipolar transistor; A third resistor is coupled between the emitter terminal of the first NPN bipolar transistor and the second terminal, and a fourth resistor is coupled between the emitter terminal of the second NPN bipolar transistor and the emitter terminal of the first NPN bipolar transistor. as well as The comparator circuit is configured to: Determine whether the first current flowing through the collector terminal of the first NPN bipolar transistor is greater than the second current flowing through the collector terminal of the second NPN bipolar transistor. In response to determining that the first current is greater than the second current, an assertion is made on the comparison signal, and In response to determining that the first current is less than the second current, an assertion comparison signal is made. The measurement circuit includes an n-channel field-effect transistor (FET), wherein the n-channel FET and a first resistor are coupled in series between a first terminal and a first node, and the gate terminal of the n-channel FET is coupled to a bias voltage source.

2. The voltage comparator circuit of claim 1, wherein the gate terminal of the n-channel FET is coupled to the third terminal.

3. The voltage comparator circuit of claim 1, wherein the drain terminal of the n-channel FET is coupled to the first terminal and the source terminal of the n-channel FET is coupled to the first node via the first resistor.

4. The voltage comparator circuit of claim 1, wherein the source terminal of the n-channel FET is coupled to a first node and the drain terminal of the n-channel FET is coupled to a first terminal via a first resistor.

5. The voltage comparison circuit as claimed in claim 1, wherein the second resistor is switchable between a first resistance value and a second resistance value according to a comparison signal.

6. The voltage comparison circuit of claim 5, wherein the second resistor comprises two resistors coupled in series between the first node and the second terminal, and an electronic switch configured to short-circuit one of the two resistors when the comparison signal is de-asserted.

7. The voltage comparison circuit of claim 1, wherein the comparison circuit comprises: The first transistor of the first current mirror is coupled between the collector terminal and the third terminal of the first NPN bipolar transistor. The second transistor of the first current mirror is coupled between the collector terminal and the third terminal of the second NPN bipolar transistor. as well as A third transistor and a pull-down resistor are coupled between a third terminal and a second terminal, wherein the control terminal of the third transistor is coupled to the collector terminal of a first NPN bipolar transistor. The comparison signal is determined based on the voltage at the node between the third transistor and the pull-down resistor.

8. The voltage comparison circuit of claim 1, wherein the comparison circuit comprises: The fifth resistor is coupled between the collector terminal and the third terminal of the first NPN bipolar transistor; The sixth resistor is coupled between the collector terminal and the third terminal of the second NPN bipolar transistor; as well as An operational amplifier having a first input terminal coupled to the collector terminal of a first NPN bipolar transistor and a second input terminal coupled to the collector terminal of a second NPN bipolar transistor. The comparison signal is determined based on the voltage at the output of the operational amplifier.

9. The voltage comparator circuit of claim 8, wherein the operational amplifier comprises: The fourth transistor and the fifth transistor, wherein the control terminals of the fourth transistor and the fifth transistor are respectively coupled to the collector terminals of the first NPN bipolar transistor and the second NPN bipolar transistor; The second current mirror includes a sixth transistor coupled to the current path of a fourth transistor between the third terminal and the second terminal, and a seventh transistor coupled to the current path of a fifth transistor between the third terminal and the second terminal. as well as An eighth transistor and a pull-up resistor are coupled between the third terminal and the second terminal, wherein the control terminal of the eighth transistor is coupled to the intermediate node between the sixth transistor and the fourth transistor. The comparison signal is determined based on the voltage at the node between the eighth transistor and the pull-up resistor.

10. The voltage comparator circuit of claim 8, wherein the fifth resistor and the sixth resistor comprise respective p-channel field-effect transistors configured to receive bias voltages at their respective gate terminals.

11. A method for operating a voltage comparator circuit, the method comprising: The input voltage is received at the first and second terminals. The supply voltage is received at the third terminal; A measurement signal indicating the input voltage is generated via a measurement circuit, wherein the measurement circuit includes a first resistor coupled between a first terminal and a first node, and a second resistor coupled between the first node and a second terminal; The measurement signal is applied to the base terminals of the first NPN bipolar transistor and the second NPN bipolar transistor; The comparison circuit determines whether the first current flowing through the collector terminal of the first NPN bipolar transistor is greater than the second current flowing through the collector terminal of the second NPN bipolar transistor. The comparison signal is asserted in response to determining that the first current is greater than the second current. In response to determining that the first current is less than the second current, assert the comparison signal; as well as The measurement signal is limited by using an n-channel field-effect transistor (FET) coupled in series with a first resistor between the first terminal and the first node.

12. The method of claim 11, wherein the gate terminal of the n-channel FET is coupled to a third terminal.

13. The method of claim 11, wherein limiting the measurement signal comprises: Couple the drain terminal of the n-channel FET to the first terminal; as well as The source terminal of the n-channel FET is coupled to the first node via a first resistor.

14. The method of claim 11, further comprising switching the second resistor between the first resistor value and the second resistor value based on a comparison signal.

15. The method of claim 14, wherein switching the second resistor includes short-circuiting one of the two resistors series coupled between the first node and the second terminal when the comparison signal is deasserted.

16. An integrated circuit, the integrated circuit including a voltage comparison circuit configured to assert a comparison signal in response to determining that an input voltage exceeds a given threshold voltage, the voltage comparison circuit including: First terminal and second terminal, the first terminal and second terminal being configured to receive input voltage; The third terminal is configured to receive the supply voltage; A measurement circuit configured to generate a measurement signal indicating an input voltage, wherein the measurement circuit includes a first resistor coupled between a first terminal and a first node, a second resistor coupled between the first node and a second terminal, and an n-channel field-effect transistor (FET) coupled in series with the first resistor between the first terminal and the first node, wherein the gate terminal of the n-channel FET is coupled to a bias voltage source, and wherein the measurement signal corresponds to the voltage at the second resistor; A first NPN bipolar transistor and a second NPN bipolar transistor, each having a collector terminal, an emitter terminal, and a base terminal, wherein the collector terminals of the first and second NPN bipolar transistors are coupled to a third terminal, and the base terminals of the first and second NPN bipolar transistors are coupled to a first node, wherein the emitter area of ​​the second NPN bipolar transistor is larger than that of the first NPN bipolar transistor; A third resistor coupled between the emitter terminal of the first NPN bipolar transistor and the second terminal, and a fourth resistor coupled between the emitter terminal of the second NPN bipolar transistor and the emitter terminal of the first NPN bipolar transistor; as well as A comparator circuit configured to determine whether a first current flowing through the collector terminal of a first NPN bipolar transistor is greater than a second current flowing through the collector terminal of a second NPN bipolar transistor, assert a comparison signal in response to determining that the first current is greater than the second current, and deassert the comparison signal in response to determining that the first current is less than the second current.

17. The integrated circuit of claim 16, further comprising a power management unit configured to change operation according to a comparison signal.

18. The integrated circuit of claim 16, wherein the gate terminal of the n-channel FET is coupled to a third terminal.

19. The integrated circuit of claim 16, wherein the second resistor is switchable between a first resistance value and a second resistance value according to a comparison signal.

20. The integrated circuit of claim 16, wherein the comparator circuit comprises: The first transistor of the first current mirror is coupled between the collector terminal and the third terminal of the first NPN bipolar transistor. The second transistor of the first current mirror is coupled between the collector terminal and the third terminal of the second NPN bipolar transistor. as well as A third transistor and a pull-down resistor are coupled between a third terminal and a second terminal, wherein the control terminal of the third transistor is coupled to the collector terminal of a first NPN bipolar transistor. The comparison signal is determined based on the voltage at the node between the third transistor and the pull-down resistor.

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