Capacitance detection circuit and electronic device

Abstract

This invention provides a capacitance detection circuit and electronic device, comprising a timing generation circuit, a capacitance detection clock circuit, a time-division sampling circuit, a time-division comparison circuit, and an execution determination circuit. It can perform time-division sampling of the capacitance-related clock count values ​​output by the capacitance detection clock circuit at n time nodes through the timing generation circuit and the time-division sampling circuit. The time-division comparison circuit compares each sampled time-division threshold frequency with a reference frequency to obtain an n-bit signal. Furthermore, the execution determination circuit can determine the capacitance variation range based on the n-bit signal, thereby performing subsequent processing. This eliminates the step of "the difference between the frequency sample value and the reference frequency value" in existing technologies, simplifying circuit design.

Description

Technical Field

[0001] This invention relates to the field of capacitance detection technology, and in particular to a capacitance detection circuit and electronic device. Background Technology

[0002] Currently, capacitance detection technology typically obtains relevant information or performs subsequent processing by detecting changes in capacitance, and is widely used in touchscreens, microphones, airflow detectors, and other fields. Especially in the field of airflow detectors, it can determine whether there is gas flow (including inflow and outflow) within the airflow channel where the detector is located by detecting changes in capacitance.

[0003] Existing capacitance detection schemes generally require a step to calculate the difference between the frequency sample value (which is obtained by converting the capacitance change value) and the reference frequency value. The circuit design is relatively complex and is not conducive to reducing the circuit area and reducing the circuit power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a capacitance detection circuit and electronic device that can simplify the capacitance detection scheme.

[0005] To achieve the above objectives, the present invention provides a capacitance detection circuit, comprising:

[0006] A timing generation circuit is used to generate a reference sampling pulse signal at a reference time node and to generate n time-division sampling pulse signals at n time-division time nodes different from the reference time node, where n is an integer greater than 1;

[0007] A capacitor detection clock circuit is coupled to the timing generation circuit and is used to charge and discharge the capacitor with a preset current, and output a clock count value that is inversely proportional to the capacitance value.

[0008] The time-division sampling circuit is coupled to the timing generation circuit and the capacitor detection clock circuit, and is used to sample the clock count value through the reference sampling pulse signal to obtain a reference frequency, and to sample the clock count value through n time-division sampling pulse signals to obtain n different time-division threshold frequencies;

[0009] The time-division comparison circuit, coupled to the time-division sampling circuit, is used to compare the n time-division threshold frequencies with the reference frequency respectively, and output the comparison result as an n-bit signal.

[0010] An execution determination circuit is coupled to the time-division comparison circuit and is used to determine the range of change of the capacitor based on the n-bit signal.

[0011] Optionally, the capacitance detection clock circuit includes:

[0012] An oscillator having the capacitor and used to generate a clock signal according to the charging and discharging of the capacitor, the frequency of the clock signal being inversely proportional to the capacitance value;

[0013] A clock counter, coupled to the oscillator, is used to count the clock signal output by the oscillator to obtain the clock count value.

[0014] Optionally, the time-division sampling circuit includes:

[0015] A reference frequency latch circuit is coupled to the capacitor detection clock circuit and the timing generation circuit, and is used to sample the clock count value through the reference sampling pulse signal to obtain and store the reference frequency;

[0016] The time-division threshold frequency latch circuit is coupled to the capacitor detection clock circuit and the timing generation circuit, and is used to sample the clock count value through n time-division sampling pulse signals to obtain the time-division threshold frequency.

[0017] Optionally, the time-division threshold frequency latching circuit is a time-division multiplexing circuit, which samples the clock count value in the order of the time nodes of the n time-division sampling pulse signals, and when storing the sampling results, the time-division threshold frequency obtained by the later sampling is used to cover the time-division threshold frequency obtained by the previous sampling.

[0018] Alternatively, the time-division threshold frequency latch circuit has n time-division threshold frequency latch branches, each of which is coupled to one of the n time-division sampling pulse signals and is also coupled to the capacitor detection clock circuit. Each of the time-division threshold frequency latch branches is used to sample the clock count value through the coupled time-division sampling pulse signal to obtain and store the corresponding time-division threshold frequency.

[0019] Optionally, the time-division comparison circuit includes:

[0020] A frequency value comparator is coupled to the reference frequency latch circuit and the time-division threshold frequency latch circuit, and is used to compare the time-division threshold frequency stored in the time-division threshold frequency latch circuit with the reference frequency.

[0021] The time-division result storage circuit is coupled to the frequency value comparator and the timing generation circuit, and is used to output the comparison results of the n time-division threshold frequencies output by the frequency value comparator with the reference frequency as the n-bit signal.

[0022] Optionally, the time-division comparison circuit includes n frequency value comparators, each corresponding to one of the n time-division threshold frequency latch circuits, and all of them are coupled to the execution determination circuit. Each frequency value comparator is used to compare the time-division threshold frequency output by the time-division threshold frequency latch circuit to which it is coupled with the reference frequency, and output the comparison result to the execution determination circuit. The comparison results output by the n frequency value comparators together constitute the n-bit signal.

[0023] Optionally, the execution determination circuit includes:

[0024] A threshold range determination circuit is coupled to the time-division comparison circuit and is used to determine the range of the clock count value based on the n-bit signal, thereby determining the range of the capacitor change, and performing subsequent processing based on the determination result of the range of the clock count value.

[0025] A reference frequency update determination circuit is coupled to the time-division comparison circuit and is used to determine whether the range of the clock count value is within a specific range and exceeds the corresponding reference time threshold based on the n-bit signal. If so, an update signal is output to update the reference frequency.

[0026] Optionally, n=4, the capacitor is a detection capacitor set in the corresponding airflow channel, and the threshold range determination circuit has four frequency threshold slopes S1 to S4 with gradually decreasing slopes, with the following conditions:

[0027] (1) If the output slope of the clock count value is between S2 and S3, it is determined that the capacitance value of the capacitor has not changed, indicating that there is no gas flow in the airflow channel;

[0028] (2) If the output slope of the clock count value is between S1 and S2 or between S3 and S4, it is determined that the capacitance value of the capacitor has changed slightly, and when the time when the output slope of the clock count value is between S1 and S2 or between S3 and S4 exceeds the reference time threshold, the reference frequency is updated.

[0029] (3) If the output slope of the clock count value is above S1, it is determined that the capacitance value of the capacitor has decreased significantly, indicating that gas is flowing into the airflow channel.

[0030] (4) If the output slant of the clock count value is below S4, it is determined that the capacitance value of the capacitor has increased significantly, indicating that gas is flowing out of the airflow channel.

[0031] Based on the same inventive concept, the present invention also provides an electronic device having a capacitance detection circuit as described in the present invention.

[0032] Optionally, the electronic device is a touch screen, a microphone, or an airflow detector. When the electronic device is an airflow detector, the airflow detector is set in the corresponding airflow channel, and the capacitance change detected by the capacitance detection circuit is used to reflect whether there is gas flow in the airflow channel.

[0033] Compared with the prior art, the capacitance detection circuit and electronic device of the present invention have a timing generation circuit, a capacitance detection clock circuit, a time-division sampling circuit, a time-division comparison circuit, and an execution determination circuit. It can perform time-division sampling of the clock count value related to capacitance output by the capacitance detection clock circuit at n time nodes through the timing generation circuit and the time-division sampling circuit, and use the time-division comparison circuit to compare each sampled time-division threshold frequency with the reference frequency to obtain an n-bit signal. The execution determination circuit can determine the range of capacitance change based on the n-bit signal, thereby performing subsequent processing. This eliminates the step of "difference between frequency sampling value and reference frequency value" in the prior art, simplifying the circuit design.

[0034] Furthermore, the capacitance detection circuit and electronic device of the present invention can be applied to fields such as touch screens, microphones, and airflow detectors. For example, when applied to the field of airflow detectors, it can determine whether there is gas flow (including inflow and outflow) in the airflow channel where the airflow detector is located by detecting changes in capacitance. Attached Figure Description

[0035] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0036] Figure 1 This is a schematic diagram of the architecture of a capacitance detection circuit according to an embodiment of the present invention.

[0037] Figure 2 and Figure 3 These are schematic diagrams of two example curves when the capacitance detection circuit of an embodiment of the present invention performs a determination.

[0038] Figures 4 to 6 These are schematic diagrams illustrating three example structures of a capacitance detection circuit according to an embodiment of the present invention. Detailed Implementation

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0040] Please refer to Figure 1 An embodiment of the present invention provides a capacitance detection circuit, which includes a timing generation circuit 10, a capacitance detection clock circuit 11, a time-division sampling circuit 12, a time-division comparison circuit 13, and an execution determination circuit 14.

[0041] The timing generation circuit 10 can generate timing signals to control the working sequence among circuit modules such as the capacitance detection clock circuit 11, the time-sharing sampling circuit 12, the time-sharing comparison circuit 13, and the execution determination circuit 14. In this embodiment, the timing signals generated by the timing generation circuit 10 include: a reference sampling pulse signal generated at the reference time node Tref, n time-sharing sampling pulse signals generated at n time-sharing time nodes T1 to Tn different from the reference time node Tref, a clock signal CLKd for controlling the operation of the execution determination circuit 14, and a clear signal CNT_RN for clearing (or "resetting", "resetting", or "resetting") the clock count value Qin output by the capacitance detection clock circuit 11 at the end of one working cycle. Among them, n is an integer greater than 1, T1 < Tref < Tn, and for the convenience of marking these pulse signals in each figure, the reference sampling pulse signal generated at the reference time node Tref is also denoted as "Tref", and the time-sharing sampling pulse signals generated at each time-sharing time node T1 to Tn are also denoted as "T1 to Tn". In addition, the clear signal CNT_RN causes the capacitance detection clock circuit 11 to re-count, so that the capacitance detection circuit starts a new working cycle.

[0042] The capacitance detection clock circuit 11 is coupled to the timing generation circuit 10 and the time-sharing sampling circuit 12 and has a capacitance C to be measured. The capacitance detection clock circuit 11 is used to charge and discharge the capacitance C through a preset current (not shown, the preset current can be a constant current with a constant magnitude), so as to output a clock count value Qin = β * T / C inversely proportional to the capacitance value of the capacitance C. In this formula, β is a coefficient related to the charging and discharging current of the capacitance, T is time, and C is the capacitance value. When C remains unchanged, the clock count value Qin at the reference time node (which can be a fixed time node within one working cycle) Tref is Qin = Q

[0043] When C changes by a Δ value, T also changes by the corresponding Δ, and Qin remains unchanged. Then there is:

[0043]

[0044] As can be seen from the above formula, within one working cycle (or "sampling cycle"), when C remains unchanged, the clock count value Qin is linearly related to time T.

[0045] The time-sharing sampling circuit 12 is coupled to the timing generation circuit 10, the capacitance detection clock circuit 11, the time-sharing comparison circuit 13, and the execution determination circuit 14, and is used to sample the clock count value Qin through the reference sampling pulse signal Tref to obtain the reference frequency Q [[ID=~15]] Tref (Optionally, further Q Tref(Record or store), and obtain n different time-division threshold frequencies Q by sampling the clock count value Qin through n time-division sampling pulse signals T1~Tn. T1 ~Q Tn (Optionally, Q) T1 ~Q Tn (Record or store), and Q can be updated in real time according to the update signal output by the execution determination circuit 14. Tref .

[0046] The time-division comparison circuit 13 is coupled to the time-division sampling circuit 12 and the execution decision circuit 14, and is used to divide the n time-division threshold frequencies Q T1 ~Q Tn Respectively compared with the reference frequency Q Tref Perform a size comparison and output the comparison result as an n-bit signal D. <n:1>(It can also be written as "D1~Dn").

[0047] The execution decision circuit 14 is coupled to the time-division comparison circuit 13 and the timing generation circuit 10, and is used to determine the n-bit signal D. <n:1>Determine the range of change of capacitor C, and then output an update signal Update based on the determination result and perform subsequent processing.

[0048] In one example, please refer to Figure 2 With n=2, the operation of the capacitance detection circuit in this embodiment is as follows:

[0049] First, after power-on, the time-division sampling circuit 12 samples the clock count value Qin output by the capacitor detection clock circuit 11 multiple times at the reference time node Tref, and records it as the reference frequency Q. Tref ,get Figure 2 The reference frequency reference line (i.e., a reference slant line) Sref is initialized, and then the working cycle begins. In addition, the execution determination circuit 14 also has preset... Figure 2 The frequency threshold slash S1 (used to determine if the Qin frequency is too high) and Figure 2 The frequency threshold slope S2 (used to determine whether the Qin frequency is too low) is in the middle, and the reference frequency line Sref is between S1 and S2, that is, the slopes of S1, Sref and S2 decrease in sequence.

[0050] Next, in each working cycle, the time-division sampling circuit 12 generates sampling pulse signals at each time-division time node T1, Tref, and T2, and samples the clock count value Qin output by the capacitance detection clock circuit 11, recording it as the time-division threshold frequency Q. T1 Reference frequency Q Tref and time-division threshold frequency Q T2 The time-division comparator circuit 13 will compare Q... T1 Q T2 respectively with Q Tref The comparison outputs a 2-bit signal D<2:1> (i.e., D1 and D2), where D1 is "1", indicating that Q... T1 Q Tref D1 is "0", indicating that Q T1 Tref D2 being "1" indicates that Q T2 Q Tref When D2 is "0", it means Q T2 Tref .

[0051] Then, after T2 is completed, the judgment circuit 14 determines the frequency range of Qin based on D<2:1>, thereby determining the range of capacitance change and performing subsequent processing. Simultaneously, the timing generation circuit 10 outputs the CNT_RN signal to clear Qin and begin a new working cycle. Specifically, when Q is sampled in T1... T1 Q Tref ​​When the execution determination circuit 14 determines that the Qin frequency is too high and exceeds the threshold (i.e., the Q frequency recorded by the time-division sampling circuit 12 is too high), the determination circuit 14 determines that the Qin frequency is too high and exceeds the threshold (i.e., the Q frequency recorded by the time-division sampling circuit 12 is too high). T1 Q Tref and Q T2 When the determined Qin output slope is above S1, the capacitance value of capacitor C decreases significantly, and the decrease Δ exceeds the corresponding threshold, thus allowing for appropriate subsequent processing (e.g., issuing a prompt); when Q is sampled at T2... T2 Tref When the time-division sampling circuit 14 determines that the Qin frequency is too low (i.e., the Q frequency recorded by the time-division sampling circuit 11 is too low), the decision circuit 14 determines that the Qin frequency is too low (i.e., the Q frequency recorded by the time-division sampling circuit 11 is too low). T1 Q Tref and Q T2 When the determined output slope of Qin is below S2, the capacitance of capacitor C increases significantly, and the increase Δ exceeds the corresponding threshold, which can be used for subsequent processing (e.g., issuing a prompt to the user); when Q is sampled in T1... T1 Q sampled with T2 T2 All are between S1 and S2 (i.e., Q is recorded by the time-division sampling circuit 12). T1 Q Tref and Q T2 When the determined Qin is between S1 and S2, the determination circuit 14 determines that the capacitance value of capacitor C does not increase or decrease significantly, and no further processing is required.

[0052] In another example, please refer to Figure 3 n=4, and capacitor C is a detection capacitor set in the corresponding airflow channel. The capacitor detection circuit in this embodiment can reflect whether there is gas flow in the airflow channel by detecting whether the capacitance changes. Its working process is as follows:

[0053] First, after power-on, the time-division sampling circuit 12 samples the clock count value Qin output by the capacitor detection clock circuit 11 multiple times at the reference time node Tref, and records it as the reference frequency Q. Tref ,get Figure 3 The reference frequency line (i.e., a reference slope) Sref is initialized, and then the working cycle begins. In addition, the execution judgment circuit 14 also presets frequency threshold slopes arranged from top to bottom: S1 (used to determine whether the Qin frequency is too high), S2 (used to determine whether the Qin frequency is too high due to environmental changes), S3 (used to determine whether the Qin frequency is too low due to environmental changes), and S4 (used to determine whether the Qin frequency is too low). The reference frequency line Sref is between S2 and S3, and the slopes of S1, S2, Sref, S3, and S4 decrease sequentially.

[0054] ​Next, in each working cycle, the time-division sampling circuit 12 generates sampling pulse signals at each time-division time node T1, T2, Tref, T3, and T4, and samples the clock count value Qin output by the capacitance detection clock circuit 11, recording it as the time-division threshold frequency Q. T1 Q T2 Reference frequency Q Tref and time-division threshold frequency, Q T3 Q T4 The time-division comparator circuit 13 will compare Q... T1 Q T2 Q T3 Q T4 respectively with Q Tref The comparison outputs a 4-bit signal D<4:1> (i.e., D1, D2, D3, D4), where D1 is "1", indicating that Q... T1 Q Tref D1 is "0", indicating that Q T1 Tref D2 being "1" indicates that Q T2 Q Tref When D2 is "0", it means Q T2 Tref D3 being "1" indicates that Q T3 Q Tref When D3 is "0", it means Q T3 Tref D4 being "1" indicates that Q T4 Q Tref When D4 is "0", it means Q T4 Tref .

[0055] Then, after T4 completes, the execution determination circuit 14 determines the frequency range of Qin based on D<4:1>, thereby determining the range of capacitance variation and performing subsequent processing. Simultaneously, the timing generation circuit 10 outputs the CNT_RN signal to clear Qin and begin a new working cycle. The execution determination circuit 14 has the following four determination results:

[0056] (1) Determine Q T1 Q T2 Q T3 Q T4 All are between S2 and S3 (i.e., Q is recorded by the time-division sampling circuit 12). T1 Q T2 Q T3 Q T4 ​​​​If the determined Qin output slope is between S2 and S3, it can be determined that the capacitance value of capacitor C has not changed (i.e., there is no change exceeding the threshold). Therefore, it can be determined that there is no gas flow in the airflow channel where capacitor C is located (i.e., no gas flows in or out of the airflow channel), and no further processing is required (e.g., no prompt or reminder is issued).

[0057] (2) Determine Q T1 Q T2 Q T3 Q T4 Each of them lies between S1 and S2 or between S3 and S4 (i.e., by Q). T1 Q T2 Q T3 Q T4 If the determined Qin output slope is between S1 and S2 or between S3 and S4, then it can be determined that there is a slight change in capacitor C (which may be caused by environmental changes). If this slight change in capacitor C exceeds the reference time threshold (i.e., a certain time), then the determination circuit 14 outputs the update signal Update to update the sampling result at the Tref time with the new Q. Tref That is, updating the reference frequency Q Tref .

[0058] (3) Determine Q T1 Q T2 Q T3 Q T4 Most of them (e.g., 3 or 4 of them) are above S1 (i.e., by Q). T1 Q T2 Q T3 Q T4 If the determined Qin output slope is above S1, it can be determined that the capacitance value of capacitor C has decreased significantly, and thus it can be determined that there is gas flowing into the airflow channel where the capacitor is located.

[0059] (4) Determine Q T1 Q T2 Q T3 Q T4 Most of them (e.g., 3 or 4 of them) are below S4 (i.e., by Q). T1 Q T2 Q T3 Q T4 If the determined Qin output slope is below S4, it can be determined that the capacitance of capacitor C has increased significantly, and thus it can be determined that there is gas flowing out of the airflow channel where the capacitor is located.

[0060] It should be understood that the larger the value of n and the more frequency threshold slashes are set, the more accurate and detailed the judgment result will be, which will also be conducive to further refinement of subsequent processing.

[0061] In this embodiment, the timing generation circuit 10, the capacitor detection clock circuit 11, the time-division sampling circuit 12, the time-division comparison circuit 13, and the execution determination circuit 14 can adopt any suitable circuit design, and the present invention does not impose any specific limitations on them.

[0062] Alternatively, please refer to Figure 4 The capacitance detection clock circuit 11 includes an oscillator 111 and a clock counter 112. The oscillator 111 has a capacitor C to be detected and generates a clock signal Clk based on the charging and discharging of the capacitor C. The frequency of the clock signal Clk is inversely proportional to the capacitance value of the capacitor C. The clock counter 112 is coupled to the oscillator 111 and the timing generation circuit 10, and counts the clock signal Clk output by the oscillator 111 in each working cycle of the capacitance detection circuit to obtain a clock count value Qin, which is then output to the time-division sampling circuit 12. At the end of one working cycle, the clock counter 112 clears its clock count value Qin according to the clear signal CNT_RN provided by the timing generation circuit 10, so that it can start counting again in the next working cycle to obtain the clock count value Qin for the next working cycle.

[0063] Alternatively, please refer to Figure 4 The time-division sampling circuit 12 includes a reference frequency latch circuit 121 and a time-division threshold frequency latch circuit 122. The reference frequency latch circuit 121 is coupled to the timing generation circuit 10 to receive the reference sampling pulse signal Tref and n time-division sampling pulse signals T1 to Tn generated by the timing generation circuit 10. It is also coupled to the capacitor detection clock circuit 11 to sample the clock count value Qin using the reference sampling pulse signal Tref in each working cycle (i.e., sampling Qin at the reference time node Tref) to obtain the reference frequency Q. Tref and Q Tref Storage (or Q) Tref The clock count value Qin is "buffered" or "latched" and sampled using time-division sampling pulse signals T1 to Tn (i.e., Qin is sampled at time nodes T1 to Tn respectively) to obtain the time-division threshold frequency Q. T1 ~Q Tn .

[0064] In one example, please refer to Figure 4 The time-division threshold frequency latch circuit 122 is a time-division multiplexing circuit. Within each working cycle of the capacitor detection circuit, it samples the clock count value Qin in the order of n time-division time nodes T1 to Tn. When storing the sampling result (i.e., the time-division threshold frequency), the time-division threshold frequency obtained from the later sampling is used to overwrite the time-division threshold frequency obtained from the previous sampling (i.e., the time-division threshold frequency latch circuit 122 only stores the latest time-division threshold frequency obtained from the sampling, to reduce storage capacity requirements). At this time, each time the time-division threshold frequency latch circuit 122 updates the recorded time-division threshold frequency, the time-division comparison circuit 13 immediately compares the latest time-division threshold frequency with Q. Tref The size is compared and the result of each comparison is stored. The result of each subsequent comparison will not overwrite the result of the previous comparison, thus obtaining an n-bit signal.

[0065] In another example, please refer to Figure 5 The time-division threshold frequency latch circuit can also have n parallel time-division threshold frequency latch branches 1 to n. Each time-division threshold frequency latch branch 1 to n is coupled one-to-one with n time-division sampling pulse signals T1 to Tn, and is also coupled to the capacitor detection clock circuit 11. Each time-division threshold frequency latch branch is used to sample the clock count value Qin through the coupled time-division sampling pulse signal to obtain and store the corresponding time-division threshold frequency. For example, in each working cycle of the capacitor detection circuit, the time-division threshold frequency latch branch 1 samples the clock count value Qin through the time-division sampling pulse signal T1 (i.e., samples Qin at the time-division time node T1 respectively) to obtain the time-division threshold frequency Q. T1 and Q T1 The time-division threshold frequency latch branch 2 samples the clock count value Qin using the time-division sampling pulse signal T2 during each working cycle of the capacitor detection circuit (i.e., samples Qin at the time-division time node T2 respectively) to obtain the time-division threshold frequency Q. T2 and Q T2 The data is stored; similarly, in each working cycle of the capacitor detection circuit, the time-division threshold frequency latch branch n-1 samples the clock count value Qin through the time-division sampling pulse signal Tn-1 (i.e., samples Qin at the time-division time node Tn-1 respectively) to obtain the time-division threshold frequency Q. Tn-1 and Q Tn-1 The time-division threshold frequency latch branch n samples the clock count value Qin using the time-division sampling pulse signal Tn during each working cycle of the capacitor detection circuit (i.e., samples Qin at each time-division time node Tn) to obtain the time-division threshold frequency Q. Tn and Q Tn Save it.

[0066] Please refer to Figure 4 and Figure 5 In one example, the time-division comparison circuit 13 includes a frequency value comparator 131 and a time-division result storage circuit 132. Both the frequency value comparator 131 and the time-division result storage circuit 132 are time-division multiplexed circuits. The frequency value comparator 131 is coupled to a reference frequency latch circuit 121 and a time-division threshold frequency latch circuit 122 (or...). Figure 5 The n-channel time-division threshold frequency latch branches shown are 1 to n, and are used to, in each working cycle, according to the order of time nodes T1 to Tn, latch the time-division threshold frequency circuit 122 (or... Figure 5 The time-division threshold frequency Q stored in the n-channel time-division threshold frequency latch branches (1 to n) shown is... T1 ~Q Tn Each one is respectively compared with the reference frequency Q Tref By comparison, the output and the time-division threshold frequency Q are obtained successively. T1 ~Q Tn Alternatively, the comparison results C1 to Cn corresponding to T1 to Tn. The time-division result storage circuit 132 is coupled to the frequency value comparator 131 and the timing generation circuit 10, and is used to store the comparison results C1 to Cn output by the frequency value comparator 131 during the time period T1 to Tn in the order of T1 to Tn within each working cycle, thereby outputting the corresponding n-bit signal D. <n:1>.

[0067] Please refer to Figure 6 In another example, the time-division threshold frequency latch circuit has n parallel time-division threshold frequency latch branches 1 to n. The time-division comparison circuit 13 includes n parallel frequency value comparators 1 to n. The frequency value comparators 1 to n are coupled one-to-one with the time-division threshold frequency latch branches 1 to n, and the outputs of the frequency value comparators 1 to n are all coupled to the execution decision circuit 14. Each frequency value comparator is used to compare the time-division threshold frequency output by the time-division threshold frequency latch branch it is coupled with the reference frequency Q. Tref The comparison results are then output to the execution decision circuit 14. The comparison results output by frequency value comparators 1 to n within the same working cycle together constitute an n-bit signal D. <n:1>For example, frequency value comparator 1 will output the time-division threshold frequency Q from time-division threshold frequency latch branch 1. T1 With reference frequency Q Tref The comparison is performed to obtain the comparison result D1; the frequency value comparator 2 outputs the time-division threshold frequency Q from the time-division threshold frequency latch branch 2. T2 With reference frequency Q Tref The comparison is performed to obtain the comparison result D2; and so on, the frequency value comparator n-1 will output the time-division threshold frequency Q from the time-division threshold frequency latch branch n-1. Tn-1 With reference frequency Q Tref The comparison is performed to obtain the comparison result Dn-1; the frequency value comparator n will output the time-division threshold frequency Q from the time-division threshold frequency latch branch n. Tn With reference frequency Q Tref The comparison is performed to obtain the comparison result Dn; and D1 to Dn constitute an n-bit signal D. <n:1>.

[0068] Alternatively, please refer to Figures 4 to 6 The execution determination circuit 14 includes a threshold range determination circuit 142 and a reference frequency update determination circuit 141. The threshold range determination circuit 142 is coupled to the time-division comparison circuit 13 and is used to determine the frequency based on the n-bit signal D output by the time-division comparison circuit 13. <n:1>The range of the clock count value Qin is determined, thereby determining the range of change in capacitor C, and subsequent processing is performed based on the determination result of the range of the clock count value Qin. The reference frequency update determination circuit 141 is coupled to the time-division comparison circuit 13 and is used to determine the range of change in capacitor C based on the n-bit signal D output by the time-division comparison circuit 13. <n:1>If the clock count value Qin is within a specific range and exceeds the corresponding reference time threshold, an update signal Update is output to update the reference frequency Q stored in the reference frequency latch circuit 121. Tref .

[0069] Based on the same inventive concept, please refer to Figures 1 to 6 An embodiment of the present invention also provides an electronic device having a capacitance detection circuit as described in the present invention.

[0070] Optionally, the electronic device is a touchscreen, a microphone, or an airflow detector. When the electronic device is an airflow detector, the airflow detector is disposed in a corresponding airflow channel, and the capacitance change detected by the capacitance detection circuit is used to reflect whether there is gas flow in the airflow channel.

[0071] For example, the airflow detector is disposed in a corresponding airflow channel and includes a gas sensor and the capacitance detection circuit of the present invention. The capacitance detection circuit is integrated into the chip of the airflow detector, so that, based on the determination result of the execution determination circuit 14 in the capacitance detection circuit, it can be determined whether there is gas flowing in or out of the airflow channel.

[0072] The airflow detector can also integrate hardware such as a rechargeable battery, display screen, indicator lights, and sound effects. If there is no air flow in the airflow channel where the airflow detector is located for an extended period, the chip of the airflow detector can be controlled to enter a sleep state, activating a low-power operating mode. If the airflow detector detects air flowing out of its airflow channel, it can control the chip of the airflow detector to respond to the airflow, and simultaneously notify the user of the airflow through sound, lights, or the display screen. If the airflow detector detects air flowing into its airflow channel, it can control the chip of the airflow detector to respond to the airflow, and simultaneously notify the user of the airflow through sound, lights, or the display screen.

[0073] In summary, the capacitance detection circuit and electronic device of the present invention include a timing generation circuit, a capacitance detection clock circuit, a time-division sampling circuit, a time-division comparison circuit, and an execution determination circuit. It can perform time-division sampling of the capacitance-related clock count values ​​output by the capacitance detection clock circuit at n time nodes through the timing generation circuit and the time-division sampling circuit. The time-division comparison circuit compares each sampled time-division threshold frequency with a reference frequency to obtain an n-bit signal. Furthermore, the execution determination circuit can determine the capacitance variation range based on the n-bit signal, thereby performing subsequent processing. This eliminates the step of "the difference between the frequency sample value and the reference frequency value" in the prior art, simplifying circuit design and making it applicable to any suitable field such as touchscreens, microphones, and airflow detectors.

[0074] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A capacitance detection circuit, characterized by, include: A timing generation circuit is used to generate a reference sampling pulse signal at a reference time node and to generate n time-division sampling pulse signals at n time-division time nodes different from the reference time node, where n is an integer greater than 1; A capacitor detection clock circuit is coupled to the timing generation circuit and is used to charge and discharge the capacitor with a preset current, and output a clock count value that is inversely proportional to the capacitance value. The time-division sampling circuit is coupled to the timing generation circuit and the capacitor detection clock circuit, and is used to sample the clock count value through the reference sampling pulse signal to obtain a reference frequency, and to sample the clock count value through n time-division sampling pulse signals to obtain n different time-division threshold frequencies; The time-division comparison circuit, coupled to the time-division sampling circuit, is used to compare the n time-division threshold frequencies with the reference frequency respectively, and output the comparison result as an n-bit signal. An execution determination circuit is coupled to the time-division comparison circuit and is used to determine the range of change of the capacitor based on the n-bit signal.

2. The capacitance detection circuit as described in claim 1, characterized in that, The capacitance detection clock circuit includes: An oscillator having the capacitor and used to generate a clock signal according to the charging and discharging of the capacitor, the frequency of the clock signal being inversely proportional to the capacitance value; A clock counter, coupled to the oscillator, is used to count the clock signal output by the oscillator to obtain the clock count value.

3. The capacitance detection circuit as described in claim 1, characterized in that, The time-division sampling circuit includes: A reference frequency latch circuit is coupled to the capacitor detection clock circuit and the timing generation circuit, and is used to sample the clock count value through the reference sampling pulse signal to obtain and store the reference frequency; The time-division threshold frequency latch circuit is coupled to the capacitor detection clock circuit and the timing generation circuit, and is used to sample the clock count value through n time-division sampling pulse signals to obtain the time-division threshold frequency.

4. The capacitance detection circuit as described in claim 3, characterized in that, The time-division threshold frequency latch circuit is a time-division multiplexing circuit, which samples the clock count value in the order of the time nodes of the n time-division sampling pulse signals, and when storing the sampling results, the time-division threshold frequency obtained by the later sampling is used to cover the time-division threshold frequency obtained by the previous sampling. Alternatively, the time-division threshold frequency latch circuit has n time-division threshold frequency latch branches, each of which is coupled to one of the n time-division sampling pulse signals and is also coupled to the capacitor detection clock circuit. Each of the time-division threshold frequency latch branches is used to sample the clock count value through the coupled time-division sampling pulse signal to obtain and store the corresponding time-division threshold frequency.

5. The capacitance detection circuit as described in claim 4, characterized in that, The time-division comparison circuit includes: A frequency value comparator is coupled to the reference frequency latch circuit and the time-division threshold frequency latch circuit, and is used to compare the time-division threshold frequency stored in the time-division threshold frequency latch circuit with the reference frequency. The time-division result storage circuit is coupled to the frequency value comparator and the timing generation circuit, and is used to output the comparison results of the n time-division threshold frequencies output by the frequency value comparator with the reference frequency as the n-bit signal.

6. The time-division threshold frequency latch circuit as described in claim 4, characterized in that, The time-division comparison circuit includes n frequency value comparators, each corresponding to one of the n time-division threshold frequency latch circuits, and all are coupled to the execution determination circuit. Each frequency value comparator is used to compare the time-division threshold frequency output by the time-division threshold frequency latch circuit it is coupled to with the reference frequency, and outputs the comparison result to the execution determination circuit. The comparison results output by the n frequency value comparators together constitute the n-bit signal.

7. The capacitance detection circuit as described in any one of claims 1-6, characterized in that, The execution determination circuit includes: A threshold range determination circuit is coupled to the time-division comparison circuit and is used to determine the range of the clock count value based on the n-bit signal, thereby determining the range of the capacitor change, and performing subsequent processing based on the determination result of the range of the clock count value. A reference frequency update determination circuit is coupled to the time-division comparison circuit and is used to determine whether the range of the clock count value is within a specific range and exceeds the corresponding reference time threshold based on the n-bit signal. If so, an update signal is output to update the reference frequency.

8. The capacitance detection circuit as described in claim 7, characterized in that, n=4, the capacitor is a detection capacitor set in the corresponding airflow channel, and the threshold range determination circuit has four frequency threshold slopes S1 to S4 with gradually decreasing slopes, with the following conditions: (1) If the output slope of the clock count value is between S2 and S3, it is determined that the capacitance value of the capacitor has not changed, indicating that there is no gas flow in the airflow channel; (2) If the output slope of the clock count value is between S1 and S2 or between S3 and S4, it is determined that the capacitance value of the capacitor has changed slightly, and when the time when the output slope of the clock count value is between S1 and S2 or between S3 and S4 exceeds the reference time threshold, the reference frequency is updated. (3) If the output slope of the clock count value is above S1, it is determined that the capacitance value of the capacitor has decreased significantly, indicating that gas is flowing into the airflow channel. (4) If the output slant of the clock count value is below S4, it is determined that the capacitance value of the capacitor has increased significantly, indicating that gas is flowing out of the airflow channel.

9. An electronic device, characterized in that, It has a capacitance detection circuit as described in any one of claims 1-8.

10. The electronic device as claimed in claim 9, characterized in that, The electronic device is a touch screen, a microphone, or an airflow detector. When the electronic device is an airflow detector, the airflow detector is set in the corresponding airflow channel, and the capacitance change detected by the capacitance detection circuit is used to reflect whether there is gas flow in the airflow channel.

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