Cascode-type device

Abstract

This invention discloses a cascaded common-source and common-gate device, belonging to the integrated circuit manufacturing technology related to the core electronics industry. Using the cascaded common-source and common-gate device in this embodiment, a current matching device is connected between the gate and source of the cascaded low-voltage MOSFET and the high-voltage first depletion-mode MOSFET. This device mainly consists of a first resistor and a second depletion-mode MOSFET. This enables leakage current matching within the device in the off-state, reducing the reliability risk of the gate of the high-voltage first depletion-mode MOSFET. This device can be integrated with the chip by adapting to semiconductor device manufacturing processes (such as dedicated lithography and etching machines). The current matching device has a small chip area, effectively reducing chip costs. Simultaneously, the off-state leakage current is smaller, reducing system power consumption and meeting the high-performance, low-cost mass production requirements of power semiconductor integrated circuits.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a common-source, common-gate cascaded device. Background Technology

[0002] A cascaded gallium nitride (GaN) device is constructed by combining a low-voltage silicon-based metal-oxide-semiconductor field-effect transistor (Si-MOSFET) with a high-voltage depletion-mode gallium nitride-based high electron mobility transistor (GaN HEMT) using a common-source, common-gate configuration. Specifically, the drain of the high-voltage depletion-mode GaN HEMT serves as the drain of the cascaded device, and the gate of the low-voltage Si-MOSFET serves as the gate. Thus, when the gate voltage is 0, the low-voltage Si-MOSFET is turned off, raising the source potential of the high-voltage depletion-mode GaN HEMT. This creates a negative potential difference between the gate and source of the high-voltage depletion-mode GaN HEMT, effectively turning off the high-voltage depletion-mode GaN HEMT and ultimately achieving enhancement-mode functionality.

[0003] Cascaded GaN devices, featuring enhancement-mode operation, easy drive, excellent reverse recovery characteristics, and high reliability, are one of the mainstream structures for commercial GaN power devices. However, due to leakage current mismatch between high-voltage GaN HEMTs and low-voltage SiMOSFETs in the off-state, with the latter exhibiting lower leakage current, a voltage difference significantly higher than the threshold voltage is required between the gate and source of the high-voltage GaN HEMT to achieve more thorough channel turn-off and match the leakage current of the low-voltage SiMOSFET. This larger gate-source voltage difference significantly increases the gate reliability risk of the high-voltage GaN HEMT. Summary of the Invention

[0004] This invention provides a cascaded common-source cascode device that reduces the gate reliability risk of the high-voltage first depletion-mode field-effect transistor while reducing chip cost and system power consumption.

[0005] One embodiment of the present invention provides a cascaded common-source cascode device, comprising: a low-voltage field-effect transistor (FET), a high-voltage first depletion-mode FET, a first resistor, and a second depletion-mode FET, wherein the threshold voltages of both the high-voltage first depletion-mode FET and the second depletion-mode FET are negative, and the threshold voltage of the second depletion-mode FET is higher than that of the high-voltage first depletion-mode FET. The drain of the low-voltage field-effect transistor is connected to the source of the high-voltage first depletion-type field-effect transistor, and the gate and source of the low-voltage field-effect transistor serve as the gate and source of the common-source cascaded device, respectively. The drain of the high-voltage first depletion-type field-effect transistor serves as the drain of the common-source cascaded device, and the gate of the high-voltage first depletion-type field-effect transistor is connected to the source of the common-source cascaded device. The source and gate of the high-voltage first depletion-type field-effect transistor are respectively connected to the drain and gate of the second depletion-type field-effect transistor, and the first resistor is connected between the source and gate of the second depletion-type field-effect transistor.

[0006] As can be seen, by employing the cascaded common-source and common-gate device in this embodiment, a current matching device, mainly composed of a first resistor and a second depletion-mode field-effect transistor, is connected between the gate and source of the cascaded low-voltage field-effect transistor and the high-voltage first depletion-mode field-effect transistor. This device enables leakage current matching within the device in the off-state, reducing the reliability risk of the gate of the high-voltage first depletion-mode field-effect transistor. Furthermore, this device can be integrated into the chip by adapting to semiconductor device manufacturing processes (such as dedicated lithography and etching machines). The current matching device occupies a small chip area, effectively reducing chip costs. Simultaneously, the off-state leakage current is even smaller, reducing system power consumption and meeting the high-performance, low-cost mass production requirements of power semiconductor integrated circuits. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of a high-voltage first depletion-type field-effect transistor and a current matching device integrated on the same chip in an embodiment of the present invention; Figure 2 This is a schematic diagram of the internal circuit of a common-source cascaded device according to an embodiment of the present invention; Figure 3 This is a diagram showing the relationship between the gate and source voltages and their resistances of the second depletion-type field-effect transistor in this embodiment of the invention. Figure 4 This is a graph showing the change of the current between the drain and source of the high-voltage first depletion-type field-effect transistor in an embodiment of the present invention as a function of the voltage between the drain and source of the low-voltage field-effect transistor. Figure 5 This is a graph showing another variation of the current between the drain and source of the high-voltage first depletion-type field-effect transistor in an embodiment of the present invention with the voltage between the drain and source of the low-voltage field-effect transistor. Figure 6This is a circuit diagram of a common-source cascaded device provided in another embodiment of the present invention; Figure 7 This is a circuit diagram of a common-source cascaded device provided in another embodiment of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0011] This invention provides a common-source, common-gate cascaded device, such as... Figure 1 and Figure 2 As shown, the system includes: a low-voltage field-effect transistor 10, a high-voltage first depletion-mode field-effect transistor 11, a first resistor 12, and a second depletion-mode field-effect transistor 13. The threshold voltages of both the high-voltage first depletion-mode field-effect transistor 11 and the second depletion-mode field-effect transistor 13 are negative, and the threshold voltage of the second depletion-mode field-effect transistor 13 is higher than the threshold voltage of the high-voltage first depletion-mode field-effect transistor 11. Specifically: The drain D1 of the low-voltage field-effect transistor 10 is connected to the source S2 of the high-voltage first depletion-type field-effect transistor 11. The gate G1 and source S1 of the low-voltage field-effect transistor 10 serve as the gate G and source S of the cascaded common-source device, respectively.

[0012] The drain D2 of the high-voltage first depletion-type field-effect transistor 11 serves as the drain D of the cascaded common-source device, and the gate G2 of the high-voltage first depletion-type field-effect transistor 11 is connected to the source S of the cascaded common-source device.

[0013] The source S2 and gate G2 of the high-voltage first depletion-type field-effect transistor 11 are connected to the drain D3 and gate G3 of the second depletion-type field-effect transistor 13, respectively, and the first resistor 12 is connected between the source S3 and gate G3 of the second depletion-type field-effect transistor 13.

[0014] It should be noted that the low-voltage field-effect transistor 10 can be a low-voltage Si MOSFET, the high-voltage first depletion-type field-effect transistor 11 can be a high-voltage depletion-type GaN HEMT, and the second depletion-type field-effect transistor 13 can be a depletion-type HEMT.

[0015] In this embodiment, the first resistor 12 and the second depletion-type field-effect transistor 13 form a current matching device. This current matching device is connected between the source S2 and gate G2 of the high-voltage first depletion-type field-effect transistor 11, which can effectively solve the leakage current mismatch between the high-voltage first depletion-type field-effect transistor 11 and the low-voltage field-effect transistor 10 when the cascaded device is in the off state. In this embodiment, the cascaded device mainly operates in the following two states: (1) When the cascaded common-source device is in the on state: The current matching device exhibits low impedance and does not affect the normal conduction of the main current path. Specifically, when a positive voltage higher than its threshold voltage is applied to the gate G1 of the low-voltage MOSFET 10, the low-voltage MOSFET 10 will conduct, thereby pulling its drain potential (i.e., the source S2 of the high-voltage first depletion-type MOSFET 11) down to near 0V. At this time, the voltage difference between the gate G2 and the source S2 of the high-voltage first depletion-type MOSFET 11 becomes a small negative voltage or 0V, which is greater than its threshold voltage, and it is in the conducting state; the source S3 potential of the second depletion-type MOSFET 13 is also pulled down, causing its gate G3 voltage to also approach 0V, which is greater than its threshold voltage, and it is in the conducting state.

[0016] In this case, the main current flows from the drain D2 of the high-voltage first depletion-type field-effect transistor 11 to the source S2, and then flows out through the conducting low-voltage field-effect transistor 10. The second depletion-type field-effect transistor 13 in the current matching device presents a low on-resistance when it is turned on. It is connected in series with the first resistor 12, and then in parallel with the low-voltage field-effect transistor 10. This will not increase the device impedance and ensure that the current matching device does not affect the normal operation and on-resistance of the main device when it is turned on.

[0017] (2) When the cascaded common-source device is in the off state: In this situation, the voltage applied to the gate G1 of the low-voltage field-effect transistor 10 becomes 0V, causing the source S2 potential of the high-voltage first depletion-type field-effect transistor 11 (i.e., the drain D1 potential of the low-voltage field-effect transistor 10) to rise from 0V, resulting in a negative voltage change between its gate G2 and source S2. Simultaneously, the current matching device starts working. Since the gate G3 of the second depletion-type field-effect transistor 13 is connected to the gate G2 of the high-voltage first depletion-type field-effect transistor 11, the source S3 potential of the second depletion-type field-effect transistor 13 rises along with the source S2 potential of the high-voltage first depletion-type field-effect transistor 11, thus creating a voltage difference across the first resistor 12.

[0018] In this situation, when the source S2 potential of the high-voltage first depletion-mode field-effect transistor 11 rises to approximately equal to the threshold voltage of the second depletion-mode field-effect transistor 13, the voltage difference across the first resistor 12 also reaches the threshold voltage of the second depletion-mode field-effect transistor 13. At this point, the second depletion-mode field-effect transistor 13 enters the subthreshold region, and its resistance increases sharply, far exceeding its on-resistance. In this state, the second depletion-mode field-effect transistor 13 and the first resistor 12 work together to limit the leakage current of the entire current matching device to a constant value I, which is approximately the threshold voltage of the second depletion-mode field-effect transistor 13 divided by the resistance of the first resistor 12.

[0019] Among them, the voltage difference between the gate G2 and the source S2 of the high-voltage first depletion-type field-effect transistor 11 needs to be slightly lower than its own threshold voltage to ensure reliable turn-off, and its leakage current is limited to a constant current value I by the current matching device; while the second depletion-type field-effect transistor 13 operates in the subthreshold region, exhibiting a high-resistance state, and works in conjunction with the first resistor 12, like a constant current source controlling the total leakage current.

[0020] As can be seen, when the common source cascade device is turned off, the current matching device is connected in parallel with the low voltage field-effect transistor 10, providing an additional leakage path. By setting the appropriate resistance value of the first resistor 12 and the threshold voltage of the second depletion field-effect transistor 13 in the current matching device, the leakage current of the high voltage first depletion field-effect transistor 11 in the off state can be maintained at a relatively stable value, that is, the current of the current matching device is constant. When the voltage between the gate G2 and source S2 of the high-voltage first depletion-mode field-effect transistor 11 reaches the threshold voltage, since the absolute value of the threshold voltage of the second depletion-mode field-effect transistor 13 is less than the absolute value of the threshold voltage of the high-voltage first depletion-mode field-effect transistor 11, the second depletion-mode field-effect transistor 13 has also reached the corresponding threshold voltage and is in a constant high-resistance state. At this time, its resistance is much greater than its on-resistance, and the current is almost constant, which is equivalent to a constant current source. The current value is approximately equal to the threshold voltage of the second depletion-mode field-effect transistor 13 divided by the resistance value of the first resistor 12. Therefore, it can effectively avoid excessive leakage current when the high-voltage first depletion-mode field-effect transistor 11 is in the off state. At the same time, compared with the scheme of using only a resistor to achieve the same current value, the scheme of using the combination of the second depletion-mode field-effect transistor 13 and the first resistor 12 in this embodiment can avoid setting a large area and a large resistance value of the first resistor 12, thereby reducing the reliability risk of the gate G2 of the high-voltage first depletion-mode field-effect transistor 11.

[0021] In this way, by combining different threshold voltages of the second depletion-mode field-effect transistor 13 and the resistance values ​​of the first resistor 12, different current values ​​can be obtained when the cascaded common-source cascode device is off.

[0022] It should be noted that the high-voltage first depletion-type field-effect transistor 11 is generally made of GaN HEMT, in which the two-dimensional electron gas (2DEG) has a much higher resistivity than the interconnect metal. Based on this characteristic, in this embodiment of the invention, the first resistor 12 in the 2DEG serpentine layout current matching device can be used inside the GaN HEMT, and the second depletion-type field-effect transistor 13 is also integrated inside the GaN HEMT. In this way, the high-voltage first depletion-type field-effect transistor 11 and the current matching device (including the first resistor 12 and the second depletion-type field-effect transistor 13) are integrated into the same chip, which can reduce packaging complexity and cost, but will occupy a part of the area of ​​the high-voltage first depletion-type field-effect transistor 11.

[0023] In this embodiment, the high-voltage first depletion-mode field-effect transistor 11 and the current matching device are integrated into the same chip. The current formed by the cooperation of the second depletion-mode field-effect transistor 13 and the first resistor 12 is determined by the threshold voltage of the second depletion-mode field-effect transistor 13 and the resistance of the first resistor 12.

[0024] Since the absolute value of the threshold voltage of the second depletion-mode field-effect transistor 13 is lower than that of the threshold voltage of the high-voltage first depletion-mode field-effect transistor 11, when the high-voltage first depletion-mode field-effect transistor 11 reaches its threshold voltage, the second depletion-mode field-effect transistor 13 will certainly have also reached its corresponding threshold voltage. To maintain the voltage difference between the gate G2 and source S2 of the high-voltage first depletion-mode field-effect transistor 11 at a stable value close to its threshold voltage, and because the resistance of the second depletion-mode field-effect transistor 13 increases when it reaches its threshold voltage, it is not necessary to set a first resistor 12 with a large resistance based on the leakage current. Instead, the target off-state leakage current is achieved through the cooperation of the first resistor 12 and the second depletion-mode field-effect transistor 13. Simultaneously, since the size of the second depletion-mode field-effect transistor 13 is much smaller than the size of the first resistor 12, the area occupied by the current matching device composed of the first resistor 12 and the second depletion-mode field-effect transistor 13 is also smaller.

[0025] like Figure 1 As shown, the high-voltage first depletion-type field-effect transistor 11 and the current matching device (including the first resistor 12 and the second depletion-type field-effect transistor 13) are integrated into the same chip, wherein the size of the second depletion-type field-effect transistor 13 is much smaller than the size of the first resistor 12.

[0026] It should be noted that the embodiments of this application employ a common-source, common-gate cascaded device with the above-described structure, such as... Figure 3 The diagram shows the relationship between the gate G3 and source S3 voltage Vgs_HEMT2 and its resistance Ron_HEMT2 of the second depletion-mode field-effect transistor 13. When the voltage Vgs_HEMT2 is lower than its threshold voltage Vth_HEMT2 by a certain range, that is, when the absolute value of the voltage Vgs_HEMT2 is greater than the absolute value of its threshold voltage by a certain range, there will be a subthreshold region. At this time, the second depletion-mode field-effect transistor 13 will not be completely turned off, but will be in a high-resistance region. When the voltage Vgs_HEMT2 is in the subthreshold region and remains constant, the second depletion-mode field-effect transistor 13 can maintain a constant high-resistance state.

[0027] Specifically, when the cascaded common-source cascode device is turned off, the drain potential D1 of the low-voltage MOSFET 10 increases from 0V to approximately equal to the threshold voltage (e.g., -20V) of the high-voltage first depletion-mode MOSFET 11. During this process, the voltage difference across the first resistor 12 (resistance value, e.g., 5MΩ) increases from 0V to the threshold voltage (e.g., -5V) of the second depletion-mode MOSFET 13. When the voltage difference across the first resistor 12 increases to the threshold voltage of the second depletion-mode MOSFET 13, the resistance of the second depletion-mode MOSFET 13 increases, limiting the increase of the leakage current across the first resistor 12. In this state, the second depletion-mode MOSFET 13 is in a high-resistance state. At this time, the second depletion-mode MOSFET 13 is in the subthreshold region, and its resistance is much greater than its on-resistance. The current is almost constant, equivalent to a constant current source. The current value of the current matching device composed of the first resistor 12 and the second depletion-mode MOSFET 13 is approximately equal to the threshold voltage of the second depletion-mode MOSFET 13 divided by the resistance value of the first resistor 12 (e.g., 1μA).

[0028] The following three methods are used to implement cascaded common-source devices: Method 1: The common-source cascaded device only includes the low-voltage MOSFET 10 and the high-voltage first depletion-mode MOSFET 11, i.e., without a current matching device. Method 2: The common-source cascaded device includes only a low-voltage field-effect transistor 10, a high-voltage first depletion-type field-effect transistor 11, and a constant resistor connected between the gate and source of the high-voltage first depletion-type field-effect transistor 11. That is, the current matching device includes only a constant resistor. Method 3: In the common-source cascaded device of the present invention, only a low-voltage field-effect transistor 10, a high-voltage first depletion-type field-effect transistor 11, a first resistor 12 and a second depletion-type field-effect transistor 13 are included. That is, the current matching device includes the first resistor 12 and the second depletion-type field-effect transistor 13.

[0029] like Figure 4 The figure shows the variation of the current Ids_HEMT1 between the drain D2 and source S2 of the high-voltage first depletion-type field-effect transistor 11 and the voltage Vds_SiMOSFET between the drain D1 and source S1 of the low-voltage field-effect transistor 10 under the three conditions described above. In this figure, the constant resistor in the current matching device under mode two has the same area as the first resistor 12 in the current matching device under mode three, meaning their resistance values ​​are also the same. Therefore, it can be concluded that: When the resistance of the first resistor 12 is 5MΩ, and the resistor area used in the current matching device is the same, the off-state leakage current of mode 2 is 4 times that of mode 3 (the mode in this embodiment). That is, the off-state loss of the common source cascade device used in this embodiment is 1 / 4 of the off-state loss of mode 2.

[0030] like Figure 5 The figure shows the variation of the current Ids_HEMT1 between the drain D2 and source S2 of the high-voltage first depletion-type field-effect transistor 11 and the voltage Vds_SiMOSFET between the drain D1 and source S1 of the low-voltage field-effect transistor 10 under the three conditions described above. In mode two, the area of ​​the constant resistor in the current matching device is greater than the area of ​​the first resistor 12 in the current matching device under mode three. Furthermore, the off-state losses remain consistent in both modes (i.e., the off-state leakage current is the same). Therefore, it can be concluded that: To maintain the same off-state loss, the current matching device in Method 2 requires a constant resistor of 20MΩ, which occupies more chip area, while the first resistor in the current matching device in Method 3 only needs 5MΩ, which occupies less chip area.

[0031] In summary, the cascaded common-source cascode device in this embodiment, by connecting a current matching device between the gate and source of the high-voltage first depletion-mode MOSFET in the cascaded low-voltage MOSFET and high-voltage first depletion-mode MOSFET, mainly composed of a first resistor and a second depletion-mode MOSFET, can achieve leakage current matching within the device in the off-state, reducing the reliability risk of the gate of the high-voltage first depletion-mode MOSFET 11. Furthermore, compared to a solution using only resistors, the current matching device in this embodiment occupies a smaller chip area, reducing chip cost, while achieving a smaller off-state leakage current, thus reducing system power consumption.

[0032] It is particularly important to note that, in order to reduce packaging complexity during the fabrication of the aforementioned cascaded common-source and cascode devices, the current matching device and the high-voltage first depletion-mode field-effect transistor 11 are integrated onto the same chip. Specifically: When forming the high-voltage first depletion-type field-effect transistor 11 and the second depletion-type field-effect transistor 13 in the current matching device, gate dielectrics of different thicknesses can be etched in different regions of the same chip to form the gate of the high-voltage first depletion-type field-effect transistor 11 and the gate of the second depletion-type field-effect transistor 13. The thickness of the gate dielectric of the high-voltage first depletion-type field-effect transistor 11 is greater than the thickness of the gate dielectric of the second depletion-type field-effect transistor 13.

[0033] Generally, on the conventional high-voltage first depletion-type field-effect transistor 11 process platform, an additional photolithography mask and a gate dielectric etching process are added. Gate dielectric etching is performed on the same chip, resulting in gate dielectrics of different thicknesses in different regions of the same chip. This allows for the realization of high-voltage first depletion-type field-effect transistors 11 and second depletion-type field-effect transistors 13 with different threshold voltages on the same chip. Specifically: A photomask can be added to a chip to perform gate dielectric etching, thereby forming the gate dielectric of the second depletion-type field-effect transistor 13 at a specific location on the chip, and the gate dielectric of the second depletion-type field-effect transistor 13 can be completely etched to form a Schottky gate. Alternatively, the absolute value of the threshold voltage of the second depletion-type field-effect transistor 13 can be made lower than the absolute value of the threshold voltage of the high-voltage first depletion-type field-effect transistor 11 by any other means.

[0034] Furthermore, when forming the first resistor 12 in the current matching device, an ion implantation process can be used to form a two-dimensional electron gas pattern with a specific equivalent aspect ratio, such as a snake, to form the first resistor 12.

[0035] This allows for the deployment of the high-voltage first depletion-mode field-effect transistor 11 and the current matching device (including the second depletion-mode field-effect transistor 13 and the first resistor 12) onto the same chip. Furthermore, this can be achieved through the above... Figure 2 The connection method involves connecting the high-voltage first depletion-type field-effect transistor 11, the second depletion-type field-effect transistor 13, and the first resistor 12 through interconnecting metal, thereby realizing a chip with an integrated current matching device for the high-voltage first depletion-type field-effect transistor 11.

[0036] Furthermore, it can be achieved through the above Figure 2 The connection method described in the invention involves packaging the high-voltage first depletion-type field-effect transistor 11, which integrates a current matching device, with the low-voltage field-effect transistor 10 to obtain the common-source cascaded device of this embodiment.

[0037] In another specific embodiment of the present invention, a common-source, common-gate cascaded device is provided, such as... Figure 6 As shown, the system includes: a low-voltage field-effect transistor 10, a high-voltage first depletion-mode field-effect transistor 11, a first resistor 12, a second depletion-mode field-effect transistor 13, and a second resistor 14. The threshold voltages of both the high-voltage first depletion-mode field-effect transistor 11 and the second depletion-mode field-effect transistor 13 are negative, and the threshold voltage of the second depletion-mode field-effect transistor 13 is higher than the threshold voltage of the high-voltage first depletion-mode field-effect transistor 11. Specifically: The drain D1 of the low-voltage field-effect transistor 10 is connected to the source S2 of the high-voltage first depletion-type field-effect transistor 11. The gate G1 and source S1 of the low-voltage field-effect transistor 10 serve as the gate G and source S of the cascaded common-source device, respectively. The drain D2 of the high-voltage first depletion-type field-effect transistor 11 serves as the drain D of the cascaded common-source device, and the gate G2 of the high-voltage first depletion-type field-effect transistor 11 is connected to the source S of the cascaded common-source device. The source S2 and gate G2 of the high-voltage first depletion-type field-effect transistor 11 are respectively connected to the drain D3 and gate G3 of the second depletion-type field-effect transistor 13. The first resistor 12 is connected between the source S3 of the second depletion-type field-effect transistor 13 and the source S of the cascaded common-source and common-gate device. The gate G3 of the second depletion-type field-effect transistor 13 is indirectly connected to the gate G2 of the high-voltage first depletion-type field-effect transistor 11. A second resistor 14 is connected between the gate G3 of the second depletion-type field-effect transistor 13 and the gate G2 of the high-voltage first depletion-type field-effect transistor 11. The area of ​​the second resistor is much smaller than the area of ​​the first resistor 12.

[0038] In this embodiment, in order to reduce packaging complexity, the above-mentioned high-voltage first depletion-mode field-effect transistor 11, first resistor 12, second depletion-mode field-effect transistor 13 and second resistor 14 can all be integrated into the same chip.

[0039] The parasitic inductance of the source S of a cascaded common-source MOSFET can cause voltage fluctuations, which in extreme cases may damage the gate G2 of the second depletion-mode MOSFET 13. In this embodiment, by integrating a second resistor 14 into the gate G2 of the second depletion-mode MOSFET 13, the impact of voltage fluctuations at the source S on the gate G2 of the second depletion-mode MOSFET 13 can be reduced, thereby increasing the reliability of the device.

[0040] In another specific embodiment of the present invention, a common-source, common-gate cascaded device is provided, such as... Figure 7 As shown, the system includes: a low-voltage field-effect transistor 10, a high-voltage first depletion-type field-effect transistor 11, a first resistor 12, and multiple (e.g., n) second depletion-type field-effect transistors 13-1, 13-2, ..., 13-n. The threshold voltages of both the high-voltage first depletion-type field-effect transistor 11 and the second depletion-type field-effect transistor 13 are negative, and the threshold voltage of each second depletion-type field-effect transistor is higher than the threshold voltage of the high-voltage first depletion-type field-effect transistor 11; that is, the absolute value of the threshold voltage of each second depletion-type field-effect transistor is less than the absolute value of the threshold voltage of the high-voltage first depletion-type field-effect transistor 11. Specifically: The drain D1 of the low-voltage field-effect transistor 10 is connected to the source S2 of the high-voltage first depletion-type field-effect transistor 11. The gate G1 and source S1 of the low-voltage field-effect transistor 10 serve as the gate G and source S of the cascaded common-source device, respectively.

[0041] The drain D2 of the high-voltage first depletion-type field-effect transistor 11 serves as the drain D of the cascaded common-source device, and the gate G2 of the high-voltage first depletion-type field-effect transistor 11 is connected to the source S of the cascaded common-source device.

[0042] Multiple second depletion-type field-effect transistors are connected in series via their drains and sources. That is, the drain of one second depletion-type field-effect transistor is connected to the source of another adjacent second depletion-type field-effect transistor, and the drain of another second depletion-type field-effect transistor is connected to the source of yet another adjacent second depletion-type field-effect transistor. In this way, multiple second depletion-type field-effect transistors are connected in series.

[0043] The gate of the first second depletion field-effect transistor 13-1 among a plurality of second depletion field-effect transistors is connected to the gate of the high-voltage first depletion field-effect transistor 11, and a first resistor 12 is connected between the source and the gate of the first second depletion field-effect transistor 13-1, and the drain of the last second depletion field-effect transistor 13-n is connected to the source S2 of the high-voltage first depletion field-effect transistor 11.

[0044] Except for the first second depletion field-effect transistor 13-1, the gate of any other second depletion field-effect transistor is shorted to the source of its adjacent first second depletion field-effect transistor. For example, the gate of the second second depletion field-effect transistor 13-2 is shorted to the source of the first second depletion field-effect transistor 13-1.

[0045] It should be noted that the low-voltage field-effect transistor 10 mentioned above can be a low-voltage Si MOSFET, the high-voltage first depletion-type field-effect transistor 11 can be a high-voltage depletion-type GaN HEMT, and the second depletion-type field-effect transistor can be a depletion-type HEMT.

[0046] In this embodiment, in order to reduce packaging complexity, the high-voltage first depletion-mode field-effect transistor 11, the first resistor 12, and multiple second depletion-mode field-effect transistors can all be integrated into the same chip.

[0047] The voltage difference between the gate and source of the i-th second depletion-type field-effect transistor is: the voltage difference between the drain and source of the (i-1)-th second depletion-type field-effect transistor. In the off state, each second depletion-type field-effect transistor is in the subthreshold region, that is, a certain voltage value is shared between the source and drain of each second depletion-type field-effect transistor. As a result, the voltage difference between the gate and drain of each second depletion-type field-effect transistor will be further reduced (avoiding high voltage breakdown) and improving device reliability.

[0048] The foregoing has provided a detailed description of a common-source cascaded device provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A common-source, common-gate cascaded device, characterized in that, include: The system comprises a low-voltage field-effect transistor (FET), a high-voltage first depletion-mode FET, a first resistor, and a second depletion-mode FET, wherein the threshold voltages of both the high-voltage first depletion-mode FET and the second depletion-mode FET are negative, and the threshold voltage of the second depletion-mode FET is higher than that of the high-voltage first depletion-mode FET. The drain of the low-voltage field-effect transistor is connected to the source of the high-voltage first depletion-type field-effect transistor, and the gate and source of the low-voltage field-effect transistor serve as the gate and source of the common-source cascaded device, respectively. The drain of the high-voltage first depletion-type field-effect transistor serves as the drain of the common-source cascaded device, and the gate of the high-voltage first depletion-type field-effect transistor is connected to the source of the common-source cascaded device. The source and gate of the high-voltage first depletion-type field-effect transistor are respectively connected to the drain and gate of the second depletion-type field-effect transistor, and the first resistor is connected between the source and gate of the second depletion-type field-effect transistor.

2. The cascaded device according to claim 1, characterized in that, When the cascaded common-source device is turned on, the gate voltage of the high-voltage first depletion-mode field-effect transistor is greater than its threshold voltage, and it is in the on state. The second depletion-type field-effect transistor has a gate voltage greater than its threshold voltage, is in the on state, and exhibits low on-resistance.

3. The cascaded device according to claim 1, characterized in that, When the cascaded common-source device is turned off, the voltage between the gate and source of the first high-voltage depletion-mode field-effect transistor reaches the threshold voltage, and the second depletion-mode field-effect transistor also reaches the corresponding threshold voltage and is in a constant high-resistance state.

4. The cascaded device according to claim 3, characterized in that, When the second depletion-type field-effect transistor is in a high-resistance state, its resistance is greater than its on-resistance, and the current is equivalent to a constant current source. Its current value is approximately equivalent to the threshold voltage of the second depletion-type field-effect transistor divided by the resistance value of the first resistor.

5. The cascaded device according to claim 1, characterized in that, When forming the high-voltage first depletion field-effect transistor and the second depletion field-effect transistor, gate dielectric etching is performed on the same chip, so that gate dielectrics of different thicknesses are formed in different regions of the chip, forming the gate of the high-voltage first depletion field-effect transistor and the gate of the second depletion field-effect transistor. The thickness of the gate dielectric of the first high-voltage depletion-type field-effect transistor is greater than the thickness of the gate dielectric of the second depletion-type field-effect transistor.

6. The cascaded device according to claim 5, characterized in that, A photomask is added to the chip to perform gate dielectric etching, so that the gate dielectric of the second depletion-type field-effect transistor is formed at a specific location on the chip, and the gate dielectric of the second depletion-type field-effect transistor is completely etched to form a Schottky gate.

7. The cascaded device according to claim 5, characterized in that, In forming the first resistor, an ion implantation process is used to form a two-dimensional electron gas pattern with a specific equivalent aspect ratio to form the first resistor.

8. The cascaded device according to any one of claims 1 to 7, characterized in that, A second resistor is connected between the gate of the second depletion-type field-effect transistor and the gate of the high-voltage first depletion-type field-effect transistor; The area of ​​the second resistor is much smaller than the area of ​​the first resistor; The high-voltage first depletion-mode field-effect transistor, the second depletion-mode field-effect transistor, the first resistor, and the second resistor are all integrated into the same chip.

9. The cascaded device according to any one of claims 1 to 7, characterized in that, If the second depletion-mode field-effect transistor comprises multiple transistors, then: Multiple second depletion-type field-effect transistors are connected in series through their drain and source. The gate of the first second depletion-type field-effect transistor is connected to the gate of the high-voltage first depletion-type field-effect transistor, and the first resistor is connected between the source and gate of the first second depletion-type field-effect transistor. The drain of the last second depletion-type field-effect transistor is connected to the source of the high-voltage first depletion-type field-effect transistor. Except for the first second depletion-type field-effect transistor, the gate of any other second depletion-type field-effect transistor is shorted to the source of its adjacent first second depletion-type field-effect transistor.

10. The cascaded device according to claim 9, characterized in that, The high-voltage first depletion-mode field-effect transistor, the plurality of second depletion-mode field-effect transistors, and the first resistor are all integrated into the same chip.

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