Superconducting voltage drive circuit and electronic product

Abstract

This invention provides a superconducting voltage drive circuit and electronic product, comprising: an SFQ pulse input module that generates complementary set and reset signals based on SFQ pulses; each RS flip-flop that receives a set pulse and a reset pulse respectively, generating a magnetic flux quantum when the set pulse arrives and releasing the magnetic flux quantum when the reset pulse arrives; a series structure of asymmetric SQUID superconducting rings cascaded sequentially; a bias current source that provides DC bias to each asymmetric SQUID superconducting ring; each asymmetric SQUID superconducting ring correspondingly sensing the magnetic flux quantum in its respective RS flip-flop and generating a corresponding output voltage under the action of the bias current source; the voltages output by each asymmetric SQUID superconducting ring are superimposed to form a total output voltage, which is transmitted to an external receiving circuit via a transmission line; and a load RL connected to the output terminal of the series structure, representing the input impedance of the transmission line. This invention employs an asymmetric SQUID design, resulting in high output swing, fast operating speed, small circuit area, compact structure, and wide applicability.

Description

Technical Field

[0001] This invention relates to the field of superconducting integrated circuit technology, and in particular to a superconducting voltage drive circuit and electronic product. Background Technology

[0002] Currently, semiconductor device manufacturing processes are nearing their physical limits, and the prediction that transistor density will double every eighteen months is becoming increasingly saturated. In future high-performance, large-scale computing systems, various new digital chips based on advanced principles are emerging to further improve computing speed and reduce power consumption. Among these, superconducting integrated circuits based on Single Flux Quantum (SFQ) technology are expected to become one of the alternatives for digital circuits with higher clock speeds and lower power consumption.

[0003] SFQ circuits utilize the flux quantization effect and the superconducting Josephson effect of superconducting closed loops to represent digital signals "0" and "1" by the presence or absence of magnetic flux in the loop containing the Josephson junction. Compared to the high-low level encoding method in traditional semiconductor CMOS circuits, SFQ circuits feature high clock frequencies (~100GHz), low logic gate power consumption (nanowatts / gate), and self-storage capabilities. SFQ circuits have achieved operating frequencies exceeding 10GHz in applications such as microprocessors, dedicated processors, analog-to-digital converters, and network switches. These SFQ circuits require superconducting interface circuits to convert SFQ pulses into CMOS logic levels when interconnecting with semiconductor circuits; therefore, superconducting interface circuits are crucial for superconducting integrated circuits.

[0004] There are currently three commonly used superconducting interface circuits. The first is the SFQ / DC converter (Q2D) proposed by VKKaplunenko et al. in 1989, such as... Figure 1 As shown. Its structure is simple; the input SFQ pulses correspond to the transition edges of the output signal, as... Figure 2 As shown; its disadvantage is that the output amplitude is too small, only a few hundred microvolts. Because the signal attenuates more at high frequencies, the amplitude of Q2D cannot support its operation at GHz frequencies. The second type is the Suzuki stack proposed by H. Suzuki et al. in 1988, such as... Figure 3 As shown. Although it has a simple structure and an output amplitude of tens of millivolts, it requires AC bias to continuously reset the circuit in order to work, such as... Figure 4As shown. Crosstalk and ground ripple issues caused by AC bias make Suzuki stacks difficult to apply to multi-channel systems. The third type is the superconducting voltage driver (SVD) based on a SQUID array. Compared to the first two interface circuits, the SVD can operate at speeds of tens of Gbps, making it the most commonly used high-speed interface circuit.

[0005] SVD can be divided into two types according to its timing method. The first type is synchronous SVD, and its block diagram is as follows: Figure 5 As shown in the diagram. It has two input ports (clock and data) and one SVD output port. Its inputs are SFQ pulse signals, and its outputs are CMOS logic level signals. Its waveform diagram is shown below. Figure 6 As shown in the diagram. Between two consecutive clock pulses, if a pulse is input to the data port, the SVD will output a bit "1" in the next clock pulse cycle; if no pulse is input to the data port, the SVD will output a bit "0" in the next clock pulse cycle. The second type is asynchronous SVD, whose block diagram is shown in the diagram. Figure 7 As shown. The asynchronous SVD has only one data input port and one SVD output port. Its input is the SFQ pulse signal, and its output is a CMOS logic level signal. Its waveform diagram is shown below. Figure 8 As shown, each input data pulse signal will generate a transition edge in the SVD output.

[0006] The two key metrics for SVD are speed and output voltage amplitude. Achieving higher speed allows for better utilization of the high clock frequency of the SFQ circuit, while achieving a high output voltage amplitude increases the signal-to-noise ratio and reduces the requirements for downstream components. Previously, increasing the output voltage was often achieved by increasing the number of squid stages, but this increases circuit area and reduces operating speed, making it difficult to simultaneously achieve high speed and high output amplitude.

[0007] Therefore, for existing superconducting interface circuits, there is a need to propose a high-speed, high-output-voltage, and compact SVD to better achieve high-speed signal conversion when interconnecting SFQ circuits with semiconductor circuits.

[0008] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superconducting voltage drive circuit and electronic product to solve the problem that the output voltage amplitude and operating speed of the SVD circuit in the prior art cannot be simultaneously achieved.

[0010] To achieve the above and other related objectives, the present invention provides a superconducting voltage driving circuit, the superconducting voltage driving circuit comprising at least:

[0011] The system consists of an SFQ pulse input module, a bias current source, N RS flip-flops, and N asymmetric SQUID superconducting rings, where N is a natural number greater than or equal to 2.

[0012] The SFQ pulse input module receives SFQ pulses and generates complementary set and reset signals based on the SFQ pulses; wherein the set signal consists of N parallel set pulses and the reset signal consists of N parallel reset pulses.

[0013] Each RS flip-flop receives a set pulse and a reset pulse respectively. When the set pulse arrives, it generates and stores a magnetic flux quantum, and when the reset pulse arrives, it releases the stored magnetic flux quantum.

[0014] Each asymmetric SQUID superconducting ring is cascaded to form a series structure; one end of the series structure is grounded, and the other end serves as the output terminal of the superconducting voltage driving circuit; the bias current source is connected to the output terminal of the series structure to provide DC bias for each asymmetric SQUID superconducting ring.

[0015] Each asymmetric SQUID superconducting ring corresponds to a magnetic flux quantum in each RS flip-flop and generates a corresponding output voltage under the action of the bias current source; the voltages output by each asymmetric SQUID superconducting ring are superimposed to form a total output voltage, which is transmitted to the external receiving circuit through the transmission line.

[0016] Optionally, the superconducting voltage drive circuit further includes a terminating resistor, which is connected in series between the ground terminal of the series structure or between any two asymmetric SQUID superconducting rings.

[0017] Optionally, the asymmetric SQUID superconducting ring includes a first Josephson junction and a parallel resistor, and a second Josephson junction;

[0018] The first Josephson junction and the parallel resistor are connected in parallel to form a first junction region, and the second Josephson junction forms a second junction region. The first junction region and the second junction region are connected in parallel.

[0019] The damping parameter of the first Josephson junction is greater than 0 and less than or equal to 1, and the damping parameter of the second Josephson junction is greater than or equal to 10.

[0020] Optionally, N is set to a natural number between 2 and 100.

[0021] Optionally, the SFQ pulse input module includes: a D flip-flop, a first-channel one-to-many pulse transmission network, and a second-channel one-to-many pulse transmission network;

[0022] The D flip-flop receives and generates complementary first and second output signals based on the clock input signal and the data input signal; wherein the clock input signal and the data input signal are both SFQ pulses;

[0023] The first one-to-many pulse transmission network is connected to the first output terminal of the D flip-flop, and divides the first output signal into N parallel set pulses;

[0024] The second one-to-many pulse transmission network is connected to the second output terminal of the D flip-flop, dividing the second output signal into N parallel reset pulses.

[0025] Alternatively, when there is a data input signal between the two clock input signals, the first output terminal of the D flip-flop is triggered to output a corresponding output signal; when there is no data input signal between the two clock input signals, the second output terminal of the D flip-flop is triggered to output a corresponding output signal.

[0026] Optionally, the SFQ pulse input module includes: a T flip-flop, a first-channel one-to-many pulse transmission network, and a second-channel one-to-many pulse transmission network;

[0027] The T flip-flop receives and generates complementary first and second output signals based on the data input signal; wherein the data input signal is an SFQ pulse;

[0028] The first one-to-many pulse transmission network is connected to the first output terminal of the T flip-flop, and divides the first output signal into N parallel set pulses;

[0029] The second one-to-many pulse transmission network is connected to the second output terminal of the T flip-flop, and divides the second output signal into N parallel reset pulses.

[0030] Alternatively, the data input signal may be based on the T flip-flop to sequentially and alternately trigger the first output terminal and the second output terminal to output corresponding output signals.

[0031] Alternatively, the RS trigger includes a first Josephson transmission line, a second Josephson transmission line, a first buffer, a second buffer, and a flux storage loop;

[0032] One end of the first Josephson transmission line receives the set pulse, and the other end is connected to the first end of the magnetic flux storage loop via the first buffer.

[0033] One end of the second Josephson transmission line receives the reset pulse, and the other end is connected to the second end of the flux storage loop via the second buffer.

[0034] To achieve the above and other related objectives, the present invention also provides an electronic product, which includes at least the superconducting voltage driving circuit described above.

[0035] As described above, the superconducting voltage drive circuit and electronic product of the present invention have the following beneficial effects:

[0036] 1. The superconducting voltage drive circuit and electronic products of the present invention adopt an asymmetric SQUID design, which has a high output swing and reduces the requirements for subsequent high-frequency link components.

[0037] 2. The superconducting voltage drive circuit and electronic products of the present invention adopt the method of connecting resistors in series in the SQUID array to reduce the falling edge time of the output signal; the actual measured operating speed of SVD is as high as 20Gbps, which ensures high-speed conversion from SFQ signal to CMOS signal in superconducting integrated circuits.

[0038] 3. The superconducting voltage drive circuit and electronic products of the present invention can effectively reduce the number of stages of the SQUID superconducting ring, resulting in a small circuit area and a compact structure.

[0039] 4. The superconducting voltage drive circuit and electronic products of the present invention adopt a modular design, which can be easily applied to multi-channel designs.

[0040] 5. The superconducting voltage drive circuit and electronic products of the present invention can be applied to both synchronous SVD and asynchronous SVD, and have a wide range of applications. Attached Figure Description

[0041] Figure 1 The diagram shows the circuit structure of the SFQ / DC converter.

[0042] Figure 2 The diagram shows the waveform of the SFQ / DC converter.

[0043] Figure 3 The diagram shows the circuit structure of the Suzuki stack.

[0044] Figure 4 The diagram shows the waveform of the Suzuki stack.

[0045] Figure 5 The diagram shows a synchronized SVD process.

[0046] Figure 6 The diagram shows a waveform for synchronous SVD.

[0047] Figure 7 The diagram is shown as an asynchronous SVD diagram.

[0048] Figure 8 The diagram shows a waveform representation of asynchronous SVD.

[0049] Figure 9 The diagram shown is a structural schematic of the superconducting voltage drive circuit of the present invention.

[0050] Figure 10 The diagram shown is a schematic representation of the synchronous superconducting voltage drive circuit of the present invention.

[0051] Figure 11 The diagram shows a waveform of the D flip-flop of the present invention.

[0052] Figure 12 The diagram shown is a schematic representation of the circuit structure of the D flip-flop of this invention.

[0053] Figure 13 The diagram shown is a schematic diagram of the circuit structure of the one-to-many pulse transmission network of the present invention.

[0054] Figure 14 The diagram shown is a schematic diagram of the circuit structure of the RS flip-flop of the present invention.

[0055] Figure 15 The diagram shows a waveform of the RS trigger of the present invention.

[0056] Figure 16 The diagram shown is a structural schematic of the asymmetric SQUID superconducting ring of the present invention.

[0057] Figure 17 The diagram shown is a schematic of the test circuit of this invention.

[0058] Figure 18 The diagram shown is a schematic representation of the test waveforms of this invention.

[0059] Figure 19 The diagram shown is a schematic representation of the asynchronous superconducting voltage drive circuit of the present invention.

[0060] Figure 20 The diagram shows a waveform of the T flip-flop of the present invention.

[0061] Figure 21 The diagram shown is a schematic representation of the circuit structure of the T flip-flop of the present invention.

[0062] Component designation explanation

[0063] 1. Superconducting voltage drive circuit

[0064] 11 SFQ Pulse Input Module

[0065] 111 D flip-flop

[0066] 112 First-channel one-to-many pulse transmission network

[0067] 113 Second-channel one-to-many pulse transmission network

[0068] 114 T trigger

[0069] 1a One divided into two units

[0070] 12 RS flip-flops

[0071] 121 First Josephson Transmission Line

[0072] 122 Second Josephson Transmission Line

[0073] 123 First Buffer

[0074] 124 Second Buffer

[0075] 125 flux storage loop

[0076] 13 Asymmetric Squid superconducting rings

[0077] 2. Duwa

[0078] 21 Test rod

[0079] 22 SVD test chips

[0080] 31 Microwave signal source

[0081] 32 Programmable Code Generator

[0082] 33 and 34 power dividers

[0083] 35, 36 Offset Tee

[0084] 37 Superconducting Testing System

[0085] 4 Low-noise amplifier

[0086] 5 Limiting Amplifier

[0087] 6. Digital Sampling Oscilloscope Detailed Implementation

[0088] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0089] Please see Figures 9-21 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0090] For the reasons mentioned above, the present invention provides a superconducting voltage driving circuit 1, such as... Figure 9 As shown, the superconducting voltage drive circuit 1 includes:

[0091] The circuit comprises an SFQ pulse input module 11, a bias current source Ib, N RS flip-flops 12, and N asymmetric SQUID superconducting rings 13, where N is a natural number greater than or equal to 2. For example, N is set to 16. In practical use, the value of N is related to the output voltage amplitude of the superconducting voltage drive circuit 1; the larger N is, the larger the output voltage amplitude. A specific value can be set as needed. Preferably, N is set to a natural number between 2 and 100 (inclusive).

[0092] The SFQ pulse input module 11 receives the SFQ pulse and generates complementary set signals Set[16:1] and reset signals Reset[16:1] based on the SFQ pulse; wherein, the set signal consists of N parallel set pulses and the reset signal consists of N parallel reset pulses.

[0093] Each RS flip-flop 12 receives a set pulse and a reset pulse respectively. When the set pulse arrives, it generates and stores a magnetic flux quantum, and when the reset pulse arrives, it releases the stored magnetic flux quantum.

[0094] Each asymmetric SQUID superconducting ring 13 is cascaded to form a series structure; one end of the series structure is grounded, and the other end serves as the output terminal of the superconducting voltage drive circuit 1; the bias current source Ib is connected to the output terminal of the series structure to provide DC bias for each asymmetric SQUID superconducting ring 13.

[0095] Each asymmetric SQUID superconducting ring 13 corresponds to a magnetic flux quantum in each RS flip-flop 12, and generates a corresponding output voltage under the action of the bias current source Ib. The voltages output by each asymmetric SQUID superconducting ring 13 are superimposed to form a total output voltage, which is transmitted to the external receiving circuit via a transmission line. Furthermore, the load resistor R... L Located at the output terminal of the series structure, it represents the input impedance of the transmission line; the load resistance R L This is the equivalent resistance, not the resistance set in this invention.

[0096] This invention improves the output swing while ensuring high-speed conversion through an asymmetric SQUID design. The invention is described below with specific examples.

[0097] Example 1

[0098] like Figure 10 As shown, this embodiment provides a synchronous superconducting voltage driving circuit 1, where N is set to 16. The superconducting voltage driving circuit 1 includes:

[0099] The SFQ pulse input module 11 and the asymmetric RS flip-flop-SQUID array (including bias current source Ib, 16 RS flip-flops 12 and 16 asymmetric SQUID superconducting rings 13).

[0100] like Figure 10 As shown, the SFQ pulse input module 11 receives the clock input signal and the pulse input signal, and generates 16 parallel set pulses Set1, Set2...Set16 and parallel reset pulses Reset1, Reset2...Reset16 accordingly.

[0101] Specifically, as an example, the SFQ pulse input module 11 includes: a D flip-flop 111, a first-channel one-to-many pulse transmission network 112, and a second-channel one-to-many pulse transmission network 113.

[0102] The D flip-flop 111 receives and generates complementary first output signal Set and second output signal Reset based on the clock input signal and data input signal; both the clock input signal and the data input signal are SFQ pulses. When a data input signal is present between the two clock input signals, the first output terminal of the D flip-flop 111 is triggered to output the corresponding output signal Set; for example... Figure 11 As shown, if there is data input between the first and second clock cycles (and between the third and fourth clock cycles), then at the second clock cycle (and fourth clock cycle), a pulse will be output from the Q terminal of the first output of the D flip-flop 111. When there is no data input signal between the two clock input signals, the second output of the D flip-flop 111 will output the corresponding output signal Reset; as shown... Figure 11As shown, there is no data input between the second and third clock cycles (the fourth and fifth clock cycles, the fifth and sixth clock cycles, and the sixth and seventh clock cycles). Therefore, at the third clock cycle (the fifth, sixth, and seventh clock cycles), the second output of the D flip-flop 111 will be... A pulse is output from the terminal. Any structure that can achieve synchronous triggering based on the above relationship between the data input signal and the clock input signal is applicable to the D flip-flop of this invention; as an example, such as Figure 12As shown, the D flip-flop 111 is composed of a Josephson junction and a superconducting transmission line inductor. The superconducting transmission line inductors L201, L202, L203, L204, L205, L206, Josephson junction J215, and superconducting transmission line inductors L207, L208, L209, L210, L211, and L212 are connected in series. The input terminal serves as the clock input, and the output terminal serves as the first output terminal Q of the D flip-flop. One end of the Josephson junction J201 is connected to the clock input, and the other end is grounded. One end of the Josephson junction J202 is connected between superconducting transmission line inductors L202 and L203, and the other end is grounded. One end of the Josephson junction J203 is connected to... One end of the superconducting transmission line inductor L203 is connected between L203 and L204, and the other end is grounded; one end of the Josephson junction J204 is connected between superconducting transmission line inductors L205 and L206, and the other end is grounded; one end of the Josephson junction J205 is connected between superconducting transmission line inductors L208 and L209, and the other end is grounded; one end of the Josephson junction J206 is connected between superconducting transmission line inductors L209 and L210, and the other end is grounded; one end of the Josephson junction J207 is connected between superconducting transmission line inductors L211 and L212, and the other end is grounded; a bias current I21 is applied between superconducting transmission line inductors L201 and L202; superconducting transmission line inductors L204 and L20... A bias current I22 is applied between inductors L206 and L211; a bias current I23 is applied between superconducting transmission line inductors L213, L214, L215, L216, L217, Josephson junction J210, superconducting transmission line inductors L218, L219, and Josephson junction J212 are connected in series, with the input terminal serving as the data input terminal, and the output terminal connected between superconducting transmission line inductor L206 and Josephson junction J215; one end of Josephson junction J208 is connected to the data input terminal, and the other end is grounded; one end of Josephson junction J209 is connected between superconducting transmission line inductors L214 and L215, and the other end is grounded; Josephson junction J211... One end of the superconducting transmission line inductor L212 is connected between the Josephson junction J210 and the superconducting transmission line inductor L212, and the other end is grounded; a bias current I24 is applied between superconducting transmission line inductors L213 and L214; one end of superconducting transmission line inductor L220 is connected between superconducting transmission line inductors L216 and L217, and the other end is connected between superconducting transmission line inductors L207 and L208; a bias current I25 is applied between superconducting transmission line inductors L215 and L216; superconducting transmission line inductors L221, L222, L223, and L224 are connected in series, with their input connected between superconducting transmission line inductors L218 and L219, and their output serving as the second output of a D flip-flop. One end of Josephson junction J213 is connected between Josephson junction J221 and superconducting transmission line inductor L222, and the other end is grounded; one end of Josephson junction J214 is connected between Josephson junction J223 and superconducting transmission line inductor L224, and the other end is grounded; a bias current I26 is applied between superconducting transmission line inductors L222 and L223.

[0103] The first-path multi-pulse transmission network 112 is connected to the first output terminal of the D flip-flop, dividing the first output signal into 16 parallel set pulses; the second-path multi-pulse transmission network 113 is connected to the second output terminal of the D flip-flop, dividing the second output signal into 16 parallel reset pulses. In this embodiment, the first-path multi-pulse transmission network 112 and the second-path multi-pulse transmission network 113 have the same structure; when a pulse arrives at the input terminal of the network, 16 pulses will be output simultaneously at the output terminal of the network. As an example, each multi-pulse transmission network includes multiple 1-to-2 units 1a, such as... Figure 13 As shown, taking a 1-to-4 split as an example, it includes three 1-to-2 split units 1a. The first 1-to-2 split unit 1a splits the input signal into two paths. The second and third 1-to-2 split units 1a further split the two output signals of the first 1-to-2 split unit 1a into two paths, resulting in four output signals. And so on, by splitting the signal into two paths four times, 16 output signals can be obtained. The details are not elaborated here. The 1-to-2 splitter unit 1a consists of a superconducting transmission line inductor and a Josephson junction. The superconducting transmission line inductors L31 and L32 are connected in series, with their input terminals serving as the input terminals of the 1-to-2 splitter unit 1a and a bias current I31 applied to their output terminals. One end of the Josephson junction J31 is connected between the superconducting transmission line inductors L31 and L32, and the other end is grounded. One end of the superconducting transmission line inductor L33 is connected to the output terminal of the superconducting transmission line inductor L32, and the other end is connected to one end of the Josephson junction J32, serving as the first output terminal of the 1-to-2 splitter unit 1a. The other end of the Josephson junction J32 is grounded. One end of the superconducting transmission line inductor L34 is connected to the output terminal of the superconducting transmission line inductor L32, and the other end is connected to one end of the Josephson junction J33, serving as the second output terminal of the 1-to-2 splitter unit 1a.

[0104] like Figure 9 As shown, the 16 RS flip-flops 12 each receive a set pulse and a reset pulse. When the set pulse arrives, they generate and store a magnetic flux quantum, and when the reset pulse arrives, they release the stored magnetic flux quantum.

[0105] Specifically, in this embodiment, the structures of each RS flip-flop 12 are identical, and any circuit structure that can realize RS triggering function based on set and reset signals is applicable to this invention. For example... Figure 14As shown, as an example, the RS trigger 12 includes a first Josephson transmission line 121, a second Josephson transmission line 122, a first buffer 123, a second buffer 124, and a flux storage loop 125. One end of the first Josephson transmission line 121 serves as a set terminal, and the other end is connected to the first end of the flux storage loop 125 via the first buffer 123; one end of the second Josephson transmission line 122 serves as a reset terminal, and the other end is connected to the second end of the flux storage loop 125 via the second buffer 124. In the first Josephson transmission line 121, superconducting transmission line inductors L41 and L42 are connected in series, with the input terminal serving as the set terminal; one end of the Josephson junction J41 is connected to the set terminal, and the other end is grounded; one end of the Josephson junction J42 is connected to the output terminal of the superconducting transmission line inductor L42, and the other end is grounded; a bias current I41 is applied between the superconducting transmission line inductors L41 and L42. The second Josephson transmission line 122 includes Josephson junctions J43 and J44, superconducting transmission line inductors J43 and J44, and a bias current I42. Its connection relationship corresponds to that of the first Josephson transmission line 121, and will not be detailed here. The first buffer 123 is composed of a Josephson junction J45, and the second buffer 124 is composed of a Josephson junction J46. Superconducting transmission line inductors L45 and L46 are connected in series between the first buffer 123 and the flux storage loop 125, and a bias current I43 is applied between L45 and L46. A superconducting transmission line inductor L47 is also connected in series between the second buffer 124 and the flux storage loop 125. The two ends of inductor Lc in the flux storage loop 125 serve as the two ends of the flux storage loop 125; one end of Josephson junction J47 is connected to the first end of inductor Lc, and the other end is grounded; one end of Josephson junction J48 is connected to the second end of inductor Lc, and the other end is grounded.

[0106] More specifically, such as Figure 14 and Figure 9 As shown, the first buffer 123 acts as a unidirectional buffer, preventing the pulse input at the Set terminal from being transmitted in the opposite direction to the Set input port; the second buffer 124 also acts as a unidirectional buffer, preventing the pulse input at the Reset terminal from being transmitted in the opposite direction to the Reset input port. When a Set pulse signal enters the RS flip-flop from the right, it first passes through the first Josephson transmission line 121 and the first buffer 123 before reaching the flux storage loop 125. This loop stores a flux quantum and begins to show a counter-clockwise loop current. The flux stored in this loop can be coupled into the corresponding asymmetric SQUID superconducting ring 13 through mutual inductance. The asymmetric SQUID superconducting ring 13 then outputs a high voltage, corresponding to the rising edge of the SVD output signal, such as... Figure 15The waveform diagram is shown below. When a Reset pulse signal enters the RS flip-flop from the left, it first passes through the second Josephson transmission line 122 and the second buffer 124 before reaching the flux storage loop 125. The flux quantum stored in this loop is then released, and the counterclockwise loop current disappears. This loop starts to output a zero voltage through the mutually inductively coupled asymmetric SQUID superconducting loop 13, which corresponds to the falling edge of the SVD output signal, as shown below. Figure 15 The waveform diagram is shown below. Furthermore, the storage loop in RS flip-flop 12 is designed to hold at most one magnetic flux quantum, so in... Figure 15 As can be seen from the waveform, when there are two consecutive Set pulses, it is equivalent to two magnetic flux quanta entering the storage loop. At this time, the storage loop can still only hold one magnetic flux quantum, and the excess magnetic flux quantum will be released along the grounding path.

[0107] like Figure 9 As shown, 16 asymmetric SQUID superconducting rings 13 are cascaded in sequence to form a series structure.

[0108] Specifically, in this embodiment, each asymmetric SQUID superconducting ring 13 has the same structure; the inductor Lc of the RS flip-flop 12 is coupled to the corresponding asymmetric SQUID superconducting ring 13 through mutual inductance. When the Set and Reset pulse signals are input to the RS flip-flop, the inductor Lc applies magnetic flux to the corresponding asymmetric SQUID superconducting ring 13. Since the asymmetric SQUID superconducting ring 13 itself is a flux-to-voltage converter, a voltage is output across the asymmetric SQUID superconducting ring 13. Sixteen such identical asymmetric SQUID superconducting rings 13 are cascaded together, resulting in a higher voltage output across the SQUID array. In fact, the high level in the CMOS logic level output by the SVD is actually a signal after low-pass filtering of continuous high-frequency Josephson oscillations, and the output link of the SVD stage (not included in this invention) acts as such a low-pass filter.

[0109] like Figure 16 As shown, each asymmetric SQUID superconducting ring 13 includes a first Josephson junction J1 and a parallel resistor Rsh, and a second Josephson junction J2. The first Josephson junction J1 and the parallel resistor Rsh are connected in parallel to form a first junction region, and the second Josephson junction J2 forms a second junction region. The first junction region and the second junction region are connected in parallel. The damping parameter β of the first Josephson junction J1 is... C Greater than 0 and less than or equal to 1; Damping parameter β of the second Josephson junction J2 C Much greater than 1, including but not limited to 10 or greater; for example, a range of 10 to 10000. L S1 and L S2It is a loop inductor of an asymmetric SQUID superconducting ring 13.

[0110] Compared to conventional SQUID superconducting rings, the two junctions are symmetrical and β C The asymmetric junction of this invention can significantly increase the output voltage of a SQUID, since the values ​​of all values ​​are less than 1. This is because when the magnetic flux in the RS flip-flop storage loop is coupled to such an asymmetric SQUID superconducting ring through mutual inductance, the second Josephson junction J2 without parallel resistance will enter a faster Josephson oscillation state, while the first Josephson junction J1 with parallel resistance Rsh is to prevent the SQUID's IV curve from exhibiting hysteresis. Thus, this asymmetric SQUID superconducting ring 13 can output a higher voltage. For SVDs, using this asymmetric SQUID can increase the output voltage amplitude of the SVD without increasing the number of SQUID array stages.

[0111] like Figure 9 As shown, in another implementation of the present invention, the superconducting voltage drive circuit 1 further includes a terminating resistor R. T Termination resistor R T It is connected in series at the ground terminal of the asymmetric SQUID superconducting ring series structure or between any two asymmetric SQUID superconducting rings 13.

[0112] Specifically, in this example, the terminating resistor R T A connection is made between the first-stage asymmetric SQUID superconducting ring 13 and ground to reduce the quality factor of the SQUID array. As the physical meaning of the quality factor is, a smaller quality factor means a shorter duration of Josephson oscillation, which reduces the fall time of the SVD output signal and thus improves the SVD's operating speed. In other words, the terminating resistor R... T The larger the value of R, the shorter the fall time of the SVD output signal, meaning the higher the maximum operating speed the SVD can support. However, the swing of the SVD output signal will decrease accordingly. Conversely, the terminating resistor R... T The smaller the value, the longer the fall time of the SVD output signal, meaning the maximum operating speed the SVD can support will decrease, while the swing of the SVD output signal will increase. For the SVD, because it is a high-speed interface circuit, the higher the supported operating speed and the larger the output signal swing, the better (a larger swing means a higher signal-to-noise ratio and stronger signal interference immunity). As an example, the terminating resistor R... T The resistance value is set to 0.1Ω~50Ω. In practical use, the requirements of operating speed and output swing need to be considered, and a compromise is made by setting the terminating resistor R. T The resistance value is not limited to that in this embodiment.

[0113] like Figure 17As shown, the synchronous superconducting voltage drive circuit 1 of this embodiment is tested. An SVD test chip 22 is designed based on the superconducting voltage drive circuit 1 of this embodiment. When designing the SVD test chip 22, some input interface circuits need to be added to the SVD test chip 22 to facilitate testing. The function of these input interface circuits is to convert the CMOS logic level signals of the data input and clock input from the bias tee 35 and 36 into SFQ pulse signals, and then provide them to the superconducting voltage drive circuit 1 of this embodiment. The critical current density J of the process used in the superconducting voltage drive circuit 1 of this embodiment is... C 6kA / cm 2 .

[0114] like Figure 17 As shown, during low-speed testing of the SVD test chip 22, the PCB with the SVD test chip 22 bonded to it is mounted on the test rod 21, which is inserted into the liquid helium Dewar 2. The superconducting testing system 37 provides the SVD test chip 22 with DC bias, data signals, and clock signals. The signals output by the SVD test chip 22 are directly connected to the superconducting testing system 37 (here). Figure 17 (Not shown in the drawing).

[0115] Figure 17 This is a system block diagram for high-speed testing of the SVD test chip 22. During high-speed testing of the SVD test chip 22, the DC bias is provided by the superconducting test system 37, while the high-frequency input and output signals of the SVD test chip 22 require numerous radio frequency devices and components. The microwave signal source 31 provides clock signals to the bias tee 36 and the digital sampling oscilloscope 6 via a power divider 33, and the programmable code generator 32 provides data signals to the bias tee 35 and the digital sampling oscilloscope 6 via a power divider 34. A 10MHz reference clock is used for synchronization between the microwave signal source 31 and the programmable code generator 32. After being output from the test probe 21, the output signal of the SVD test chip 22 is first pre-amplified by a low-noise amplifier 4, then limited and shaped by a limiting amplifier 5, and finally connected to the digital sampling oscilloscope 6.

[0116] like Figure 18As shown, this is the low-speed test waveform of the SVD test chip 22. The clock input and data input signals are the input current signals provided by the superconducting test system 37 to the test chip. The SVD output signal is the voltage signal output by the SVD test chip 22. It can be seen that the SVD output and data input patterns are consistent (the SVD output lags behind the data input), indicating that the SVD in this embodiment is working correctly. Because the SVD uses an asymmetric squuid, the signal swing of the SVD output can reach up to 6.8mV (considered a high amplitude in existing SVD literature). The high-speed test of this SVD can achieve a maximum speed of 15Gbps. 9 -1 pseudo-random number signal input and 20Gbps sine wave signal input.

[0117] Example 2

[0118] like Figure 19 As shown, this embodiment provides an asynchronous superconducting voltage drive circuit 1, where N is set to 16; the difference from Embodiment 1 is that the D flip-flop in the SFQ pulse input module 11 is replaced with a T flip-flop.

[0119] like Figure 19 As shown, in this embodiment, the SFQ pulse input module 11 includes: a T flip-flop 114, a first-channel one-to-many pulse transmission network 112, and a second-channel one-to-many pulse transmission network 113.

[0120] The T flip-flop 114 receives and generates complementary first output signals Set and Reset based on the data input signal; the data input signal is an SFQ pulse. The data input signal sequentially and alternately triggers the first and second output terminals of the T flip-flop 114 to output corresponding output signals. For example... Figure 20 As shown, when a pulse arrives at the data input terminal, the first output terminal Q of the T flip-flop 114 outputs a pulse; when another pulse arrives at the data input terminal, the second output terminal of the T flip-flop 114 outputs a pulse. The output terminal generates a pulse; this process repeats. Any structure capable of asynchronous triggering based on a data input signal is suitable for the T flip-flop of this invention; as an example, such as... Figure 21As shown, in the T flip-flop 114, superconducting transmission line inductors L501 and L502 are connected in series, with the input terminal serving as the data input terminal; one end of the Josephson junction J51 is connected between superconducting transmission line inductors L501 and L502, and the other end is grounded; a bias current I51 is also applied between superconducting transmission line inductors L501 and L502; one end of the Josephson junction J52 is connected to the output terminal of superconducting transmission line inductor L502, and the other end is connected to the first terminal of the Josephson junction J54 via superconducting transmission line inductor L503; the second terminal of the Josephson junction J54 is grounded; one end of the Josephson junction J53 is connected to the output terminal of superconducting transmission line inductor L502, and the other end is connected to the first terminal of the Josephson junction J55 via superconducting transmission line inductor L504; the Josephson junction J55... The second end is grounded; superconducting transmission line inductors L505, L506, and L507 are connected in series between the first ends of Josephson junctions J54 and J55; superconducting transmission line inductors L508, L509, and L510 are connected in series, with one end connected between superconducting transmission line inductors L505 and L506, and the other end serving as the first output terminal Q of T flip-flop 114; a bias current I52 is applied between transmission line inductors L508 and L509; one end of Josephson junction J56 is connected between transmission line inductors L509 and L510, and the other end is grounded; superconducting transmission line inductors L511, L512, and L513 are connected in series, with one end connected between superconducting transmission line inductors L506 and L507, and the other end serving as the second output terminal of T flip-flop 114. One end of the Josephson junction J57 is connected between transmission line inductors L511 and L512, and the other end is grounded; a bias current I53 is applied between transmission line inductors L512 and L513.

[0121] The structure and connection relationship of the first-path multi-pulse transmission network 112 and the second-path multi-pulse transmission network 113 are the same as those in Embodiment 1, and will not be described in detail here.

[0122] It should be noted that the specific circuit structures provided in this invention (D flip-flop, T flip-flop, one-to-many pulse transmission network, RS flip-flop) are only examples and are not limited to this embodiment.

[0123] The present invention also provides an electronic product, which includes the superconducting voltage driving circuit 1 of the present invention; the superconducting voltage driving circuit 1 of the present invention has the advantages of high speed, high output voltage and compact structure.

[0124] In summary, this invention provides a superconducting voltage driving circuit and electronic product, comprising: an SFQ pulse input module, a bias current source, N RS flip-flops, and N asymmetric SQUID superconducting rings, where N is a natural number greater than or equal to 2; the SFQ pulse input module receives SFQ pulses and generates complementary set and reset signals based on the SFQ pulses; wherein the set signal consists of N parallel set pulses, and the reset signal consists of N parallel reset pulses; each RS flip-flop receives one set pulse and one reset pulse respectively, generating and storing a magnetic flux quantum when the set pulse arrives, and storing a magnetic flux quantum when the reset pulse arrives. When a bit pulse arrives, the stored magnetic flux quantum is released; each asymmetric SQUID superconducting ring is cascaded to form a series structure; one end of the series structure is grounded, and the other end serves as the output terminal of the superconducting voltage drive circuit; a bias current source is connected to the output terminal of the series structure to provide DC bias for each asymmetric SQUID superconducting ring; each asymmetric SQUID superconducting ring senses the magnetic flux quantum in each RS flip-flop and generates a corresponding output voltage under the action of the bias current source; the voltages output by each asymmetric SQUID superconducting ring are superimposed to form a total output voltage, which is transmitted to the external receiving circuit via a transmission line. The superconducting voltage drive circuit and electronic products of this invention employ an asymmetric SQUID design, resulting in high output swing, fast operating speed, small circuit area, compact structure, and wide applicability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0125] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superconducting voltage drive circuit, characterized in that, The superconducting voltage driving circuit includes at least: The system consists of an SFQ pulse input module, a bias current source, N RS flip-flops, and N asymmetric SQUID superconducting rings, where N is a natural number greater than or equal to 2. The SFQ pulse input module receives SFQ pulses and generates complementary set and reset signals based on the SFQ pulses; wherein the set signal consists of N parallel set pulses and the reset signal consists of N parallel reset pulses. Each RS flip-flop receives a set pulse and a reset pulse respectively. When the set pulse arrives, it generates and stores a magnetic flux quantum, and when the reset pulse arrives, it releases the stored magnetic flux quantum. Each asymmetric SQUID superconducting ring is cascaded to form a series structure; one end of the series structure is grounded, and the other end serves as the output terminal of the superconducting voltage driving circuit; the bias current source is connected to the output terminal of the series structure to provide DC bias for each asymmetric SQUID superconducting ring. Each asymmetric SQUID superconducting ring corresponds to a magnetic flux quantum in each RS flip-flop and generates a corresponding output voltage under the action of the bias current source; the voltages output by each asymmetric SQUID superconducting ring are superimposed to form a total output voltage, which is transmitted to the external receiving circuit through the transmission line.

2. The superconducting voltage drive circuit according to claim 1, characterized in that: The superconducting voltage drive circuit also includes a terminating resistor, which is connected in series between the ground terminal of the series structure or between any two asymmetric SQUID superconducting rings.

3. The superconducting voltage drive circuit according to claim 1, characterized in that: The asymmetric SQUID superconducting ring includes a first Josephson junction and a parallel resistor, and a second Josephson junction; The first Josephson junction and the parallel resistor are connected in parallel to form a first junction region, and the second Josephson junction forms a second junction region. The first junction region and the second junction region are connected in parallel. The damping parameter of the first Josephson junction is greater than 0 and less than or equal to 1, and the damping parameter of the second Josephson junction is greater than or equal to 10.

4. The superconducting voltage drive circuit according to claim 1, characterized in that: N is set to a natural number between 2 and 100.

5. The superconducting voltage drive circuit according to claim 1, characterized in that: The SFQ pulse input module includes: a D flip-flop, a first-channel one-to-many pulse transmission network, and a second-channel one-to-many pulse transmission network; The D flip-flop receives and generates complementary first and second output signals based on the clock input signal and the data input signal; wherein the clock input signal and the data input signal are both SFQ pulses; The first one-to-many pulse transmission network is connected to the first output terminal of the D flip-flop, and divides the first output signal into N parallel set pulses; The second one-to-many pulse transmission network is connected to the second output terminal of the D flip-flop, dividing the second output signal into N parallel reset pulses.

6. The superconducting voltage drive circuit according to claim 5, characterized in that: When there is a data input signal between the two clock input signals, the first output terminal of the D flip-flop is triggered to output the corresponding output signal; when there is no data input signal between the two clock input signals, the second output terminal of the D flip-flop is triggered to output the corresponding output signal.

7. The superconducting voltage drive circuit according to claim 1, characterized in that: The SFQ pulse input module includes: a T trigger, a first-channel one-to-many pulse transmission network, and a second-channel one-to-many pulse transmission network; The T flip-flop receives and generates complementary first and second output signals based on the data input signal; wherein the data input signal is an SFQ pulse; The first one-to-many pulse transmission network is connected to the first output terminal of the T flip-flop, and divides the first output signal into N parallel set pulses; The second one-to-many pulse transmission network is connected to the second output terminal of the T flip-flop, and divides the second output signal into N parallel reset pulses.

8. The superconducting voltage drive circuit according to claim 7, characterized in that: The data input signal is based on the T flip-flop, which sequentially and alternately triggers the first output terminal and the second output terminal to output the corresponding output signal.

9. The superconducting voltage drive circuit according to any one of claims 1-3, characterized in that: The RS trigger includes a first Josephson transmission line, a second Josephson transmission line, a first buffer, a second buffer, and a flux storage loop; One end of the first Josephson transmission line receives the set pulse, and the other end is connected to the first end of the magnetic flux storage loop via the first buffer. One end of the second Josephson transmission line receives the reset pulse, and the other end is connected to the second end of the flux storage loop via the second buffer.

10. An electronic product, characterized in that, The electronic product includes at least the superconducting voltage drive circuit as described in any one of claims 1-9.

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