Phase-locked loop with synchronized clock signal

Abstract

This invention relates to a phase-locked loop (PLL), comprising: a phase acquisition unit for detecting the phase of a reference signal and outputting a measurement signal; a phase deviation acquisition unit for generating an error signal from the measurement signal and a target signal; a loop filter for filtering the error signal; a modulator unit for modulating the filtered error signal and generating a tuned signal; and an oscillator for generating an output signal from the tuned signal, wherein a feedback signal formed by the output signal of the PLL is provided to the phase acquisition unit, wherein the PLL further comprises: a frequency divider unit configured to create a modulator clock signal from the oscillator clock signal of the oscillator and provide the modulator clock signal to the modulator unit; and a sampler unit for detecting the offset between the reference signal and the modulator clock signal to take the offset into account when acquiring the error signal.

Description

Technical Field

[0001] This invention relates to a phase-locked loop (PLL). The PLL has a modulator. Here, the modulated clock signal is adapted to an external reference. Background Technology

[0002] In digital phase-locked loops (PLLs), Delta-Sigma modulation is known, for example. The start of modulation in a PLL is inherently tied to the available clock edges of the modulator clock, as these clock edges control the variation of the tuned signal generated by the modulator. While the phase relationship between the reference signal and the oscillator can be determined by phase measurement if this clock is derived from the oscillator clock, the phase relationship between the reference clock and the modulator clock cannot be determined. Summary of the Invention

[0003] The phase-locked loop according to the invention, having a modulator clock derived from an oscillator, implements a reset-free clock divider, characterized by low leakage current and high-speed operation. For this purpose, the internal divider state is sampled and / or a phase counter is used for a portion of the divider stage, wherein the divider is configured to generate a modulator clock from the oscillator clock.

[0004] A phase-locked loop (PLL) comprises a phase acquisition unit, a phase deviation acquisition unit, a loop filter, a modulator unit, and an oscillator, particularly a voltage-controlled oscillator (VCO). The phase acquisition unit detects the phase difference between a reference signal and a feedback signal and outputs a measurement signal representing that phase difference. The phase deviation calculation unit is used to obtain the phase deviation from the measured signal. and target signal Generate error signal The loop filter settings are used to filter error signals. Filtering is performed. The modulator unit is used to modulate the filtered error signal and generate a tuned signal, wherein the oscillator is configured to generate an output signal from the tuned signal.

[0005] The phase acquisition unit is provided with a feedback signal formed by the output signal of the phase-locked loop. This forms an adjustment loop that regulates the phase of the output signal.

[0006] Furthermore, the phase-locked loop (PLL) has a frequency divider unit, such as a frequency divider unit. The frequency divider unit is configured to generate a modulator clock signal from the oscillator clock signal of the oscillator. The PLL is configured to provide the modulator clock signal to the modulator unit. Therefore, the start of modulation depends on the presence of the oscillator clock signal. By creating the modulator clock signal from the oscillator clock signal, the defined phase relationship between the modulator clock signal and the oscillator clock signal is naturally known. This invention also enables the determination of the phase relationship between the modulator clock signal and the oscillator clock signal to achieve precise synchronization of the modulation.

[0007] Thus, the phase-locked loop has a sampler unit configured to detect the offset between the reference signal and the modulator clock signal. The phase deviation calculation unit is configured to calculate the error signal. This offset is taken into account. Therefore, the modulation can be aligned with the reference signal.

[0008] Preferred extensions of the invention are shown below.

[0009] The sampler unit is preferably configured to sample the state of the flip-flops of the frequency divider unit. In this way, the state of the frequency divider unit can be detected. Subsequently, the modulator clock signal generated by the frequency divider unit can be directly inferred from the state of the frequency divider unit. The sampler unit is configured to perform each sampling step according to the clock of the reference signal. In this way, the offset between the reference signal and the modulator clock signal can be obtained.

[0010] The frequency divider unit advantageously has an N-bit counter module for detecting the clock of the oscillator clock signal. Here, N is a natural number and thus represents the size of the counter module. One of the N bits can be output as the modulator clock signal, thereby performing frequency division. By selecting appropriate bits, the desired division ratio can be set to a power of 2. In this case, the sampler unit has at least one sampler for sampling the N bits of the counter module. The sampler can be controlled by the data output of a control flip-flop. It is particularly advantageous to have multiple samplers, especially two, where each sampler has its own control flip-flop. One of the two samplers is set for the rising edge, and the other is set for the falling edge. Thus, the oscillator clock signal can be considered both positively and negatively. This enables reliable detection of the oscillator clock signal. The data input of the control flip-flop is a reference signal. The clock input of the control flip-flop is the oscillator clock signal. If multiple samplers and therefore multiple control flip-flops exist, one of the control flip-flops is configured to use the oscillator clock signal as its clock input in reverse order, thus responding to the falling edge. The sampler unit also includes a calculation unit configured to calculate the offset based on the division ratio of the divider unit and the sampler's output. Since the division ratio is a power of 2, this can be performed very simply. In particular, the current duration until the next rising edge of the modulator clock signal can be easily calculated using the following formula. : .

[0011] Here, It is the period of the oscillator. It is the frequency division ratio, and It is the output of the sampler.

[0012] A particularly advantageous feature is that the frequency divider unit has additional logic circuitry for achieving further division ratios that are not powers of 2. One implementation is an additional shift register. This additional shift register is typically formed by connected flip-flops. The additional shift register is clocked by one of the N output bits of the counter module. In this way, division ratios that are not powers of 2 can be achieved. For this purpose, a bit of the additional shift register can replace the bit of the counter module that clocks the additional shift register as the modulator clock signal output. In other words, the clock of this bit is further divided by the additional shift register. The size of the additional shift register is used to set this subdivision, thereby achieving any division ratio in the final result.

[0013] In this configuration, the sampler unit also samples the additional shift register. For this purpose, the sampler unit has at least one additional sampler for sampling the additional shift register, which can be controlled by a control flip-flop. It is also preferable to use two additional samplers, one of which can be driven by a control flip-flop for the rising edge, and the other by a control flip-flop for the falling edge. The calculation unit is configured to calculate the deviation based on the division ratio of the divider unit and the outputs of the sampler and the additional samplers. In particular, the current duration until the next rising edge of the modulator clock signal can be easily calculated using the following formula. : .

[0014] Here, It is the period of the oscillator. It is the frequency division ratio. It is the output of the additional sampler, and It concerns the bit for clocking the additional sampler. The output of the sampler. Function It is a classic conversion from thermometer code to binary code, that is, for example for 3 bits: 000->0, 001->1, 011->2, 111->3, 110->4, 100->5.

[0015] In an alternative configuration, the sampler unit preferably has an N-bit counter module for detecting the clock of the oscillator clock signal, where N is a natural number. The divider unit is configured to output the modulator clock signal. Furthermore, it is preferable that the sampler unit has at least one sampler for sampling the N bits of the counter module, said sampler being controllable by the data output of a control flip-flop. It is particularly advantageous to have multiple samplers, especially two, where each sampler has its own control flip-flop. One of the two samplers is used for the rising edge, and the other for the falling edge. Therefore, the oscillator clock signal can be considered both positively and negatively. This allows for reliable detection of the oscillator clock signal. The data input to the control flip-flop is a reference signal. The clock input to the control flip-flop is the oscillator clock signal. If multiple samplers and therefore multiple control flip-flops exist, one of the control flip-flops is configured to use the oscillator clock signal as its clock input in reverse phase, thus responding to the falling edge. In this alternative configuration, the divider unit and the sampler unit are particularly constructed completely separately. In this case, the sampler unit also samples the divider unit. For this purpose, the sampler unit has at least one additional sampler for sampling the frequency divider unit, which can be controlled by a control trigger. It is also preferable to use two additional samplers, one of which can be driven by a control trigger for the rising edge, and the other by a control trigger for the falling edge. The sampler unit also has a calculation unit configured to calculate the offset based on the division ratio of the frequency divider unit, the output of the sampler, and the output of the additional samplers. In particular, the current duration until the next rising edge of the modulator clock signal can be calculated, as in other configurations. The formula to be used for this purpose is specific to the exact configuration of the frequency divider unit, and in particular to the specific implementation of the frequency divider unit through the circuit.

[0016] The phase-locked loop preferably includes a timing unit. The timing unit is configured to determine the offset from the offset between the modulator clock signal and the reference signal. Offset It can be provided to the phase deviation acquisition unit for use in obtaining the measured signal. Offset and target signal Generate error signal In this way, the offset during modulation can be taken into account. Therefore, the modulation is correctly aligned with the reference signal.

[0017] The modulator unit preferably includes a modulator and a scrambler connected downstream of the modulator. The scrambler is particularly used for "mismatch shaping" and / or "transition control." The scrambler is preferably configured to provide metadata describing the basic properties of the selection of the active elements of the modulator. The modulator unit also preferably includes an impairment module configured to extract signal impairment from the metadata of the scrambler and from predefined calibration data. Additionally, the impairment module is configured to feed the signal impairment back to the modulator. Therefore, the modulator can take into account the impairment of the active elements in the next modulation step. This allows the effects of many detailed impairments to be considered without providing highly complex or completely impossible oscillator models. Thus, the phase-locked loop achieves high modulation accuracy with low implementation cost and simplicity.

[0018] Modulators, especially Delta-Sigma modulators, can be used to create, in particular, digital tuning words as tuning signals. It is especially advantageous that the entire phase-locked loop (PLL) is a digital PLL.

[0019] The phase-locked loop preferably has a pre-defined unit. The pre-defined unit is configured to generate the target signal. The pre-given unit is also configured to output information about the target signal to the modulator. The information includes, in particular, a ramp generator for generating a ramp signal. This ramp signal is then converted into the target signal via an integrator. The ramp signal is also output to the modulator.

[0020] The phase acquisition unit preferably has a series circuit consisting of a digital-to-time converter and a phase measurement unit. The phase measurement unit is, for example, a time-to-digital converter. The digital-to-time converter is particularly connected upstream of the phase measurement unit. A reference signal can be provided to the digital-to-time converter, and the output of the digital-to-time converter can be provided to the phase measurement unit. In particular, the output of the digital-to-time converter can be provided to the phase measurement unit as a clock signal. The digital-to-time converter is particularly used to apply dithering to the reference signal based on a relatively coarse quantization step size of the phase measurement unit, especially the time-to-digital converter. Furthermore, a feedback signal can be provided to the phase measurement unit. In this way, the measurement signal can be obtained simply and reliably. . Attached Figure Description

[0021] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the drawings: Figure 1This is a schematic diagram of a phase-locked loop according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a first variation of the combination of the frequency divider unit, counter unit, and sampler unit of the phase-locked loop according to this embodiment of the invention, with a frequency division ratio that is a power of 2. Figure 3 This is a schematic diagram of a second variation of the combination of the frequency divider unit, counter unit, and sampler unit of the phase-locked loop according to this embodiment of the invention for other frequency division ratios, and... Figure 4 This is a schematic diagram of a third variation of the phase-locked loop with a separate frequency divider unit, sampler unit, and counter unit according to an embodiment of the present invention.

[0022] Preferably, the same parts, elements and / or units in all the figures are given the same reference numerals. Detailed Implementation

[0023] Figure 1 Phase-locked loop 1, also known as a phase-locked loop (PLL), is schematically shown. In particular, PLL 1 is a digital phase-locked loop, also known as a digital phase-locked loop (DPLL), or an all-digital phase-locked loop, also known as an all-digital phase-locked loop (ADPLL).

[0024] Phase-locked loop 1 is used to track the phase of oscillator 6 based on the phase of reference signal 100. In the illustrated embodiment, digitally controlled oscillator 6, also known as digitally controlled oscillator (DCO), is provided. Phase-locked loop 1 has a phase acquisition unit 2 configured to detect the phase difference between reference signal 100 and feedback signal 200 and output a measurement signal representing that phase difference. .

[0025] Phase acquisition unit 2 has a series circuit consisting of a digital-to-time converter 11 and a phase measurement unit 12. The phase measurement unit 12 is, for example, a time-to-digital converter. The digital-to-time converter 11 is connected upstream of the phase measurement unit 12 and is used to apply dithering to a reference signal 100, which can be provided to the digital-to-time converter 11. The output of the digital-to-time converter 11 can be provided to the phase measurement unit 12, wherein the applied dithering is advantageous considering the relatively coarse quantization step size of the time-to-digital converter, which is the phase measurement unit 12. Furthermore, a feedback signal 200 can be provided to the phase measurement unit 12.

[0026] The phase-locked loop 1 also includes a modulator unit 5, wherein, in the illustrated embodiment, modulation is applied as a two-point modulation. For this purpose, pre-set units 13 and 14 are provided, configured to generate a target signal. In the illustrated embodiment, the pre-given units 13 and 14 have a ramp generator 13 for generating a ramp signal. This ramp signal is converted into a target signal by an integrator 14. The ramp signal is also output to modulator unit 5.

[0027] Phase deviation acquisition unit 3 is configured to obtain the phase deviation from the measured signal. and target signal Generate error signal By considering the target signal Modulation is performed at the first point to achieve the two-point modulation.

[0028] Phase-locked loop 1 has a function for processing error signals. The loop filter 4 performs filtering, and its output can be provided to the modulator unit 5. The loop filter 4 is, for example, a digital loop filter, also known as a digital loop filter (DLF).

[0029] Modulator unit 5 is configured to modulate the filtered error signal and generate a tuning signal 500. Oscillator 6 can be controlled by tuning signal 500, wherein oscillator 6 is configured to generate an output signal 300 from tuning signal 500. Feedback signal 200 provided to phase acquisition unit 2 is formed from output signal 300 of phase-locked loop 1.

[0030] Modulator unit 5 represents the second point of a two-point modulation. Modulator unit 5 has a modulator 7 and a scrambler 9 connected downstream of modulator 7. Modulator 7 is, for example, a Delta-Sigma modulator. Scrambler 9 is used specifically for "mismatch shaping" and / or "transition control". Scrambler 9 is configured to provide metadata 600, which describes the basic properties of the selection of active elements of oscillator 6.

[0031] Modulator unit 5 has an impairment module 10. Impairment module 10 is used to extract signal impairment from metadata 600 of scrambler 9 and predefined calibration data 400. Signal impairment 700 is fed back to modulator 7.

[0032] Phase-locked loop 1 also includes a frequency divider unit 8 and a sampler unit 15. Modulation performed by modulator unit 5 is controlled by a modulator clock signal 800, which is created from the oscillator clock signal 400 of oscillator 6 by means of frequency divider unit 8. Therefore, frequency divider unit 8 is configured to create the modulator clock signal 800 and provide it to the clock input of modulator unit 5. In this way, although the relationship between oscillator clock signal 400 and modulator clock signal 800 created by frequency division is given, the relationship between reference signal 100 and modulator clock signal 800 is unknown. However, this information is relevant if modulation should be precisely aligned with reference signal 100. Therefore, sampler unit 15 is provided. Sampler unit 15 is configured to detect the offset 900 between reference signal 100 and modulator clock signal 800. This allows for the determination of the error signal. Consider an offset of 900.

[0033] In particular, the illustrated embodiment includes a time setting unit 16 configured to calculate the offset from an offset of 900. The offset obtained in this way The signal is provided to the phase deviation calculation unit 3. Therefore, the phase calculation unit uses the measurement signal. Offset and target signal To generate error signals Therefore, it is shown that an offset of 900° is considered during modulation, thereby ensuring that the modulation is correctly aligned with the reference signal 100.

[0034] Basically, the sampler unit 15 is configured to sample the state of the flip-flops in the frequency divider unit 8. This allows the state of the frequency divider unit 8 to be identified. Each sampling step can be performed according to the clock of the reference signal 100. Therefore, the offset 900 can be reliably determined. The exact determination of the offset 900 depends on the specific structure of the frequency divider unit 8. Different variations are described below.

[0035] Figure 2 The first variant is schematically shown, where the division ratio of the frequency divider unit 8 is a power of 2. In this case, the frequency divider unit 8 has an N-bit counter module 17, where N is a natural number, for detecting the clock of the oscillator clock signal 400, wherein the counter module 17 directly has the state required for detecting the offset 900. In this case, frequency division is performed very simply by using one of the N bits as the modulator clock signal 800. Figure 2 In this context, this is represented by a multiplexer, where one bit of its N output bits serves as the modulator clock signal 400. Therefore, by selecting the appropriate bit k, the corresponding division ratio can be set. .

[0036] Sampler unit 15 has at least one first sampler 18a and a second sampler 18b for sampling N bits of counter module 17. The first sampler 18a is controlled by the data output of a first control flip-flop 19a, and the second sampler 18b is controlled by a second control flip-flop 19b. The first sampler 18a is configured for rising edges, and the second sampler 18b is configured for falling edges. Therefore, the oscillator clock signal 400 can be considered both positively and negatively. This allows for reliable detection of the oscillator clock signal 400. The respective data inputs of control flip-flops 19a and 19b are reference signals 100. The clock input of the first control flip-flop 19a is the oscillator clock signal 400. The second control flip-flop 19b uses the oscillator clock signal 400 in reverse phase as its clock input, thus responding to falling edges. The first sampler 18a and the second sampler 18b are connected via a multiplexer that selects the desired output from the two samplers 18a and 18b.

[0037] Sampler unit 15 has a calculation unit 22 connected downstream of the multiplexer, and therefore selectively receives the output of the first sampler 18a or the output of the second sampler 18b. Calculation unit 22 is configured to calculate the offset 900 based on the division ratio of the divider unit 8 and the output of either the first sampler 18a or the second sampler 18b. Since the division ratio is a power of 2, this can be performed very simply. In particular, the current duration until the next rising edge of the modulator clock signal 800 can be easily calculated using the following formula. : .

[0038] Here, It is the period of the oscillator. It is the frequency division ratio, and The output is selected by the multiplexer from the two samplers 18a and 18b.

[0039] The second variation is Figure 3 As shown in the diagram, a division ratio other than a power of 2 is implemented here. For this purpose, the divider unit 8 has at least one additional shift register 21. The additional shift register 21 is formed, for example, by a connected flip-flop. Furthermore, the additional shift register is clocked by one of the N bits of the counter module 17. Therefore, further division is possible, where the size of the additional shift register 21 determines the division ratio.

[0040] Instead of the output counter module 17, which clocks the additional shift register 21, one bit of the additional shift register 21 is output as the modulator clock signal 800. Figure 3In the variant shown, the additional shift register 21 is a 3-bit shift register. This achieves a division ratio of 12.

[0041] In order to also sample the state of the additional shift register 21, the sampler unit 15 has at least one additional sampler 20a, 20b that can be controlled by control flip-flops 19a, 19b for sampling the additional shift register 21. The first additional sampler 20a is configured for the rising edge, and the second additional sampler 20b is configured for the falling edge.

[0042] The calculation unit 22 is reconfigured. Calculation unit 22 is configured to calculate the deviation 900 based on the division ratio of the frequency divider unit 8 and the outputs of the first sampler 18a or the second sampler 18b and the first additional sampler 20a or the second additional sampler 20b, wherein the respective multiplexers are selected among the outputs of samplers 18a, 18b and additional samplers 20a, 20b. In particular, the current duration up to the next rising edge of the modulator clock signal 800 can be easily calculated using the following formula. : .

[0043] Here, It is the period of the oscillator. It is the frequency division ratio. It is the output of the additional sampler, and It concerns the bit for clocking the additional sampler. The output of the sampler. Function It is a classic conversion from thermometer code to binary code, such as 000->0, 001->1, 111->3, 100->5.

[0044] The third variation is Figure 4 As shown in the diagram. Any frequency divider unit 8 can be used here, where the principles explained above still apply.

[0045] In the third variant, the sampler unit 15 has an N-bit counter module 17 for detecting the clock of the oscillator clock signal 400, where N is a natural number. Unlike the variant described above, this counter module 17 is not used for actual frequency division. Instead, for this purpose, the frequency divider unit 8 is separately configured for outputting the modulator clock signal 800.

[0046] The sampler unit 15 further includes a first sampler 18a and a second sampler 18b, which are constructed and configured similarly to the first or second variant for sampling N bits of the counter module 17. The first sampler 18a and the second sampler 18b are controlled by corresponding data outputs of the first control flip-flop 19a and the second control flip-flop 19b, which are constructed and arranged similarly to the first or second variant.

[0047] In order to sample the frequency divider unit 8, the sampler unit 15 has a first additional sampler 20a and a second additional sampler 20b, similar to the second variant. The additional samplers 20a and 20b can be controlled by corresponding control triggers 19a and 19b.

[0048] Sampler unit 15 also has a calculation unit 22 similar to the first or second variant. Therefore, the calculation unit is configured to calculate the offset 900 based on the division ratio of divider unit 8 and the outputs of the first sampler 18a or the second sampler 18b and the first additional sampler 20a or the second additional sampler 20b. The formula used for this is specific to the exact configuration of the divider unit, and especially specific to the specific implementation of the divider unit through the circuitry.

Claims

1. A phase-locked loop (1), comprising: - Phase acquisition unit (2), used to detect the phase of the reference signal (100) and output the measurement signal. , - Phase deviation calculation unit (3), used to obtain the phase deviation from the measured signal and target signal Generate error signal , - Loop filter (4), used to filter the error signal Perform filtering. - Modulator unit (5), used to modulate the filtered error signal and generate a tuning signal (500), and - Oscillator (6) for generating output signal (300) from the tuning signal (500). in, The phase acquisition unit (2) is provided with a feedback signal (200) formed by the output signal (300) of the phase-locked loop (1), and The phase-locked loop (1) further comprises: - A frequency divider unit (8), configured to create a modulator clock signal (800) from the oscillator clock signal (400) of the oscillator (6) and provide the modulator clock signal (800) to the modulator unit (5), and - Sampler unit (15), the sampler unit is used to detect the offset (900) between the reference signal (100) and the modulator clock signal (800) in order to obtain the error signal The offset (900) is taken into account.

2. The phase-locked loop (1) according to claim 1, characterized in that, The sampler unit (15) is configured to sample the state of the flip-flops of the frequency divider unit (8), wherein each sampling step can be performed according to the clock of the reference signal (100).

3. The phase-locked loop (1) according to claim 1 or 2, characterized in that, The frequency divider unit (8) has an N-bit counter module (17) for detecting the clock of the oscillator clock signal (400). Where N is a natural number, Of these, one bit out of the N bits can be used as the modulator clock signal (800) output. The sampler unit (15) has at least one sampler (18a, 18b) for sampling N bits of the counter module (17), and the sampler can be controlled by the data output of the control triggers (19a, 19b). The data input of the control triggers (19a, 19b) is the reference signal (100), and the clock input of the control triggers (19a, 19b) is the oscillator clock signal (400). The sampler unit (15) has a calculation unit (22) configured to calculate the offset (900) based on the division ratio of the frequency divider unit (8) and the output of the samplers (18a, 18b).

4. The phase-locked loop (1) according to claim 3, characterized in that, The frequency divider unit (8) has at least one additional shift register (21), which is formed, in particular, by a connected flip-flop. The additional shift register is clocked by one of the N bits of the counter module (17). In this configuration, bits of the additional shift register (21) can replace the bits of the counter module (17) that control the clock of the additional shift register (21) as the output of the modulator clock signal (800). The sampler unit (15) has at least one additional sampler (20a, 20b) controllable by the control triggers (19a, 19b) for sampling the additional shift register (21), and The calculation unit (22) is configured to calculate the offset (900) based on the division ratio of the frequency divider unit (8), the output of the samplers (18a, 18b), and the output of the additional samplers (20a, 20b).

5. The phase-locked loop (1) according to claim 1 or 2, characterized in that, The sampler unit (15) has an N-bit counter module (17) for detecting the clock of the oscillator clock signal (400). Where N is a natural number, The frequency divider unit (8) is configured to output the modulator clock signal (800). The sampler unit (15) has at least one sampler (18a, 18b) for sampling N bits of the counter module (17), and the sampler can be controlled by the data output of the control triggers (19a, 19b). The data input of the control triggers (19a, 19b) is the reference signal (100), and the clock input of the control triggers (19a, 19b) is the oscillator clock signal (400). The sampler unit (15) has at least one additional sampler (20a, 20b) controllable by the control triggers (19a, 19b) for sampling the frequency divider unit (8), and The sampler unit (15) has a calculation unit (22) configured to calculate the offset (900) based on the division ratio of the frequency divider unit (8) and the outputs of the samplers (18a, 18b) and the outputs of the additional samplers (20a, 20b).

6. The phase-locked loop (1) according to any one of the preceding claims, characterized in that... Time setting unit (16), the time setting unit being configured to obtain the offset from the offset (900) , wherein the offset It can be provided to the phase deviation calculation unit (3) for obtaining the measurement signal. The offset and the target signal Generate the error signal .

7. The phase-locked loop (1) according to any one of the preceding claims, characterized in that, The modulator unit (5) has a modulator (7) and a scrambler (9) connected downstream of the modulator (7), and The modulator unit (5) has an impairment module (10) configured to obtain signal impairment from metadata (600) of the scrambler (9) and predefined calibration data (400), and the impairment module is configured to feed back the signal impairment to the modulator (7).

8. The phase-locked loop (1) according to any one of the preceding claims, characterized in that, The modulator (7) is a Delta-Sigma modulator.

9. The phase-locked loop (1) according to any one of the preceding claims, characterized in that... Pre-given units (13, 14), the pre-given units being configured to generate the target signal The pre-given units (13, 14) are further configured to output the target signal to the modulator (7). Information.

10. The phase-locked loop (1) according to any one of the preceding claims, characterized in that, The phase acquisition unit (2) has a series circuit consisting of a digital-to-time converter (11) and a phase measurement unit (12), wherein a reference signal (100) can be provided to the digital-to-time converter (11), and wherein the output of the digital-to-time converter (11) and the feedback signal (200) can be provided to the phase acquisition unit (12).

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