Frequency synthesizer system with kick-start circuitry
The frequency synthesizer system with kick-start circuitry efficiently starts up high-frequency oscillators using a low-frequency phase locked loop for synchronization, addressing parasitic oscillation issues and reducing phase noise through hardware reuse.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
- Filing Date
- 2024-12-02
- Publication Date
- 2026-06-11
Smart Images
Figure EP2024084328_11062026_PF_FP_ABST
Abstract
Description
[0001] P109464W001
[0002] 1
[0003] FREQUENCY SYNTHESIZER SYSTEM WITH KICK-START CIRCUITRY
[0004] TECHNICAL FIELD
[0005] Embodiments herein relate to frequency synthesizer system. In particular, they relate to frequency synthesizer system with kick-start circuitry, method for operating the frequency synthesizer system, antenna array and electronic apparatus comprising the frequency synthesizer system.
[0006] BACKGROUND
[0007] In wireless communication systems, advanced antenna systems (AAS) and especially such operating at millimeter waves (mmW) or higher frequencies (HF) have stringent requirements on phase noise of local oscillator (LO) signals. Typically, LO signals are generated by frequency synthesizers using phase locked loops (PLLs) operating with a reference oscillator. A key phase noise contributor is the reference clock, where a higher reference frequency may be beneficial as the phase noise multiplication from reference frequency to LO frequency is reduced. However, increasing the reference oscillator frequency is associated with several technical issues. For example, the frequency accuracy is reduced when implementing the higher frequency reference oscillator using a crystal oscillator (XO), distribution of the higher frequency reference signal may be both power hungry and lossy in terms of purity of the signal, a high frequency crystal oscillator (HF XO) is more sensitive to parasitic oscillations far from the desired resonance frequency and may need assistance in order to start at the wanted resonance frequency.
[0008] A solution to these issues may be to place XOs locally close to Radio Frequency (RF) or HF synthesizers of the AAS. To achieve the frequency and phase accuracy, a loop is formed around the RF synthesizer using a lower stable frequency as a “golden” reference. The system is described in patent US 10,505,555 B2. Although the solution offers an opportunity to use HF XOs for superior phase noise and energy efficient reference signal distribution, the HF XO suffers from larger sensitivity to parasitic oscillations and especially if driven with a too large current to start up the HF XO quickly, chances of ending up at a parasitic oscillation instead of the desired resonance frequency are large.
[0009] In patent US 9,692,354 B2, a solution is provided mainly to aid fast XO start-up for reduced power consumption. The solution may also be beneficial for avoiding parasitic oscillations. In patent US 10,312,860 B2, an oscillator core including a kick-starting circuitry provides fast start-up as well as avoidance of parasitic oscillations. However, both solutions require a substantial amount of additional hardware for the XO start-up. Further, the P109464W001
[0010] 2 frequency accuracy of the kick start signals may be affected by process, voltage and temperature (PVT) meaning that the time for start-up signal injection is limited and thereby also the energy that could be used for kick start.
[0011] SUMMARY
[0012] Therefor it is an object of embodiments herein to provide a frequency synthesizer system and a method for operating the frequency synthesizer system with improved performance.
[0013] According to a first aspect of embodiments herein, the object is achieved by a frequency synthesizer system. The frequency synthesizer system comprises a first phase tracking circuitry configured to receive a first frequency reference signal generated by a first reference oscillator and a first feedback signal to generate a frequency control signal. The frequency synthesizer system further comprises a second Phase Locked Loop (PLL) configured to receive a second frequency reference signal and generate an output signal. The frequency synthesizer system further comprises a second reference oscillator configured to generate the second frequency reference signal. The frequency synthesizer system further comprises a first frequency divider configured to generate the first feedback signal from the output signal of the second PLL. The frequency synthesizer system further comprises a kickstart circuitry. During a start-up period of the frequency synthesizer system, the kick-start circuitry is configured to calibrate the second PLL based on the first frequency reference signal using the first phase tracking circuitry and inject a kick-start signal generated from the output signal of the second PLL to the second reference oscillator for starting-up the second reference oscillator.
[0014] According to a second aspect of embodiments herein, the object is achieved by a method for operating the frequency synthesizer system described above. During a start-up period of the frequency synthesizer system, the second PLL is calibrated based on the first frequency reference signal using the first phase tracking circuitry and a kick-start signal generated from the output signal of the second PLL is injected to the second reference oscillator for starting-up the second reference oscillator.
[0015] In other words, embodiments herein provide a frequency synthesizer system comprising several frequency synthesizers with phase lock loops, e.g. a low frequency PLL and a high frequency PLL, each has a local frequency reference oscillator. A central “golden” reference, i.e. the low frequency reference oscillator, is used to synchronize the frequency synthesizers outputs in frequency and phase. For fast startup and robustness against parasitic oscillations in the high frequency reference oscillator, the high frequency P109464W001
[0016] 3
[0017] PLL synthesizer is first locked only to the golden reference and a frequency divided output thereof is used to kick-start the high frequency reference oscillator at the preferred resonance frequency.
[0018] The frequency synthesizer system and method according to embodiment herein have some advantages.
[0019] For example, using high frequency reference oscillator has a potential to reduce RF synthesizer phase noise through reduced synthesizer divider ratio.
[0020] Using high frequency reference oscillator for localized reference generation enables an energy efficient clock distribution solution.
[0021] Hardware already existing in the frequency synthesizer system is reused instead of using a separate PLL to kick-start the high frequency reference oscillator.
[0022] Using the calibrated RF oscillator for startup enables the high frequency reference oscillator startup at the correct resonance frequency.
[0023] Startup of the high frequency reference oscillator is efficient in that no extra time is needed to lock a separate PLL to a golden reference since the calibration of the RF oscillator is needed in any way during normal operation.
[0024] Therefore, the embodiments herein provide an improved frequency synthesizer system and an improved method for operating the frequency synthesizer system with regard to, e.g. phase noise, startup time, hardware reuse, frequency accuracy etc.
[0025] BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Examples of embodiments herein are described in more detail with reference to attached drawings in which:
[0027] Figure 1 is a schematic block view of a frequency synthesizer system according to prior art;
[0028] Figure 2 is a schematic block view of a frequency synthesizer system according to embodiments herein;
[0029] Figure 3 is a schematic block view of an RF frequency synthesizer according to embodiments herein;
[0030] Figure 4 is a flow chart for operating a frequency synthesizer system according to embodiments herein;
[0031] Figure 5 is a flow chart illustrating a method for operating a frequency synthesizer system according to embodiments herein;
[0032] Figure 6 is a schematic block view illustrating an exemplary AAS; P109464W001
[0033] 4
[0034] Figure 7 is a block diagram illustrating an electronic apparatus in which a frequency synthesizer system according to embodiments herein may be implemented.
[0035] DETAILED DESCRIPTION
[0036] As part of developing embodiments herein, problems and limitations related to the prior art solutions will be first identified and discussed.
[0037] Figure 1 shows a frequency synthesizer system 100 according to prior art. The frequency synthesizer system 100 comprises a low bandwidth digital phase tracking system 110 comprising a digital phase detector Dig PD 112 and a digital low pass filter DLF 114. The frequency synthesizer system 100 further comprises a high bandwidth RF synthesizer RF Synth 120 with a fractional-N divider, a low frequency (LF) reference oscillator LF RO 130 to generate an LF reference signal to the low bandwidth digital phase tracking system 110, a high frequency reference oscillator HF RO 140 to generate an HF reference signal to the high bandwidth Fractional-N RF synthesizer 120. The LF reference signal is referred to as a golden reference REF Golden due to its high accuracy and stability. The HF RO 140 is free running. The frequency synthesizer system 100 may further comprise a frequency divider Freq. Div 150.
[0038] Using local HF reference oscillators, e.g. the HF reference oscillator HF RO 140, in an RF synthesizer, e.g. the RF synthesizer 120, has many benefits, whereof the major is a possibility to reduce the phase noise multiplication factor related to the overall divide ratio N in the RF synthesizer 120. A drawback of HF reference oscillators is that the higher the frequency, the higher the sensitivity to parasitic components, potentially creating unwanted resonances in the HF reference oscillators. Furthermore, high frequency reference oscillators implemented by crystal oscillators (XO) with smaller geometries reduces fabrication relative accuracy resulting in a less accurate centre reference frequency. This means that tuning of the HF XO by adding capacitance is undesired as the HF XO overall quality factor then is reduced drastically, potentially degrading phase noise performance and reducing the benefits of using the higher frequency.
[0039] In an RF synthesizer using a fractional-N divider, there is a possibility to overcome the frequency and phase variation through controlling a frequency control word (FCW) to the fractional-N divider in a loop. As shown in Figure 1, an output of the RF synthesizer 120 or a frequency divided RF synthesizer output signal is compared to the golden reference signal REF Golden generated by the LF reference oscillator 130 in the digital phase detector Dig PD 112 to generate a phase error Ph Err. The phase error PH Err is filtered by the digital filter DLF 114 to generate a control signal Ctl. The control signal Ctl is adjusted by an initial frequency control word FCW to generate an adjusted frequency control word FCW'. The P109464W001
[0040] 5 adjusted frequency control word FCW' is used to control the fractional-N divider comprised in the RF synthesizer 120.
[0041] However, the difficulty to make the HF RO 140 start up at the desired resonance is not immediately resolved by the above solution and furthermore, for optimal phase noise performance, one might like to design the oscillator core in such a way that startup of the oscillator is literally impossible. Therefor it is desired to help the HF RO 140 start with a signal having a frequency very close to the desire resonance. Furthermore, to start up the HF RO 140 safely it is preferred that frequency accuracy of the startup signal is high and that the energy injected is spread out over a larger number of periods, making sure that the desired resonance is reached.
[0042] Most RF synthesizer oscillators of today are tuned coarsely through digital control of capacitor banks. The digital value needs to be set during startup through a calibration algorithm. Once calibrated, the output signal frequency of the RF synthesizer is the desired operating frequency. Then dividing the output signal frequency of the RF synthesizer with a divide ratio aimed for high performance operation will generate a frequency very close to the HF RO wanted resonance frequency.
[0043] According to embodiments herein, the divided signal of the RF synthesizer 120 is used for injection into the HF RO 140 for a fast startup and robust operation.
[0044] Figure 2 shows a frequency synthesizer system 200 with a kick-start circuitry according to embodiments herein. The frequency synthesizer system 200 comprises a first phase tracking circuitry 210 comprising a first digital phase detector Dig PD 212 and a first digital low pass filter DLF 214. The frequency synthesizer system 200 further comprises a second HF Phase Locked Loop HF PLL 220 and a kick-start circuitry 230. The frequency synthesizer system 200 may further comprise a first LF reference oscillator LF RO 240, a second HF reference oscillator HF RO 250 and a first frequency divider Freq Div 260. The first reference oscillator LF RO 240 may be part of the frequency synthesizer system 200 or external thereto.
[0045] The first phase tracking circuitry 210 is configured to receive a first frequency reference signal 241 from the first reference oscillator LF RO 240, and a first feedback signal 261 from the first frequency divider Freq Div 260 to generate a frequency control signal 215.
[0046] The first digital phase detector Dig PD 212 is configured to generate a first digital representation of a detected phase error Ph Err 213 between the first frequency reference signal 241 and the first feedback signal 261 generated from the output signal 221 of the second PLL 220. P109464W001
[0047] 6
[0048] The first digital loop filter DLF 214 is configured to generate the frequency control signal 215 based on the first phase error 213 generated by the first phase detector Dig PD 212.
[0049] The first phase tracking circuitry 210 further comprises a combiner 218 configured to generate an adjusted frequency control word FCW’ based on an initial frequency control word FCW and the frequency control signal 215.
[0050] The second HF PLL 220 is configured to receive a second frequency reference signal 251 generated by the second reference oscillator HF RO 250 and generate an output signal 221.
[0051] The first frequency divider 260 is configured to generate the first feedback signal 261 from the output signal 221 of the second HF PLL 220.
[0052] During a start-up period of the frequency synthesizer system 200, the kick-start circuitry 230 is configured to tune or calibrate the second HF PLL 220 based on the first frequency reference signal 241 using the first phase tracking circuitry 210 and inject a kick-start signal 223 generated from the output signal 221 of the second PLL 220 to the second reference oscillator 250 for starting-up the second reference oscillator 250.
[0053] The kick-start circuitry 230 may comprise a controller Conti 232 configured to generate different control signals to the first phase tracking circuitry 210 and the second HF PLL 220.
[0054] The kick-start circuitry 230 may further comprise a switch 234 connected in a path between the second reference oscillator HF RO 250 and a second frequency divider comprised in the second HF PLL 220.
[0055] The kick-start circuitry 230 may further comprise a multiplexer 236 configured to select a frequency control word among the initial frequency control word FCW and the adjusted frequency control word FC to apply to the second HF PLL 220 based on a first control signal Sei 231 from the controller 232.
[0056] The kick-start circuitry 230 may further comprise a register R 238 configured to apply a tuning signal TS 239 to the second HF PLL 220 based on a second control signal RFO Ctrl hold 235 from the controller 232.
[0057] The kick-start circuitry 230 may generate a third control signal LF hold 233 to apply to the second HF PLL 220.
[0058] The kick-start circuitry 230 may generate a fourth control signal, i.e. a kick-start enable signal 237 for turn-on or turn-off the switch 234.
[0059] Figure 3 shows a schematic block view of the second HF PLL 220. The second HF PLL 220 comprises a second phase detector PD 224 configured to generate a second phase P109464W001
[0060] 7 error 225 between the second frequency reference signal 251 and a second feedback signal 223 generated from the output signal 221 of the second HF PLL 210.
[0061] The second HF PLL 220 further comprises a second loop filter LF 226 configured to generate an output signal 227 based on the second phase error 225 generated by the second phase detector PD 224.
[0062] The second HF PLL 220 further comprises a controlled oscillator, e.g. a radio frequency oscillator RFO 228, configured to receive the output signal 227 from the second loop filter 226 and generate the output signal 221 of the second HF PLL 220.
[0063] The second HF PLL 220 further comprises a second frequency divider Freq Div 222 configured to generate the second feedback signal 223 from the output signal 221 of the second HF PLL 220.
[0064] The second PLL 220 is configured to receive at least one control signals from the kickstart circuitry 230, such as a divider control signal N for controlling the divide ratio of the second frequency divider 222, a low pass filter hold signal LF Hold 233 for holding the output signal 221 of the second loop filter 226, a tuning signal TS 239 for coarse tuning the controlled oscillator RFO 228, a kick-start enable signal 237 for turn-on or turn-off the switch 234.
[0065] Figure 4 is a flow chart showing an exemplary start-up process 400 for the frequency synthesizer system 200. The start-up process 400 comprises a coarse tuning or calibration procedure, a kick-start procedure and a fine-tuning procedure which may be performed by e.g. the kick-start circuitry 230, as described in the following steps which may be performed in any suitable order or simultaneously.
[0066] 410: The frequency synthesizer system 200 is powered on.
[0067] 412: An initial frequency control word FCW is applied to control a divide ratio of the second frequency divider 222, and an initial tuning signal is applied to control the frequency of RFO 228. The initial tuning signal may be an initial coarse tuning word applied to the capacitor banks comprised in the RFO 228to digitally control the frequency of RFO 228.
[0068] 413: A divide ratio is calculated for the first frequency divider 260 based on the desired frequency of the RFO 228 and the first frequency reference signal 241.
[0069] 414: Calibrating the RFO 228 is started, i.e. a coarse tuning procedure of the RFO 228 is started using the first phase tracking circuitry 210 by applying the divide ratio to the first frequency divider 260, comparing the divided output signal 261 of the RFO 228 with the first frequency reference signal 241 in the first digital phase detector Dig PD 212 to generate a digital representation of the phase error between the output signal of the RFO 228 and the P109464W001
[0070] 8 first frequency reference signal 241 , filtering the phase error to generate a frequency control signal 215. adjusting the initial tuning signal based on the t frequency control signal 215.
[0071] 415: Whether the RFO 228 is calibrated is checked, i.e. by checking if the output signal of the RFO 228 is locked to the first reference oscillator 240, by e.g. checking the DLF 214 output behaviour, i.e. the status, locked / unlocked can be determined from observing the DLF 214 output, i.e. the frequency control signal 215. If the RFO 228 is calibrated, the divided output signal 261 of the RFO 228 will have the same frequency as the first reference signal 241 , and the phase difference will remain stable or within an acceptable range, the frequency control signal 215 reaches a final frequency control signal and a final coarse tuning word will be generated based on the final frequency control signal 215. If the phase difference is not stable or not within an acceptable threshold, the frequency control signal 215 will change and the coarse tuning signal will be adjusted based on the frequency control signal 215 to adjust the frequency of the RFO 228 until the phase difference remains stable or within an acceptable threshold.
[0072] 416: A divided output signal of the RFO 228 is injected into the HF RO 250 when the RFO 228 has been calibrated. Once the RFO 228 is calibrated, the output signal frequency is the desired operating frequency and dividing it with the divide ratio aimed for high performance operation will generate a frequency very close to the HF RO 250 wanted resonance frequency.
[0073] 417: Waiting a predefined number of cycles so that the second reference oscillator HF RO 250 is started.
[0074] 418: The final tuning signal obtained during the coarse tuning procedure of the RFO 228 is kept and applied to the capacitors bank of the RFO 228, a pre-set fine tuning of the RFO 228 is released, i.e. the loop of the second PLL 220 is closed and the second reference oscillator 250, the second phase detector PD 224 and the second low pass filter LF 226 of second PLL 220 are used to fine tune the RFO 228.
[0075] 419: Waiting a predefined number of cycles.
[0076] 420: Whether the second PLL 220 is locked is checked, i.e. by checking if the output signal of the RFO 228 is locked to the second reference oscillator 250, by e.g. checking the LF 226 output behaviour, i.e. the status, locked / unlocked can be determined from observing the LF 226 output signal 227. If the RFO 228 is locked, the RFO 228 output signal will have the same frequency as the second reference signal, and the phase difference will remain stable or within an acceptable range.
[0077] If the second PLL 220 is not locked, the method goes back to step 419 to wait a few more cycles until the second PLL 220 is locked. P109464W001
[0078] 9
[0079] If the second PLL 220 is locked, the method goes to step 421: An operation of the first phase tracking circuitry 210 is started as usual procedure.
[0080] According to some embodiments herein, to perform the start-up process 400 for the frequency synthesizer system 200, the kick-start circuitry 230 may be configured to calibrate or tune coarsely the second PLL 220 based on the first frequency reference signal 241. The kick-start circuitry 230 may be configured to, by the controller 232, apply different control signals to control the second HF PLL. The different control signals may be applied in any suitable order or simultaneously.
[0081] The kick-start circuitry 230 may be configured to apply a first control signal 231 to the multiplexer 236 to select the initial frequency control word FCW to control a divide ratio of the second frequency divider 222.
[0082] The kick-start circuitry 230 may be configured to apply a second control signal 235 to the register 238 to apply a tuning signal 239 based on the frequency control signal 215 to the controlled oscillator 228.
[0083] The kick-start circuitry 230 may be configured to apply a third control signal 233 to the second PLL 220 to open the phase locked loop of the second PLL 220 by holding the output signal 227 generated from the second loop filter 226. That is, the output signal 227 from the second loop filter 226 is kept constant in order not to interfere with the calibration. If the second loop filter 226 is implemented by an analog loop filter, it may be done by generating pre-defined voltages and connecting capacitors in the loop filter to the pre-defined voltages through switches. If the second loop filter 226 is implemented by a digital loop filter, one may add a corresponding feature when designing the loop filter. It is wise to assign a value in the middle of the available range for the output signal 227 in order not to overflow or underflow as soon as the loop closes.
[0084] After the second PLL 220 is calibrated or tuned, the kick-start circuitry 230 is configured to inject a kick-start signal 223 generated from the output signal 221 of the second PLL 220 to the second reference oscillator 250 by being configured to apply a fourth control signal 237 to the switch 234 to turn on the switch 234 for a predefined time period to inject the second feedback signal 223 generated by the second frequency divider 222 as a kick-start signal to the second reference oscillator HF RO 250.
[0085] Several implementation variants are possible depending on divide ratios of the second frequency divider 222. The most accurate HF RO kick start injection signal may be achieved making sure that the RFO 228 oscillator frequency is an integer multiple of the desired HF RO resonance frequency. In that case the phase tracking loop divide ratio, i.e. the first P109464W001
[0086] 10 frequency divider 260 might have to be altered from the final used during phase tracking operation, also meaning that the RFO 228 needs further calibration after the HF RO 250 startup.
[0087] In case of a higher divide ratio in the second frequency divider of the RF synthesizer, i.e. the second HF PLL 220, modulation of the divide ratio and thereby the divided signal period may still suffice to have a stable enough frequency for the injection signal. In such case, the final divide ratio of the first frequency divider 260 for the phase tracking loop may be applied for the start-up procedure and the RFO 228 will not need further calibration.
[0088] According to some embodiments herein, a fractional-N RF synthesizer topology well- suited for the proposed solution may be a PLL with a Digital to Time Converter (DTC) and a Bang-Bang Phase Detector (DTC-BB). The frequency divided output is modified using the DTC to align the frequency reference signal and divided output signal phases as closely as possible and the remaining noise induced phase error is detected by the binary Bang-Bang (BB) phase detector. This topology generates a smaller period variation than e.g., a divide ratio modulated signal and thereby the injection into the HF RO 250 may be done with higher accuracy.
[0089] US 9,692,354 B2 provides a formula for estimating a suitable duration of a time period used for kick-starting, based on the frequency deviation between the kick-start signal and the resonance frequency of the reference oscillator that is subject to the kick-starting. The golden reference is assumed to have a considerably higher accuracy than the HF RO 250. Therefore, the frequency deviation between the divided frequency used for kick-starting and the resonance frequency of the HF RO 250 is almost exclusively determined by the inaccuracy of the latter. Typically, a maximum deviation is given from the crystal vendor and as an example a 983.04 MHz crystal may have a 300ppm frequency accuracy, where most of this is sample-sample variation. Compared with e.g. 1.9 % accuracy, which is used as an example in US 9,692,354 B2, a higher accuracy such as 300 ppm, allows for a longer duration of the kick-start period and increases the likelihood of hitting the desired resonance frequency.
[0090] According to some embodiments herein, after the second reference oscillator HF RO 250 has been started, the kick-start circuitry 230 may be further configured to operate the second PLL 220 to lock to the second frequency reference signal 222 by applying different control signals. The different control signals may be applied in any suitable order or simultaneously. P109464W001
[0091] 11
[0092] The kick-start circuitry 230 may be configured to apply a fourth control signal 237 to the switch 234 to turn off the switch 234 after the predefined time period.
[0093] The kick-start circuitry 230 may be configured to apply a first control signal 231 to the multiplexer 236 to select the adjusted frequency control word FCW to control the divide ratio of the second frequency divider 222.
[0094] The kick-start circuitry 230 may be configured to apply a third control signal 233 to the second PLL 220 to close the phase locked loop of the second PLL 220 by releasing the holding of the output signal 227 generated from the second loop filter 226.
[0095] The kick-start circuitry 230 may be configured to apply a second control signal, i.e. RFO Ctrl hold 235, to the register 238 to store and hold a final tuning signal 239, to the controlled oscillator 228 based on a final frequency control signal 215 generated by the first digital loop filter 214 when the second PLL 220 is calibrated.
[0096] According to embodiments herein, a method for operating the frequency synthesizer system 200 will be described with reference to Figure 5. The method comprises the following actions which may be performed in any suitable order or simultaneously.
[0097] Action 510
[0098] Tuning or calibrating the second HF PLL 220 based on the first frequency reference signal 241 using the first phase tracking circuitry 210 during a start-up period of the frequency synthesizer system 200.
[0099] According to some embodiments herein, tuning or calibrating the second PLL 220 may comprise the following actions.
[0100] Action 511
[0101] Applying a first control signal Sei 231 to a multiplexer 236 comprised in the kick-start circuitry 230 to select an initial frequency control word FCW to control a divide ratio of a second frequency divider 222 comprised in the second PLL 220.
[0102] Action 512
[0103] Applying a second control signal, i.e. disabling the holding signal RFO Ctrl hold 235, to a register 238 comprised in the kick-start circuitry 230 to apply a tuning signal 239 based on a frequency control signal 215 generated by the first phase tracking circuitry 210 to a controlled oscillator RFO 228 comprised in the second HF PLL 220.
[0104] Action 513
[0105] Applying a third control signal, LF hold 233, to the second HF PLL 220 to open the phase locked loop of the second HF PLL 220 by holding an output signal 227 generated from a second loop filter LF 226 comprised in the second HF PLL 220.
[0106] Action 520 P109464W001
[0107] 12
[0108] Injecting a kick-start signal 223 generated from the output signal 221 of the second HF PLL 220 to the second reference oscillator HF RO 250 for starting-up the second reference oscillator HF RO 250.
[0109] According to some embodiments herein, injecting a kick-start signal 223 may comprise the following action.
[0110] Action 521
[0111] Applying a fourth control signal, Kick start enable / disable 237, to turn on the switch 234 connected in a path between the second reference oscillator HF RO 250 and the second frequency divider 222 to inject a second feedback signal 223 generated by the second frequency divider 222 from the output signal 221 of the second HF PLL 220 as a kick-start signal to the second reference oscillator HF RO 250 for a predefined time period.
[0112] Action 530
[0113] Operating the second HF PLL 220 to lock to the second frequency reference signal 222, after the second HF PLL 220 has been calibrated.
[0114] According to some embodiments herein, operating the second HF PLL 220 to lock to the second frequency reference signal 222 may comprise the following actions,
[0115] Action 531
[0116] Applying a fourth control signal, Kick start enable / disable 237, to the switch 234 to turn off the switch 234 after the predefined time period.
[0117] Action 532
[0118] Applying a first control signal, Sei 231 , to the multiplexer 236 to select an adjusted frequency control word FCW generated by the combiner 218 comprised in the first phase tracking circuitry 210 based on the initial frequency control word FCW and a frequency control signal 215 generated by the DLF 214, to control the divide ratio of the second frequency divider 222.
[0119] Action 533
[0120] Applying a third control signal, i.e. disabling the holding signal LF hold 233, to the second HF PLL 220 to close the phase locked loop of the second HF PLL 220 by releasing the holding of the output signal 227 generated from the second loop filter 226.
[0121] Action 534
[0122] Applying a second control signal, i.e. enabling the holding signal RFC Ctrl hold 235, to the register 238 to store and hold a final tuning signal 239 to the controlled oscillator RFC 228 based on a final frequency control signal 215 generated by the first phase tracking circuitry 210 when the second HF PLL 220 is calibrated. P109464W001
[0123] 13
[0124] Figure 6 shows an exemplary antenna array 600 in which one or more frequency synthesizer system 200 may be implemented. In this case, the antenna array 600 comprises four antenna array units 610, 620, 630, 640, each with a 4x2 antenna array 611, 621, 631, 641 and an RF synthesizer RF Synth 612, 622, 632, 642, i.e. the second HF PLL 228. For each RF synthesizer a separate HF crystal oscillator HF RO 613, 623, 633, 643 is associated enabling short clock routing and low phase noise. Digital phase tracking loops Dig 614, 624, 634, 644 are formed having a central block with phase detectors (PD) and digital loop filters (DLF).
[0125] To summarize, a frequency synthesizer system 200 comprising several frequency synthesizers with phase lock loops LF / HF PLLs 210 / 220, having local frequency references implemented as crystal oscillators HF / LF ROs 250 / 240 is provided. A central “golden” reference, i.e. the LF RO 240, is used to synchronize the frequency synthesizers outputs in frequency and phase. For fast startup and robustness against parasitic oscillations in the HF RO 250, the HF PLL 220 synthesizer is first locked only to the golden reference and a frequency divided output thereof is used to kick-start the HF RO 250 at the preferred resonance frequency. That is a digital phase locked loop (DPLL), i.e. the first phase tracking circuitry 210, is used to lock the RF oscillator RFO 228 output to a golden low frequency reference through control of the RFO 228 coarse tuning word (TW). A frequency divider, i.e. the second frequency divider 222, is connected to the output of the RFO 228 and generates a signal for injection into the HF RO 250 for startup of the same. Once the HF RO 250 is started, the digital phase locked loop is opened and locking the output of the HF PLL 220 to the HF RO 250 is initiated instead. The tuning from the first phase tracking circuitry 210 is switched in for controlling the frequency control word (FCW) to the second frequency divider 222 of the second HF PLL 220 locking to the HF RO 250 instead of controlling the RFO TW directly during the coarse tuning procedure.
[0126] The frequency synthesizer system 200 and methods for operating the frequency synthesizer system 200 according to embodiment herein have some advantages.
[0127] For example, the high frequency HF RO 250 has a potential to reduce RF synthesizer phase noise through reduced synthesizer divider ratio and the localized reference generation enabling an energy efficient clock distribution solution. Instead of using a separate PLL to kick-start the HF RO 250 to the correct resonance frequency, hardware already existing in the frequency synthesizer system 200 with golden reference synchronization is reused. Using the calibrated RF oscillator RFO 228 for startup is also efficient in that no extra time is needed to lock a separate PLL to a golden reference. Calibration of the RF oscillator RFO 228 is needed in any way during normal operation. P109464W001
[0128] 14
[0129] The frequency synthesizer system 200 may be employed in various integrated circuits, electronic circuits, communication devices or apparatus. Figure 7 shows a block diagram for an electronic apparatus 700 in which the frequency synthesizer system 200 according to embodiments herein may be implemented. The electronic apparatus 700 may comprise a receiver or a transmitter or both i.e. a transceiver TX / RX 710 in which the frequency synthesizer system 200 according to embodiments herein may be implemented. The electronic apparatus 700 may comprise other units, where a memory 720, a processing unit 730 are shown. The electronic apparatus 700 may be any one of a communication apparatus such as any one of a base station, a wireless communication device such as a user equipment or a mobile device for a cellular communication system.
[0130] According to some embodiments herein, the electronic apparatus 700 may comprise at least one, or more frequency synthesizer system 200.
[0131] The embodiments herein for operating the frequency synthesizer system 200 may be implemented through one or more processors, such as the processing unit 730 in the electronic apparatus 700, together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product 740, for instance in the form of a data carrier carrying computer program code 750 for performing the embodiments herein when being loaded into the electronic device 700. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server or cloud and downloaded to the electronic apparatus 700.
[0132] Therefore, according to some embodiments herein, it is provided a computer program product 740 comprising program code 750 which when the program is executed by a computer / processor in the the electronic apparatus 700, cause the computer / processor to carry out the method for operating the frequency synthesizer system 200 according to embodiments herein.
[0133] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Those skilled in the art will understand that the frequency synthesizer system 200 according to embodiments herein may be implemented in any semiconductor technology, e.g., Complementary Metal Oxide Semiconductor (CMOS), Silicon on Insulator (SOI) CMOS, field-effect transistor (FET), MOSFET technology etc. P109464W001
[0134] 15
[0135] Those skilled in the art will also appreciate that the Dig PD 212, the DLF 214, the combiner 218 in the first phase tracking circuitry 210 may be referred to as one circuit or one module, or one or more processors configured with software and / or firmware and / or any other digital hardware performing the function of each module. The controller 232, the multiplexer 236, the register 238 in the kick-start circuitry 230 may be referred to as one circuit or one module, or one or more processors configured with software and / or firmware and / or any other digital hardware performing the function of each module. One or more of these processors, the combination of analog and digital circuits as well as the other digital hardware, may be included in a single application-specific integrated circuitry (ASIC), or several processors and various analog / digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).
[0136] The word "comprise" or “comprising”, when used herein, shall be interpreted as non- limiting, i.e. meaning "consist at least of".
[0137] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.
Claims
P109464W00116CLAIMS1. A frequency synthesizer system (200) comprising: a first phase tracking circuitry (210) configured to receive a first frequency reference signal (241), generated by a first reference oscillator (240), and a first feedback signal to generate a frequency control signal (215); a second Phase Locked Loop, PLL (220) configured to receive a second frequency reference signal (251) and generate an output signal (221); a second reference oscillator (250) configured to generate the second frequency reference signal (251); a first frequency divider (260) configured to generate the first feedback signal from the output signal (221) of the second PLL (220); and a kick-start circuitry (230); wherein during a start-up period of the frequency synthesizer system (200), the kickstart circuitry (230) is configured to: calibrate the second PLL (220) based on the first frequency reference signal (241) using the first phase tracking circuitry (210); and inject a kick-start signal (223) generated from the output signal (221) of the second PLL (220) to the second reference oscillator (250) for starting-up the second reference oscillator (250).
2. The frequency synthesizer system (200) according to claim 1 , wherein the kick-start circuitry (230) comprises: a controller (232) configured to generate control signals (231 , 233, 235, 237); a switch (234) connected in a path between the second reference oscillator (250) and a second frequency divider (222) comprised in the second PLL (220); a multiplexer (236) configured to select a frequency control word (FCW, FCW’) to the second PLL (220) based on a first control signal (231) from the controller (232); and a register (238) configured to apply a tuning signal (239) to the second PLL (220) based on a second control signal (235) from the controller (232).
3. The frequency synthesizer system (200) according to any one of claims 1-2, wherein the first phase tracking circuitry (210) comprises: a first digital phase detector (212) configured to generate a first digital representation of a detected phase error (213) between the first frequencyP109464W00117 reference signal (241) and the first feedback signal (261) generated from the output signal (221) of the second PLL (220), a first digital loop filter (214) configured to generate a frequency control word (215) based on the first phase error (213) generated by the first phase detector (212), a combiner (218) configured to generate an adjusted frequency control word (FCW) based on an initial frequency control word (FCW) and the frequency control signal (215) generated from the first digital loop filter (214); and the second PLL (220) comprises: a second phase detector (224) configured to generate a second phase error (225) between the second frequency reference signal (251) and a second feedback signal (223) generated from the output signal (220) of the second PLL (220), a second loop filter (226) configured to generate an output signal (227) based on the second phase error (225) generated by the second phase detector (224), a controlled oscillator (228) configured to receive the output signal (227) from the second loop filter (226) and generate the output signal (221) of the second PLL (220), a second frequency divider (222) configured to generate the second feedback signal (223) from the output signal (221) of the second PLL (220); and wherein the kick-start circuitry (230) is configured to calibrate the second PLL (220) based on the first frequency reference signal (241) by being configured to: apply a first control signal (231) to the multiplexer (236) to select the initial frequency control word (FCW) to control a divide ratio of the second frequency divider (222), apply a second control signal (235) to the register (238) to apply a tuning signal (239) based on the frequency control signal (215) generated from the first digital loop filter (214) to the controlled oscillator (228), and apply a third control signal (233) to the second PLL (220) to open the phase locked loop of the second PLL (220) by holding the output signal (227) generated from the second loop filter (226).
4. The frequency synthesizer system (200) according to any one of claims 1-3, wherein the kick-start circuitry (230) is configured to inject a kick-start signal (223) generatedP109464W00118 from the output signal (221) of the second PLL (220) to the second reference oscillator (250) by being configured to: apply a fourth control signal (237) to the switch (234) to turn on the switch (234) for a predefined time period to inject the second feedback signal (223) generated by the second frequency divider (222) as a kick-start signal to the second reference oscillator (250).
5. The frequency synthesizer system (200) according to claim 4, wherein the kick-start circuitry (230) is further configured to operate the second PLL (220) to lock to the second frequency reference signal (222) by being configured to: apply a fourth control signal (237) to the switch (234) to turn off the switch (234) after the predefined time period, apply a first control signal (231) to the multiplexer (236) to select the adjusted frequency control word (FCW) to control the divide ratio of the second frequency divider (222), apply a third control signal (233) to the second PLL (220) to close the phase locked loop of the second PLL (220) by releasing the holding of the output signal (227) generated from the second loop filter (226), and apply a second control signal (235) to the register (238) to store and hold a final tuning signal (239) to the controlled oscillator (228) based on a final frequency control signal (215) generated by the first digital loop filter (214) when the second PLL (220) is calibrated.
6. A method for operating a frequency synthesizer system (200), wherein the frequency synthesizer system (200) comprises: a first phase tracking circuitry (210) configured to receive a first frequency reference signal (241) and a first feedback signal to generate a frequency control signal (215); a second Phase Locked Loop, PLL (220) configured to receive a second frequency reference signal (251) and a frequency control signal from the first phase tracking circuitry (210) to generate an output signal (221); a first reference oscillator (240) configured to generate the first frequency reference signal (241); a second reference oscillator (250) configured to generate the second frequency reference signal (251);P109464W00119 a first frequency divider (260) configured to generate the first feedback signal from the output signal (221) of the second PLL (220); and a kick-start circuitry (230); the method comprising: during a start-up period of the frequency synthesizer system (200), calibrating (510) the second PLL (220) based on the first frequency reference signal (241) using the first phase tracking circuitry (210); and injecting (520) a kick-start signal (223) generated from the output signal (221) of the second PLL (220) to the second reference oscillator (250) for starting-up the second reference oscillator (250).
7. The method according to claim 6, wherein calibrating (510) the second PLL (220) based on the first frequency reference signal (241) using the first phase tracking circuitry (210) comprises: applying (511) a first control signal (231) to a multiplexer (236) comprised in the kick-start circuitry (230) to select an initial frequency control word (FCW) to control a divide ratio of a second frequency divider (222) comprised in the second PLL (220); applying (512) a second control signal (235) to a register (238) comprised in the kick-start circuitry (230) to apply a tuning signal (239) based on a frequency control signal (215) generated by the first phase tracking circuitry (210) to a controlled oscillator (228) comprised in the second PLL (220); and applying (513) a third control signal (233) to the second PLL (220) to open the phase locked loop of the second PLL (220) by holding an output signal (227) generated from a second loop filter (226) comprised in the second PLL (220).
8. The method according to claim 6, wherein injecting (520) a kick-start signal (223) generated from the output signal (221) of the second PLL (220) to the second reference oscillator (250) comprising: applying (521) a fourth control signal (237) to turn on a switch (234) connected in a path between the second reference oscillator (250) and the second frequency divider (222) to inject a second feedback signal (223) generated by the second frequency divider (222) from the output signal (221) of the second PLL (220) as a kick-start signal to the second reference oscillator (250) for a predefined time period.P109464W001209. The method according to claim 8, further comprises: operating (530) the second PLL (220) to lock to the second frequency reference signal (222) by: applying (531) a fourth control signal (237) to the switch (234) to turn off the switch (234) after the predefined time period, applying (532) a first control signal (231) to the multiplexer (236) to select an adjusted frequency control word (FCW) generated by a combiner (218) comprised in the first phase tracking circuitry (210) based on the initial frequency control word (FCW) and the frequency control signal (215) generated from the first digital loop filter (214), to control the divide ratio of the second frequency divider (222), applying (533) a third control signal (233) to the second PLL (220) to close the phase locked loop of the second PLL (220) by releasing the holding of the output signal (227) generated from the second loop filter (226), and applying (534) a second control signal (235) to the register (238) to store and hold a final tuning signal (239) to the controlled oscillator (228) based on a final frequency control signal (215) generated by the first phase tracking circuitry (210) when the second PLL (220) is calibrated.
10. An antenna array (600) comprising one or more frequency synthesizer system (200) according to any one of claims 1-5.11 . An electronic apparatus (700) comprising one or more frequency synthesizer system (200) according to any one of claims 1-5.
12. The electronic apparatus (700) according to claim 11 , wherein the electronic apparatus is a communication apparatus.
13. The electronic apparatus (700) according to claim 12, wherein the communication apparatus is any one of a wireless communication device and a base station for a cellular communications system.