High-speed multi-mode CMOS clock divider

Abstract

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

Description

Technical Field

[0001] An electronic circuit is provided for frequency division of an input signal. Background Technology

[0002] A clock divider is used to convert the frequency of an input signal to a lower frequency of the output signal. The ratio of the input signal frequency to the output signal frequency is called the division factor. Clock dividers are widely used in phase-locked loops (PLLs).

[0003] In a phase-locked loop (PLL), the generated clock needs to be divided to be compared with a reference clock. It is well known that the entire clock divider is divided into several stages, with the first stage having the highest speed and therefore being the most difficult to design.

[0004] The bottleneck of clock dividers is the maximum speed at which they can operate while providing a stable division ratio, taking into account variations in process voltage and temperature (PVT) under conditions of device aging or degradation.

[0005] Figure 1 is a simplified schematic diagram of an example 100 of a divide-3 CMOS logic circuit according to the prior art. The circuit consists of four gated inverters 110, 120, 130, and 140 connected in series. The outputs of the second gated inverter 120 and the fourth gated inverter 140 are connected to inputs 152 and 154 of a NAND gate 150, and its output 156 is connected to the input of the first gated inverter 110. Each gated inverter has complementary control signal inputs. As an example, the first gated inverter 110 includes a first complementary input 112 and a second complementary input 114. Each of these inputs is driven by an asymmetric clock driver 160. The asymmetric clock driver 160 provides a clock with a duty cycle greater than 50%, such that each PMOS and NMOS transistor within the gated inverter is turned on for more than 50% of the clock cycle. This is to improve the maximum operating speed. In any case, the maximum speed is limited by the propagation delay through the NAND gate 150. To accelerate NAND gate 150, its drive strength can be increased by increasing its size, but this increases the load on node div3_stage4 170, especially div3_stage2 172, which in turn becomes a speed bottleneck. If a single divider circuit must be used to provide multiple division ratios, the maximum achievable speed will be further reduced due to the complexity of this circuit, which requires more combinational logic and gated inverters. Summary of the Invention

[0006] An electronic circuit is provided.

[0007] The electronic circuit can be a high-speed CMOS logic circuit or something suitable for it.

[0008] Electronic circuits can be clock dividers.

[0009] The electronic circuit may include a ring oscillator. The ring oscillator may include multiple gated inverters. At least one of the gated inverters may be configured to receive an oscillation signal and a control signal at two complementary inputs. The electronic circuit may be configured to be partially gated, such that the division ratio may be selectable.

[0010] A ring oscillator may include at least three gated inverters. These at least three gated inverters may be arranged in series. The output of each gated inverter can be applied to the input of a subsequent gated inverter in the ring oscillator.

[0011] The control signal may include a first signal and a second signal. The first signal and the second signal may be opposite to each other.

[0012] The duty cycle of the control signal can be greater than 0.5.

[0013] At least one gated inverter can be partially gated, causing it to output either a logic high or a logic low signal depending on the logic state of the input signal. The output signal can be selected by applying partial gates to a PMOS or NMOS transistor.

[0014] Electronic circuits may include interconnections.

[0015] Gated inverters can have bus hold.

[0016] The electronic circuit can be a three-mode clock divider.

[0017] A frequency division ratio of at least 1 to 3, 4, and 5 can be selected.

[0018] In another aspect, a clock divider is provided. The clock divider may include a plurality of gated inverters subsequently coupled to each other. At least one of the gated inverters may be configured to receive an oscillation signal and a control signal. The clock divider may be configured such that the division ratio is selectable based on the control signal.

[0019] According to another aspect, an electronic circuit is provided. The electronic circuit may include a ring oscillator. The ring oscillator may include a plurality of gated inverters. At least one of the gated inverters may be configured to receive an oscillation signal and at least one auxiliary signal at an additional input. The electronic circuit may include multiple interconnections. The electronic circuit may provide a frequency division ratio selectable based on at least one auxiliary signal. Attached Figure Description

[0020] Other aspects and features of this application will become apparent from the following description of preferred embodiments with reference to the accompanying drawings, wherein:

[0021] Figure 1 is a simplified schematic diagram of an example of a CMOS logic circuit used as a 3-division clock divider according to the prior art;

[0022] Figure 2 This is a simplified schematic diagram of an example of a clock divider used as a multimode clock divider;

[0023] Figure 3 This is a simplified schematic diagram of the process signals of an example clock divider;

[0024] Figure 4 This is a simplified schematic diagram of another example of a clock divider, which is an improved multimode clock divider;

[0025] Figure 5 This is a simplified schematic diagram of a gated inverter; and

[0026] Figure 6 This is a simplified schematic diagram of the process signals based on an example clock divider. Detailed Implementation

[0027] Figure 2 This is a simplified schematic example of an electronic circuit configured as a clock divider 200. The clock divider 200 includes first to sixth gated inverters 205, 210, 215, 220, 225, and 230. The first to sixth gated inverters 205, 210, 215, 220, 225, and 230 are arranged in series and are part of a ring oscillator 201. The clock divider 200 also incorporates combinational logic to obtain the desired division factors of 3, 4, and 5.

[0028] An example of a gated inverter 280 is shown in more detail inside dashed box 290. The gated inverter 280 includes additional inputs for controlling its operating state.

[0029] The gated inverter 280 includes two p-metal-oxide-semiconductor (PMOS) transistors 283 and 284 and two n-metal-oxide-semiconductor (NMOS) transistors 285 and 286. The drain of the first PMOS 283 is coupled to the source of the second PMOS 284. The source of the first NMOS 285 is coupled to the drain of the second NMOS 286. A node 282 providing the output signal Y is arranged between the PMOS 283, 284 pair and the NMOS 285, 286 pair. This means that the output signal Y is provided at node 282 between the drain of the second PMOS 284 and the drain of the first NMOS 285.

[0030] Input signal A is coupled to the gates of the first PMOS 283 and the second NMOS 286 of the gated inverter 280. Control signals include a first signal CLK and a second signal CLKB. The first signal CLK is coupled to the gate of the first NMOS 285. The second signal CLKB is coupled to the gate of the second PMOS 284. The second signal CLKB is the opposite of the first signal CLK. This means that if CLK is logic "high", then CLKB is logic "low".

[0031] If the first signal CLK is low and the second signal CLKB is high, the gated inverter 280, supplied with the first signal CLK and the second signal CLKB, can be in a high-impedance configuration. Similarly, if the first signal CLK is high and the second signal CLKB is low, the gated inverter 280 can be in an inverter configuration. In the inverter configuration, if the input signal A is low, the gated inverter 280 can output high, and vice versa. If CLK remains low, the gated inverter 280 can always output high. In this configuration, it is expected that CLKB toggle, and the input signal A toggle or remain low. It is required that CLKB and the input signal A both go low together at a specific time. If CLKB remains high, the gated inverter 280 can always output low. In this configuration, it is expected that CLK toggle, and the input signal A toggle or remain high. It is required that CLKB and the input signal A both go high together at a specific time.

[0032] The power supply voltage 287 is coupled to the source of the first PMOS 283. The source of the second NMOS 286 is coupled to ground 288. The second, fourth, and sixth gated inverters 210, 220, and 230 of the clock divider 200 are similar to gated inverter 280. Except that the first signal CLK and the second signal CLKB are swapped compared to gated inverter 280, the first, third, and fifth gated inverters 205, 215, and 225 are similar to gated inverter 280.

[0033] The clock divider 200 includes multiple interconnects 235, 240, 245, and 250. The first interconnect 235 is located between ground 236 and node divN_stage7 237. The second interconnect 240 is located between ground 236 and node divN_stage7 237. The third interconnect 245 is located between ground 236 and node divN_stage7 237. The fourth interconnect 250 is located between the power supply voltage VA11 238 and node divN_stage7 237.

[0034] Interconnects 235, 240, 245, and 250 each include a series connection of two PMOS transistors. The gate of one PMOS transistor in the second to fourth interconnects 240, 245, and 250 is coupled to node divN_stage4 239 and is therefore shared among these interconnects. Furthermore, the gate of the first interconnect 235 is coupled to node divN_stage2 241. Node divN_stage2 241 is also coupled to the second gate of the fourth interconnect 250.

[0035] Select signal sel <3> 242 is coupled to the second gate of the first interconnect 235. Selection signal sel <4> 243 is coupled to the second gate of the second interconnect 240. The second gate of the third interconnect 245 is coupled to node divN_stage6 244.

[0036] After the additional inverter 248 has been applied for stabilization, buffering and / or runtime adjustment, the DIVout 246 of the clock divider 200 is provided at node divN_stage3 247.

[0037] The clock divider 200 operates on the basis of interconnects 235, 240, 245, and 250. The first interconnect 235 creates one cycle (1T) of DIVout high time (meaning DIVout in the state logic "high"). The second interconnect 240 creates two cycles (2T) of DIVout high time. The third interconnect 245 creates three cycles (3T) of DIVout high time. The fourth interconnect 250 creates two cycles (2T) of DIVout low time (meaning DIVout in the state logic "low").

[0038] Select signal sel <3> 242 and sel <4> 243 can be used to switch between different division ratios at DIVout 246. Since the first to third interconnects 235, 240, and 245 share the same PMOS (pull-up), the load is reduced, making the low time of DIVout 246 equal for all division ratios; that is, the low time of DIVout 246 is equal for the selection signal sel. <3> 242 and sel <4> All configurations of 243 are 2T. This results in clock divider 200 providing different division ratios. Clock divider 200 is tri-mode, allowing three different division ratios of / 3, / 4, and / 5 to be provided via selection signals 242 and 243. Control signals can therefore be used to effectively modify the operating state of clock divider 200, enabling different division ratios. Clock divider 200 is suitable for a wide range of applications. Clock divider 200 can operate over a wide range of input clock frequencies, from a few MHz to GHz. The maximum operating speed of clock divider 200 can be very high, approaching 10 GHz.

[0039] On the other hand, the duty cycles of gated inverters 205, 210, 215, 220, 225, and 230 may be distorted. This means that duty cycles greater than 0.5 can be applied, providing more "on" time. This can be achieved by using additional inverters to buffer the clock signals with asymmetric pull-up (PMOS) and pull-down (NMOS) strengths, namely the first signal CLK and the second signal CLKB. This results in a further increase in the maximum speed of clock divider 200 (sampling time, maximum frequency at which clock divider 200 can operate).

[0040] Figure 3 A schematic diagram of the process signal 300 of the clock divider 200 is shown. The x-axis shows time in nanoseconds. The y-axis shows the amplitude of the corresponding signal switching between "high" and "low".

[0041] Clk_stgln3 312 and clkb_stgln3 314 are the clock signal and the inverted clock signal for the gated inverters 205, 210, 215, 220, 225, and 230 of the gated clock divider 200. Figure 3 The clock signal frequency is 10GHz.

[0042] divN_stage1 to divN_stage7 320 are the output signals of the gated inverters 205, 210, 215, 220, 225, and 230 of the clock divider 200 as described above.

[0043] sel <4> 322 is one of the selection signals used to select between different division ratios Div-3, Div-4, and Div-5 in clock divider 200. Therefore, the output signals of the gated inverter, i.e., signals divN_stage1 to divN_stage7320, correspond to sel at different time points. <4> The 322 switch varies between Div-3, Div-4, and Div-5. DIVout324 shows the crossover output of a fresh silicon analog, and DIVout326 shows the crossover output after 10 years of aging. They are based on sel <3> , especially sel <4> The state of 322 provides different ratios between logic "high" and logic "low," allowing clock divider 200 to provide different division ratios. A comparison of DIVout 324 and the "aged" DIVout 326 of clock divider 200 clearly shows that even after 10 years of aging, clock divider 200 provides a stable output signal for a division ratio of / 3. This means that for a / 3 ratio, the output signal DIVout 326 is essentially the same as the "fresh" DIVout 324 (within negligible tolerance). However, for the remaining division ratios of / 4 and / 5, DIVout 326 differs from the "fresh" DIVout 324. This means that, considering all (physically meaningful) process voltage and temperature (PVT) variations of this device, clock divider 200 cannot yet provide a constant division ratio at a 10GHz input clock frequency within a predefined tolerance range (depending on industrial requirements) over a 10-year analog lifespan.

[0044] Figure 4 An improved high-speed CMOS logic circuit configured as a clock divider 400 is shown. Even at very high input clock rates, this high-speed divider 400 can divide the input clock signal to 1 / 3, 1 / 4, and 1 / 5. Therefore, it is a high-speed multimode divider.

[0045] Clock divider 400 includes first through seventh gated inverters 410, 415, 420, 425, 430, 435, and 440. The gated inverters 410, 415, 420, 425, 430, 435, and 440 of clock divider 400 are similar in type to those described in detail with reference to clock divider 200. Clock divider 400 includes an additional inverter 460 arranged in reverse order between node divN_stage2 416 and node divN_stage2b 470, with node divN_stage2b 470 itself coupled to the input of the first gated inverter 410.

[0046] The clock divider 400 also includes a NAND2 445, wherein the first input of the NAND2 445 is coupled to node divN_stage4 426. The second input of the NAND2 445 is coupled to the control signal clkb_stgln3427. The output of the NAND2 445 is coupled to the PMOS control input of the first gated inverter 410.

[0047] Furthermore, the clock divider 400 includes a NAND3 450, with its first input coupled to node divN_stage5431. The second input of the NAND3 450 is coupled to node divN_stage7 441, which itself is coupled to the output of the seventh gated inverter 440. The third input of the NAND3 450 is coupled to the control signal clk_stg2n4 442. The output of the NAND3 450 is coupled to the PMOS control input of the second gated inverter 415.

[0048] Based on clock signal CLK, inverted clock signal CLKB, and selection signal sel <3> 481 and sel <4> 482 provides control signal 480. Similarly, based on the selection signal sel... <3> 481 and sel <4> 482, the different division ratios of the clock divider 400 are selectable.

[0049] After applying runtime adjustment, stabilization, and / or buffering via additional inverters 491, 492, and 493, DIVout 495 of the clock divider 400 is provided at node divN_stage2b 470.

[0050] The NAND2 445 creates a two-cycle (2T) high-time DIVout 495. An additional inverter 460 creates a one-cycle (1T) low-time DIVout 495. Node divN_stage5 431 creates a two-cycle (2T) low-time DIVout 495. Node divN_stage7 441 creates a three-cycle (3T) low-time DIVout 495. Because the NAND2 445 is shared by different moduli of the clock divider 400, different division ratios result in a two-cycle (2T) high-time DIVout 495.

[0051] Furthermore, clock-gated PMOS pull-ups to a gated inverter can be used to increase the low-time output of its output over any number of cycles.

[0052] Clock divider 400 provides different moduli (division ratios) that are selectable by gating only the clock signal CLK (first control signal) coupled to the NMOS in gated inverter 430 (“half-latch”) or gated inverter 440. This means that gated inverter 430 or gated inverter 440 is partially (half-gated) as the inverted clock signal CLKB (second control signal), and the introduced input signal pulls the output to a known state through the PMOS.

[0053] In other words, only one of the PMOS and NMOS (pull-up or pull-down) clocks of the gated inverter is gated. Therefore, power consumption is lower because only one side of the gated inverter is gated, as the gated clock requires a lower drive strength. Power consumption can be further reduced if only the NMOS is gated, since the PMOS is at least twice the size of the NMOS for the same drive strength. With half-gating, the circuit is much simpler and more compact compared to the scenario where both the PMOS and NMOS are gated. On the other hand, if both are gated, the gated inverter will be a "tri-state" inverter with an undefined output. By only gated, such as the NMOS, the PMOS will periodically pull the output up to a known state because the data entering the gated inverter will change up and down. In other words, the output signal is limited based on the data entering the gated inverter.

[0054] Unlike clock divider 200, for clock divider 400, the three different moduli (division ratios) are selected by gating the clock rather than using combinational logic on the data. The clock can be "open-loop" buffered, which allows breaking out of the speed box, meaning that clock divider 400 can operate at a maximum speed even higher than that of clock divider 200.

[0055] The clock dividers 200 and 400 described herein can be configured for high frequencies, such as frequencies above 100 MHz, preferably above 1 GHz, more preferably close to or even above 10 GHz, or radio frequency. The clock dividers 200 and 400 can be suitable for use with analog-to-digital converters (ADCs) or phase-locked loops (PLLs).

[0056] Clock dividers 200 and 400 can be configured to operate robustly throughout the lifecycle of the underlying product (over ten years). Due to their robustness, clock dividers 200 and 400 can be configured to provide predefined specifications for all (physically meaningful) process voltage and temperature (PVT) variations in the presence of device aging or degradation. Specifically, clock divider 400 can be configured to operate at frequencies greater than 10 GHz in a 65nm topology for all (physically meaningful) PVT variations in the presence of device aging or degradation.

[0057] In one example use case, the electronic circuitry can be implemented as clock dividers 200 and 400 in a PLL. The clock generated by the PLL may need to be divided to compare with a reference clock. To provide speedup, the entire clock divider can be divided into several stages, with the first stage likely having the highest speed (the operating frequency at which this stage can operate) and being the most difficult to design. For a specific use case of the PLL, the first-stage (pre-divider) clock divider may need to be tri-modular, thus providing selectable division ratios of / 3, / 4, and / 5. This electronic circuitry representing example clock dividers 200 and 400 can be configured to meet these requirements.

[0058] However, electronic circuits are general-purpose and therefore not limited to implementation in ADCs or PLLs.

[0059] Figure 5 This is a simplified schematic diagram of a gated inverter including a bus hold.

[0060] In block 510, the gated inverter is shown according to the gate level representation. In block 530, the gated inverter is shown according to the transistor representation.

[0061] In block 510, a ring configuration including a first inverter 516 and a second inverter 518 is shown after node 512. The output signal Y is provided at node 514.

[0062] In block 530, a first inverter 516 and a second inverter 518 are shown according to transistor representation. Each of the first inverter 516 and the second inverter 518 includes PMOS 536, 540 and NMOS 538, 542.

[0063] In any case, the first inverter 516 and the second inverter 518 provide a capacitive effect. Therefore, the clock can be stopped without the outputs 514 and 534 of the gated inverters dropping or changing their values. This avoids crow-bar currents.

[0064] All gated inverters in clock dividers 200 and 400 include bus hold. However, in general, bus hold is optional rather than mandatory for clock dividers 200 and 400.

[0065] Figure 6 This is a simplified schematic diagram of process signal 600 based on an example of clock divider 400. Figure 6 The principle layout corresponds to Figure 3The process signal 300 of clock divider 200 is shown. Therefore, the comparison of these graphs provides a measure of the performance of two examples of clock dividers 200 and 400. Similarly, time in nanoseconds is shown on the x-axis. The y-axis shows the amplitude of the corresponding signal switching between "high" and "low".

[0066] Clk_stgln3 612 and clkb_stgln3 614 are the clock signal and the inverting clock signal used to gate the gated inverter. Figure 6 The clock signal frequency is 11 GHz.

[0067] divN_stage1 to divN_stage7 620 are the output signals of the gated inverters 410, 415, 420, 425, 430, 435, and 440 of the clock divider 400.

[0068] sel <4> 622 is one of the selection signals used to select between different division ratios Div-3, Div-4, and Div-5 in the clock divider 400. Therefore, the output signals of the gated inverter, i.e., signals divN_stage1 to divN_stage7620, correspond to switching sel at different time points. <4> The variations occur between Div-3, Div-4, and Div-5. DIVout 626 shows the crossover output of a fresh silicon analog, while DIVout 628 shows the crossover output after 10 years of aging. They are based on sel <3> , especially sel <4> The 622 states provide different ratios between logic "high" and logic "low", allowing the clock divider 400 to provide different division ratios.

[0069] A comparison of the "aged" DIVout 628 and the "fresh" DIVout 626 clearly shows that even after a 10-year analog lifetime and all (physically meaningful) PVT variations, the two signals are essentially identical for all division ratios / 3, / 4, and / 5. This means that the clock divider 400 achieves maximum speed by avoiding the application of slow combinational logic to the data, by only half-gating the gated inverters, and by configuring the clock divider 400 according to an "open-loop" clock buffer configuration. The clock divider 400 is operable at frequencies above 11 GHz and provides a constant division ratio at these frequencies for over 10 years of lifetime (within negligible tolerances). Therefore, a division ratio is provided at these frequencies even for all (physically meaningful) process voltage and temperature (PVT) variations where device aging or degradation occurs.

[0070] Although this disclosure has been described above with reference to specific examples, this disclosure is not limited to these examples, and there is no doubt that those skilled in the art will conceive of further alternatives within the scope of the claimed clock divider.

Claims

1. An electronic circuit comprising a high-speed CMOS logic circuit including a ring oscillator, said ring oscillator comprising: The first group of gated inverters is coupled between the first node and the second node; The second set of gated inverters is coupled between the second node and the third node; A first switching circuit includes a first switch and a second switch connected in series between a first voltage node and the first node, the first switch having a control terminal coupled to the second node, and the second switch having a control terminal coupled to the third node. The second switching circuit includes a third switch and a fourth switch coupled in series between a second voltage node and a first node, the third switch having a control terminal coupled to the second node, and the fourth switch having a control terminal coupled to receive a first selection signal. as well as The third switching circuit includes a fifth switch and a sixth switch connected in series between the second voltage node and the first node, the fifth switch having a control terminal coupled to the third node, and the sixth switch having a control terminal coupled to receive a second selection signal. At least one of the gated inverters is configured to receive an oscillation signal at an inverter input, a first clock signal at a first complementary input, and a second clock signal at a second complementary input that is an inverted signal of the first clock signal. The division ratio of the ring oscillator is selectable based on the logic levels of the first selection signal and the second selection signal.

2. The electronic circuit according to claim 1, wherein the electronic circuit is a clock divider.

3. The electronic circuit according to claim 1, wherein the ring oscillator further comprises: The third group of gated inverters is coupled between the third node and the fourth node; as well as A fourth switching circuit includes a seventh switch and an eighth switch connected in series between the second voltage node and the first node, the seventh switch having a control terminal coupled to the third node, and the eighth switch having a control terminal coupled to the fourth node.

4. The electronic circuit according to claim 1, wherein the first group of gated inverters and the second group of gated inverters each include two gated inverters coupled in series.

5. The electronic circuit of claim 1, wherein at least one gated inverter is partially gated such that it outputs logic high or logic low according to the logic state of the input signal, and is selectable by applying partial gate on a PMOS or NMOS.

6. The electronic circuit according to claim 1, wherein the duty cycle of the first selection signal or the second selection signal is greater than 0.

5.

7. The electronic circuit according to claim 1, wherein each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch is a transistor.

8. The electronic circuit according to claim 3, wherein each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch is a transistor.

9. The electronic circuit according to claim 1, wherein the first group of gated inverters includes a first gated inverter and a second gated inverter, the first gated inverter receiving a first logic signal at a first complementary input and a second logic signal that is the inverted signal of the first logic signal at a second complementary input, and the second gated inverter receiving a third logic signal at a first complementary input and a fourth logic signal that is the inverted signal of the third logic signal at a second complementary input. The first logic signal and the fourth logic signal have the same logic, and the second logic signal and the third logic signal have the same logic.

10. The electronic circuit of claim 1, wherein the gated inverter has a bus hold.

11. The electronic circuit according to claim 1, wherein the electronic circuit is a three-mode clock divider.

12. The electronic circuit of claim 11, wherein a frequency division ratio of at least 1 to 3, 4 and 5 is selectable.

13. A clock divider, comprising: N gated inverters coupled in series, each of the gated inverters having an input for receiving an oscillation signal, an output for outputting the oscillation signal, a first control input for receiving a first control signal, and a second control input for receiving a second control signal; An inverter coupled between the output of the second gated inverter and the input of the first gated inverter; A first logic circuit with a logic OR function, the first logic circuit having a first input coupled to the output of an Nth gated inverter, a second input coupled to the output of a fifth gated inverter, a third input coupled to receive a first logic signal, and an output coupled to the first control input of a second gated inverter; as well as A second logic circuit with a logical AND function, the second logic circuit having a first input coupled to the output of a fourth gated inverter, a second input of a second logic signal coupled to be received as the inverted signal of the first logic signal, and an output coupled to the first control input of the first gated inverter. Two adjacent gated inverters are alternately gated by corresponding first and second control signals, and The frequency division ratio can be selected based on either the first control signal or the second control signal.

14. The clock divider of claim 13, wherein the first input of the first logic circuit is coupled to the output signal of the seventh gated inverter.

15. The clock divider of claim 13, wherein the first control signal and the second control signal are opposite to each other.

16. The clock divider of claim 15, wherein the first control signal and the second control signal of at least one gated inverter are complementary inputs, and the at least one gated inverter is partially gated such that it outputs logic high or logic low according to the logic state of the input signals, and is selectable by applying partial gate on a PMOS or NMOS.

17. The clock divider according to claim 13, wherein the duty cycle of the first control signal or the second control signal is greater than 0.

5.

18. The clock divider according to claim 13, wherein the clock divider is a three-mode clock divider.

19. The clock divider of claim 18, wherein at least a division ratio of 1 to 3, 4 and 5 is selectable.

20. The clock divider of claim 13, wherein the gated inverter has a bus hold.

21. An electronic circuit comprising a ring oscillator, the ring oscillator comprising: The first group of gated inverters is coupled between the first node and the second node; The second set of gated inverters is coupled between the second node and the third node; A first switching circuit includes a first switch and a second switch connected in series between a first voltage node and the first node, the first switch having a control terminal coupled to the second node, and the second switch having a control terminal coupled to the third node. The second switching circuit includes a third switch and a fourth switch coupled in series between a second voltage node and a first node, the third switch having a control terminal coupled to the second node, and the fourth switch having a control terminal coupled to receive a first selection signal. as well as The third switching circuit includes a fifth switch and a sixth switch connected in series between the second voltage node and the first node, the fifth switch having a control terminal coupled to the third node, and the sixth switch having a control terminal coupled to receive a second selection signal. At least one of the gated inverters is configured to receive an oscillation signal and at least one auxiliary signal at an additional input; The frequency division ratio of the ring oscillator is selectable based on the at least one auxiliary signal.

22. The electronic circuit of claim 21, wherein a division ratio of 1 to 3, 4 and 5 can achieve a lifespan of 10 years at frequencies greater than 10 GHz.

23. The electronic circuit of claim 22, wherein the at least one gated inverter outputs logic high or logic low according to the logic state of the input signal, and is selectable by applying partial gating on a PMOS or NMOS.

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