Low power delay circuit and voltage controlled oscillator suitable for voltage controlled oscillator

Abstract

This application provides a low-power delay circuit and a voltage-controlled oscillator (VCO) suitable for use in the field of electronic technology. The low-power delay circuit includes a push-pull module, a current module, and an inverting latch module. The push-pull module provides a dynamic drive signal based on the input signal; the control terminal of the current module is connected to a control voltage and is activated only when the dynamic drive signal flips, charging and discharging the output terminal according to the control voltage, and turning off when the dynamic drive signal stabilizes; the inverting latch module includes a cross-coupled first and second inverting latch unit, which, in conjunction with the push-pull module, maintain the output terminal at a relative first and second level after the output voltage reaches a threshold voltage. After the output level flips, no static DC path from the power supply to ground is generated in the push-pull module and the inverting latch module. The delay time varies with the control voltage to control the oscillation frequency of the multi-stage cascaded VCO.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and in particular to a low-power delay circuit and a voltage-controlled oscillator suitable for voltage-controlled oscillators. Background Technology

[0002] Currently, voltage-controlled oscillators (VCOs) are widely used in clock circuits such as phase-locked loops (PLLs) and frequency-locked loops (LLLs). Their power consumption and frequency adjustment range directly affect system performance. Ring VCOs are typically constructed using cascaded multi-stage delay circuits. When the output state is stable, the delay circuits have a static DC path from the power supply to ground, which leads to a significant increase in static power consumption when generating low-frequency clocks, making it difficult to meet the requirements of ultra-low power applications. Summary of the Invention

[0003] This application provides a low-power delay circuit and a voltage-controlled oscillator suitable for reducing the power consumption of the voltage-controlled oscillator.

[0004] In a first aspect, embodiments of this application provide a low-power delay circuit suitable for voltage-controlled oscillators, comprising: The push-pull module has a signal input terminal for receiving input signals, and is also connected to a power supply and a ground terminal. The first power transmission terminal of the push-pull module is used to provide dynamic drive signals, and the second power transmission terminal of the push-pull module is used to conduct electricity to ground. A current module is provided, wherein the control terminal of the current module is used to connect to the control voltage, the first transmission terminal of the current module is connected to the first transmission terminal of the push-pull module, the second transmission terminal of the current module is connected to the second transmission terminal of the push-pull module, and the first and second output terminals of the current module are both output terminals of the low-power delay circuit. After the dynamic drive signal undergoes a level flip, the current module charges and discharges the output terminal of the low-power delay circuit according to the control voltage. An inverting latch module includes a cross-coupled first inverting latch unit and a second inverting latch unit. The two output terminals of the first inverting latch unit are respectively connected to the first and second output terminals of the push-pull module, and the control terminal of the first inverting latch unit is connected to the first output terminal of the current module. The two output terminals of the second inverting latch unit are respectively connected to the first and second output terminals of the push-pull module, and the control terminal of the second inverting latch unit is connected to the second output terminal of the current module. The inverting latch module is used to, in conjunction with the push-pull module, maintain the output terminal of the low-power delay circuit at a relative first level and a second level after the voltage at the output terminal of the low-power delay circuit reaches a preset threshold voltage. Wherein, after the output terminal of the low-power delay circuit completes the level flip, the push-pull module and the inverting latch module do not generate a static DC path from the power supply directly to the ground terminal. The delay time of the low-power delay circuit changes with the control voltage to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits.

[0005] Secondly, embodiments of this application provide a voltage-controlled oscillator, comprising: A linearization control voltage module is used to receive an external control voltage (Vc) and generate a first control voltage (Vcp) and a second control voltage (Vcn). A ring oscillator composed of multiple cascaded low-power delay circuits as described in any one of the embodiments of this application; In this circuit, the first output terminal (ON) and the second output terminal (OP) of each delay circuit provide differential clock outputs. The output frequency of the voltage-controlled oscillator is continuously adjusted by the external control voltage (Vc) and the frequency range is discretely switched by the switches in the low-power delay circuit.

[0006] This application provides a low-power delay circuit suitable for voltage-controlled oscillators (VCOs). The low-power delay circuit includes a push-pull module, a current module, and an inverting latch module. The push-pull module's signal input terminal receives an input signal and is also connected to a power supply and a ground terminal. The push-pull module's first output terminal provides a dynamic drive signal, and its second output terminal is connected to ground. The current module's control terminal receives a control voltage. The first and second output terminals of the current module are connected to the first and second output terminals of the push-pull module. Both the first and second output terminals of the current module are output terminals of the low-power delay circuit. After the dynamic drive signal undergoes a level flip, the current module charges and discharges the output terminals of the low-power delay circuit according to the control voltage. The inverting latch module includes a cross-coupled first and second inverting latch unit. The two output terminals of the first inverting latch unit are connected to the first and second output terminals of the push-pull module, respectively. The second power supply terminal is connected accordingly, and the control terminal of the first inverting latch unit is connected to the first output terminal of the current module; the two power supply terminals of the second inverting latch unit are respectively connected to the first power supply terminal and the second power supply terminal of the push-pull module, and the control terminal of the second inverting latch unit is connected to the second output terminal of the current module; the inverting latch module is used to maintain the output terminal of the low-power delay circuit at a relative first level and second level respectively in conjunction with the push-pull module after the voltage at the output terminal of the low-power delay circuit reaches a preset threshold voltage; wherein, after the output terminal of the low-power delay circuit completes the level flip, no static DC path from the power supply to the ground terminal is generated in the push-pull module and the inverting latch module, and the delay time of the low-power delay circuit changes with the control voltage to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits. In the aforementioned low-power delay circuit, when the input signal undergoes a level flip, the dynamic drive signal generated by the push-pull module activates the current module. The current module then charges and discharges the output terminal according to the control voltage. During this process, the first and second inverting latch units in the inverting latch module, through a cross-coupling structure, quickly work together with the push-pull module to lock the output level after the output voltage reaches a preset threshold voltage. This shortens the flip time window of the current module where a static DC path exists, effectively reducing the dynamic power consumption during the signal flip stage. In the stable stage after the output level flip is completed, the dynamic drive signal turns off the current module. At this time, the push-pull module and the inverting latch module jointly maintain the output level, and neither of them forms a static DC path from the power supply to the ground, eliminating the static power consumption during the signal stabilization stage. Through the synergistic optimization of the above two stages, this application achieves adjustable delay time with control voltage to control the oscillation frequency of the voltage-controlled oscillator while reducing the overall power consumption of the delay circuit, thereby reducing the power consumption of the voltage-controlled oscillator composed of multiple cascaded delay circuits. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A schematic block diagram of a first type of low-power delay circuit suitable for voltage-controlled oscillators provided in the embodiments of this application; Figure 2 A schematic block diagram of a second low-power delay circuit suitable for voltage-controlled oscillators provided in an embodiment of this application; Figure 3 A schematic block diagram of a third type of low-power delay circuit suitable for voltage-controlled oscillators provided in the embodiments of this application; Figure 4 A schematic block diagram of a fourth low-power delay circuit suitable for voltage-controlled oscillators provided in the embodiments of this application; Figure 5 A signal variation diagram provided in an embodiment of this application; Figure 6 A multi-stage current diagram of a low-power delay circuit provided in this application embodiment; Figure 7 This is a circuit diagram of a voltage-controlled oscillator provided in an embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described below with reference to the accompanying drawings.

[0010] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0011] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0012] It should be understood that in this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0013] Please see Figure 1 , Figure 1 This is a schematic block diagram of a low-power delay circuit suitable for a voltage-controlled oscillator, provided in an embodiment of this application. Figure 1 As shown, the low-power delay circuit 100 suitable for voltage-controlled oscillators includes: a push-pull module 11, a current module 12, and an inverting latch module 13.

[0014] The push-pull module 11 has a signal input terminal for receiving input signals and is also connected to the power supply Vdd and ground GND. The first power input terminal of the push-pull module 11 provides a dynamic drive signal, and the second power input terminal is used for grounding. For example, the push-pull module 11 typically consists of two complementary switching transistors, such as a PMOS pull-up transistor and an NMOS pull-down transistor. Their gates are connected to the signal input terminal, their sources are connected to the power supply and ground, and their drains are connected to the first and second power input terminals. It should be noted that both the first and second power input terminals have off, partially on, and fully on states during the operation of the push-pull module 11. For example, the first power input terminal is in the off state when it is at the first level, in the fully on state when it is at the second level, and in the partially on state during the transition from the first level to the second level. The first level and the second level are relative levels. For example, the first level is a high level and the second level is a low level, or vice versa. Different relative relationships determine the selection of internal components of the push-pull module 11, and the resulting variations in embodiments are all within the protection scope of this application.

[0015] The control terminal of the current module 12 is used to connect to the control voltage. The first output terminal of the current module 12 is connected to the first output terminal of the push-pull module 11, and the second output terminal of the current module 12 is connected to the second output terminal of the push-pull module 11. The first and second output terminals of the current module 12 are both output terminals of the low-power delay circuit 100, denoted as the first output terminal OP and the second output terminal ON, respectively, and are used to output differential signals. After the dynamic drive signal undergoes a level flip, the current module 12 charges and discharges the output terminals of the low-power delay circuit 100 according to the control voltage. For example, the control terminal of the current module 12 is used to connect to the first control voltage Vcp and the second control voltage Vcn derived from the external control voltage Vc. The current module 12 includes a pull-up current source and a pull-down current source, which are controlled by the first control voltage Vcp and the second control voltage Vcn, respectively. After the dynamic drive signal completes its level transition, the corresponding current source in the current module 12 is activated: if the output needs to transition from low to high, the pull-up current source is turned on, providing charging current to the output load capacitor; if the output needs to transition from high to low, the pull-down current source is turned on, providing discharging current to the output load capacitor. The activation of the current module 12 occurs after the dynamic drive signal transition is complete, meaning its activation time is delayed relative to the transition start point, ensuring that the current module 12 performs supplementary charging and discharging after the push-pull module 11 completes its main drive. Once the output level stabilizes, the current module 12 automatically turns off because the voltage difference between the first transmission terminal and the output terminal approaches zero, thus preventing the introduction of additional static power consumption. The control voltage Vc continuously adjusts the magnitude of the current source, thereby changing the charging and discharging rate and achieving continuous adjustment of the delay time.

[0016] The inverting latch module 13 includes a cross-coupled first inverting latch unit 131 and a second inverting latch unit 132. The two power input terminals of the first inverting latch unit 131 are respectively connected to the first and second power input terminals of the push-pull module 11, and the control terminal of the first inverting latch unit 131 is connected to the first output terminal of the current module 12. The two power input terminals of the second inverting latch unit 132 are respectively connected to the first and second power input terminals of the push-pull module 11, and the control terminal of the second inverting latch unit 132 is connected to the second output terminal of the current module 12. The inverting latch module 13, in conjunction with the push-pull module 11, maintains the output terminal of the low-power delay circuit 100 at a relative first level and a second level after the voltage at the output terminal of the low-power delay circuit 100 reaches a preset threshold voltage. It should be noted that "maintaining" here includes not only static maintenance after the output terminal level stabilizes, but also the entire dynamic process from the point where the output terminal voltage reaches the preset threshold voltage until final stable locking. Specifically, the first inverting latch unit 131 and the second inverting latch unit 132 form a positive feedback loop: the output terminal of the first inverting latch unit 131 (i.e., the first output terminal of the current module 12) is connected to the control terminal of the second inverting latch unit 132, and the output terminal of the second inverting latch unit 132 (i.e., the second output terminal of the current module 12) is connected to the control terminal of the first inverting latch unit 131. When the voltage of the first output terminal OP and the second output terminal ON reaches a preset threshold voltage due to the charging and discharging action of the current module 12, the cross-coupled inverting latch unit begins to intervene, and its positive feedback structure rapidly amplifies the voltage difference between the output nodes, accelerating the locking of the output state. During this process, the inverting latch module 13 not only participates in the rapid establishment of the output level (including the rapid boost or buck phase starting from the threshold voltage), but also continuously maintains its state after the output stabilizes. The two power supply terminals of the inverting latch module 13 are respectively connected to the first power supply terminal and the second power supply terminal of the push-pull module 11, and its power supply path is dynamically controlled by the push-pull module 11. After the output voltage flips and enters a steady state, the first or second input terminal of the push-pull module 11 is in a high-impedance state, cutting off the complete path from the power supply to ground of the inverting latch module 13, so that it does not generate a static DC path. During the flipping process (especially after the output voltage reaches the threshold voltage), the first and second input terminals of the push-pull module 11 briefly provide a path simultaneously, and the inverting latch module 13 obtains operating current, playing a positive feedback acceleration role, and assisting in the rapid establishment process from the threshold voltage to the final steady state.

[0017] In this circuit, after the output level of the low-power delay circuit 100 completes its level flip, no static DC path from the power supply to ground is generated in the push-pull module 11 and the inverting latch module 13. Since the two output terminals of the inverting latch module 13 are connected to the first and second output terminals of the push-pull module 11 respectively, its operation is dynamically controlled by the push-pull module 11. When the output level stabilizes, the corresponding pull-up or pull-down transistor in the push-pull module 11 is in the off state, causing the first or second output terminal to present a high impedance state, cutting off the complete current path from the power supply to ground in the inverting latch module 13. Therefore, regardless of the stable state of the output terminal, there is no continuous DC conduction path within the entire delay circuit; dynamic power consumption is only generated during the transient process of signal flipping, which greatly reduces the overall power consumption of the voltage-controlled oscillator. The delay time of the low-power delay circuit 100 varies with the control voltage to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits 100. The delay time adjustment mechanism originates from the current module 12: the control voltage directly adjusts the charging and discharging rate of the output load capacitor by changing the output current of the controllable current source in the current module 12. When the control voltage increases, the charging and discharging current provided by the current module 12 increases accordingly, the level switching speed of the output node accelerates, and the single-stage delay time shortens; conversely, when the control voltage decreases, the charging and discharging current decreases, the switching speed slows down, and the delay time increases. The oscillation frequency of the ring oscillator, which is composed of multiple cascaded delay circuits, depends on the sum of the delay times of each stage. Therefore, by continuously adjusting the control voltage, precise and continuous tuning of the voltage-controlled oscillator output frequency can be achieved. At the same time, since there is no static DC path in the circuit, the frequency adjustment process does not involve an increase in static power consumption, thus maintaining low power consumption characteristics over a wide tuning range.

[0018] It should be noted that, Figure 1 This is only a schematic block diagram. There are many possible specific transistor-level implementations of the push-pull module 11, the current module 12, and the inverting latch module 13. Subsequent embodiments of this application will provide preferred circuit structures and their operating modes in conjunction with the accompanying drawings. However, any variations based on the same concept fall within the protection scope of this application.

[0019] This application provides a low-power delay circuit suitable for voltage-controlled oscillators (VCOs). The low-power delay circuit includes a push-pull module, a current module, and an inverting latch module. The signal input terminal of the push-pull module receives the input signal, its first output terminal provides the dynamic drive signal, and its second output terminal is grounded. The control terminal of the current module is connected to a control voltage. The first output terminal of the current module is connected to the first output terminal of the push-pull module, and the second output terminal of the current module is connected to the second output terminal of the push-pull module. The current module is activated only when the dynamic drive signal flips from a first level to a second level, and charges and discharges the output terminal of the low-power delay circuit according to the control voltage to shorten the level transition time of the low-power delay circuit's output terminal. The current module is in a turned-off state when the dynamic drive signal is stable. An inverting latch module is also included. The first power supply terminal of the latch module is connected to the first power supply terminal of the push-pull module, and the second power supply terminal of the inverting latch module is connected to the second power supply terminal of the push-pull module. The output terminal of the inverting latch module is the output terminal of the low-power delay circuit, and the control terminal of the inverting latch module is connected to the output terminal of the push-pull module. The inverting latch module is used to maintain the state of the output terminal of the low-power delay circuit when the dynamic drive signal is stable. When the dynamic drive signal is stable, no static DC path to ground is generated in the push-pull module and the inverting latch module. The delay time of the low-power delay circuit varies with the control voltage to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits. In the aforementioned low-power delay circuit, during the transition of the input signal from the first level to the second level, the push-pull unit drives the current module to charge and discharge the corresponding output port of the low-power delay circuit, causing the equivalent load capacitance of the output port of the low-power delay circuit to enter a saturated state, thereby shortening the level transition time of the output terminal of the low-power delay circuit. Since there is a static DC path to ground during the transition phase, shortening the level transition time can reduce the power consumption during the signal transition phase. Secondly, when the output port of the low-power delay circuit is at the first level, the push-pull module and the inverting latch module maintain the first level of the output port of the low-power delay circuit, and do not generate a static DC path to ground, thus reducing the power consumption during the signal stabilization phase. Through the power consumption optimization of the above two stages, the power consumption of the delay circuit can be reduced, thereby reducing the power consumption of the voltage-controlled oscillator using this delay circuit.

[0020] To more clearly illustrate the technical solution of this application, the technical solution of this application will be described below through specific embodiments. It should be noted that the specific embodiments are used to expand the description of the technical solution of this application, and are not intended to limit this application.

[0021] In some embodiments, such as Figure 2The push-pull module 11 includes a first push-pull unit 111 and a second push-pull unit 112. The current module 12 includes a first current unit 121 and a second current unit 122. The inverting latch module 13 includes a first inverting latch unit 131 and a second inverting latch unit 132.

[0022] The first push-pull unit 111 has an input terminal for receiving an inverted input signal IN and an output terminal for providing a first drive signal.

[0023] The second push-pull unit 112 has an input terminal for receiving a positive input signal IP and an output terminal for providing a second drive signal.

[0024] A first current unit 121 has its control terminal connected to a first control voltage Vcp and a second control voltage Vcn. The first output terminal of the first current unit 121 is connected to the first output terminal of the first push-pull unit 111, and the second output terminal of the first current unit 121 is connected to the second output terminal of the first push-pull unit 111. The first current unit 121 is activated only during the level transition of the output terminal of the low-power delay circuit and, in conjunction with the first push-pull unit 111, charges or discharges the first output terminal OP of the low-power delay circuit.

[0025] The second current unit 122 has its control terminals connected to the first control voltage Vcp and the second control voltage Vcn, respectively. The first output terminal of the second current unit 122 is connected to the first output terminal of the second push-pull unit 112, and the second output terminal of the second current unit 122 is connected to the second output terminal of the second push-pull unit 112. The second current unit 122 is activated only during the level transition of the output terminal of the low-power delay circuit and, in conjunction with the second push-pull unit 112, charges or discharges the second output terminal ON of the low-power delay circuit.

[0026] A first inverting latch unit 131 has its first power supply terminal connected to the first power supply terminal of the first current unit 121, and its second power supply terminal connected to the second power supply terminal of the first current unit 121. The output terminal of the first inverting latch unit 131 is the first output terminal OP of the low-power delay circuit. The control terminal of the first inverting latch unit 131 is connected to the output terminal of the second inverting latch unit 132. After the voltage at the output terminal of the low-power delay circuit reaches a preset voltage threshold, the first inverting latch unit 131 and the first push-pull unit 111 jointly maintain the first output terminal OP of the low-power delay circuit at a second level, and do not generate a static DC path directly from the power supply to the ground terminal.

[0027] The second inverting latch unit 132 has its first power supply terminal connected to the first power supply terminal of the second current unit 122, and its second power supply terminal connected to the second power supply terminal of the second current unit 122. The output terminal of the second inverting latch unit 132 is the second output terminal (ON) of the low-power delay circuit. The control terminal of the second inverting latch unit 132 is connected to the output terminal of the first inverting latch unit 131. After the voltage at the output terminal of the low-power delay circuit reaches a preset voltage threshold, the second inverting latch unit 132 and the second push-pull unit 112 jointly maintain the second output terminal (ON) of the low-power delay circuit at a first level, and do not create a static DC path directly from the power supply to the ground terminal.

[0028] The first control voltage Vcp and the second control voltage Vcn are obtained by converting the external control voltage Vc and change in opposite directions. The charging time or discharging time of the output terminal of the low-power delay circuit changes continuously with the external control voltage Vc, thereby adjusting the delay time of the low-power delay circuit to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits.

[0029] In this embodiment, the inverting input signal IP and the outverting input signal IN are inversely related and together form a differential input. When the input signal level flips, the corresponding push-pull unit starts operating, and simultaneously, the current unit is activated during the output level flip, working in conjunction with the push-pull unit to charge or discharge the output, accelerating the establishment of the output level. During this process, the activation of the current unit is transient, operating only during the output level flip and automatically turning off once the flip is complete.

[0030] When the voltages at the first output terminal OP and the second output terminal ON reach a preset voltage threshold, the cross-coupled first inverting latch unit 131 and second inverting latch unit 132 begin to function. Since the control terminal of the first inverting latch unit 131 is connected to the second output terminal ON, and the control terminal of the second inverting latch unit 132 is connected to the first output terminal OP, they form a positive feedback structure. When the voltages at the first output terminal OP and the second output terminal ON exceed the threshold, the positive feedback mechanism is triggered. The first inverting latch unit 131 and the second inverting latch unit 132 mutually accelerate each other's turn-on and turn-off, causing the voltages at the first output terminal OP and the second output terminal ON to quickly approach a stable value. After the first output terminal OP and the second output terminal ON complete their level flip and enter a steady state, the first inverting latch unit 131 and the first push-pull unit 111 jointly maintain the state of the first output terminal OP, and the second inverting latch unit 132 and the second push-pull unit 112 jointly maintain the state of the second output terminal ON.

[0031] During this process, since the two output terminals of the first inverting latch unit 131 are respectively connected to the first and second output terminals of the first push-pull unit 111, and the two output terminals of the second inverting latch unit 132 are respectively connected to the first and second output terminals of the second push-pull unit 112, the power supply path of the inverting latch module 13 is controlled by the first push-pull unit 111 and the second push-pull unit 112. After the levels of the first output terminal OP and the second output terminal ON stabilize, the corresponding switching transistors in the first push-pull unit 111 and the second push-pull unit 112 are in the off state, making their first or second output terminals present a high impedance state, thereby cutting off the complete current path from the power supply to the ground terminal for the first inverting latch unit 131 and the second inverting latch unit 132. Therefore, the entire low-power delay circuit 100 does not generate a static DC path directly from the power supply to the ground terminal in steady state, and only consumes dynamic power consumption during the transient process of the output terminal level flipping.

[0032] By continuously adjusting the first control voltage Vcp and the second control voltage Vcn using an external control voltage Vc, the charging and discharging currents of the first current unit 121 and the second current unit 122 can be linearly changed, thereby precisely controlling the charging or discharging time of the first output terminal OP and the second output terminal ON, achieving continuous adjustment of the delay time. The ring oscillator, composed of multiple cascaded low-power delay circuits 100, has an oscillation frequency that depends on the sum of the delay times of each stage. Therefore, precise and continuous tuning of the voltage-controlled oscillator's output frequency can be achieved by adjusting the external control voltage Vc.

[0033] In some embodiments, such as Figure 3As shown, the first push-pull unit 111 includes a first switch (Q1) and a second switch (Q2), and the second push-pull unit 112 includes a third switch (Q3), a fourth switch (Q4) and a fifth switch (S5).

[0034] The source of the first switching transistor (Q1) is connected to a preset supply voltage, the drain is connected to the first terminal of the first current unit, and the gate is used to receive the inverted input signal (IN). The preset supply voltage is V. dd It is powered by a preset power supply.

[0035] The drain of the second switch (Q2) is connected to the second terminal of the first current unit, the source is grounded, and the gate is used to receive the inverted input signal (IN).

[0036] The source of the third switch (Q3) is connected to a preset power supply voltage through the fifth switch (S5), the drain is connected to the first terminal of the second current unit, and the gate is used to receive the positive input signal (IP).

[0037] The drain of the fourth switch (Q4) is connected to the second terminal of the second current unit, the source is grounded, and the gate is used to receive the positive input signal (IP).

[0038] In some embodiments, such as Figure 3 As shown, the first inverting latch unit includes: a fifth switch (Q5), a sixth switch (Q6), a first switch (S1), and a second switch (S2), and the second inverting latch unit includes: a seventh switch (Q7), an eighth switch (Q8), a third switch (S3), and a fourth switch (S4).

[0039] The source of the fifth switch (Q5) is connected to the drain of the first switch (Q1), and the drain is connected to the first output terminal (OP) of the low-power delay circuit through the first switch (S1). The gate is connected to the second output terminal (ON) of the low-power delay circuit.

[0040] The source of the sixth switch (Q6) is connected to the drain of the second switch (Q2), and the drain is connected to the first output terminal (OP) of the low-power delay circuit through the second switch (S2). The gate of the sixth switch (Q6) is connected to the gate of the fifth switch (Q5).

[0041] The source of the seventh switch (Q7) is connected to the drain of the third switch (Q3), and the drain is connected to the second output terminal (ON) of the low-power delay circuit through the third switch (S3). The gate is connected to the first output terminal (OP) of the low-power delay circuit.

[0042] The source of the eighth switch (Q8) is connected to the drain of the fourth switch (Q4), and the drain is connected to the second output terminal (ON) of the low-power delay circuit through the fourth switch (S4). The gate of the eighth switch (Q8) is connected to the gate of the seventh switch (Q7).

[0043] In some embodiments, such as Figure 3 As shown, the first current unit includes a first pull-up current source (MI1) and a first pull-down current source (MI2), and the second current unit includes a second pull-up current source (MI3) and a second pull-down current source (MI4).

[0044] The first terminal of the first pull-up current source (MI1) is connected to the drain of the first switching transistor (Q1), the second terminal is connected to the first output terminal (OP) of the low-power delay circuit, and the control terminal is connected to the first control voltage (Vcp).

[0045] The first terminal of the first pull-down current source (MI2) is connected to the first output terminal (OP) of the low-power delay circuit, the second terminal is connected to the drain of the second switching transistor (Q2), and the control terminal is connected to the second control voltage (Vcn).

[0046] The first terminal of the second pull-up current source (MI3) is connected to the drain of the third switching transistor (Q3), the second terminal is connected to the second output terminal (ON) of the low-power delay circuit, and the control terminal is connected to the first control voltage (Vcp).

[0047] The first terminal of the second pull-down current source (MI4) is connected to the second output terminal (ON) of the low-power delay circuit, the second terminal is connected to the drain of the fourth switching transistor (Q4), and the control terminal is connected to the second control voltage (Vcn).

[0048] In one embodiment, such as Figure 3 When all switches from the first switch (S1) to the fifth switch (S5) shown are closed, the following result is obtained: Figure 4 The low-power delay circuit 100 is shown. (As shown in the image...) Figure 4 The signal variation diagram of the low-power delay circuit 100 shown is as follows: Figure 5 As shown. Figure 5 The signal changes at the positive input signal IP, the first output terminal OP, and the second output terminal ON are illustrated in four stages: Stage 1, Stage 2, Stage 3, and Stage 4. The current diagrams for each stage are shown below. Figure 6 As shown.

[0049] Stage 1: The voltage flipping process at the output of the low-power delay circuit 100 after the positive input signal IP completes its transition from high to low level.

[0050] Phase 2: The process of maintaining the output level of the low-power delay circuit 100 when the positive input signal IP is low.

[0051] Phase 3: The voltage flipping process at the output of the low-power delay circuit 100 after the positive input signal IP completes its transition from low to high. Phase 4: The positive input signal IP flips from high level to low level (falling edge).

[0052] Below, in conjunction with Figure 4 , Figure 5 and Figure 6 The specific working principle of the circuit in the four stages is explained.

[0053] At the start of stage 1, the positive input signal IP has completed its transition from high to low, and the negative input signal IN has completed its transition from low to high.

[0054] The third switch Q3 (PMOS) is in the ON state because its gate non-inverting input signal IP is low, and its drain is pulled up to the supply voltage Vdd. The fourth switch Q4 (NMOS) is in the OFF state because its gate non-inverting input signal IP is low, and its drain is in a high-impedance state. The first switch Q1 (PMOS) is in the OFF state because its gate inverting input signal IN is high, and its drain is in a high-impedance state. The second switch Q2 (NMOS) is in the ON state because its gate inverting input signal IN is high, and its drain is pulled down to ground.

[0055] During the output level transition, the second pull-up current source MI3 (controlled by the first control voltage Vcp) is activated, charging the second output terminal ON and gradually increasing its voltage. The first pull-down current source MI2 (controlled by the second control voltage Vcn) is activated, discharging the first output terminal OP and gradually decreasing its voltage. When the voltage of the second output terminal ON rises to a certain value and the voltage of the first output terminal OP falls to a certain value, the current sources complete their main charging and discharging tasks and then automatically turn off, and the circuit enters stage 2.

[0056] Upon entering stage 2, the non-inverting input signal IP remains low, and the inverting input signal IN remains high. At this time, the voltage at the second output terminal ON has risen to the first voltage threshold (Vthn), and the voltage at the first output terminal OP has fallen to the second voltage threshold (Vcc-Vthp). Since the third switch Q3 is in the on state, its drain has been pulled up to Vdd, and the gate of the seventh switch Q7 (PMOS) is connected to the first output terminal OP (low level). Therefore, the seventh switch Q7 is turned on, and the second output terminal ON is quickly pulled up to a high level through the seventh switch Q7, completing the voltage transition. After the second output terminal ON reaches a high level, the voltage difference across the second pull-up current source MI3 approaches zero and remains off.

[0057] Simultaneously, the high level of the second output terminal ON acts on the gate of the sixth switch Q6 (NMOS), turning it on. After the sixth switch Q6 is turned on, its source is connected to the drain (ground potential) of the second switch Q2, and the drain is connected to the first output terminal OP through the second switch S2, providing an additional discharge path for the first output terminal OP, causing the first output terminal OP to quickly drop to ground potential, completing the voltage transition. After the first output terminal OP reaches a low level, the voltage difference across the first pull-down current source MI2 approaches zero and remains off.

[0058] At this point, the output is stable: the first output terminal OP is low, and the second output terminal ON is high. In the inverting latch module, the fifth switch Q5 is off because its gate is connected to the second output terminal ON (high level); the sixth switch Q6 is on because its gate is connected to the second output terminal ON (high level), but its source is grounded and its drain is connected to the first output terminal OP (low level), so the voltage difference between the two terminals is zero and there is no current; the seventh switch Q7 is on because its gate is connected to the first output terminal OP (low level), but its source is connected to Vdd and its drain is connected to the second output terminal ON (high level), so the voltage difference between the two terminals is zero and there is no current; the eighth switch Q8 is off because its gate is connected to the first output terminal OP (low level). Therefore, there is no static DC path from the power supply to ground in steady state.

[0059] At the start of stage 3, the positive input signal IP has completed its transition from low to high, and the negative input signal IN has completed its transition from high to low.

[0060] The third switch Q3 (PMOS) is off because its gate inverting input signal IP is high, and its drain is in a high-impedance state. The fourth switch Q4 (NMOS) is on because its gate inverting input signal IP is high, and its drain is pulled down to ground. The first switch Q1 (PMOS) is on because its gate inverting input signal IN is low, and its drain is pulled up to Vdd. The second switch Q2 (NMOS) is off because its gate inverting input signal IN is low, and its drain is in a high-impedance state.

[0061] The first pull-up current source MI1 (controlled by the first control voltage Vcp) is activated, charging the first output terminal OP and gradually increasing its voltage. The second pull-down current source MI4 (controlled by the second control voltage Vcn) is activated, discharging the second output terminal ON and gradually decreasing its voltage. When the voltage of the first output terminal OP rises to a certain value and the voltage of the second output terminal ON falls to a certain value, the current sources complete their main charging and discharging tasks and then automatically turn off, and the circuit enters stage 4.

[0062] Upon entering stage 4, the non-inverting input signal IP remains high, and the inverting input signal IN remains low. At this time, the voltage at the first output terminal OP has risen to the first voltage threshold (Vthn), and the voltage at the second output terminal ON has fallen to the second voltage threshold (Vcc-Vthp). Since the first switch Q1 is in the on state, its drain has been pulled up to Vdd. The gate of the eighth switch Q8 (NMOS) is connected to the first output terminal OP (high level), so the eighth switch Q8 is turned on. The second output terminal ON is quickly pulled down to ground potential through the eighth switch Q8, completing the voltage transition. After the second output terminal ON reaches a low level, the voltage difference across the second pull-down current source MI4 approaches zero and remains off.

[0063] Simultaneously, the low level of the second output terminal ON acts on the gate of the fifth switch Q5 (PMOS), turning it on. After the fifth switch Q5 is turned on, its source is connected to the drain (Vdd) of the first switch Q1, and the drain is connected to the first output terminal OP through the first switch S1, providing an additional charging path for the first output terminal OP, causing the first output terminal OP to quickly rise to Vdd and complete the voltage transition. After the first output terminal OP reaches a high level, the voltage difference across the first pull-up current source MI1 approaches zero and remains off.

[0064] At this point, the output is stable: the first output terminal OP is high, and the second output terminal ON is low. In the inverting latch module, the fifth switch Q5 is turned on with its gate connected to the second output terminal ON (low level), but its source is connected to Vdd and its drain is connected to the first output terminal OP (high level), resulting in zero voltage difference and no current. The sixth switch Q6 is turned off with its gate connected to the second output terminal ON (low level); the seventh switch Q7 is turned off with its gate connected to the first output terminal OP (high level); and the eighth switch Q8 is turned on with its gate connected to the first output terminal OP (high level), but its source is grounded and its drain is connected to the second output terminal ON (low level), resulting in zero voltage difference and no current. Therefore, in steady state, there is also no static DC path from the power supply to ground.

[0065] After the input signal flips, the circuit performs initial charging and discharging of the output terminal by a current source (stages 1 and 3). During the steady-state holding phase (stages 2 and 4), the push-pull transistor and the inverting latch work together to achieve a rapid voltage transition and stabilize at the desired level. Throughout the steady-state holding process, all devices that could potentially form a power-to-ground path cannot generate quiescent current because the drain-source voltage difference is zero or the source is floating, thus achieving ultra-low quiescent power consumption. Simultaneously, the pre-charging mechanism for the next flip via the cross-coupled latch in stages 2 and 4 effectively improves the circuit's dynamic response speed.

[0066] In some embodiments, by controlling the on and off of the first switch (S1) to the fifth switch (S5), the equivalent load capacitance of the first output terminal (OP) and the equivalent load capacitance of the second output terminal (ON) are changed, thereby configuring the operating frequency range of the low-power delay circuit.

[0067] In some embodiments, the low-power delay circuit 100 includes the following operating modes: First mode, such as Figure 3 As shown, all switches from the first (S1) to the fifth (S5) are turned on. The equivalent load capacitance of the first output terminal (OP) and the second output terminal (ON) is the first capacitance value, and the low-power delay circuit operates in the lowest frequency range. Thus, the equivalent load capacitance connected to the first output terminal OP and the second output terminal ON is the largest, including the gate capacitance, drain capacitance, and output capacitance of all latching transistors, denoted as the first capacitance value. Because the load capacitance is the largest, under the same charging and discharging current, the level switching speed of the output node is the slowest, and the single-stage delay time is the longest. Therefore, the low-power delay circuit operates in the lowest frequency range.

[0068] Second mode, such as Figure 4 As shown, the second switch (S2), the fourth switch (S4), and the fifth switch (S5) are turned on, while the first switch (S1) and the third switch (S3) are turned off. The equivalent load capacitance of the first output terminal (OP) and the second output terminal (ON) is the second capacitance value, and the low-power delay circuit operates in the mid-to-high frequency range. Thus, the equivalent load capacitance connected to the first output terminal OP and the second output terminal ON is smaller than in the first mode, mainly including the capacitance of the NMOS latch and some parasitic capacitance, denoted as the second capacitance value. Because only the NMOS latch is connected, the equivalent load capacitance of the output node is moderate, the level switching speed is fast, and the single-stage delay time is short. Therefore, the low-power delay circuit operates in the mid-to-high frequency range.

[0069] The third mode, such as Figure 3 As shown, the first switch (S1), the third switch (S3), and the fifth switch (S5) are turned on, while the second switch (S2) and the fourth switch (S4) are turned off. The equivalent load capacitance of the first output terminal (OP) and the second output terminal (ON) is equal to the third capacitance value. The low-power delay circuit operates in the mid-to-low frequency range. Thus, the equivalent load capacitance connected to the first output terminal OP and the second output terminal ON is slightly larger than in the second mode, mainly including the capacitance of the PMOS latch and some parasitic capacitance, denoted as the third capacitance value. Since only the PMOS latch is connected, the equivalent load capacitance of the output node is moderate but slightly larger than in the second mode. The level switching speed is slightly slower than in the second mode, and the single-stage delay time is slightly longer. Therefore, the low-power delay circuit operates in the mid-to-low frequency range.

[0070] The fourth mode, such as Figure 3As shown, all switches from the first (S1) to the fifth (S5) are off. The equivalent load capacitance of the first output terminal (OP) and the second output terminal (ON) is the fourth capacitance value. The low-power delay circuit operates in the highest frequency range and in single-ended output mode. Thus, the equivalent load capacitance connected to the first output terminal OP and the second output terminal ON is minimized, consisting only of the output capacitance of the current source and a very small amount of parasitic capacitance, denoted as the fourth capacitance value. Because the load capacitance is minimal, under the same charging and discharging current, the level transition speed of the output node is the fastest, and the single-stage delay time is the shortest. Therefore, the low-power delay circuit operates in the highest frequency range. It is worth noting that in this mode, since the inverting latch module is completely disconnected, the first output terminal OP and the second output terminal ON are no longer constrained by the cross-coupling of the latch. The circuit operates in single-ended output mode, and the output waveform no longer guarantees strict differential symmetry, but in exchange, it achieves the highest oscillation frequency.

[0071] The equivalent load capacitances, arranged from largest to smallest, are: first capacitance value, third capacitance value, second capacitance value, and fourth capacitance value. Through this switching configuration, the low-power delay circuit can achieve discrete switching of the frequency range while maintaining a constant control voltage of the voltage-controlled current source. This allows it to cover a wide frequency range while avoiding excessive ring oscillator gain and optimizing phase noise performance.

[0072] This invention improves the output structure of existing ring oscillators and adds a gating switch within a minimal chip area, providing a voltage-controlled oscillator (VCO) circuit capable of achieving a wide resonant frequency range and low oscillator gain in low-power applications. The circuit dynamically adjusts the charging and discharging time of the output node capacitor using a voltage-controlled current source. As the charging and discharging current changes with the control voltage, the delay time of the output node changes accordingly, thus achieving continuous adjustment of the output frequency: increasing the charging and discharging current shortens the delay time, increasing the equivalent output frequency. Within each charging and discharging cycle, the circuit only experiences a single process of the output node discharging to ground or the power supply charging and discharging the output node. There is no DC path from the power supply to ground throughout the entire output frequency cycle, completely avoiding power waste caused by quiescent current, and significantly reducing average power consumption when generating extremely low-frequency clock signals. Because the circuit integrates a linearization control voltage module, the charging and discharging current range of the output node remains relatively constant, ensuring the linearity and stability of frequency adjustment. Meanwhile, by controlling the internal switches of the delay module, the equivalent load capacitance of the output node can be selectively changed, achieving discrete step adjustment of the resonant center frequency. Compared to schemes that rely on a single, wide-range adjustment of the control voltage to achieve a wide frequency range, the switching method of this invention effectively avoids excessive ring oscillator gain and significantly improves phase noise performance. Therefore, this circuit is suitable for various low-supply-voltage, low-power, and high-precision applications, achieving dual optimization of chip area and power consumption.

[0073] In some embodiments, the fifth switch (Q5), the sixth switch (Q6), the seventh switch (Q7), and the eighth switch (Q8) are all transistors having a first threshold voltage. The first switch (Q1), the second switch (Q2), the third switch (Q3), and the fourth switch (Q4) are all transistors having a second threshold voltage, wherein the first threshold voltage is less than or equal to the second threshold voltage.

[0074] For example, since the fifth to eighth switches Q5 and Q8 form a cross-coupled inverting latch module, their function is to provide positive feedback acceleration during the output node switching process and maintain the output state in steady state. Using a lower first threshold voltage allows these latches to turn on or off more quickly when the output node voltage changes slightly, thereby enhancing the positive feedback strength, significantly shortening the output level transition time, and improving the symmetry of the rising and falling edges. A lower threshold voltage also helps improve the response speed of the latches, making the regenerative feedback mechanism more sensitive and effective.

[0075] In contrast, the first to fourth switches, Q1 and Q4, constitute a push-pull module. Their main function is to cut off the power supply path to the inverting latch module in steady state and provide basic drive capability during switching. Using a higher second threshold voltage effectively reduces the subthreshold leakage current of these switches in the off state, thereby further reducing static power consumption. Since the push-pull transistors are in the off state in steady state, the higher threshold voltage ensures a more thorough turn-off, minimizing any potential leakage paths from the power supply to ground.

[0076] In some embodiments, the first pull-up current source (MI1), the first pull-down current source (MI2), the second pull-up current source (MI3), and the second pull-down current source (MI4) are all controllable current sources, and each controllable current source is composed of at least one MOS transistor or at least one bipolar transistor.

[0077] For example, when using MOS transistors to construct a controllable current source, the transistors are typically biased in the saturation region, so that their drain current has a square-law relationship with the gate-source voltage. The output current is linearly adjusted by controlling the gate voltage (i.e., the first control voltage Vcp or the second control voltage Vcn). To obtain a wider current adjustment range and better linearity, a current mirror structure of multiple MOS transistors connected in parallel or cascaded can be used. When using bipolar transistors to construct a controllable current source, the exponential relationship between their base-emitter voltage and collector current is utilized to achieve linear adjustment through a voltage conversion circuit. Bipolar transistors typically have better matching characteristics and lower noise.

[0078] This application also provides a voltage-controlled oscillator, such as... Figure 7As shown, the voltage-controlled oscillator 200 includes: a ring oscillator 100 composed of multiple cascaded low-power delay circuits according to any one of the embodiments of this application, and a linearization control voltage module 20. The linearization control voltage module is used to receive an external control voltage (Vc) and generate a first control voltage (Vcp) and a second control voltage (Vcn).

[0079] In this circuit, the first output (ON) and the second output (OP) of each delay circuit provide differential clock outputs. The output frequency of the voltage-controlled oscillator is continuously adjusted by an external control voltage (Vc) and the frequency range is discretely switched by a switch in the low-power delay circuit.

[0080] For example, the linearization control voltage module converts the external control voltage Vc to generate a pair of control voltages Vcp and Vcn with opposite directions of change. Specifically, when the external control voltage Vc increases, the first control voltage Vcp decreases and the second control voltage Vcn increases; when the external control voltage Vc decreases, the first control voltage Vcp increases and the second control voltage Vcn decreases. Through this conversion relationship, Vcp and Vcn can coordinately control the output current of the voltage-controlled current source: the larger Vc is, the stronger the current capability of the first pull-up current source MI1 and the second pull-up current source MI3 (controlled by Vcp), and the stronger the current capability of the first pull-down current source MI2 and the second pull-down current source MI4 (controlled by Vcn), thereby increasing the overall charging and discharging current to the output node.

[0081] When the current magnitude of the voltage-controlled current source is fixed, its charging and discharging time for the equivalent load capacitance at the output terminal is also determined. The output node level transition time of a single-stage delay unit... It can be represented as: ; Among them, C load The equivalent load capacitance of the first output terminal OP or the second output terminal ON, ΔV is the voltage swing of the output level switching, I is the charging and discharging current provided by the voltage-controlled current source, and R is the equivalent load capacitance of the first output terminal OP or the second output terminal ON. VCCS This represents the equivalent impedance corresponding to the average current generated by the voltage-controlled current source under the control of Vcp and Vcn within the periodic voltage difference.

[0082] For a ring oscillator composed of three cascaded delay units, its oscillation frequency depends on the sum of the delay times of each stage. Considering the time required for the output voltage of each delay unit to drop to half its original value, the oscillation frequency can be obtained by taking the reciprocal of the total delay time after one loop through the three stages back to the output port. , can be represented as: ; The ln(2) factor is derived from the time constant relationship when the output voltage drops to half.

[0083] In practical applications, the first output terminal OP and the second output terminal ON of each delay circuit stage provide a differential clock output, and adjacent stages are cross-connected to form a ring oscillator. The output frequency of the voltage-controlled oscillator is adjusted in two ways: firstly, by continuously adjusting R through an external control voltage Vc. VCCS First, by changing the magnitude of the charging and discharging current of the voltage-controlled current source, fine and continuous frequency tuning is achieved; second, by using the switching configuration of the first switch S1 to the fifth switch S5 inside the low-power delay circuit, the equivalent load capacitance C at the output terminal is discretely switched. load This enables large-step switching across the frequency range. This dual-mode regulation mechanism allows the voltage-controlled oscillator to cover a wide frequency range while maintaining a low oscillator gain (KVCO), effectively optimizing phase noise performance.

[0084] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A low-power delay circuit suitable for voltage-controlled oscillators, characterized in that, include: The push-pull module has a signal input terminal for receiving input signals, and is also connected to a power supply and a ground terminal. The first power transmission terminal of the push-pull module is used to provide dynamic drive signals, and the second power transmission terminal of the push-pull module is used to conduct electricity to ground. A current module is provided, wherein the control terminal of the current module is used to connect to the control voltage, the first transmission terminal of the current module is connected to the first transmission terminal of the push-pull module, the second transmission terminal of the current module is connected to the second transmission terminal of the push-pull module, and the first and second output terminals of the current module are both output terminals of the low-power delay circuit. After the dynamic drive signal undergoes a level flip, the current module charges and discharges the output terminal of the low-power delay circuit according to the control voltage. An inverting latch module includes a cross-coupled first inverting latch unit and a second inverting latch unit. The two output terminals of the first inverting latch unit are respectively connected to the first and second output terminals of the push-pull module, and the control terminal of the first inverting latch unit is connected to the first output terminal of the current module. The two output terminals of the second inverting latch unit are respectively connected to the first and second output terminals of the push-pull module, and the control terminal of the second inverting latch unit is connected to the second output terminal of the current module. The inverting latch module is used to, in conjunction with the push-pull module, maintain the output terminal of the low-power delay circuit at a relative first level and a second level after the voltage at the output terminal of the low-power delay circuit reaches a preset threshold voltage. Wherein, after the output terminal of the low-power delay circuit completes the level flip, the push-pull module and the inverting latch module do not generate a static DC path from the power supply directly to the ground terminal. The delay time of the low-power delay circuit changes with the control voltage to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits.

2. The low-power delay circuit according to claim 1, characterized in that, The push-pull module includes: a first push-pull unit and a second push-pull unit; the current module includes: a first current unit and a second current unit; and the inverting latch module includes: a first inverting latch unit and a second inverting latch unit. The first push-pull unit has an input terminal for receiving an inverted input signal and an output terminal for providing a first drive signal. The second push-pull unit has an input terminal for receiving a positive input signal and an output terminal for providing a second drive signal. The first current unit has its control terminal connected to a first control voltage and a second control voltage, respectively. The first transmission terminal of the first current unit is connected to the first transmission terminal of the first push-pull unit, and the second transmission terminal of the first current unit is connected to the second transmission terminal of the first push-pull unit. The first current unit is activated only during the level flipping process of the output terminal of the low-power delay circuit, and works with the first push-pull unit to charge or discharge the first output terminal of the low-power delay circuit. The second current unit has its control terminal connected to the first control voltage and the second control voltage, respectively. The first transmission terminal of the second current unit is connected to the first transmission terminal of the second push-pull unit, and the second transmission terminal of the second current unit is connected to the second transmission terminal of the second push-pull unit. The second current unit is activated only during the level flipping process of the output terminal of the low-power delay circuit, and works with the second push-pull unit to charge or discharge the second output terminal of the low-power delay circuit. The first inverting latch unit has its first power supply terminal connected to the first power supply terminal of the first current unit, and its second power supply terminal connected to the second power supply terminal of the first current unit. The output terminal of the first inverting latch unit is the first output terminal of the low-power delay circuit. The control terminal of the first inverting latch unit is connected to the output terminal of the second inverting latch unit. After the voltage at the output terminal of the low-power delay circuit reaches a preset voltage threshold, the first inverting latch unit and the first push-pull unit are used together to maintain the first output terminal of the low-power delay circuit at the second level and to prevent the generation of a static DC path from the power supply directly to the ground terminal. The second inverting latch unit has its first power supply terminal connected to the first power supply terminal of the second current unit, and its second power supply terminal connected to the second power supply terminal of the second current unit. The output terminal of the second inverting latch unit is the second output terminal of the low-power delay circuit. The control terminal of the second inverting latch unit is connected to the output terminal of the first inverting latch unit. After the voltage at the output terminal of the low-power delay circuit reaches a preset voltage threshold, the second inverting latch unit and the second push-pull unit are used together to maintain the second output terminal of the low-power delay circuit at the first level and to prevent the generation of a static DC path from the power supply directly to the ground terminal. The first control voltage and the second control voltage are obtained by conversion from an external control voltage and change in opposite directions. The charging time or discharging time of the output terminal of the low-power delay circuit changes continuously with the external control voltage, thereby adjusting the delay time of the low-power delay circuit to control the oscillation frequency of the voltage-controlled oscillator composed of multiple cascaded low-power delay circuits.

3. The low-power delay circuit according to claim 2, characterized in that, The first push-pull unit includes: a first switch and a second switch; the second push-pull unit includes: a third switch and a fourth switch. The source of the first switching transistor is connected to a preset power supply voltage, the drain is connected to the first terminal of the first current unit, and the gate is used to receive an inverted input signal. The drain of the second switching transistor is connected to the second terminal of the first current unit, the source is grounded, and the gate is used to receive the inverted input signal; The source of the third switch is connected to the preset power supply voltage through the fifth switch, the drain is connected to the first terminal of the second current unit, and the gate is used to receive the positive input signal. The drain of the fourth switch is connected to the second terminal of the second current unit, the source is grounded, and the gate is used to receive the positive input signal.

4. The low-power delay circuit according to claim 2, characterized in that, The first inverting latch unit includes: a fifth switch, a sixth switch, a first switch, and a second switch; the second inverting latch unit includes: a seventh switch, an eighth switch, a third switch, and a fourth switch. The source of the fifth switch is connected to the drain of the first switch, the drain is connected to the first output terminal of the low-power delay circuit through the first switch, and the gate is connected to the second output terminal of the low-power delay circuit. The source of the sixth switch (Q6) is connected to the drain of the second switch, and the drain is connected to the first output terminal of the low-power delay circuit through the second switch. The gate of the sixth switch is connected to the gate of the fifth switch. The source of the seventh switch is connected to the drain of the third switch, the drain is connected to the second output terminal of the low-power delay circuit through the third switch (S3), and the gate is connected to the first output terminal of the low-power delay circuit. The source of the eighth switch is connected to the drain of the fourth switch, and the drain is connected to the second output terminal of the low-power delay circuit through the fourth switch. The gate of the eighth switch is connected to the gate of the seventh switch.

5. The low-power delay circuit according to claim 2, characterized in that, The first current unit includes a first pull-up current source and a first pull-down current source, and the second current unit includes a second pull-up current source and a second pull-down current source; The first end of the first pull-up current source is connected to the drain of the first switching transistor, the second end is connected to the first output terminal of the low-power delay circuit, and the control terminal is connected to the first control voltage. The first terminal of the first pull-down current source is connected to the first output terminal of the low-power delay circuit, the second terminal is connected to the drain of the second switching transistor, and the control terminal is connected to the second control voltage. The first end of the second pull-up current source is connected to the drain of the third switching transistor, the second end is connected to the second output terminal of the low-power delay circuit, and the control terminal is connected to the first control voltage. The first end of the second pull-down current source is connected to the second output end of the low-power delay circuit, the second end is connected to the drain of the fourth switching transistor, and the control end is connected to the second control voltage.

6. The low-power delay circuit according to claim 4, characterized in that, By controlling the on and off states of the first to fifth switches, the equivalent load capacitance of the first output terminal and the equivalent load capacitance of the second output terminal are changed, thereby configuring the operating frequency range of the low-power delay circuit.

7. The low-power delay circuit according to claim 6, characterized in that, The low-power delay circuit includes the following operating modes: In the first mode, all switches from the first to the fifth are turned on, the equivalent load capacitance of the first output terminal and the second output terminal is the first capacitance value, and the low-power delay circuit operates in the lowest frequency range. In the second mode, the second, fourth, and fifth switches are turned on, the first and third switches are turned off, and the equivalent load capacitance of the first and second output terminals is equal to the second capacitance value. The low-power delay circuit operates in the mid-to-high frequency range. In the third mode, the first, third, and fifth switches are turned on, the second and fourth switches are turned off, the equivalent load capacitance of the first and second output terminals is the third capacitance value, and the low-power delay circuit operates in the mid-to-low frequency range. In the fourth mode, all switches from the first to the fifth are off, the equivalent load capacitance of the first output terminal and the second output terminal is the fourth capacitance value, and the low-power delay circuit operates in the highest frequency range and is in single-ended output mode. The equivalent load capacitances, in descending order, are: the first capacitance value, the third capacitance value, the second capacitance value, and the fourth capacitance value.

8. The low-power delay circuit according to claim 4, characterized in that, The fifth, sixth, seventh, and eighth switching transistors are all transistors with a first threshold voltage; the first, second, third, and fourth switching transistors are all transistors with a second threshold voltage, wherein the first threshold voltage is less than or equal to the second threshold voltage.

9. The low-power delay circuit according to claim 3, characterized in that, The first pull-up current source, the first pull-down current source, the second pull-up current source, and the second pull-down current source are all controllable current sources, and each of the controllable current sources is composed of at least one MOS transistor or at least one bipolar transistor.

10. A voltage-controlled oscillator, characterized in that, include: A linearization control voltage module is used to receive external control voltage and generate a first control voltage and a second control voltage. A ring oscillator composed of multiple cascaded low-power delay circuits as described in any one of claims 1 to 9; In this circuit, the first and second output terminals of each delay circuit provide differential clock outputs, the output frequency of the voltage-controlled oscillator is continuously adjusted by the external control voltage, and the frequency range is discretely switched by the switches in the low-power delay circuit.

Images