A delay control circuit

Abstract

This invention discloses a delay control circuit, including a delay module, a control module, and a current mirror. The first input terminal of the control module is electrically connected to a clock input signal, and the second input terminal is electrically connected to the output terminal of the delay module. The first input terminal of the delay module is also electrically connected to the clock input signal. The output terminal of the control module is electrically connected to the input terminal of the current mirror, and the output terminal of the current mirror is electrically connected to the second input terminal of the delay module. The delay module delays the clock input signal to generate a delayed signal. The control module receives the clock input signal and the delayed signal, and generates a control signal for the current mirror based on these signals. The current mirror receives the control signal and converts it into a bias current, which is then sent to the delay module to change the delay time. Using this structure, closed-loop feedback eliminates the need for a digital calibration circuit, improving the delay accuracy of the delay module and reducing static power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a delay control circuit. Background Technology

[0002] In integrated circuit design, precisely controllable delay cells are core modules for critical circuits such as clock synchronization, data sampling, and signal conditioning. Traditional RC delay lines and inverter chain delay structures are significantly affected by process, voltage, and temperature fluctuations, with delay time drifts exceeding ±20%, leading to insufficient system timing margins. To compensate for the sensitivity to PVT, existing solutions require the integration of additional digital calibration circuits (such as delay-locked loops (DLLs) or phase-locked loops (PLLs). However, this approach increases the overall circuit area and power consumption, and the calibration process is time-consuming. Multiple delay requirements necessitate the independent design of multiple delay chains, making it difficult to guarantee the consistency of delays across different paths and hindering the achievement of high-precision coordinated control. Summary of the Invention

[0003] This invention provides a delay control circuit that, by forming a closed-loop feedback system with a delay module, a control module, and a current mirror, achieves precise control of the delay amount of the delay module without the need for digital calibration. This effectively overcomes the delay drift problem caused by changes in process, voltage, and temperature, improves the delay accuracy of the delay module, reduces static power consumption, and has a small size.

[0004] This invention provides a delay control circuit, including a delay module, a control module, and a current mirror; the first input terminal of the control module is electrically connected to a clock input signal, and the second input terminal is electrically connected to the output terminal of the delay module; the first input terminal of the delay module is electrically connected to the clock input signal; the output terminal of the control module is electrically connected to the input terminal of the current mirror, and the output terminal of the current mirror is electrically connected to the second input terminal of the delay module. The delay module is used to delay the clock input signal to generate a delayed signal; The control module is used to receive clock input signals and delay signals, and generate control signals to the current mirror based on the clock input signals and delay signals; The current mirror is used to receive control signals and convert them into bias currents to send to the delay module, thereby changing the delay time of the delay module.

[0005] Optionally, the delay module includes a current-controlled delay inverter.

[0006] Optionally, the control module includes a phase detector, an XOR gate, and an integrator; The first input terminal of the phase detector is electrically connected to the clock input signal, the second input terminal is electrically connected to the output terminal of the delay module, and the output terminal is electrically connected to the input terminal of the XOR gate; the output terminal of the XOR gate is electrically connected to the negative input terminal of the integrator; the positive input terminal of the integrator is electrically connected to the reference voltage, and the output terminal is electrically connected to the input terminal of the current mirror. A phase detector is used to determine the phase difference between the clock input signal and the delayed signal; The XOR gate is used to convert the phase difference into a pulse signal corresponding to the phase difference and then output the inverted signal. The integrator is used to receive pulse signals and convert them into control signals that are transmitted to the current mirror.

[0007] Optionally, the circuit also includes at least one inverter; the inverters are connected in series; the power supply terminal of the inverter is electrically connected to the power supply voltage, and the ground terminal is grounded; the input terminal of the first inverter is electrically connected to the output terminal of the current mirror, and the output terminal of the previous inverter is electrically connected to the input terminal of the next inverter.

[0008] Optionally, the pulse width of the pulse signal is the time interval corresponding to the phase difference between the delayed signal and the clock input signal.

[0009] Optionally, the delay time Tdelay of the delay module, the power supply voltage VDD of the clock input signal, the period Tclk of the clock input signal, and the reference voltage Vref satisfy the following: .

[0010] Optional, 0 < Vref / VDD < 1.

[0011] Optionally, the current mirror includes a first NMOS transistor and a second NMOS transistor; The gates of both the first and second NMOS transistors are electrically connected to the output of the control module, and their sources are both grounded; the drain of the first NMOS transistor is electrically connected to the second input of the delay module. The width-to-length ratios of the first and second NMOS transistors are different.

[0012] Optionally, the control signal may include a control voltage signal.

[0013] The technical solution of this invention involves transmitting the clock input signal directly to the control module and to a delay module. The delay module performs a controllable delay on the clock input signal and outputs a delayed signal to the control module. Upon receiving the clock input signal and the delayed signal, the control module compares the phase difference between them and generates a corresponding control signal, which is then output to the current mirror. The current mirror converts this control signal into a bias current and feeds it back to the second input terminal of the delay module. The delay module is configured as a current-regulated delay unit. When the input clock signal changes, the bias current output by the current mirror changes accordingly. The delay module uses this bias current to dynamically adjust the delay time, ultimately stabilizing the system at the target delay value. When the PVT changes, the clock input signal changes, which in turn changes the control signal output by the control module, causing the bias current to change. This changing bias current, transmitted to the delay module, alters the delay time, ensuring its stability. Using the above structure, by forming a closed-loop feedback system with the delay module, control module and current mirror, precise control of the delay amount of the delay module is achieved without the need for digital calibration. This effectively overcomes the delay drift problem caused by process, voltage and temperature changes, improves the delay accuracy of the delay module to ±0.1ns, reduces static power consumption by more than 40%, and has a small size.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a delay control circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another delay control circuit provided in an embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] In one embodiment, Figure 1 This is a schematic diagram of a delay control circuit provided in an embodiment of the present invention. This embodiment is applicable to situations where a delay circuit that is insensitive to PVT does not require a digital calibration circuit, thus ensuring that the delay time can be precisely controlled and determined. Figure 1 As shown, the delay control circuit includes a delay module 1, a control module 2, and a current mirror 3. The first input terminal of the control module 2 is electrically connected to the clock input signal CLK, and the second input terminal is electrically connected to the output terminal of the delay module 1. The first input terminal of the delay module 1 is electrically connected to the clock input signal CLK. The output terminal of the control module 2 is electrically connected to the input terminal of the current mirror 3, and the output terminal of the current mirror 3 is electrically connected to the second input terminal of the delay module 1. The delay module 1 is used to delay the clock input signal CLK to generate a delayed signal. The control module is used to receive the clock input signal CLK and the delayed signal, and generate a control signal to the current mirror 3 based on the clock input signal CLK and the delayed signal. The current mirror 3 is used to receive the control signal and convert the control signal into a bias current and send it to the delay module 1 to change the delay time of the delay module 1.

[0020] The delay module 1 is a circuit unit used to introduce a controllable time delay into the clock input signal CLK. It receives the clock input signal CLK and, under the control of the bias current, generates an output signal with a specific delay, i.e., a delayed signal. In this embodiment, the delay module 1 includes a Current-Controlled Delay Inverter (CCDI), an analog adjustable delay unit that, while achieving logical inversion, precisely controls its propagation delay time using an externally provided bias current. The delay time of the CCDI is approximately inversely proportional to the bias current. The control module 2 is the core control structure of this embodiment, used to receive the clock input signal CLK and the delayed signal, determine the delay error, and generate a feedback control signal. In this embodiment, the control signal generated by the control module 2 may include a control voltage signal, a control current signal, or a control level signal, etc., which can be determined according to the actual situation and is not limited here. In this embodiment, the preferred control signal is a control voltage signal. The current mirror 3 is a circuit structure that converts the input control signal into a bias current and outputs it. In this embodiment, the current mirror 3 may include a pair of NMOS transistors or a pair of PMOS transistors, which can be determined according to the actual situation and is not limited here.

[0021] Specifically, after the system is powered on, a clock input signal CLK is generated under the supply voltage (i.e., power supply voltage VDD). The generated clock input signal CLK is split into two paths: one is directly transmitted to control module 2, and the other is transmitted to delay module 1. Delay module 1 performs a controllable delay on the clock input signal CLK and outputs a delayed signal to control module 2. After receiving the clock input signal CLK and the delayed signal, control module 2 compares the phase difference between the clock input signal CLK and the delayed signal, generates a control signal corresponding to the phase difference, and outputs it to current mirror 3. After receiving the control signal generated by control module 2, current mirror 3 converts the control signal into a bias current and feeds it back to the second input terminal (i.e., the bias control terminal) of delay module 1. In this embodiment, delay module 1 is configured as a current-controlled delay unit, whose propagation delay depends not only on the edge changes of the input signal but also, more critically, on an externally provided bias current. When the input clock signal CLK changes, the bias current output by the current mirror 3 changes accordingly. The delay module 1 charges and discharges the equivalent load capacitance of its output node through this bias current. The charging and discharging speed directly determines the flip time of the output signal, thus determining the overall delay time. The larger the bias current, the faster the charging and discharging, and the shorter the delay; the smaller the bias current, the slower the charging and discharging, and the longer the delay. In this way, the delay time of the delay module 1 is dynamically adjusted, so that the system eventually stabilizes at the target delay.

[0022] It should be noted that during actual circuit operation, process deviations, voltage fluctuations, or temperature changes may cause the actual delay of delay module 1 to deviate from the target delay. In this case, control module 2 detects the phase difference between the clock input signal CLK and the delayed signal output by delay module 1, and adjusts its output control signal accordingly. This control signal is converted into a new bias current via current mirror 3 and fed back to delay module 1, thereby changing the delay time of delay module 1 and achieving automatic compensation for delay time drift. For example, when the delay is too long, control module 2 increases the control signal to increase the bias current output by current mirror 3 to accelerate signal transmission; when the delay is too short, it decreases the bias current to appropriately "lengthen" the transmission time. Through this continuous and adaptive adjustment mechanism, the delay time of delay module 1 is stably maintained near the set target delay, achieving a highly robust constant delay output.

[0023] The technical solution of this invention involves transmitting the clock input signal directly to the control module and to a delay module via another path. The delay module performs a controllable delay on the clock input signal and outputs a delayed signal to the control module. Upon receiving the clock input signal and the delayed signal, the control module compares the phase difference between them and generates a corresponding control signal, which is then output to the current mirror. The current mirror converts this control signal into a bias current and feeds it back to the second input terminal of the delay module. The delay module is configured as a current-regulated delay unit. When the input clock signal changes, the bias current output by the current mirror changes accordingly. The delay module uses this bias current to dynamically adjust the delay time, ultimately stabilizing the system at the target delay value. When the PVT changes, the clock input signal changes, which in turn changes the control signal output by the control module, causing the bias current to change. This changing bias current, transmitted to the delay module, alters the delay time, ensuring its stability. Using the above structure, by forming a closed-loop feedback system with the delay module, control module and current mirror, precise control of the delay amount of the delay module is achieved without the need for digital calibration. This effectively overcomes the delay drift problem caused by process, voltage and temperature changes, improves the delay accuracy of the delay module to ±0.1ns, reduces static power consumption by more than 40%, and has a small size.

[0024] In another specific embodiment, optionally, Figure 2 This is a schematic diagram of another delay control circuit provided in an embodiment of the present invention, with reference to... Figure 2 As shown, the control module 2 includes a phase detector 21, an XOR gate 22, and an integrator 23. The first input terminal of the phase detector 21 is electrically connected to the clock input signal CLK, the second input terminal is electrically connected to the output terminal of the delay module 1, and the output terminal is electrically connected to the input terminal of the XOR gate 22. The output terminal of the XOR gate 22 is electrically connected to the negative input terminal of the integrator 23. The positive input terminal of the integrator 23 is electrically connected to the reference voltage Vref, and the output terminal is electrically connected to the input terminal of the current mirror 3. The phase detector 21 is used to determine the phase difference between the clock input signal and the delay signal. The XOR gate 22 is used to convert the phase difference into a pulse signal corresponding to the phase difference and output it after inversion. The integrator 23 is used to receive the pulse signal and convert the pulse signal into a control signal to be transmitted to the current mirror.

[0025] Optionally, the pulse width of the pulse signal is the time interval corresponding to the phase difference between the delayed signal and the clock input signal.

[0026] The phase detector 21 is a circuit unit used to detect the phase relationship between two periodic signals. In this embodiment, the phase detector 21 compares the phase of the clock input signal CLK with the delayed signal to determine the phase difference information between them, and outputs this information as an electrical signal to the XOR gate 22. This output signal itself does not directly represent the pulse width, but serves as the basis for subsequent processing by the XOR gate 22. The XOR gate 22 is a digital logic gate that outputs a high level when the two input signals are different and a low level when they are the same, used to convert the phase difference into a pulse signal and invert it. The integrator 23 is an analog circuit with high DC gain and low-pass filtering characteristics, which may include operational amplifiers and feedback capacitors, etc. The specific components can be determined according to the actual situation and are not limited here.

[0027] Specifically, the clock input signal CLK and the delayed signal output from delay module 1 are input to the two input terminals (i.e., the first input terminal and the second input terminal) of phase detector 21, respectively. After receiving these two signals, phase detector 21 compares the phase of the clock input signal CLK and the delayed signal to determine the phase difference, and transmits the determined phase difference information to XOR gate 22. After receiving the phase difference, XOR gate 22 generates a digital pulse signal whose pulse width is proportional to the time corresponding to the phase difference, where the pulse width is the time interval corresponding to the phase difference between the delayed signal and the clock input signal. Then, the pulse signal is logically inverted to correct the feedback polarity, ensuring that the feedback polarity is correct and forming a stable negative feedback loop. The final output of XOR gate 22 is a pulse signal that is proportional to the phase difference and has the correct polarity. The generated pulse signal is transmitted to the negative input terminal of integrator 23, while the positive input terminal of integrator 23 is connected to a fixed reference voltage Vref. Under the action of high-gain negative feedback, integrator 23 continuously adjusts its power supply voltage, making the average voltage at the negative input terminal approach Vref, thereby accurately mapping the duty cycle of the pulse signal to a continuous control voltage signal. This control voltage is output to current mirror 3 to drive current mirror 3 to generate a corresponding bias current. The generated bias current is fed back to the second input terminal of delay module 1, thereby dynamically adjusting the signal transmission speed inside delay module 1 and changing the delay time of delay module 1. When the delay deviates from the target delay amount due to changes in process, voltage, or temperature, the above closed-loop feedback loop automatically detects the error, generates a correction signal, and adjusts the deviation through the current mirror, ultimately stabilizing the delay time near the target delay amount. The entire process achieves adaptive delay control with no digital calibration, fast response, and high precision.

[0028] In another specific embodiment, optionally, the delay time Tdelay of the delay module, the power supply voltage VDD of the clock input signal, the period Tclk of the clock input signal, and the reference voltage Vref satisfy: .

[0029] Optional, 0 < Vref / VDD < 1.

[0030] Specifically, the delay time Tdelay generated by the delay module is stabilized at a target value determined by an externally set voltage ratio through a closed-loop feedback mechanism. Specifically, Tdelay satisfies the following relationship with the clock input signal period Tclk, the power supply voltage VDD (i.e., the logic high-level voltage driving the clock input signal, typically the system power supply voltage), and the reference voltage Vref: This relationship originates from the steady-state equilibrium condition of the control closed-loop feedback loop: when the system is stable, the control voltage output by integrator 23 causes the bias current provided by current mirror 3 to act on delay module 1, and the propagation delay time generated by delay module 1 satisfies the above relationship. It can be seen that the delay time of delay module 1 is directly determined by the ratio of Tclk and voltage Vref / VDD, rather than by absolute parameters such as the transconductance, threshold voltage, or parasitic capacitance of the transistor in current mirror 3, which are easily affected by process, voltage, and temperature (PVT). Therefore, even under conditions of VDD fluctuation, process angle offset, or temperature change (i.e., PVT fluctuation), as long as the ratio of Vref and VDD has a similar trend, its ratio can remain highly stable, thereby significantly suppressing delay drift.

[0031] Furthermore, to ensure that the delay time has physical meaning and is within the effective operating range, a reasonable constraint needs to be applied to the voltage ratio of Vref and VDD. In this embodiment, 0 < Vref / VDD < 1, i.e., 0 < Vref < VDD. By adjusting the value of Vref within the range of (0, VDD), any target value of Tdelay within the range of (0, Tclk) can be continuously and accurately configured, meeting the nanosecond-level programmable delay requirements of applications such as high-speed interface sampling, multi-phase clock generation, and time-to-digital conversion (TDC).

[0032] In another specific embodiment, optionally, reference continues. Figure 2 The circuit also includes at least one inverter (not shown in the figure); the inverters are connected in series; the power supply terminal of the inverter is electrically connected to the power supply voltage VDD, and the ground terminal is grounded to GND; the input terminal of the first inverter is electrically connected to the output terminal of the current mirror 3, and the output terminal of the previous inverter is electrically connected to the input terminal of the next inverter.

[0033] Inverters are circuit devices used to achieve multiple levels of output with different delay values. In this embodiment, there are one or more inverters. When there are multiple inverters, they are connected end-to-end, meaning the output terminal of one inverter is electrically connected to the input terminal of the next inverter, forming a series connection. Furthermore, the power supply terminal of the inverter is electrically connected to the power supply voltage VDD to power it. The input terminal of the inverter is electrically connected to the output terminal of the current mirror 3. Thus, the bias current generated by the current mirror 3 is transmitted to the inverter, enabling it to achieve different delay times. In this embodiment, the bias current is inversely proportional to the delay value; that is, the larger the bias current, the shorter the delay time, and the smaller the bias current, the longer the delay time. Therefore, the magnitude of the bias current output by the current mirror 3 can be determined according to the required multiple levels of different fixed delay values, thereby adjusting the bias current of the current mirror 3. For example, if the bias current output by current mirror 3 is I0, and the corresponding delay time of delay module 1 is 5ns, then the bias current I1 input to the first inverter can be set to I1 = 0.5I0, thus achieving an output delay of 10ns. If the bias current I1 input to the first inverter is set to I1 = 2I0, then an output delay of 2.5ns can be achieved, and so on. It should be noted that an inverter is essentially a basic CMOS unit composed of PMOS and NMOS transistors: when the input signal changes, the PMOS or NMOS is turned on, charging or discharging the parasitic capacitance of the output node, thereby completing the high-low level conversion; and the speed of this charging and discharging process directly determines the signal propagation delay, achieving outputs with different delay amounts.

[0034] Optional, continue to refer to Figure 2 The current mirror 3 includes a first NMOS transistor 31 and a second NMOS transistor 32; the gates of both the first NMOS transistor 31 and the second NMOS transistor 32 are electrically connected to the output terminal of the control module 2, and the sources of both are grounded; the drain of the first NMOS transistor 31 is electrically connected to the second input terminal of the delay module 1; the width-to-length ratios of the first NMOS transistor 31 and the second NMOS transistor 32 are different.

[0035] The first NMOS transistor 31 and the second NMOS transistor 32 are both components of the current mirror 3, and are N-type metal-oxide-semiconductor field-effect transistors. The first NMOS transistor 31 and the second NMOS transistor 32 form a common-gate current mirror structure, which converts the control voltage into a precise bias current. By setting different width-to-length ratios (W / L), different mirror currents can be generated under the same gate voltage, thereby supporting differentiated bias or proportional control of multiple delay cells.

[0036] In this embodiment, the current mirror 3 can be specifically implemented as a mirror structure composed of a first NMOS transistor 31 and a second NMOS transistor 32. The gates of both transistors are connected to the control module 2, receiving the same control voltage, and their sources are both grounded, forming a typical common-source common-gate current mirror configuration. The drain of the first NMOS transistor 31 is connected to the second input terminal (i.e., the bias control terminal) of the delay module 1, used to provide the main bias current to the delay module 1; the second NMOS transistor 32 can serve as a mirror reference transistor or be used to drive other auxiliary circuits (such as the input terminal of an inverter). In this embodiment, the channel width-to-length ratio (W / L) of the first NMOS transistor 31 and the second NMOS transistor 32 is different, so that their conduction currents are proportional under the same gate voltage. By reasonably setting this ratio, not only can the magnitude of the bias current be precisely controlled, but it can also be extended to multi-channel delay output scenarios. For example, if the width-to-length ratio (W / L) of the NMOS transistor corresponding to a certain inverter is large, its output bias current is stronger, resulting in faster charging and discharging and shorter delay for the inverter; conversely, a smaller W / L ratio results in weaker bias current and longer delay. By configuring the W / L ratio of each NMOS transistor in the current mirror 3, different amplitude bias currents can be provided to multiple inverters, even if they share the same control voltage and power supply voltage VDD, achieving multiple independent and precisely controllable delay values. This structure not only simplifies the control logic but also ensures high consistency of multi-channel delays under variations in process technology, voltage, and temperature, making it suitable for high-performance applications such as multiphase clock generation and time-domain signal processing.

[0037] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0038] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A delay control circuit, characterized in that, It includes a delay module, a control module, and a current mirror; the first input terminal of the control module is electrically connected to a clock input signal, and the second input terminal is electrically connected to the output terminal of the delay module; the first input terminal of the delay module is electrically connected to the clock input signal; the output terminal of the control module is electrically connected to the input terminal of the current mirror, and the output terminal of the current mirror is electrically connected to the second input terminal of the delay module. The delay module is used to delay the clock input signal to generate a delayed signal; The control module is used to receive the clock input signal and the delay signal, and generate a control signal to the current mirror based on the clock input signal and the delay signal. The current mirror is used to receive the control signal and convert the control signal into a bias current to be sent to the delay module to change the delay time of the delay module.

2. The delay control circuit according to claim 1, characterized in that, The delay module includes a current-controlled delay inverter.

3. The delay control circuit according to claim 1, characterized in that, The control module includes a phase detector, an XOR gate, and an integrator. The first input terminal of the phase detector is electrically connected to the clock input signal, the second input terminal is electrically connected to the output terminal of the delay module, and the output terminal is electrically connected to the input terminal of the XOR gate; the output terminal of the XOR gate is electrically connected to the negative input terminal of the integrator; the positive input terminal of the integrator is electrically connected to the reference voltage, and the output terminal is electrically connected to the input terminal of the current mirror. The phase detector is used to determine the phase difference between the clock input signal and the delayed signal; The XOR gate is used to convert the phase difference into a pulse signal corresponding to the phase difference and then output the inverted signal. The integrator is used to receive the pulse signal and convert the pulse signal into the control signal, which is then transmitted to the current mirror.

4. The delay control circuit according to claim 3, characterized in that, It also includes at least one inverter; the inverters are connected in series; the power supply terminal of the inverter is electrically connected to the power supply voltage, and the ground terminal is grounded; the input terminal of the first inverter is electrically connected to the output terminal of the current mirror, and the output terminal of the previous inverter is electrically connected to the input terminal of the next inverter.

5. The delay control circuit according to claim 3, characterized in that, The pulse width of the pulse signal is the time interval corresponding to the phase difference between the delayed signal and the clock input signal.

6. The delay control circuit according to claim 3, characterized in that, The delay time Tdelay of the delay module, the power supply voltage VDD of the clock input signal, the period Tclk of the clock input signal, and the reference voltage Vref satisfy the following: .

7. The delay control circuit according to claim 6, characterized in that, 0 < Vref / VDD < 1.

8. The delay control circuit according to claim 1, characterized in that, The current mirror includes a first NMOS transistor and a second NMOS transistor; The gates of both the first NMOS transistor and the second NMOS transistor are electrically connected to the output terminal of the control module, and their sources are both grounded; the drain of the first NMOS transistor is electrically connected to the second input terminal of the delay module. The width-to-length ratios of the first NMOS transistor and the second NMOS transistor are different.

9. The delay control circuit according to claim 1, characterized in that, The control signal includes a control voltage signal.

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