A frequency synthesis integer boundary spur optimization method based on a lookup table mode

Abstract

This invention discloses a frequency synthesis integer boundary spurious optimization method based on a lookup table. The method includes constructing a spurious avoidance configuration table, which maps the optimal loop parameters corresponding to each frequency point within the tuning range of a voltage-controlled oscillator (VCO). After determining the target frequency, the corresponding VCO frequency is analyzed. If it falls within a spurious-sensitive region, the phase detection frequency, loop bandwidth, and modulator parameters are loaded by looking up the table. The phase-locked loop (PLL) is dynamically configured to suppress first-order or second-order integer boundary spurious emissions. This invention can achieve active avoidance and precise suppression of spurious emissions at any frequency point. By pre-constructing a spurious avoidance configuration table containing sensitive region identifiers and optimal parameters, the matching combination of parameters such as the phase detection frequency and loop bandwidth is queried after the target frequency is determined, guiding the operating frequency to a low-spurious region. This method combines offline simulation and measured data to construct a high-dimensional mapping table. During runtime, parameter loading can be completed with only one table lookup, improving spectral purity while balancing suppression performance and response speed.

Description

Technical Field

[0001] This invention relates to the fields of communication engineering and radio frequency integrated circuit technology, and more specifically to a frequency synthesis integer boundary spurious optimization method based on a lookup table approach. Background Technology

[0002] Frequency synthesizers are key components in electronic systems. Their main function is to generate stable signals of the required frequencies. Through internal phase-locked loops (PLLs) or other frequency synthesis techniques, frequency synthesizers generate a series of accurate and stable output frequencies based on one or more reference signals. These output frequencies can be fixed or dynamically adjusted according to external control signals. With the evolution of technology, frequency synthesis methods have gradually developed into mainstream types such as direct frequency synthesis, phase-locked frequency synthesis, and direct digital frequency synthesis.

[0003] In the widely used frequency synthesizer architecture based on phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs), the system can output a radio frequency (RF) signal at a specific frequency. Ideally, this output should only contain the target carrier signal. However, in practice, interference spurious signals and phase noise are unavoidable. Among these, integer boundary spurious signals are a particularly prominent problem. This is caused by the need to introduce a prescaler at the input of the fractional-division PLL structure, which excites spurious components close to the carrier under specific frequency conditions. These spurious signals are usually located close to the carrier and are difficult to suppress effectively by conventional filtering methods, significantly affecting the spectral purity and receiver sensitivity of the communication system.

[0004] Existing technologies for suppressing integer boundary spurious emissions mainly include optimizing loop bandwidth, adjusting phase detection frequency, and using modulator noise shaping. However, these methods often struggle to balance spurious emission suppression with system flexibility when faced with arbitrary frequency output requirements. Especially when the target output frequency causes the VCO operating frequency to fall into a region prone to generating integer boundary spurious emissions, traditional configuration strategies may cause first- or second-order boundary spurious emissions to get too close to the carrier, thus affecting overall signal quality. Furthermore, some solutions rely on complex real-time computation or additional hardware resources, which limits their implementation in resource-constrained applications or those requiring high response speeds.

[0005] In summary, existing frequency synthesizers still face challenges in suppressing integer boundary spurious emissions, including uncontrollable spurious emission locations, reliance on specific configuration conditions for suppression effectiveness, and a lack of universal optimization mechanisms applicable to output at any frequency point across a wide bandwidth. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a frequency synthesizer integer boundary spurious optimization method based on a lookup table approach. This method aims to solve the deficiencies of existing frequency synthesizers in suppressing integer boundary spurious emissions, such as uncontrollable spurious location, suppression effectiveness dependent on specific configuration conditions, and lack of a universal optimization mechanism applicable to output at any frequency point in a wide bandwidth.

[0007] Specifically, to achieve active avoidance and precise suppression of integer boundary spurious emissions, based on the problem that first-order or second-order integer boundary spurious emissions close to the carrier are generated at a specific operating frequency due to the prescaler in the fractional frequency division phase-locked loop structure, a spurious avoidance configuration table containing the mapping relationship between spurious sensitive area identifiers and optimal configuration parameters is pre-constructed. After the target output frequency is determined, the table is queried to obtain the corresponding combination of configuration parameters such as phase detection frequency, loop bandwidth, modulator order and noise shaping coefficient, thereby guiding the operating frequency to a region with lower spurious energy and avoiding it from falling into the critical range that easily generates integer boundary spurious emissions;

[0008] To improve the spectral purity and configuration flexibility of the frequency synthesizer system at any output frequency, a high-dimensional configuration mapping table is constructed by combining offline simulation and measured data. This table covers all potential output frequencies within the entire tuning range, and each frequency is associated with a set of optimized and verified loop parameters. During runtime, parameter loading can be completed with only one table lookup operation, without the need for complex online calculations or additional hardware resources, thus balancing spurious suppression performance and system response speed.

[0009] To achieve the above objectives, the present invention provides the following technical solution: A frequency synthesizer integer boundary spurious optimization method based on table lookup includes the following steps: The spurious sensitive region modeling steps are based on the fractional frequency division architecture of the phase-locked loop, analyzing the generation mechanism of integer boundary spurious spurs, determining the mathematical relationship between the output frequency of the voltage-controlled oscillator, the phase detection frequency, and the integer frequency division ratio, identifying the critical frequency range within the tuning range that leads to a significant increase in the first-order or second-order integer boundary spurious energy, and marking these ranges as spurious sensitive regions. The configuration parameter optimization steps involve, based on each discrete frequency point within the tuning range, using an electromagnetic simulation platform or hardware-in-the-loop test system, traversing different combinations of phase detection frequencies, loop filter bandwidths, modulator orders, and noise transfer function coefficients, measuring the integer boundary spurious power level of the corresponding output signal, and selecting the optimal parameter set that makes the spurious power lower than the preset threshold. The steps for constructing the spurious avoidance configuration table are as follows: the tuning range is divided into multiple discrete frequency bands, each frequency band is associated with its corresponding optimal parameter set, and a mapping table is established with the target frequency as the index and the optimal parameter set as the value. The target frequency analysis step involves receiving the target output frequency command from an external input, deducing the corresponding operating frequency based on the frequency synthesis formula of the phase-locked loop, and determining whether the frequency falls into any spurious sensitive region. In the table lookup and parameter loading steps, if the operating frequency falls within the spurious sensitive region, the spurious avoidance configuration table is queried using that frequency as the key, the corresponding optimal parameter set is read, and the phase detection frequency, loop bandwidth, and modulator configuration parameters are written into the corresponding registers of the frequency synthesizer; if it does not fall within the spurious sensitive region, the default configuration parameters are used.

[0010] Furthermore, the stray sensitive region modeling step includes a boundary frequency calculation strategy, which includes a first-order boundary determination step and a second-order boundary determination step. The first-order boundary determination step includes a first-order formula: ,in It is an integer frequency division ratio. This refers to the output frequency of the voltage-controlled oscillator. For phase detection frequency, The frequency offset is defined as the output frequency range of the voltage-controlled oscillator that meets this condition when the frequency offset approaches zero. This range is then marked as the first-order sensitive region. The second-order boundary determination step includes a second-order formula: ,in and All are integers, and If the value is greater than 1, and the output frequency of the voltage-controlled oscillator satisfies the second-order formula, then the neighborhood of such frequencies is marked as the second-order sensitive region.

[0011] Furthermore, the configuration parameter optimization step includes a spurious power evaluation strategy, which includes a spectrum scanning step and a threshold comparison step; The spectrum scanning step involves controlling the spectrum analyzer to perform a high-resolution scan of the phase-locked loop output signal at a fixed target output frequency, and extracting the power of spurious components within a preset range from the carrier. The threshold comparison step compares the extracted spurious power with a preset spurious suppression threshold. If the power is lower than the threshold, the current parameter combination is recorded as a candidate optimal solution.

[0012] Furthermore, the spurious avoidance configuration table construction step includes a frequency band allocation strategy, which includes a uniform allocation step and an adaptive refinement step. The uniform division step divides the entire tuning range of the voltage-controlled oscillator into an initial frequency band grid with a fixed step size. The adaptive refinement step uses a smaller partitioning step size than the initial frequency band grid within the spurious sensitive region to ensure that each sensitive sub-region is independently mapped to a dedicated set of optimized parameters.

[0013] Furthermore, the table lookup and parameter loading steps include an interpolation compensation strategy, which includes a neighboring frequency point retrieval step and a linear interpolation step. In the neighboring frequency retrieval step, when the target frequency does not precisely match the index in the table, the two stored frequencies that are adjacent to it are retrieved. The linear interpolation step involves linearly interpolating the parameter values ​​corresponding to two adjacent frequency points to generate an intermediate parameter set suitable for the current target frequency.

[0014] Furthermore, the loop dynamic configuration step includes a stability verification strategy, which includes a phase margin detection step and a lock-in time monitoring step. The phase margin detection step, after parameter loading, estimates the phase margin of the current loop through the built-in loop diagnosis module. If it is lower than the safety threshold, it reverts to the previous stable configuration. The lock time monitoring step records the time from parameter switching to frequency lock. If the time exceeds the preset upper limit, a configuration anomaly alarm is triggered.

[0015] Furthermore, it also includes a configuration table update step. During system operation, if the ambient temperature change exceeds a preset value or the power supply voltage fluctuation exceeds a preset rate, the configuration parameter optimization step is triggered to be re-executed, and the newly generated parameter set is written to the corresponding position in the stray avoidance configuration table.

[0016] Furthermore, it also includes a multi-mode compatibility step, wherein the spurious avoidance configuration table is divided into multiple sub-tables, corresponding to low power mode, high speed switching mode and high purity mode respectively. Each sub-table adopts a different objective function in the parameter optimization stage, and the corresponding sub-table is selected for querying according to the current system working mode when looking up the table.

[0017] Furthermore, the frequency synthesizer includes a phase detector, a loop filter, a modulator, and a voltage-controlled oscillator, with each module interconnected via an internal bus.

[0018] The beneficial effects of this invention are as follows: By pre-building and storing a spurious avoidance configuration table, active avoidance of integer boundary spurious signals can be completed by performing only one table lookup operation during system operation. This avoids the drawbacks of traditional methods that rely on complex real-time calculations or sacrifice system flexibility. This method does not introduce additional hardware overhead and is suitable for resource-constrained integrated RF systems. The configuration table covers the entire tuning range and supports spurious suppression at any frequency output, significantly improving the spectral purity and reliability of the frequency synthesizer in high-precision communication, radar, and test and measurement scenarios. At the same time, by introducing interpolation compensation, stability verification, and online update mechanisms, the robustness and environmental adaptability of the system are enhanced. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall process of the integer boundary spurious optimization method in this invention; Figure 2 This is a schematic diagram showing the mapping relationship between the stray sensitive area and the configuration parameters within the tuning range of the voltage-controlled oscillator in this invention; Figure 3 This is a functional module association diagram of the frequency synthesizer integer boundary spurious optimization system of the present invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Identical components are denoted by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "upper," and "lower" used in the following description refer to directions in the accompanying drawings, and the terms "bottom surface," "top surface," "inner," and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0021] The hardware components include a frequency synthesizer main control unit, non-volatile memory, Σ-Δ modulator, phase detector, loop filter, voltage-controlled oscillator (VCO), and spectrum monitoring interface. All modules are interconnected via an internal bus.

[0022] The optimization method section, such as Figure 1 As shown, the first step is to model the spurious sensitive region. First, based on the fractional frequency division phase-locked loop architecture, the VCO output frequency is established. With phase detection frequency Integer frequency division ratio The mathematical relationships between them include first-order and second-order formulas, where the first-order formulas are configured as follows: ,in It is an integer frequency division ratio. This refers to the output frequency of the voltage-controlled oscillator. For phase detection frequency, For the frequency offset, the second-order formula is configured as follows: ,in and All are integers, and If the value is greater than 1, in the first-order boundary determination step, when the frequency offset approaches zero, the system is prone to exciting first-order integer boundary spurious emissions. The output frequency range of the voltage-controlled oscillator that satisfies this condition is marked as the first-order sensitive region. In the second-order boundary determination step, considering the higher-order modulation effect introduced by the Σ-Δ modulator, when the output frequency of the voltage-controlled oscillator satisfies the second-order formula, it may excite second-order boundary spurious emissions. Such frequency neighborhoods are marked as second-order sensitive regions. Finally, a spurious sensitive region mapping map covering the entire VCO tuning range is formed.

[0023] The second step involves optimizing the configuration parameters. Based on each discrete frequency point within the VCO tuning range, different combinations of phase detection frequencies, loop filter bandwidths, Σ-Δ modulator orders (1st to 4th order), and noise transfer function coefficients are explored using an electromagnetic simulation platform or hardware-in-the-loop test system. In the spectrum scanning step, an external spectrum analyzer is controlled to perform a high-resolution scan of the PLL output signal, extracting spurious component power within a range of ±1 MHz from the carrier. In the threshold comparison step, the extracted spurious power is compared with a preset spurious suppression threshold (e.g., ...). The parameters are compared with 60dBc. If the parameter combination is lower than the threshold, the current parameter combination is recorded as a candidate optimal solution. Finally, an optimal set of parameters that minimizes the spurious power of the integer boundary is selected for each frequency point.

[0024] The third step involves constructing a spurious avoidance configuration table. The VCO tuning range is divided into an initial frequency band grid using a uniform partitioning process, forming a basic index structure. In the adaptive refinement step, a finer partitioning granularity is applied to the identified first- and second-order sensitive regions to ensure that each sensitive sub-region is independently mapped to a dedicated set of optimized parameters. Finally, a mapping table is constructed with the target VCO frequency as the index and the optimal parameter set as the value. This table is stored in non-volatile memory in a structured data format, supporting fast random access.

[0025] The fourth step is target frequency resolution, receiving the target output frequency command from an external input. According to the frequency synthesis formula of the phase-locked loop ,in From the output division ratio, the corresponding VCO operating frequency can be derived. Then, the stray sensitive area mapping map was queried to determine the... Check if it falls within any marked first- or second-order sensitive areas. If not, maintain the default configuration parameters; if it does, proceed with the table lookup process.

[0026] The fifth step is dynamic loop configuration. Based on the loaded parameters, the phase-locked loop is reconfigured, and the operating frequency of the phase detector is adjusted to the new value. The loop filter's RC network parameters are updated to match the target bandwidth, and the feedback path of the Σ-Δ modulator is configured to achieve noise shaping of a specified order. In the phase margin detection step, the phase margin of the current loop is estimated by the built-in loop diagnostic module (such as a Bode analysis unit based on injected perturbation). If it is lower than the safety threshold, it reverts to the previous stable configuration. In the lock-in time monitoring step, the time from parameter switching to frequency lock is recorded. If it exceeds the preset upper limit, a configuration anomaly alarm is triggered and the log is recorded.

[0027] It also includes a configuration table update step. During system operation, if the temperature sensor or power monitoring module detects an ambient temperature change exceeding ±10℃ or a power supply voltage fluctuation exceeding ±5%, the configuration parameter optimization step is triggered to be re-executed, and the newly generated parameter set is written to the corresponding position in the stray avoidance configuration table through the write protection release mechanism, thereby realizing online adaptive updates of the configuration table.

[0028] The system also includes a multi-mode compatibility step, whereby the spurious emission avoidance configuration table is divided into multiple sub-tables, corresponding to low-power mode, high-speed switching mode, and high-purity mode, respectively. Each sub-table employs a different objective function during the parameter optimization phase: high-purity mode prioritizes minimizing spurious power, high-speed switching mode prioritizes shortening lock-in time, and low-power mode aims to reduce Σ-Δ modulator power consumption. During table lookup, the appropriate sub-table is selected based on the current system operating mode.

[0029] In practical applications, this invention includes a frequency synthesis optimization control system deployed in a communication base station or radar radio frequency front-end, such as... Figure 3 As shown, the system includes a spurious sensitive area modeling module, a configuration parameter optimization module, a spurious avoidance configuration table construction module, a target frequency parsing module, a table lookup and parameter loading module, and a loop dynamic configuration module, which are connected in sequence and work together. After receiving external frequency commands, the target frequency parsing module transmits the parsed VCO frequency to the table lookup and parameter loading module; the latter reads parameters from non-volatile memory and writes them to the frequency synthesizer register; the loop dynamic configuration module performs hardware reconfiguration and feeds back the stability status; the entire process is scheduled by the main control microprocessor and implemented through a software platform. The software platform adopts a state machine architecture design, and the modules communicate with each other through shared memory and interrupt signals to ensure the real-time performance and reliability of configuration switching.

[0030] Parameter Example: The frequency synthesis integer boundary spurious optimization system described in this invention is deployed in the radio frequency transceiver unit of a 5G millimeter-wave communication base station, such as... Figure 1 As shown, the system coordinates the operation of various functional modules through a main control microprocessor. When the base station needs to switch to the downlink channel with a center frequency of 28.35 GHz, the external baseband unit sends a target output frequency command to the frequency synthesizer main control unit. The target frequency analysis module is based on the phase-locked loop frequency synthesis formula. (where the output frequency division ratio is) Calculate the corresponding VCO operating frequency. Subsequently, the module queries the spurious sensitive region mapping map pre-stored in non-volatile memory and finds that 113.4 GHz falls within the first-order sensitive region marked by the first-order boundary determination step. This region corresponds to the phase detection frequency. time scope.

[0031] The table lookup and parameter loading module then retrieves the spurious emission avoidance configuration table using 113.4GHz as the keyword. The spurious emission avoidance configuration table is shown below:

[0032] Since the configuration table only stores two neighboring frequency points, 113.3GHz and 113.5GHz, the module performs a neighboring frequency point search step, reading the corresponding parameters for both: the 113.3GHz item contains... Loop bandwidth 350 kHz, Σ-Δ order 3, noise shaping factor [0.75, 0.25]; the 113.5 GHz term includes... Loop bandwidth 380kHz, Σ-Δ order 3, noise shaping factor [0.78, 0.22]. In the linear interpolation step, the module calculates the intermediate parameters corresponding to 113.4GHz proportionally: The loop bandwidth is 365 kHz, and the noise shaping factor is [0.765, 0.235].

[0033] The above parameters are written to the internal register group of the frequency synthesizer via the SPI bus. The loop dynamic configuration module adjusts the operating frequency of the phase detector to 56.5MHz accordingly, and updates the programmable RC network in the loop filter through the digital control interface to match its zero and pole positions to the 365kHz bandwidth requirement. At the same time, the feedback coefficient of the Σ-Δ modulator is configured, and the third-order noise shaping structure is enabled. In the phase margin detection step, the built-in Bode analysis unit injects a small-amplitude disturbance signal into the phase detector. By measuring the phase shift at the loop gain crossover frequency, the current phase margin is estimated to be 52°, which is higher than the safety threshold of 45°. Therefore, the configuration is confirmed to be effective. The lock-in time monitoring unit records that the time from parameter loading to VCO output stabilization is 85μs, which does not exceed the upper limit of 100μs. The system normally enters the high-purity working mode.

[0034] In this configuration, the first-order integer boundary spurious power originally located at ±600kHz of the carrier is... 48dBc dropped to 63dBc, lower than The preset threshold of 60dBc enables active avoidance of integer boundary spurious signals. The principle behind this is that by adjusting the phase detection frequency from the default 60MHz to 56.5MHz, [the system achieves this]. No longer satisfied Critical condition (at this time) Offset This avoids periodic current mismatch in the phase detector charge pump during the fractional frequency division switching cycle (1%), thus cutting off the main excitation source of integer boundary spurious noise. At the same time, the third-order Σ-Δ modulator, in conjunction with optimized noise shaping coefficients, further pushes the quantization noise energy to the high-frequency end, suppressing the accumulation of second-order modulation sideband components in the near-carrier region.

[0035] The base station subsequently triggered a configuration table update mechanism due to a 12°C increase in ambient temperature. The temperature sensor transmitted the signal to the main control microprocessor, which then initiated a configuration parameter optimization process, re-traversing the frequency range around 113.4 GHz. The combination of 54MHz to 59MHz was measured by a spectrum analyzer to generate a new optimal parameter set. The updated data was then written to the non-volatile memory at the storage address corresponding to 113.4GHz through a write protection release circuit to ensure that the system maintains spurious suppression performance under temperature drift conditions.

[0036] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A frequency synthesis integer boundary spurious optimization method based on table lookup, characterized in that: Includes the following steps: The spurious sensitive region modeling steps are based on the fractional frequency division architecture of the phase-locked loop, analyzing the generation mechanism of integer boundary spurious spurs, determining the mathematical relationship between the output frequency of the voltage-controlled oscillator, the phase detection frequency, and the integer frequency division ratio, identifying the critical frequency range within the tuning range that leads to a significant increase in the first-order or second-order integer boundary spurious energy, and marking these ranges as spurious sensitive regions. The configuration parameter optimization steps involve, based on each discrete frequency point within the tuning range, using an electromagnetic simulation platform or hardware-in-the-loop test system, traversing different combinations of phase detection frequencies, loop filter bandwidths, modulator orders, and noise transfer function coefficients, measuring the integer boundary spurious power level of the corresponding output signal, and selecting the optimal parameter set that makes the spurious power lower than the preset threshold. The steps for constructing the spurious avoidance configuration table are as follows: the tuning range is divided into multiple discrete frequency bands, each frequency band is associated with its corresponding optimal parameter set, and a mapping table is established with the target frequency as the index and the optimal parameter set as the value. The target frequency analysis step involves receiving the target output frequency command from an external input, deducing the corresponding operating frequency based on the frequency synthesis formula of the phase-locked loop, and determining whether the frequency falls into any spurious sensitive region. In the table lookup and parameter loading steps, if the operating frequency falls within the spurious sensitive region, the spurious avoidance configuration table is queried using that frequency as the key, the corresponding optimal parameter set is read, and the phase detection frequency, loop bandwidth, and modulator configuration parameters are written into the corresponding registers of the frequency synthesizer; if it does not fall within the spurious sensitive region, the default configuration parameters are used.

2. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 1, characterized in that: The stray sensitive region modeling step includes a boundary frequency calculation strategy, which includes a first-order boundary determination step and a second-order boundary determination step. The first-order boundary determination step includes a first-order formula: ,in It is an integer frequency division ratio. This refers to the output frequency of the voltage-controlled oscillator. For phase detection frequency, The frequency offset is defined as the output frequency range of the voltage-controlled oscillator that meets this condition when the frequency offset approaches zero. This range is then marked as the first-order sensitive region. The second-order boundary determination step includes a second-order formula: ,in and All are integers, and If the value is greater than 1, and the output frequency of the voltage-controlled oscillator satisfies the second-order formula, then the neighborhood of such frequencies is marked as the second-order sensitive region.

3. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 1 or 2, characterized in that: The configuration parameter optimization step includes a spurious power evaluation strategy, which includes a spectrum scanning step and a threshold comparison step. The spectrum scanning step involves controlling the spectrum analyzer to perform a high-resolution scan of the phase-locked loop output signal at a fixed target output frequency, and extracting the power of spurious components within a preset range from the carrier. The threshold comparison step compares the extracted spurious power with a preset spurious suppression threshold. If the power is lower than the threshold, the current parameter combination is recorded as a candidate optimal solution.

4. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 3, characterized in that: The spurious avoidance configuration table construction step includes a frequency band partitioning strategy, which includes a uniform partitioning step and an adaptive refinement step. The uniform division step divides the entire tuning range of the voltage-controlled oscillator into an initial frequency band grid with a fixed step size. The adaptive refinement step uses a smaller partitioning step size than the initial frequency band grid within the spurious sensitive region to ensure that each sensitive sub-region is independently mapped to a dedicated set of optimized parameters.

5. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 4, characterized in that: The table lookup and parameter loading steps include an interpolation compensation strategy, which includes a neighboring frequency point retrieval step and a linear interpolation step. In the neighboring frequency retrieval step, when the target frequency does not precisely match the index in the table, the two stored frequencies that are adjacent to it are retrieved. The linear interpolation step involves linearly interpolating the parameter values ​​corresponding to two adjacent frequency points to generate an intermediate parameter set suitable for the current target frequency.

6. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 5, characterized in that: The loop dynamic configuration step includes a stability verification strategy, which includes a phase margin detection step and a lock-in time monitoring step. The phase margin detection step, after parameter loading, estimates the phase margin of the current loop through the built-in loop diagnosis module. If it is lower than the safety threshold, it reverts to the previous stable configuration. The lock time monitoring step records the time from parameter switching to frequency lock. If the time exceeds the preset upper limit, a configuration anomaly alarm is triggered.

7. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 1, characterized in that: It also includes a configuration table update step. During system operation, if the ambient temperature change exceeds the preset value or the power supply voltage fluctuation exceeds the preset rate, the configuration parameter optimization step is triggered to be re-executed, and the newly generated parameter set is written to the corresponding position in the stray avoidance configuration table.

8. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 6, characterized in that: It also includes a multi-mode compatibility step, wherein the stray avoidance configuration table is divided into multiple sub-tables, which correspond to low power mode, high speed switching mode and high purity mode respectively. Each sub-table adopts a different objective function in the parameter optimization stage, and the corresponding sub-table is selected for querying according to the current system working mode when looking up the table.

9. The frequency synthesis integer boundary spurious optimization method based on table lookup as described in claim 8, characterized in that: The frequency synthesizer includes a phase detector, a loop filter, a modulator, and a voltage-controlled oscillator, and the modules are interconnected through an internal bus.

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