A digital frequency discriminator and all-digital phase-locked loop

Abstract

This invention provides a digital frequency discriminator and a fully digital phase-locked loop (PLL), comprising: a rising edge sampling module that samples the rising edges of a reference signal and a feedback signal to obtain a first-level output signal; a falling edge sampling module that, under the control of the first-level output signal, samples the falling edges of the reference signal and the feedback signal to obtain a second-level output signal; and a latch output module that latches and samples the second-level output signal to output a digital control signal. This digital frequency discriminator has a large dead-time range. When applied to a fully digital PLL, in conjunction with a time-to-digital converter (TD-SCDMA), the TD-SCDMA operates when the phase difference between the reference signal and the feedback signal is within the dead-time range; otherwise, the digital frequency discriminator operates. This ensures that the fully digital PLL does not lose lock while effectively controlling the loop gain through the TD-SCDMA, solving the problems of easy lock-up and unstable loop gain in existing fully digital PLLs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a digital frequency discriminator and an all-digital phase-locked loop. Background Technology

[0002] Frequency sources are a crucial component of communication systems, typically generated by phase-locked loops (PLLs). Historically, PLL structures were implemented using analog circuits, specifically transistor-based type-two charge pump PLLs. These PLLs contained an internal charge pump (CP) circuit, whose power supply voltage was often relatively high, resulting in a wide output voltage range and thus ensuring a broad output frequency range. However, with advancements in integrated circuit technology, transistor gate lengths and gate oxide thicknesses have decreased, leading to lower transistor power supply voltages. Consequently, the power supply voltage of the designed CP circuits has also decreased, resulting in a narrower output frequency range for the PLLs.

[0003] To address this issue, researchers proposed an all-digital phase-locked loop (ADPLL). In an ADPLL, the voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO), and the output frequency range of the PLL is determined by the input digital control bits. In other words, the more digital control bits, the larger the output frequency range of the PLL, thus avoiding the influence of power supply voltage on the PLL's output frequency range. Simultaneously, in an ADPLL, the phase-frequency detector (PFD) and charge pump (CP) are replaced by a time-to-digital converter (TDC) or a digital phase-frequency detector (DPFD). However, existing TDCs only perform phase detection and not frequency detection, while existing DPFDs, although capable of both, suffer from device noise in their phase detection gain formula. This device noise is highly uncontrollable, leading to unstable loop gain and making the ADPLL prone to lock-out problems, thus affecting its performance. Summary of the Invention

[0004] The purpose of this invention is to provide a digital frequency discriminator and an all-digital phase-locked loop (PLL) to at least solve the problems of easy lockout and unstable loop gain of existing all-digital PLLs.

[0005] To address the aforementioned technical problems, this invention provides a digital frequency discriminator, comprising a rising edge sampling module, a falling edge sampling module, and a latch output module connected in sequence. The rising edge sampling module samples the rising edge of the reference signal and the rising edge of the feedback signal to obtain a first-level output signal. The falling edge sampling module, under the control of the first-level output signal, samples the falling edge of the reference signal and the falling edge of the feedback signal to obtain a second-level output signal. The latch output module latches and samples the second-level output signal to output a digital control signal.

[0006] Optionally, in the digital frequency discriminator, the rising edge sampling module includes a first flip-flop, a second flip-flop, and a logic circuit; the first flip-flop receives an enable signal at its input terminal, a reference signal at its clock terminal, a reset terminal connected to the output terminal of the logic circuit, and outputs a first upsampled signal; the second flip-flop receives an enable signal at its input terminal, a feedback signal at its clock terminal, a reset terminal connected to the output terminal of the logic circuit, and outputs a second upsampled signal; the logic circuit includes a first NAND gate and a NOT gate, the two input terminals of the first NAND gate respectively receive the first upsampled signal and the second upsampled signal, the input terminal of the NOT gate is connected to the output terminal of the first NAND gate, and the output terminal of the NOT gate is the output terminal of the logic circuit; the first-level output signal includes the first upsampled signal and the second upsampled signal.

[0007] Optionally, in the digital frequency discriminator, the falling edge sampling module includes a third flip-flop and a fourth flip-flop; the input terminal of the third flip-flop receives a first upsampled signal, the clock terminal receives an inverted reference signal, and the output terminal outputs a first downsampled signal; the input terminal of the fourth flip-flop receives a second upsampled signal, the clock terminal receives an inverted feedback signal, and the output terminal outputs a second downsampled signal; the secondary output signal includes the first downsampled signal and the second downsampled signal.

[0008] Optionally, in the digital frequency discriminator, the latch output module includes a latch, a fifth flip-flop, and a sixth flip-flop; the latch includes a second NAND gate and a third NAND gate; one input of the second NAND gate receives a first downsampled signal, and the other input is connected to the output of the third NAND gate; one input of the third NAND gate receives a second downsampled signal, and the other input is connected to the output of the second NAND gate; the input of the fifth flip-flop is connected to the output of the second NAND gate, the clock input is an inverted feedback signal, and the output output is a first control signal; the input of the sixth flip-flop is connected to the output of the third NAND gate, the clock input is an inverted feedback signal, and the output output is a second control signal; the digital control signal includes a first control signal and a second control signal.

[0009] Optionally, in the digital frequency discriminator, the first flip-flop, the second flip-flop, the third flip-flop, the fourth flip-flop, the fifth flip-flop, and the sixth flip-flop are all D flip-flops.

[0010] Optionally, in the digital frequency discriminator, when the phase difference between the reference signal and the feedback signal is within the range of -π to π, the digital frequency discriminator outputs 0; when the phase difference between the reference signal and the feedback signal is outside the range of -π to π, the digital frequency discriminator outputs 1.

[0011] To address the aforementioned technical problems, the present invention also provides an all-digital phase-locked loop, including the digital frequency discriminator as described in any of the preceding claims.

[0012] Optionally, in the all-digital phase-locked loop, the all-digital phase-locked loop further includes a first time-to-digital converter, a second time-to-digital converter, and a digitally controlled oscillator; the two input terminals of the digital frequency discriminator respectively input a reference signal and a feedback signal, and the output terminal outputs a digital control signal; the two input terminals of the first time-to-digital converter respectively input a reference signal and a feedback signal, and the output terminal outputs a first time conversion signal; the two input terminals of the second time-to-digital converter respectively input a digital control signal and a first time conversion signal, and the output terminal outputs a second time conversion signal; the input terminal of the digitally controlled oscillator inputs the second time conversion signal, and the output terminal outputs a frequency signal.

[0013] Optionally, in the all-digital phase-locked loop, when the phase difference between the reference signal and the feedback signal is within the range of -π to π, the digital frequency discriminator outputs 0, and the second time-to-digital converter is controlled by the first time-to-digital converter; when the phase difference between the reference signal and the feedback signal is outside the range of -π to π, the digital frequency discriminator outputs 1, and the second time-to-digital converter is controlled by the digital frequency discriminator.

[0014] Optionally, in the all-digital phase-locked loop, the all-digital phase-locked loop further includes a frequency divider, the frequency divider inputting a frequency signal and outputting a feedback signal.

[0015] The digital frequency discriminator and all-digital phase-locked loop (PLL) provided by this invention include a rising edge sampling module, a falling edge sampling module, and a latch output module connected in sequence. The rising edge sampling module samples the rising edges of the reference signal and the feedback signal to obtain a first-level output signal. The falling edge sampling module, under the control of the first-level output signal, samples the falling edges of the reference signal and the feedback signal to obtain a second-level output signal. The latch output module latches and samples the second-level output signal to output a digital control signal. The digital frequency discriminator provided by this invention has a large dead-time range. When applied to an all-digital PLL, in conjunction with a time-to-digital converter (TD-SCDMA), the TD-SCDMA operates when the phase difference between the reference signal and the feedback signal is within the dead-time range, and the digital frequency discriminator operates when the phase difference is outside the dead-time range. This ensures that the all-digital PLL does not lose lock while effectively controlling the loop gain of the all-digital PLL through the time-to-digital converter, solving the problems of easy lock-up and unstable loop gain in existing all-digital PLLs. Attached Figure Description

[0016] Figure 1This is a block diagram of the digital frequency discriminator provided in this embodiment; Figure 2 This is a circuit diagram of the digital frequency discriminator provided in this embodiment; Figure 3 This is a structural block diagram of the all-digital phase-locked loop provided in this embodiment; Figure 4 This is a block diagram of the all-digital phase-locked loop with a frequency divider provided in this embodiment. Detailed Implementation

[0017] The digital frequency discriminator and all-digital phase-locked loop proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0018] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] This embodiment provides a digital frequency discriminator, such as Figure 1 As shown, it includes a rising edge sampling module, a falling edge sampling module, and a latch output module connected in sequence. The rising edge sampling module is used to sample the rising edge of the reference signal and the rising edge of the feedback signal to obtain a first-level output signal. The falling edge sampling module is used to sample the falling edge of the reference signal and the falling edge of the feedback signal under the control of the first-level output signal to obtain a second-level output signal. The latch output module is used to latch and sample the second-level output signal to output a digital control signal.

[0020] The digital frequency discriminator provided in this embodiment has a large dead zone range. When applied to a fully digital phase-locked loop (PLL), it works in conjunction with a time-to-digital converter (TD-C). When the phase difference between the reference signal and the feedback signal is within the dead zone range, the TD-C operates; when the phase difference is outside the dead zone range, the digital frequency discriminator operates. This ensures that the fully digital PLL does not lose lock while effectively controlling the loop gain of the PLL through the time-to-digital converter. This solves the problems of easy lock-out and unstable loop gain in existing fully digital PLLs.

[0021] Specifically, in this embodiment, such as Figure 2 As shown, the rising edge sampling module includes a first flip-flop DFF1, a second flip-flop DFF2, and a logic circuit. The first flip-flop DFF1 receives an enable signal at its input D, a reference signal REF at its clock input CLK, and a reset input RST connected to the output of the logic circuit. Its output Q outputs a first upsampled signal. The second flip-flop DFF2 receives an enable signal at its input D, a feedback signal DIV at its clock input CLK, and a reset input RST connected to the output of the logic circuit. Its output Q outputs a second upsampled signal. The logic circuit includes a first NAND gate NAND1 and a NOT gate INV. The two inputs of the first NAND gate NAND1 receive the first and second upsampled signals, respectively. The input of the NOT gate INV is connected to the output of the first NAND gate NAND1, and the output of the NOT gate INV is the output of the logic circuit. The first-level output signal includes the first upsampled signal and the second upsampled signal.

[0022] In this embodiment, the enable signal input to the input terminals of the first flip-flop DFF1 and the second flip-flop DFF2 is 1, that is, a continuous high-level signal, thereby ensuring that the first flip-flop DFF1 and the second flip-flop DFF2 can work continuously.

[0023] In practical applications, the rising edge sampling module provided in this embodiment can be replaced by an existing traditional frequency and phase detector (PFD).

[0024] The working principle of the rising edge sampling module provided in this embodiment is roughly as follows: by comparing the phase difference between the reference signal REF input to the first flip-flop DFF1 and the feedback signal DIV input to the second flip-flop DFF2, corresponding first upsampled signals and second upsampled signals are generated. Specifically, if the rising edge of the reference signal REF arrives first, the first upsampled signal changes from 0 to 1; after time t1, the rising edge of the feedback signal DIV also arrives, at which point the second upsampled signal changes from 0 to 1; after the first upsampled signal and the second upsampled signal have a delay time τ between the first NAND gate NAND1 and the NOT gate INV in the logic circuit, the first flip-flop DFF1 and the second flip-flop DFF2 are reset, and the output returns to 0.

[0025] Furthermore, in this embodiment, as Figure 2 As shown, the falling edge sampling module includes a third flip-flop DFF3 and a fourth flip-flop DFF4; the input terminal D of the third flip-flop DFF3 receives a first upsampled signal, the clock terminal CLK receives an inverted reference signal REF, and the output terminal Q outputs a first downsampled signal; the input terminal D of the fourth flip-flop DFF4 receives a second upsampled signal, the clock terminal CLK receives an inverted feedback signal DIV, and the output terminal Q outputs a second downsampled signal; the secondary output signal includes the first downsampled signal and the second downsampled signal.

[0026] The falling edge sampling module provided in this embodiment works roughly as follows: The inverted reference signal REF is input to the clock input CLK of the third flip-flop DFF3, which is equivalent to sampling the falling edge of the reference signal REF. Similarly, the inverted feedback signal DIV is input to the clock input CLK of the fourth flip-flop DFF4, which is equivalent to sampling the falling edge of the feedback signal DIV. Thus, under the control of the first-level output signal, the outputs of the third flip-flop DFF3 and the fourth flip-flop DFF4 will only output 1 when the phase difference between the reference signal REF and the feedback signal DIV is π; otherwise, they will output 0.

[0027] Furthermore, in this embodiment, as Figure 2 As shown, the latch output module includes a latch, a fifth flip-flop, and a sixth flip-flop; the latch includes a second NAND gate NAND2 and a third NAND gate NAND3; one input of the second NAND gate NAND2 receives a first downsampled signal, and the other input is connected to the output of the third NAND gate NAND3; one input of the third NAND gate NAND3 receives a second downsampled signal, and the other input is connected to the output of the second NAND gate NAND2; the input D of the fifth flip-flop DFF5 is connected to the output of the second NAND gate NAND2, the clock input CLK receives the inverted feedback signal DIV, and the output QN outputs the first control signal UP; the input D of the sixth flip-flop DFF6 is connected to the output of the third NAND gate NAND3, the clock input CLK receives the inverted feedback signal DIV, and the output QN outputs the second control signal DN; the digital control signals include the first control signal UP and the second control signal DN.

[0028] The working principle of the latch output module provided in this embodiment is roughly as follows: the secondary output signal is latched by the latch, and the feedback signal DIV is sampled by the fifth flip-flop DFF5 and the sixth flip-flop DFF6 under the output control of the latch, and finally the digital control signal is output.

[0029] Thus, by sequentially sampling the rising edge and falling edge of the reference signal REF and the feedback signal DIV using two stages of flip-flops, the phase difference between the reference signal REF and the feedback signal DIV is kept within the range of -π to π, meaning the dead zone of the digital frequency discriminator is -π to π. Compared to existing digital frequency discriminators, its dead zone is effectively expanded, which is beneficial for expanding the output frequency range of the phase-locked loop.

[0030] In practical applications, the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are all D flip-flops. The output terminals of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3, and the fourth flip-flop DFF4 are selected as positive output terminals, while the output terminals of the fifth flip-flop DFF5 and the sixth flip-flop DFF6 are selected as inverted output terminals.

[0031] This embodiment also provides an all-digital phase-locked loop, including the digital frequency discriminator (DFD) as described above.

[0032] Specifically, in this embodiment, such as Figure 3 As shown, the all-digital phase-locked loop further includes a first time-to-digital converter (TDC1), a second time-to-digital converter (TDC2), and a digitally controlled oscillator (DCO). The two input terminals of the digital frequency discriminator (DFD) are respectively input to a reference signal REF and a feedback signal DIV, and the output terminal outputs a digital control signal. The two input terminals of the first time-to-digital converter (TDC1) are respectively input to the reference signal REF and the feedback signal DIV, and the output terminal outputs a first time conversion signal. The two input terminals of the second time-to-digital converter (TDC2) are respectively input to the digital control signal and the first time conversion signal, and the output terminal outputs a second time conversion signal. The input terminal of the digitally controlled oscillator (DCO) receives the second time conversion signal, and the output terminal outputs a frequency signal OUT.

[0033] The fully digital phase-locked loop provided in this embodiment works roughly as follows: When the phase difference between the reference signal REF and the feedback signal DIV is within the -π to π interval (i.e., the dead zone range of the digital frequency discriminator), the output of the digital frequency discriminator DFD is 0, and the second time-to-digital converter TDC2 is controlled by the first time-to-digital converter TDC1; when the phase difference between the reference signal REF and the feedback signal DIV is outside the -π to π interval, the output of the digital frequency discriminator DFD is not 0, specifically 1 for the digital frequency discriminator, and the second time-to-digital converter TDC2 is controlled by the digital frequency discriminator DFD.

[0034] The all-digital phase-locked loop (PLL) using the digital frequency discriminator provided in this embodiment has a large dead zone. When applied to the all-digital PLL, it works in conjunction with a time-to-digital converter. When the phase difference between the reference signal and the feedback signal is within the dead zone, the time-to-digital converter operates; when the phase difference is outside the dead zone, the digital frequency discriminator operates. This ensures that the all-digital PLL does not lose lock while effectively controlling the loop gain of the all-digital PLL through the time-to-digital converter. This solves the problems of easy lock-out and unstable loop gain in existing all-digital PLLs.

[0035] Preferably, in this embodiment, such as Figure 4 As shown, the all-digital phase-locked loop also includes a frequency divider. The frequency divider receives the frequency signal OUT at its input and outputs a feedback signal DIV at its output. Thus, the operating state of the all-digital phase-locked loop is affected by its output frequency signal OUT, enabling more flexible and precise timely control of the frequency signal OUT.

[0036] In practical applications, the first time-to-digital converter (TDC1) and the second time-to-digital converter (TDC2) can be existing conventional time-to-digital converters (TDC), the digital control oscillator (DCO) can be existing conventional digital control oscillator (DCO), and the frequency divider (FD) can be existing conventional frequency divider (FD). This minimizes the development complexity and cost of the all-digital phase-locked loop (PLL) and allows for modifications and adjustments to existing all-digital PLLs to obtain the all-digital PLL provided in this embodiment.

[0037] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0038] The digital frequency discriminator and all-digital phase-locked loop (PLL) provided in this embodiment include a rising edge sampling module, a falling edge sampling module, and a latch output module connected in sequence. The rising edge sampling module samples the rising edge of the reference signal and the rising edge of the feedback signal to obtain a first-level output signal. The falling edge sampling module samples the falling edge of the reference signal and the falling edge of the feedback signal under the control of the first-level output signal to obtain a second-level output signal. The latch output module latches and samples the second-level output signal to output a digital control signal. The digital frequency discriminator provided by this invention has a large dead-time range. When applied to an all-digital PLL, in conjunction with a time-to-digital converter (TD-SCDMA), the TD-SCDMA operates when the phase difference between the reference signal and the feedback signal is within the dead-time range, and the digital frequency discriminator operates when the phase difference is outside the dead-time range. This ensures that the all-digital PLL does not lose lock while effectively controlling the loop gain of the all-digital PLL through the time-to-digital converter, solving the problems of easy lock-up and unstable loop gain in existing all-digital PLLs.

[0039] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A digital frequency discriminator characterized by, It includes a rising edge sampling module, a falling edge sampling module, and a latch output module connected in sequence; the rising edge sampling module is used to sample the rising edge of the reference signal and the rising edge of the feedback signal to obtain a first-level output signal; the falling edge sampling module is used to sample the falling edge of the reference signal and the falling edge of the feedback signal under the control of the first-level output signal to obtain a second-level output signal; the latch output module is used to latch and sample the second-level output signal to output a digital control signal.

2. The digital frequency discriminator of claim 1, wherein, The rising edge sampling module includes a first flip-flop, a second flip-flop, and a logic circuit; the input terminal of the first flip-flop receives an enable signal, the clock terminal receives a reference signal, the reset terminal is connected to the output terminal of the logic circuit, and the output terminal outputs a first upsampled signal. The second flip-flop receives an enable signal at its input terminal, a feedback signal at its clock terminal, and a reset terminal connected to the output terminal of the logic circuit. The output terminal outputs a second upsampled signal. The logic circuit includes a first NAND gate and a NOT gate. The two input terminals of the first NAND gate receive the first upsampled signal and the second upsampled signal, respectively. The input terminal of the NOT gate is connected to the output terminal of the first NAND gate, and the output terminal of the NOT gate is the output terminal of the logic circuit. The first-level output signal includes the first upsampled signal and the second upsampled signal.

3. The digital frequency discriminator of claim 2, wherein, The falling edge sampling module includes a third flip-flop and a fourth flip-flop; the third flip-flop receives a first upsampled signal at its input terminal, an inverted reference signal at its clock terminal, and outputs a first downsampled signal at its output terminal; the fourth flip-flop receives a second upsampled signal at its input terminal, an inverted feedback signal at its clock terminal, and outputs a second downsampled signal at its output terminal; the secondary output signal includes the first downsampled signal and the second downsampled signal.

4. The digital frequency discriminator of claim 3, wherein, The latch output module includes a latch, a fifth flip-flop, and a sixth flip-flop; the latch includes a second NAND gate and a third NAND gate; one input of the second NAND gate receives a first downsampled signal, and the other input is connected to the output of the third NAND gate; one input of the third NAND gate receives a second downsampled signal, and the other input is connected to the output of the second NAND gate; the input of the fifth flip-flop is connected to the output of the second NAND gate, the clock input is the inverted feedback signal, and the output output is a first control signal; the input of the sixth flip-flop is connected to the output of the third NAND gate, the clock input is the inverted feedback signal, and the output output is a second control signal; the digital control signal includes a first control signal and a second control signal.

5. The digital frequency discriminator of claim 4, wherein, The first flip-flop, the second flip-flop, the third flip-flop, the fourth flip-flop, the fifth flip-flop, and the sixth flip-flop are all D flip-flops.

6. The digital frequency discriminator of claim 1, wherein, When the phase difference between the reference signal and the feedback signal is within the range of -π to π, the digital frequency discriminator outputs 0; when the phase difference between the reference signal and the feedback signal is outside the range of -π to π, the digital frequency discriminator outputs 1.

7. An all-digital phase-locked loop, characterized by Includes the digital frequency discriminator as described in any one of claims 1 to 6.

8. The all-digital phase locked loop of claim 7, wherein, The all-digital phase-locked loop further includes a first time-to-digital converter, a second time-to-digital converter, and a digitally controlled oscillator; the two input terminals of the digital frequency discriminator respectively input a reference signal and a feedback signal, and the output terminal outputs a digital control signal; the two input terminals of the first time-to-digital converter respectively input a reference signal and a feedback signal, and the output terminal outputs a first time conversion signal; the two input terminals of the second time-to-digital converter respectively input a digital control signal and a first time conversion signal, and the output terminal outputs a second time conversion signal; the input terminal of the digitally controlled oscillator inputs the second time conversion signal, and the output terminal outputs a frequency signal.

9. The all-digital phase-locked loop according to claim 8, characterized in that, When the phase difference between the reference signal and the feedback signal is within the range of -π to π, the digital frequency discriminator outputs 0, and the second time-to-digital converter is controlled by the first time-to-digital converter; when the phase difference between the reference signal and the feedback signal is outside the range of -π to π, the digital frequency discriminator outputs 1, and the second time-to-digital converter is controlled by the digital frequency discriminator.

10. The all-digital phase-locked loop according to claim 8, characterized in that, The all-digital phase-locked loop also includes a frequency divider, which receives a frequency signal at its input and outputs a feedback signal at its output.

Images