Communication bus matching resistance automatic matching method and device based on spread spectrum detection

Abstract

This invention relates to the field of electronic communication technology, and in particular to an automatic matching method and apparatus for communication bus matching resistors based on spread spectrum detection. This invention achieves automatic matching of the matching resistor through spread spectrum detection, eliminating the need for manual experience in resistor configuration and solving the core problem of poor adaptability of static matching schemes. This invention can automatically sense the link status, accurately extract signal parameters and calculate the terminal impedance through cross-correlation calculations, and dynamically adjust the matching resistor, effectively suppressing problems such as signal reflection and waveform distortion, thus improving the reliability of bus communication. Simultaneously, the parallel processing capabilities of an FPGA ensure the real-time performance of the matching process, adapting to complex scenarios with dynamically changing link parameters, and significantly reducing manual debugging and maintenance costs.

Description

Technical Field

[0001] This invention relates to the field of electronic communication technology, and in particular to an automatic matching method and apparatus for communication bus matching resistors based on spread spectrum detection. Background Technology

[0002] Communication buses are real-time serial communication protocols and physical layer technologies widely used in industrial control, automotive electronics, and automation. They typically employ differential signal transmission, exchange data via twisted-pair cables, and possess strong resistance to electromagnetic interference and long transmission distances, making them one of the most widely used fieldbuses today.

[0003] In current applications using various communication buses such as RS422 (Recommended Standard 422), RS485 (Recommended Standard 485), and CAN (Controller Area Network), multiple devices are interconnected via differential buses, resulting in dense wiring and complex electromagnetic environments. In practical applications, due to variations in bus topology, cable length, or improper termination matching, signals are prone to reflection at impedance discontinuities during transmission. This reflection can lead to waveform distortion, ringing, or overshoot, resulting in data errors, communication delays, and in severe cases, communication interruptions or even transceiver damage. The impedance matching problem is particularly prominent in high-speed communication or long-distance transmission scenarios, directly impacting the reliability and stability of the system.

[0004] Traditional communication bus systems rely on manual experience to configure a 120Ω terminating resistor, ensuring the load impedance equals the characteristic impedance of the transmission line to eliminate signal reflection. This is a simple, low-cost, experience-based static matching scheme that performs well in systems with stable structures and controllable environments. However, as industrial systems evolve towards intelligence, modularity, and scalability, their lack of sensing and adaptive capabilities has become increasingly apparent. They can no longer meet the demands of complex scenarios such as high reliability, long distances, and dynamic topologies. Any omissions, errors, or link changes can trigger signal reflections, waveform distortion, and communication errors, significantly impacting bus communication quality.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] The technical problem to be solved by this invention is that the static matching scheme of the matching resistor of the traditional communication bus lacks sensing and adaptive capabilities, and is prone to problems such as signal reflection in environments with uncertain link parameters and dynamic changes, thus failing to guarantee the quality of bus communication.

[0007] The present invention adopts the following technical solution: Firstly, a method for automatic matching of matching resistors in a communication bus based on spread spectrum detection is provided, including: A pseudo-random sequence is generated as a detection signal, the detection signal is sent to the communication bus, and the reflected echo signal of the detection signal on the communication bus is collected; Perform cross-correlation calculation on the detected signal and the reflected echo signal, and extract the correlation peak parameters; The cable link length and termination impedance are calculated based on the relevant peak parameters to determine the impedance matching status. If the impedance is not matched, the resistance value of the termination matching resistor is dynamically adjusted to achieve automatic impedance matching.

[0008] Preferably, the generation of the pseudo-random sequence as a probe signal specifically includes: A linear feedback shift register is used to generate an m-sequence as the pseudo-random sequence within a Field Programmable Gate Array (FPGA), including... Generate an m-sequence from the primitive polynomial, with the initial state set to 1111 and the period of the m-sequence being... , where n is the number of stages of the linear feedback shift register; The m-sequence uses the 50MHz~60MHz external clock of the FPGA as the clock source, and outputs the chip at the rising edge of the clock to achieve a nanosecond-level chip width.

[0009] Preferably, the step of sending the detection signal to the communication bus and collecting the reflected echo signal of the detection signal on the communication bus specifically includes: The pseudo-random sequence is converted into a differential signal, which is then sent to the communication bus after being isolated from DC by an AC capacitor. The collected differential reflected echo is isolated from DC by an AC capacitor and processed by differential amplification. It is then sampled by an AD sampling chip and transmitted to the FPGA via an LVDS signal to obtain the reflected echo signal.

[0010] Preferably, the calculation formula for the cross-correlation operation is: ; in, It is a pseudo-random sequence. To reflect the echo signal, For time offset, For relevant values, The length of the pseudo-random sequence; The main peak position of relevant peaks was extracted using a pipelined step-by-step comparison method. Secondary peak position Main peak amplitude and the amplitude of the secondary peak .

[0011] Preferably, the method for calculating the cable link length includes: Based on the location of the main peak and secondary peak position Calculate time delay , ; Calculate cable link length based on time delay , ; in, The sampling period is Let v be the speed of signal propagation in the cable link, v≈0.66c~0.8c, c=3× m / s.

[0012] Preferably, the method for calculating the terminating impedance includes: Based on the amplitude of the main peak and secondary peak amplitude The reflection coefficient Γ is calculated, Γ= ; Calculate the terminal impedance based on the reflection coefficient Γ. , ; in, This refers to the standard impedance characteristic of communication cables.

[0013] Preferably, determining the impedance matching state specifically includes: Calculate the reflection coefficient Γ and determine the cable link length L. Set the reflection coefficient threshold to A%, and divide the short-distance link threshold Lth according to the cable link length L. When L≤Lth and Γ≤A%, or L>Lth and Γ≤A%, it indicates that the matching resistor has been matched; When L≤Lth and Γ>A%, or L>Lth and Γ>A%, it indicates that the matching resistors are mismatched.

[0014] Preferably, the matching resistor The calculation method is as follows: ; in, For the terminating impedance, This refers to the standard impedance characteristic of communication cables.

[0015] Secondly, an automatic matching device for a communication bus matching resistor based on spread spectrum detection is provided. The automatic matching device for a communication bus matching resistor based on spread spectrum detection includes: a processor and a memory for storing processor-executable instructions. The processor is configured to execute the automatic matching method for communication bus matching resistors based on spread spectrum detection.

[0016] Thirdly, a non-volatile computer storage medium is provided, the computer storage medium storing computer-executable instructions, which are executed by one or more processors to perform the automatic matching method for communication bus matching resistors based on spread spectrum detection described in the first aspect.

[0017] Fourthly, a chip is provided, comprising: a processor and an interface for calling and running a computer program stored in a memory, executing the automatic matching method for communication bus matching resistors based on spread spectrum detection as described in the first aspect.

[0018] Fifthly, a computer program product containing instructions is provided, which, when executed on a computer or processor, causes the computer or processor to perform the automatic matching method for communication bus matching resistors based on spread spectrum detection as described in the first aspect.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention performs cross-correlation calculations on the detected signal and the reflected echo signal, extracts the correlation peak parameters, and calculates the cable link length and termination impedance based on the correlation peak parameters to determine the impedance matching status. If the impedance is not matched, the resistance value of the termination matching resistor is dynamically adjusted, thereby achieving automatic impedance matching. Automatic matching of the matching resistor is achieved through spread spectrum detection, eliminating the need for manual experience in resistor configuration and solving the core problem of poor adaptability of static matching schemes. This invention can automatically sense the link status, accurately extract signal parameters and calculate the termination impedance through cross-correlation calculations, and dynamically adjust the matching resistor, effectively suppressing signal reflection, waveform distortion, and other problems, thus improving the reliability of bus communication. Simultaneously, the parallel processing capabilities of the FPGA ensure the real-time performance of the matching process, adapting to complex scenarios with dynamically changing link parameters and significantly reducing manual debugging and maintenance costs. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of an automatic matching system for communication bus matching resistors based on spread spectrum detection, provided in an embodiment of the present invention. Figure 2This is a flowchart illustrating an automatic matching method for communication bus matching resistors based on spread spectrum detection, provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a pseudo-random sequence generation process provided by an embodiment of the present invention; Figure 4 This is a schematic diagram of a process for transmitting a detection signal and receiving a reflected echo signal provided in an embodiment of the present invention; Figure 5 This is a schematic flowchart of a communication bus matching resistor automatic matching method based on spread spectrum detection provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an automatic matching device for a communication bus matching resistor based on spread spectrum detection, provided in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0023] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0024] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0025] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0026] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] Example 1: Before detailing the automatic matching method and apparatus for communication bus matching resistors based on spread spectrum detection proposed in this invention, this embodiment first proposes an automatic matching system for communication bus matching resistors based on spread spectrum detection. In one embodiment, such as... Figure 1 As shown, the system includes: a PN code generation module, a bus transmission module, a bus reception and sampling module, a spread spectrum correlation detection algorithm processing module, an impedance calculation and decision module, a matching resistor control execution module, and a protocol interface and control switching module. The specific connection method is described in [reference needed]. Figure 1 In one embodiment, the protocol interface and control switching module, the PN code generation module, the spread spectrum correlation detection algorithm processing module, the impedance calculation and decision module, and the matching resistor control execution module are all built into the FPGA.

[0028] To address the shortcomings of traditional static matching schemes for communication bus matching resistors, which lack sensing and adaptive capabilities and are prone to signal reflection in environments with uncertain and dynamically changing link parameters, thus failing to guarantee bus communication quality, this embodiment proposes an automatic matching method for communication bus matching resistors based on spread spectrum detection. In one embodiment, such as... Figure 1 and Figure 2 As shown, the method includes: Step 101: Generate a pseudo-random sequence as a probe signal, send the probe signal to the communication bus, and collect the reflected echo signal of the probe signal on the communication bus.

[0029] The communication bus can be RS422, RS485 or CAN.

[0030] In one embodiment, a pseudo-random sequence can be generated as a probe signal by the PN code generation module inside the FPGA. The pseudo-random sequence can be an m-sequence generated based on a linear feedback shift register. In another embodiment, a stable output with a nanosecond-level chip width can be achieved by using a 50MHz clock external to the FPGA as the clock source.

[0031] In one embodiment, the FPGA transmits the generated CMOS level pseudo-random sequence to the bus transmission module, performs level-to-differential signal conversion via a differential signal converter, and after isolating the DC signal through an AC capacitor, sends the probe signal to the communication bus.

[0032] Simultaneously, the control bus receiving sampling module starts the signal acquisition work, and captures the reflected echo signal generated by the probe signal on the communication bus during transmission in real time. In one embodiment, the reflected echo signal is first isolated by AC capacitor coupling and then amplified by fully differential operational amplifier. Subsequently, the high-speed AD sampling chip completes the signal sampling, and the sampled signal is transmitted to the FPGA through LVDS signal to complete the acquisition and full-process preprocessing of the reflected echo signal.

[0033] Step 102: Perform cross-correlation calculation on the detected signal and the reflected echo signal, and extract the relevant peak parameters.

[0034] Specifically, the spread spectrum correlation detection algorithm processing module inside the FPGA retrieves the locally pre-stored pseudo-random sequence of the detection signal and performs high-speed cross-correlation operation on it with the pre-processed reflected echo sampling signal.

[0035] After the cross-correlation operation is completed, a pipelined step-by-step comparison method is used to analyze and filter the results of the cross-correlation operation to accurately extract the relevant peak parameters. In one embodiment, the relevant peak parameters include the position of the main peak, the position of the secondary peak, the amplitude of the main peak, and the amplitude of the secondary peak. After the relevant peak parameters are extracted, the FPGA synchronously transmits all the above relevant peak parameters to the internal impedance calculation and decision module to provide data support for subsequent parameter calculation and matching status judgment.

[0036] Step 103: Calculate the cable link length and termination impedance based on the relevant peak parameters to determine the impedance matching status. If the impedance is not matched, dynamically adjust the resistance value of the termination matching resistor to achieve automatic impedance matching.

[0037] The impedance calculation and decision module inside the FPGA calculates the cable link length based on the received relevant peak parameters and a preset sampling period. At the same time, the impedance calculation and decision module calculates the reflection coefficient based on the extracted main peak amplitude and secondary peak amplitude, and then combines the calculated cable link length to comprehensively judge the impedance matching status of the communication bus. The threshold for judging the reflection coefficient can be set to A.

[0038] In one embodiment, if the reflection coefficient is less than or equal to A%, the communication bus is determined to be in an impedance-matched state, and no adjustment of the terminal matching resistor is required; if the reflection coefficient is greater than A%, it is determined to be an impedance mismatch. At this time, the impedance calculation and decision module further calculates the terminal impedance of the communication bus based on the reflection coefficient, and calculates the matching resistor value adapted to the current bus state based on the terminal impedance and the standard characteristic impedance of the communication cable, wherein the standard characteristic impedance of the communication cable is 120Ω.

[0039] The FPGA then calculates the matching resistor value and transmits it via its internal I2C (Inter-Integrated Circuit) communication module. Figure 1 (Not shown) The digital potentiometer transmits the signal to the matching resistor control execution module. The digital potentiometer dynamically adjusts the actual input resistance of the terminal matching resistor according to the resistance value, thereby completing the automatic impedance matching adjustment of the communication bus and realizing the precise matching between the terminal impedance of the communication bus and the characteristic impedance of the cable, thus eliminating signal reflection problems.

[0040] In summary, this embodiment performs cross-correlation calculations on the detected signal and the reflected echo signal, extracts relevant peak parameters, and calculates the cable link length and terminal impedance based on these parameters to determine the impedance matching status. If the impedance is not matched, the resistance value of the terminal matching resistor is dynamically adjusted, thereby achieving automatic impedance matching. Automatic matching of the matching resistor is achieved through spread spectrum detection, eliminating the need for manual experience in resistor configuration and solving the core problem of poor adaptability of static matching schemes. This invention can automatically sense the link status, accurately extract signal parameters and calculate the terminal impedance through cross-correlation calculations, and dynamically adjust the matching resistor, effectively suppressing signal reflection, waveform distortion, and other problems, thus improving the reliability of bus communication. Simultaneously, the parallel processing capability of the FPGA ensures the real-time performance of the matching process, adapting to complex scenarios with dynamically changing link parameters and significantly reducing manual debugging and maintenance costs.

[0041] In one embodiment, such as Figure 3 As shown, generating the pseudo-random sequence as the probe signal specifically includes: using a linear feedback shift register to generate an m-sequence inside the FPGA as the pseudo-random sequence, including... Generate an m-sequence from the primitive polynomial, with the initial state set to 1111 and the period of the m-sequence being... , where n is the number of stages of the linear feedback shift register; wherein, the m sequence uses the 50MHz~60MHz clock external to the FPGA as the clock source, and outputs the chip at the rising edge of the clock to achieve a nanosecond-level chip width.

[0042] Specifically, a linear feedback shift register (LFSR) is used to build a sequence generation circuit within the FPGA through pure hardware logic, generating an m-sequence as the pseudo-random sequence. The number of stages n of the linear feedback shift register is selected as 4 stages, based on the primitive polynomial. As the core logic basis for sequence generation, the initial state of the linear feedback shift register is configured to 1111 to avoid sequence generation failure caused by an all-zero initial state.

[0043] Based on the above parameter configuration, the period of the generated m-sequence is: This satisfies the sequence period requirements of the detection signal during the automatic matching process of the matching resistor. The m-sequence uses a 50MHz~60MHz clock external to the FPGA as the clock source. This clock source can be a 50MHz clock, a 60MHz clock, or any frequency clock within the 50MHz~60MHz range, adapting to the clock configuration requirements of different FPGA hardware platforms. At each rising edge of the corresponding clock source, the linear feedback shift register synchronously outputs one bit of m-sequence chip, thereby achieving a nanosecond-level chip width, significantly improving the time resolution of the detection signal, and laying the foundation for subsequent accurate acquisition of reflected echo signals and extraction of relevant peak parameters.

[0044] In one embodiment, such as Figure 4 As shown, the detection signal is sent to the communication bus, and the reflected echo signal of the detection signal on the communication bus is collected. First, the transmission process of the detection signal is introduced: the pseudo-random sequence is converted into a differential signal, and after being isolated from DC by an AC capacitor, it is sent to the communication bus.

[0045] First, the host computer sends a probe command, which is parsed by the protocol interface and control switching module inside the FPGA and outputs an enable control signal to the PN code generation module, triggering the generation and output of a pseudo-random sequence.

[0046] The single-ended CMOS level pseudo-random sequence output by the FPGA is converted into a differential signal by the driving and level conversion circuit (differential driver), and then sent to the differential communication bus (such as RS422 / RS485 / CAN, etc.) in the form of a probe signal after being isolated by the AC capacitor through the coupling and isolation circuit (AC isolation) to avoid the influence of DC bias on the normal communication of the bus.

[0047] The process of receiving the reflected echo signal is then described. In one embodiment, refer to... Figure 4 The collected differential reflected echo is isolated from DC by an AC capacitor and processed by differential amplification. It is then sampled by a 500MSPS / 12-bit high-speed AD sampling chip and transmitted to the FPGA via LVDS signal to obtain the reflected echo signal.

[0048] In this process, when the detection signal is transmitted on the differential communication bus, the generated reflected echo signal is isolated from DC by the AC capacitor in the coupling and isolation circuit (AC isolation) and then captured by the system. The captured weak differential reflected echo signal enters the differential amplifier circuit for signal amplification and noise suppression, thereby improving the signal amplitude and signal-to-noise ratio.

[0049] In one embodiment, the amplified reflected echo signal undergoes high-precision, high-sampling-rate analog-to-digital conversion by a 500MSPS / 12-bit high-speed AD acquisition circuit, converting the analog signal into a digital signal. The digital signal after AD sampling is transmitted at high speed to the FPGA in LVDS signal form through the LVDS differential input pin, completing the digital acquisition and preprocessing of the reflected echo signal, providing a data foundation for subsequent cross-correlation calculations and impedance analysis.

[0050] In one embodiment, the calculation formula for the cross-correlation operation is: ; in, It is a pseudo-random sequence. To reflect the echo signal, For time offset, For relevant values, The length of the pseudo-random sequence is given in this embodiment. =512; The main peak position of relevant peaks was extracted using a pipelined step-by-step comparison method. Secondary peak position Main peak amplitude and the amplitude of the secondary peak .

[0051] The spread spectrum correlation detection algorithm processing module inside the FPGA starts the pipeline step-by-step comparison process after completing the cross-correlation operation to obtain the correlation peak sequence.

[0052] In one embodiment, the pipeline step-by-step comparison process is used to divide all data points of the cross-correlation output into multiple consecutive comparison segments. In each clock cycle, only the amplitude of the correlation peaks in the current segment is compared in parallel to filter out the maximum amplitude and its corresponding position in the segment. Then, the maximum values ​​of each segment are sent to the next stage pipeline in sequence and compared with the maximum values ​​of the adjacent segments again to gradually eliminate candidate peaks with smaller amplitudes until the entire correlation peak sequence has been traversed.

[0053] During the step-by-step comparison process, the system records and updates the global amplitude maximum value and its position in real time; this maximum value is the amplitude of the main peak. The corresponding position is recorded as the main peak position. Simultaneously, the system records and updates the global second-largest value and its position; this second-largest value is the amplitude of the second peak. The corresponding position is recorded as the secondary peak position. .

[0054] In summary, the pipelined step-by-step comparison method can efficiently extract relevant peak parameters within a limited clock cycle, avoiding a second traversal of the entire sequence data and significantly improving the real-time performance of parameter extraction and the utilization rate of hardware resources.

[0055] After obtaining the relevant peak parameters, the cable link length and termination impedance need to be calculated based on the corresponding peak parameters. In one embodiment, the calculation method for the cable link length includes: based on the position of the main peak... and secondary peak position Calculate time delay , Calculate cable link length based on time delay. , ;in, The sampling period is Let v be the speed of signal propagation in the cable link, v≈0.66c~0.8c, c=3× m / s.

[0056] In one embodiment, the calculation of the terminating impedance includes: based on the amplitude of the main peak. and secondary peak amplitude The reflection coefficient Γ is calculated, Γ= ; Calculate the terminal impedance based on the reflection coefficient Γ , ;in, This refers to the standard impedance characteristic of communication cables.

[0057] After calculating the cable link length and terminal impedance, the impedance matching status determination specifically includes: calculating the reflection coefficient Γ and determining the cable link length L, setting the reflection coefficient threshold to A%, and dividing the short-distance link threshold Lth according to the cable link length L; when L≤Lth and Γ≤A%, or L>Lth and Γ≤A%, it indicates that the matching resistor is matched; when L≤Lth and Γ>A%, or L>Lth and Γ>A%, it indicates that the matching resistor is not matched.

[0058] Among them, Lth can be preset according to the bus communication protocol, for example, 50m for CAN bus and 100m for RS485 bus. The value of A ranges from 4 to 6.

[0059] When the matching resistors are mismatched, a new matching resistor needs to be calculated. The calculation method is as follows: ; in, For the terminating impedance, This refers to the standard impedance characteristic of communication cables.

[0060] The matching resistor control execution module is used to generate control signals based on the decision results and control the digital potentiometer to adjust the terminal impedance via the I2C bus. The matching resistor control execution module includes the FPGA internal I2C bus control module and the digital potentiometer that supports I2C protocol communication.

[0061] In one embodiment, such as Figure 5 The diagram shows the signal processing and decision-making execution flow for steps 102 and 103 in this embodiment. The process of performing cross-correlation calculations on the probe signal and the reflected echo signal, extracting correlation peak parameters, calculating link and impedance parameters, and implementing matching decisions in this embodiment specifically includes the following steps: The bus receiving sampling module outputs the preprocessed reflected echo signal to the cross-correlation calculation module, while the PN code generation module synchronously provides a local pseudo-random sequence to the cross-correlation calculation module. The input data of the two modules are used to perform high-speed cross-correlation calculation in the cross-correlation calculation module to obtain the correlation peak parameters that reflect the correlation between the probe signal and the reflected echo signal.

[0062] The correlation peak parameters output by the cross-correlation calculation module are transmitted to the correlation peak detection and capture module. The correlation peak detection and capture module extracts the correlation peak characteristic parameters through a pipelined step-by-step comparison method, accurately captures the position of the main peak, the position of the secondary peak, the amplitude of the main peak and the amplitude of the secondary peak, and synchronously distributes the above parameters to the subsequent time delay calculation module and reflection coefficient calculation module.

[0063] The time delay calculation module calculates the transmission time delay of the probe signal in the bus link based on the received primary and secondary peak positions. This time delay parameter is then input to the cable length calculation module, which, combined with the signal propagation characteristics in the cable, calculates the actual cable link length of the current communication bus. Simultaneously, the reflection coefficient calculation module calculates the reflection coefficient of the bus link based on the received primary and secondary peak amplitudes, and inputs this reflection coefficient to the termination impedance calculation module to further calculate the termination impedance of the communication bus.

[0064] The matching decision module receives the cable link length from the cable length calculation module and the terminal impedance from the terminal impedance calculation module. Combining the preset judgment threshold and adaptation rules, it comprehensively judges the current impedance matching status of the bus. If the impedance is determined to be mismatched, the matching decision module will determine the required target matching resistor value based on the calculation parameters.

[0065] Finally, the matching decision module transmits the target matching resistor value to the I2C communication module, which then sends the resistance adjustment command to the digital potentiometer according to the I2C communication protocol. The digital potentiometer dynamically adjusts its own input resistance value according to the received command, completing the precise adjustment of the terminal matching resistor and ultimately realizing automatic impedance matching of the communication bus.

[0066] In summary, compared with the experience-based static matching schemes in traditional methods, this invention proposes an automatic matching method for communication bus matching resistors based on spread spectrum detection, which has the following advantages: (1) Greatly reduce operation and maintenance costs: When bus nodes are added or removed, cables are replaced or terminal loads change, the system can automatically detect the link status after power-on and the system can automatically re-match to avoid communication abnormalities. There is no need for technicians to manually replace the matching resistor, reducing on-site debugging time and manpower input, which is especially suitable for large-scale, distributed systems.

[0067] (2) By spreading correlation detection, the reflected signal is accurately extracted, the reflection coefficient Γ and the terminal impedance ZL are calculated, and the optimal matching resistor is matched according to the actual link to effectively suppress signal reflection, ringing and overshoot, improve eye diagram quality, and effectively improve long-distance bus communication transmission.

[0068] (3) The hardware implementation is simple, low cost, and highly reliable. The system is based on FPGA and the core algorithms (spread spectrum generation, correlation detection, and impedance calculation) are all completed in the FPGA, with fast response and strong real-time performance.

[0069] (4) It can be adapted to differential communication protocols such as CAN, RS-485 and RS-422, and is suitable for various scenarios such as industrial control, automotive electronics and power systems.

[0070] (5) It can measure cable length, signal propagation speed, terminal impedance, reflection coefficient, etc. in real time for fault location.

[0071] Example 2: In Embodiment 1, an automatic matching method for communication bus matching resistors based on spread spectrum detection was provided. In this embodiment, an automatic matching device for communication bus matching resistors based on spread spectrum detection will be proposed. The automatic matching device for communication bus matching resistors based on spread spectrum detection includes: a processor and a memory for storing processor-executable instructions; wherein, the processor is configured to execute the automatic matching method for communication bus matching resistors based on spread spectrum detection described in Embodiment 1.

[0072] like Figure 6 As shown, the automatic matching device for the matching resistor of the communication bus based on spread spectrum detection includes a processor 21 and a memory 22, wherein the processor 21 and the memory 22 can be connected by a bus or other means.

[0073] Processor 21 can be a central processing unit (CPU). Processor 21 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0074] The memory 22, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the automatic matching method for communication bus matching resistors based on spread spectrum detection in Embodiment 1 of this invention. The processor executes various functional applications and training processes by running the non-transitory software programs, instructions, and modules stored in the memory.

[0075] The memory 22 may include a program storage area and a training storage area. The program storage area may store the operating system and applications required for at least one function; the training storage area may store training data created by the processor. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory, or other non-transitory solid-state storage device. In some embodiments, the memory 22 may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The one or more modules stored in the memory 22, when executed by the processor 21, perform functions such as... Figure 1 The automatic matching method for communication bus matching resistors based on spread spectrum detection is shown in Embodiment 1. For specific details of the above-described automatic matching method for communication bus matching resistors based on spread spectrum detection, please refer to the relevant documentation. Figure 1 , Figure 2 and Figure 3 The relevant descriptions and effects in the embodiments shown are for reference only and will not be repeated here.

[0076] This embodiment also provides a computer storage medium storing a computer program that can be executed by a processor to complete the automatic matching method for communication bus matching resistors based on spread spectrum detection described in Embodiment 1.

[0077] The computer storage medium stores computer-executable instructions, which can execute the automatic matching method for communication bus matching resistors based on spread spectrum detection in any of the above method embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium may also include combinations of the above types of memory.

[0078] The specific steps of the automatic matching method for the matching resistor of the communication bus based on spread spectrum detection are described in Example 1, and will not be repeated in this example.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An automatic matching method for matching resistors of a communication bus based on spread spectrum detection, characterized in that, include: A pseudo-random sequence is generated as a detection signal, the detection signal is sent to the communication bus, and the reflected echo signal of the detection signal on the communication bus is collected; Perform cross-correlation calculation on the detected signal and the reflected echo signal, and extract the correlation peak parameters; The cable link length and termination impedance are calculated based on the relevant peak parameters to determine the impedance matching status. If the impedance is not matched, the resistance value of the termination matching resistor is dynamically adjusted to achieve automatic impedance matching.

2. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 1, characterized in that, The generation of the pseudo-random sequence as a probe signal specifically includes: The pseudo-random sequence is generated internally within the FPGA using a linear feedback shift register, including... Generate an m-sequence from the primitive polynomial, with the initial state set to 1111 and the period of the m-sequence being... , where n is the number of stages of the linear feedback shift register; The m-sequence uses the 50MHz~60MHz external clock of the FPGA as the clock source, and outputs the chip at the rising edge of the clock to achieve a nanosecond-level chip width.

3. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 1, characterized in that, The step of sending the detection signal to the communication bus and collecting the reflected echo signal of the detection signal on the communication bus specifically includes: The pseudo-random sequence is converted into a differential signal, which is then sent to the communication bus after being isolated from DC by an AC capacitor. The collected differential reflected echo is isolated from DC by an AC capacitor and processed by differential amplification. It is then sampled by an AD sampling chip and transmitted to the FPGA via an LVDS signal to obtain the reflected echo signal.

4. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 1, characterized in that, The calculation formula for the cross-correlation operation is as follows: ； in, It is a pseudo-random sequence. To reflect the echo signal, For time offset, For relevant values, The length of the pseudo-random sequence; The main peak position of relevant peaks was extracted using a pipelined step-by-step comparison method. Secondary peak position Main peak amplitude and the amplitude of the secondary peak .

5. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 4, characterized in that, The calculation method for the cable link length includes: Based on the location of the main peak and secondary peak position Calculate time delay , ; Calculate cable link length based on time delay , ; in, The sampling period is Let v be the speed of signal propagation in the cable link, v≈0.66c~0.8c, c=3× m / s.

6. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 4, characterized in that, The calculation methods for the termination impedance include: Based on the amplitude of the main peak and secondary peak amplitude The reflection coefficient Γ is calculated, Γ= ; Calculate the terminal impedance based on the reflection coefficient Γ. , ; in, This refers to the standard impedance characteristic of communication cables.

7. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 1, characterized in that, The determination of impedance matching status specifically includes: Calculate the reflection coefficient Γ and determine the cable link length L. Set the reflection coefficient threshold to A%, and divide the short-distance link threshold Lth according to the cable link length L. When L≤Lth and Γ≤A%, or L>Lth and Γ≤A%, it indicates that the matching resistor has been matched; When L≤Lth and Γ>A%, or L>Lth and Γ>A%, it indicates that the matching resistors are mismatched.

8. The automatic matching method for communication bus matching resistors based on spread spectrum detection according to claim 1, characterized in that, The matching resistor The calculation method is as follows: ； in, For the terminating impedance, This refers to the standard impedance characteristic of communication cables.

9. An automatic matching device for matching resistors of a communication bus based on spread spectrum detection, characterized in that, The automatic matching device for the matching resistor of the communication bus based on spread spectrum detection includes: a processor and a memory for storing processor-executable instructions; The processor is configured to execute the automatic matching method for communication bus matching resistors based on spread spectrum detection as described in any one of claims 1-8.

10. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, which are executed by one or more processors to perform the automatic matching method for communication bus matching resistors based on spread spectrum detection as described in any one of claims 1-8.

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