Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an interlayer insulating film disposed on a substrate and having a recessed portion of the substrate exposed; a bottom electrode contact embedded in at least a portion of the recessed portion; a magnetic tunnel junction (MTJ) layer disposed on the interlayer insulating film and the bottom electrode contact; and a offset cancellation layer with a magnetization direction parallel to the antiparallel side of a fixed layer, wherein the offset cancellation layer may include a Co alloy, Fe alloy, Ni alloy, or Mn alloy comprising at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals, or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy comprising one selected from the group consisting of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0189518, filed on December 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments disclosed herein relate to semiconductor technology, and more specifically, to semiconductor devices including magnetic tunnel junction structures and methods for manufacturing the same. Background Technology

[0004] In recent years, with the trend towards miniaturization, low power consumption, high performance, and diversification of electronic devices, there is a need for semiconductor devices capable of storing data in various electronic devices (such as computers, portable communication devices, etc.). Researchers and industry are researching and developing such semiconductor devices. These semiconductor devices store data by utilizing the characteristic of switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses. Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor devices and methods of manufacturing the same, which provide stable exchange coupling at high temperatures and achieve high exchange bias field (Hex) and magnetoresistance (MR) by forming a synthetic antiferromagnetic (SAF) structure under a magnetic tunnel junction (MTJ) structure and an offset offset layer (SCL) using a specific alloy, thereby preventing SAF performance degradation that may occur during high-temperature heat treatment.

[0006] According to one embodiment of this disclosure, a semiconductor device includes: a substrate; an interlayer insulating film disposed on the substrate and having a recess exposing a portion of the substrate; a bottom electrode contact (BEC) embedded in at least a portion of the recess; a magnetic tunnel junction (MTJ) layer including a fixed layer disposed on the interlayer insulating film and the bottom electrode contact and having a fixed magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer between the free layer and the fixed layer; and an offset cancellation layer having a magnetization direction antiparallel to the fixed layer, wherein the offset cancellation layer comprises a magnetic alloy selected from the group consisting of: (i) a cobalt (Co)-based alloy or an iron (Fe)-based alloy containing (ii) a nickel (Ni)-based alloy or a manganese (Mn)-based alloy containing at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf), and rare earth metals; and (iii) a ternary or quaternary alloy containing Co, Fe, or Ni, further containing one of platinum (Pt) or palladium (Pd), and at least one element selected from the group consisting of chromium (Cr), aluminum (Al), terbium (Tb), silicon (Si), and boron (B).

[0007] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming an interlayer insulating film on a substrate; selectively etching the interlayer insulating film to form a recess exposing a portion of the substrate; forming a bottom electrode contact embedded in at least a portion of the recess; and forming an offset cancellation layer and a variable resistance element on the bottom electrode contact, wherein the offset cancellation layer comprises a magnetic alloy selected from the group consisting of: (i) cobalt (Co)-based alloys or iron (Fe)-based alloys, comprising at least one selected from aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (... (ii) elements selected from the group consisting of Zr, hafnium (Hf) and rare earth metals; and (iii) nickel (Ni) based alloys or manganese (Mn) based alloys containing at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf) and rare earth metals; and (iii) ternary or quaternary alloys containing Co, Fe or Ni, further containing one of platinum (Pt) or palladium (Pd), and at least one element selected from the group consisting of chromium (Cr), aluminum (Al), terbium (Tb), silicon (Si) and boron (B). Attached Figure Description

[0008] Figures 1A to 1C This is a perspective view and a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 2A to 2GThis is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0010] Figures 3A to 3H This is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. Detailed Implementation

[0011] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure more comprehensive and to fully convey the scope of the disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments.

[0012] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0013] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When referring to the first layer as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that a third layer exists between the first layer and the second layer or the substrate.

[0014] Figures 1A to 1C This is a perspective view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 1A This is a perspective view. Figure 1B and Figure 1C For along Figure 1A The cross-sectional view taken by line A-A' in the diagram.

[0015] refer to Figures 1A to 1C According to one embodiment, a semiconductor device may have a crossover structure. The crossover structure may include: a first wiring 110 formed on a substrate 100 and extending along a first direction; a second wiring 180 located on the first wiring 110 and extending along a second direction intersecting the first direction; and memory cells 170 disposed at each crossover point between the first wiring 110 and the second wiring 180.

[0016] The substrate 100 may contain a semiconductor material, such as silicon. Any desired predetermined substructure may be formed within the substrate 100. For example, the substructure may include drive circuitry electrically connected to control a first wiring 110 and / or a second wiring 180 formed on the substrate 100.

[0017] The first wiring 110 and the second wiring 180 may be connected to the memory cell 170 to deliver voltage or current to the memory cell 170 to drive the memory cell 170. One of the first wiring 110 and the second wiring 180 may be used as a word line, and the other may be used as a bit line. Both the first wiring 110 and the second wiring 180 may have a single-film structure or a multi-film structure containing conductive material. Examples of conductive materials include, but are not limited to, metals, metal nitrides, conductive carbon materials, or combinations thereof. For example, the first wiring 110 and the second wiring 180 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), palladium (Pd), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), or any combination thereof.

[0018] The storage cells 170 can be arranged in a matrix along a first direction and a second direction to overlap with the intersection area of ​​the first wiring 110 and the second wiring 180. In this embodiment, the size of the storage cells 170 is less than or equal to the intersection area of ​​the first wiring 110 and the second wiring 180. In other embodiments, the size of the storage cells 170 can be larger than the intersection area. The space between the first wiring 110, the second wiring 180 and the storage cells 170 can be embedded with insulating material.

[0019] The memory cell 170 may include a stacked structure that may include a bottom electrode contact 120, an offset cancellation layer 130, a spacer layer 140, a magnetic tunnel junction (MTJ) layer 150, and a selector layer 160. Furthermore, a first interlayer insulating film 125 may be formed to cover the sidewalls of the bottom electrode contact 120, and a second interlayer insulating film 165 may be formed to cover the sidewalls of the multilayer (ML) offset cancellation layer 130, the spacer layer 140, the MTJ layer 150, and the selector layer 160.

[0020] Bottom electrode contact 120 may be formed between the first wiring 110 and the offset cancellation layer 130. Bottom electrode contact 120 may be located at the bottom of the storage cell 170, electrically connected to the first wiring 110, and may serve as a channel for transmitting current or voltage between the first wiring 110 and the storage cell 170. Bottom electrode contact 120 may contain a material capable of forming an insulating layer. For example, bottom electrode contact 120 may be made of tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), palladium (Pd), manganese (Mn), niobium (Ni), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), or any combination thereof.

[0021] An offset cancellation layer 130 may be formed between the bottom electrode contact 120 and the spacer layer 140. The offset cancellation layer 130 is positioned such that its magnetization direction is aligned with the fixing layer of the MTJ layer 150 (e.g., ...). Figure 2C The fixed layer 251 is antiparallel to compensate for magnetic offset, thereby reducing sensitivity to changes in the external magnetic field, improving the reliability of the MTJ layer 150, and reducing data errors. By setting the magnetization direction to antiparallel, unwanted magnetization offset caused by the external magnetic field can be counteracted, improving stability. This reduces magnetic noise in the storage element, keeps the MTJ layer 150 in a constant state, and ensures accurate data storage and retrieval. Furthermore, the offset compensation layer 130 can form a synthetic antiferromagnetic (SAF) structure with the fixed layer to improve magnetic stability and control the hysteresis of the MTJ layer 150, thereby maintaining high sensitivity under low magnetic fields. The offset compensation layer 130 can be magnetically coupled to the fixed layer through a spacer layer 140, which is typically composed of non-magnetic metals such as ruthenium (Ru), iridium (Ir), and chromium (Cr).

[0022] A proposed multilayer (ML) offset cancellation layer may have a stacked structure with alternating magnetic (FM) and nonmagnetic (NM) layers in a repeating structure. For example, an ML offset cancellation layer is a structure such as [FM / NM]n, where each magnetic and nonmagnetic layer can be combined to form the desired magnetic properties. For example, an ML offset cancellation layer may have a structure such as [FM / NM]n, where "FM" represents a ferromagnetic layer, "NM" represents a nonmagnetic layer, and "n" is an integer representing the number of repetitions of the FM / NM double layer. In this configuration, alternating ferromagnetic and nonmagnetic layers are stacked multiple times to form a multilayer structure that provides the desired magnetic properties. Multilayer offset cancellation layers have low thermal stability, reduced interfacial magnetic anisotropy, and reduced synthetic antiferromagnetic properties due to the possibility of interlayer diffusion during high-temperature processes. However, the offset cancellation layer 130 made of a specific alloy of this embodiment can obtain its magnetic properties directly from the bulk properties of the material itself and generally has high magnetic anisotropy, making it thermally stable and suitable for high-temperature processes. Furthermore, the offset cancellation layer 130 can be made of a homogeneous alloy and has unique magnetic properties.

[0023] The offset cancellation layer 130 may comprise a Co alloy, Fe alloy, Ni alloy, or Mn alloy containing at least one selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf), and rare earth metals; or a ternary or quaternary Co alloy, Fe alloy, Ni alloy, or Mn alloy containing one of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B. The offset cancellation layer 130 provides an SAF structure that maintains perpendicular magnetic anisotropy (PMA) at high temperatures without reducing its synthetic antiferromagnetic (SAF) properties, thereby providing a SAF structure resistant to high-temperature heat treatment. Overcoming the limitations of previously proposed multilayer offset cancellation layers, the inventors have for the first time discovered an offset cancellation layer 130 composed of an alloy that does not reduce its synthetic antiferromagnetic properties at high temperatures.

[0024] Specifically, the offset cancellation layer 130 may comprise a cobalt alloy, an iron alloy, a nickel alloy, or a manganese alloy, containing at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf), and rare earth metals. For example, the offset cancellation layer 130 may comprise a Co-Fe-B alloy, a Co-Ir alloy, a Co-Zr-B alloy, an Fe-Ga alloy, a Co-Pt-B alloy, a Co-Tb alloy, or a Ni-Zr-B alloy. The Co-Fe-B alloy provides stable perpendicular magnetic anisotropy (PMA) at high temperatures and prevents degradation of SAF performance during high-temperature heat treatment. In particular, boron (B) stabilizes the grains and helps maintain magnetic properties even after heat treatment. The Co-Ir alloy is an ordered phase alloy with an L11 structure. The Co-Ir alloy exhibits strong PMA properties and maintains magnetic stability at high temperatures. In particular, iridium (Ir) enhances corrosion resistance and helps maintain stable performance in high-temperature and high-humidity environments. Co-Zr-B alloys exhibit minimal performance degradation at high temperatures and maintain PMA (Potentially Magnetoresistance) due to the oxidation resistance of zirconium and the grain stabilizing effect of boron (B). Co-Zr-B alloys also maintain SAF (Self-Focused Aspect) performance at high temperatures, making them suitable for high-density MTJ (Metal-to-Jet) devices. Fe-Ga alloys possess a high magnetostriction coefficient, maintaining their PMA performance even during high-temperature heat treatment. In particular, gallium (Ga) enhances magnetic domain stability, thereby improving the high-temperature performance of MTJ devices. Co-Pt-B alloys are ordered phase alloys with an L10 structure. The high-temperature stability of platinum (Pt) and the grain boundary suppression effect of boron (B) provide excellent PMA, maintaining good SAF characteristics even after high-temperature heat treatment. Pt increases structural stability after heat treatment, allowing for stable long-term performance. Co-Tb alloys are ordered phase alloys with a D0 (Diagram of 0.05-1000 ohms). 19 These ordered phase alloys are also rare-earth transition metal alloys. Co-Tb alloys offer high PMA (partial magnetic mass) and thermal stability, resulting in excellent magnetic properties at high temperatures. The addition of rare-earth metal Tb imparts a strong magnetic moment, which helps suppress magnetic degradation. Ni-Zr-B alloys exhibit excellent high-temperature oxidation resistance, maintaining stable magnetic properties even after heat treatment. In particular, the oxidation resistance of Zr combined with the grain boundary suppression effect of boron provides high thermal stability. As offset offset layers (SCLs), these Ni-Zr-B alloys offer advantages such as high-temperature stability, PMA retention, oxidation resistance, and grain stability, resulting in excellent magnetic properties and long-term performance in high-density MTJ devices even after high-temperature heat treatment. Ordered phase alloys possess L10, L11, and D0... 19 The structure provides excellent vertical magnetic anisotropy for the offset cancellation layer 130, while the rare earth-transition metal alloy, through the combination of rare earth and transition metal, enables the offset cancellation layer 130 to have high thermal stability and magnetic properties.

[0025] The offset offset layer 130 may comprise a ternary or quaternary Co alloy, Fe alloy, or Ni alloy, containing one of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B. The offset offset layer 130 may comprise, for example, a Co-Pt-Cr alloy, an Fe-Pd-Al alloy, a Co-Ni-Tb alloy, or a Ni-Pd-Si-B alloy.

[0026] Co-Pt-Cr alloys maintain stable magnetic properties at high temperatures and provide strong magnetic anisotropy, maximizing offset cancellation effects. The high magnetic moment of Co-Pt-Cr alloys is due to the combination of Co and Pt, while the addition of Cr provides oxidation resistance. Fe-Pd-Al alloys maintain both electrical and magnetic stability. As Fe-based alloys, they possess a high magnetic moment, and Pd and Al enhance their stability. Fe-Pd-Al alloys exhibit oxidation resistance even at high temperatures, with Al providing oxidation resistance and lightweighting, improving the overall thermal stability of SCLs. Co-Ni-Tb alloys are rare-earth transition metal alloys, with the addition of the rare-earth element Tb to improve magnetic properties and maintain magnetic stability at high temperatures. This is because the combination of Co and Ni provides a strong magnetic moment, while Tb retains the magnetism, ensuring stable performance of SAFs even at high temperatures. Ni-Pd-Si-B alloys contain Si and B, exhibiting soft magnetic properties and good oxidation resistance. Specifically, boron (B) plays a role in stabilizing magnetic properties, minimizing performance changes at high temperatures, while the addition of Pd induces a smooth magnetic transition. These ternary and quaternary alloys are characterized by good oxidation resistance and high-temperature stability, while maintaining a magnetic moment as high as that of SCL. This allows ternary and quaternary alloys to maximize the offset cancellation effect in MTJ devices and maintain stable magnetic properties, especially during high-temperature heat treatment.

[0027] MTJ layer 150 and selector layer 160 may be laminated on spacer layer 140. MTJ layer 150 includes a fixed layer with a fixed magnetization direction, a free layer with a variable magnetization direction, and a tunnel barrier layer between the fixed layer and the free layer. According to embodiments of this disclosure, in Figure 2G and Figure 3H It is described in more detail in the text.

[0028] Selector layer 160 is implemented as a thin film within memory cell 170, functioning to control electrical access to one of the plurality of memory cells 170 in the array and to prevent leakage current that may occur between memory cells 170 sharing a first wiring 110 or a second wiring 180. To this end, selector layer 160 may exhibit threshold switching characteristics, blocking current or allowing minimal current flow when the voltage applied to its top and bottom is below a predetermined threshold voltage; and allowing rapid current flow when the voltage exceeds the threshold voltage. Selector layer 160 can be turned on when the voltage exceeds the threshold voltage and turned off when the voltage is below the threshold voltage. For example, selector layer 160 may comprise an insulating material doped with dopant.

[0029] Both the first interlayer insulating film 125 and the second interlayer insulating film 165 may contain insulating materials, polycrystalline silicon (Poly-Si), or combinations thereof, and may employ a single-film or multi-film structure. For example, both the first interlayer insulating film 125 and the second interlayer insulating film 165 may contain silicon oxide, silicon nitride, silicon oxynitride, and / or low-k materials. Materials with a dielectric constant (k) of 4 or lower are generally referred to as low-k materials. A lower dielectric constant provides better electrical insulation performance, thereby reducing parasitic capacitance between devices. These low-k materials include, but are not limited to, silicon oxide, organosiloxanes, silicon carbide, organic-based materials containing benzene rings or fluorine, and porosilicate materials.

[0030] refer to Figure 1B and 1C The structure may have a bottom electrode contact 120 embedded in the entire recess, and an offset offset layer 130 formed on top of the bottom electrode contact 120 such that the offset offset layer 130 is not embedded in the recess at all; or, the structure may have a bottom electrode contact 120 embedded in a portion of the recess, and an offset offset layer 130 formed on top thereof such that the offset offset layer 130 is embedded in a portion of the recess.

[0031] Figures 2A to 2G According to one embodiment of the present disclosure Figure 1B A cross-sectional view of a semiconductor device and its manufacturing method. Figures 2A to 2G for Figure 1B The image shows an enlarged cross-sectional view of a single memory cell among multiple memory cells in the semiconductor device. Since some components are substantially the same as in the aforementioned embodiment, detailed descriptions will be omitted.

[0032] First, the manufacturing method will be explained.

[0033] refer to Figure 2A and Figure 2BThe first wiring 210 can be formed on a substrate 200 in which a predetermined substructure is formed. The first wiring 210 can be formed as follows: an interlayer insulating film having trenches for forming the first wiring 210 is formed on the substrate 200; a conductive layer for forming the first wiring 210 is formed in the trenches; and the conductive layer is etched using a linear mask pattern extending along a first direction.

[0034] Subsequently, a bottom electrode contact 220 can be formed on the first wiring 210. The bottom electrode contact 220 can be formed as follows: a first interlayer insulating film 225 with recesses is formed on the structure formed by the first wiring 210; the recesses are filled with a material layer for forming the bottom electrode contact 220; and then a planarization process, such as a chemical mechanical planarization process, is performed. The bottom electrode contact 220 can fill the entire recess. If the bottom electrode contact 220 completely fills the recess, the physical stability of the bottom electrode contact 220 is improved, which is beneficial for supporting the upper structure. In addition, in this case, the electrical connection area is maximized, the contact resistance may be reduced, the planarization process is relatively easy, and surface flatness can be achieved more easily. Specifically, a precisely sized recess is made at the location where the bottom electrode contact 220 is placed using photolithography and etching processes, and the formed recess is filled with a material layer for the bottom electrode contact 220. The material used for the bottom electrode contact 220 may be tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), palladium (Pd), manganese (Mn), niobium (Ni), or tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), or any combination thereof.

[0035] refer to Figure 2CThe material layer for forming the offset cancellation layer 230 can be formed on the planarized bottom electrode contact 220 and the first interlayer insulating film 225, and the material layer for forming the spacer layer 240 can be formed on top of the offset cancellation layer 230. Subsequently, the material layers for forming the MTJ layer 250 (including the material layers for forming the fixed layer 251, the material layers for forming the tunnel barrier layer 252, and the material layers for forming the free layer 253) can be formed on top of the material layers for forming the spacer layer 240. Subsequently, the material layer for forming the selector layer 260 can be formed. The material layers for forming the fixed layer 251 and the material layers for forming the free layer 253 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electron beam deposition. The material layer for forming the tunnel barrier layer 252 can be deposited by alkali metal oxide or atomic layer deposition (ALD). This method can obtain a very thin and uniform oxide film, thereby enabling precise control of the tunneling current.

[0036] refer to Figure 2G Spacer layer 240A may be located between fixed layer 251A and offset cancellation layer 230A, acting as a buffer layer between them to achieve antiferromagnetic exchange coupling and improve the performance of bottom electrode contact 220. Spacer layer 240A may contain noble metals, such as Ru, Ir, Cr, or combinations thereof. For example, the thickness of spacer layer 240A may be at least 0.5 nm. Therefore, a thickness of at least 0.5 nm for spacer layer 240A can prevent intermaterial diffusion or interaction that may occur during high-temperature heat treatment processes. These thick spacers can prevent material deformation or reaction at high temperatures, thereby protecting fixed layer 251A and offset cancellation layer 230A from performance changes or degradation. Thus, stability at high temperatures can be maintained. Furthermore, when the thickness of spacer layer 240A is at least 0.5 nm, the antiferromagnetic exchange bond between fixed layer 251A and offset cancellation layer 230A can be stronger. This is because the spacer layer 240A can more effectively modulate the interaction between the fixed layer 251A and the offset cancellation layer 230A, thereby better controlling the magnetization direction of the fixed layer 251A and improving magnetic stability. Furthermore, an intermediate layer can be inserted between the tunnel barrier layer 252A and the fixed layer 251A. The intermediate layer can be the magnetic layer closest to the tunnel barrier layer 252A and can include Co, Fe, Ni, B, other noble metals, or combinations thereof.

[0037] refer to Figure 2D and Figure 2EA columnar hard mask layer 262 may be deposited on the top surface of the material layer used to form the selector layer 260, which may be formed of an insulating material (e.g., silicon nitride or silicon oxynitride). For example, the hard mask layer 262 may contain at least one of carbon (C), silicon (Si), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), and aluminum (Al), as well as nitrides, oxides, borides, and metal nitrides (e.g., titanium nitride and tantalum nitride) containing at least one of the above elements. The hard mask layer 262 is columnar and serves as an etch stop layer. Material layers forming the offset offset layer 230A, spacer layer 240A, anchor layer 251A, tunnel barrier layer 252A, free layer 253A, and selector layer 260A are selectively etched to form columnar patterned offset offset layer 230A, spacer layer 240A, anchor layer 251A, tunnel barrier layer 252A, free layer 253A, and selector layer 260A. The anchor layer 251A, tunnel barrier layer 252A, and free layer 253A can form the MTJ layer 250A.

[0038] refer to Figure 2F A second interlayer insulating film 265 can be formed, covering the sidewalls of the offset offset layer 230A, spacer layer 240A, selector layer 260A, and magnetic tunnel junction layer 250A (including a fixed layer 251A, a tunnel barrier layer 252A, and a free layer 253A). The second interlayer insulating film 265 can be made of a highly insulating material, such as an insulating material, polysilicon (Poly-Si), or a combination thereof, which provides stability at high temperatures to prevent damage in subsequent processes. The second interlayer insulating film 265 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering processes to uniformly cover the sidewalls of the magnetic tunnel junction layer 250A and the selector layer 260A. This allows each memory cell to be electrically isolated along the sidewalls of the MTJ layer 250A and the selector layer 260A, thereby minimizing surface conductivity and leakage current.

[0039] refer to Figure 2G A second wiring 280 can be formed on top of the memory cell. The second wiring 280 can be formed as follows: a trench for forming the second wiring 280 is formed; a conductive layer for forming the second wiring 280 is deposited in the trench; and the conductive layer is etched using a line mask pattern extending along a second direction. The second wiring 280 can be patterned at a 90-degree angle to the first wiring 210, that is, the first wiring 210 can be patterned along... Figure 1A The first direction extends, while the second wiring 280 can extend along... Figure 1A The second direction extends within the structure. This configuration yields a semiconductor device with an intersection structure, wherein memory cells are disposed between the first wiring 210 and the second wiring 280 that intersect each other.

[0040] Through the above-described process, a semiconductor device according to an embodiment of this disclosure can be formed. (See again...) Figure 2G The semiconductor device according to this embodiment includes: a substrate 200, a first wiring 210, a bottom electrode contact 220, an offset cancellation layer 230A, a spacer layer 240A, an MTJ layer 250A (including a fixed layer 251A, a tunnel barrier layer 252A, and a free layer 253A), a selector layer 260A, and a second wiring 280. Furthermore, the semiconductor device may include a first interlayer insulating film 225 covering the sidewalls of the bottom electrode contact 220 and a second interlayer insulating film 265 covering the sidewalls of the offset cancellation layer 230A, the spacer layer 240A, the MTJ layer 250A (including a fixed layer 251A, a tunnel barrier layer 252A, and a free layer 253A), and the selector layer 260A.

[0041] Both the free layer 253A and the fixed layer 251A can contain materials with interfacial perpendicular magnetic anisotropy. Interfacial perpendicular magnetic anisotropy refers to the phenomenon where a magnetic layer with inherent horizontal magnetization characteristics has a magnetization direction perpendicular to the direction of magnetization due to the influence of the interface with another adjacent layer. Here, inherent horizontal magnetization characteristics refer to the magnetization direction of a magnetic layer being parallel to its widest surface when there are no external factors. For example, when a magnetic layer with inherent horizontal magnetization characteristics is formed on a substrate and there are no external factors, the magnetization direction of the magnetic layer can be substantially parallel to the top surface of the substrate. Both the free layer 253A and the fixed layer 251A can have a multi-film structure or a single-film structure containing ferromagnetic materials. The ferromagnetic material may include Fe, Ni, or Co-based alloys, such as Fe-Pt alloys, Fe-Pd alloys, Co-Fe alloys, Co-Pd alloys, Co-Pt alloys, Co-Fe-Ni alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, Co-Fe-B alloys, etc., or may include layered structures, such as Co / Pt, Co / Pd, etc. The positions of the free layer 253A and the fixed layer 251A can be interchanged across the tunnel barrier layer 252A; that is, the free layer 253A may be located above the tunnel barrier layer 252A, while the fixed layer 251A may be located below the tunnel barrier layer 252A and above the bottom electrode pattern 221. The tunnel barrier layer 252A can allow electrons to tunnel between the free layer 253A and the fixed layer 251A during write operations, thereby changing the resistance state of the variable resistor element and causing a change in the magnetization direction of the free layer 253A. The tunnel barrier layer 252A may comprise at least one of the following materials: magnesium (Mg) oxide, titanium (Ti) oxide, aluminum (Al), magnesium-zinc (MgZn) oxide, magnesium-boron (Mg-B) oxide, titanium (Ti) nitride, and vanadium (V) nitride. In one example, the tunnel barrier layer 252A may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier layer 252A may also comprise multiple layers. The free layer 253A, the tunnel barrier layer 252A, and the fixed layer 251A may form an MTJ layer 250A, and the variable resistance layer may comprise such an MTJ layer 250A.

[0042] The resistance of the MTJ layer 250A can depend on the magnetization directions of the fixed layer 251A and the free layer 253A. For example, when the magnetization directions of the fixed layer 251A and the free layer 253A are antiparallel, the resistance of the MTJ layer 250A can be much larger than when the fixed layer 251A and the free layer 253A are parallel. Therefore, the resistance of the MTJ layer 250A can be adjusted by changing the magnetization direction of the free layer 253A, which can serve as a data storage principle for the semiconductor device according to this disclosure.

[0043] The semiconductor device of this embodiment provides a lower synthetic antiferromagnetic (SAF) structure by placing the offset cancellation layer 230A at the bottom of the MTJ layer 250A. Figure 2G The structure (a) in the figure, namely the structure formed by the offset cancellation layer 230A, the spacer layer 240A and the fixed layer 251A in sequence, provides strong vertical magnetic anisotropy (PMA), thereby enhancing the exchange bias field (Hex). By placing the SAF structure at the bottom, this embodiment can improve the stability of the device against external magnetic fields, thereby improving the reliability of data storage.

[0044] Furthermore, in this embodiment, the semiconductor device replaces the proposed multilayer offset offset layer (SCL layer) with an offset offset layer 230A comprising a Co alloy, Fe alloy, Ni alloy, or Mn alloy (containing at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals) or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy (containing one of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B). This replacement enables high-temperature heat treatment of the MTJ layer 250A, thereby promoting crystallization and significantly improving magnetoresistance (MR). There is a concern that the proposed multilayer SCL structure may experience interdiffusion within the SCL layer during high-temperature heat treatment, leading to a decrease in synthesized antiferromagnetic properties. However, in this embodiment, the multilayer SCL structure is replaced with a specific alloy, such as an ordered phase alloy with bulk magnetic anisotropy, a rare earth-transition metal (RE-TM) alloy, or a ternary or quaternary Co, Fe, or Ni alloy containing specific elements, to enhance the thermal stability of the SAF. The offset cancellation layer 230A, made of this specific alloy, exhibits superior magnetic properties compared to the previously proposed [FM / NM]*n structure, which improves the structure of the fixed layer 251A, tunnel barrier layer 252A, and free layer 253A arranged in sequence (i.e., Figure 2G The magnetoresistance (MR) of the structure (b) in the example is greatly improved. Therefore, the read / write efficiency of the semiconductor device can be significantly improved. Thus, the offset cancellation layer 230A of this embodiment can realize a high-performance spintronic device by simultaneously achieving the combination of exchange bias field (Hex) enhancement and magnetoresistance (MR) increase, and provides a solution to overcome the limitations of high-temperature thermal processing in conventional technologies.

[0045] Figure 2G The process structure can be the same as the above. Figure 1B The basic process structures are the same. That is, the substrate 200, the first wiring 210, the bottom electrode contact 220, the first interlayer insulating film 225, the offset cancellation layer 230A, the spacer layer 240A, the MTJ layer 250A, the selector layer 260A, the second interlayer insulating film 265, and the second wiring 280 correspond to respectively Figure 1BThe substrate 100, first wiring 110, bottom electrode contact 120, first interlayer insulating film 125, offset cancellation layer 130, spacer layer 140, MTJ layer 150, selector layer 160, second interlayer insulating film 165, and second wiring 180 are included. Therefore, [details omitted]. Figure 1B A detailed description of the process structure and its corresponding parts.

[0046] Figures 3A to 3H To illustrate another embodiment according to this disclosure Figure 1C A cross-sectional view of a semiconductor device and its manufacturing method. Figures 3A to 3H To show Figure 1C The diagram shows an enlarged cross-sectional view of a single memory cell among multiple memory cells in the semiconductor device. Since its structure is largely the same as that of the aforementioned embodiments, it will not be described again.

[0047] First, the manufacturing method will be explained.

[0048] refer to Figure 3A and Figure 3B The first wiring 310 can be formed on the substrate 300 in which the predetermined substructure is formed.

[0049] Subsequently, a bottom electrode contact 320 can be formed on the first wiring 310. The bottom electrode contact 320 can be formed as follows: a first interlayer insulating film 325 with recesses is formed on the structure formed by the first wiring 310; the recesses are filled with a material layer for forming the bottom electrode contact 320; and then a planarization process, such as a chemical or mechanical planarization process, is performed. The bottom electrode contact 320 may fill only a portion of the recess. If the bottom electrode contact 320 fills only a portion of the recess, the amount of filler material can be reduced, thereby shortening the process time and reducing costs. This formation method also helps to reduce potential internal stress. This formation method is very useful when the film is thicker, the greater the possibility of stress-induced cracking or deformation. Specifically, designing the bottom electrode contact 320 such that the bottom electrode contact 320 fills only a portion of the recess and offsetting the offset layer portion embedding can also create conditions that allow the offset layer to function more effectively.

[0050] refer to Figure 3C A material layer may first be deposited to form a spacer 326, which covers the inner wall of the recess and the surface of the first interlayer insulating film 325. The spacer 326 may be formed by partially removing the material layer used to form the spacer 326. The process for forming the spacer 326 may include anisotropic etching, isotropic etching, or a combination thereof.

[0051] The spacer 326 may comprise a material with etch selectivity relative to the first interlayer insulating film 325. The spacer 326 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. For example, the spacer 326 may comprise a material with poor step coverage and low conductivity. For example, the spacer 326 may comprise a material having carbon groups. The spacer 326 may comprise amorphous carbon or oxides, such as undoped silica glass (USG). The spacer 326 may be formed on the sidewalls of the recess. The lower surface of the spacer 326 may contact the bottom electrode contact 320. The top surface of the spacer 326 may be formed at a level lower than the top surface of the first interlayer insulating film 325. The sidewalls of the recess may be exposed at the top of the spacer 326. The bottom of the recess may expose the first interlayer insulating film 325.

[0052] Subsequently, a first electrode layer 327 can be formed in the recess. The formation of the first electrode layer 327 can be achieved using a thin film formation process and an etch-back process. The first electrode layer 327 may contain a conductive material, such as a metal, metal nitride, metal oxide, metal silicide, conductive carbon, or a combination thereof. For example, the first electrode layer 327 may contain TiN. The first electrode layer 327 may contact the bottom electrode contact 320. The top of the first electrode layer 327 may be formed at a level higher than the top of the spacer 326. The sides of the first electrode layer 327 may be surrounded by the spacer 326. The first electrode layer 327 may be constrained by the spacer 326. The top of the first electrode layer 327 may have various shapes, such as a recessed shape with a lower level towards the center, or a convex shape with a higher level towards the center. However, for simplicity, it is described as having a flat shape.

[0053] refer to Figure 3D A material layer for forming the offset cancellation layer 330 can be formed on the planarized first electrode layer 327 and the first interlayer insulating film 325, and a material layer for forming the spacer layer 340 can be formed on the offset cancellation layer 330. Subsequently, a material layer for forming the MTJ layer 350 (including a material layer for forming the fixed layer 351, a material layer for forming the tunnel barrier layer 352, and a material layer for forming the free layer 353) can be formed sequentially on top of the spacer layer 340. Subsequently, a material layer for forming the selector layer 360 and a material layer for forming the second electrode layer 361 can be formed.

[0054] refer to Figure 3E and Figure 3FA columnar hard mask layer 362 is deposited on the upper surface of the material layer used to form the second electrode layer 361. The columnar hard mask layer 362 serves as an etch stop layer to selectively etch the material layers used to form the offset offset layer 330, the spacer layer 340, the fixing layer 351, the tunnel barrier layer 352, the free layer 353, the selector layer 360, and the second electrode layer 361 to form a columnar patterned offset offset layer 330A, spacer layer 340A, fixing layer 351A, tunnel barrier layer 352A, free layer 353A, selector layer 360A, and second electrode layer 361A. The fixing layer 351A, tunnel barrier layer 352A, and free layer 353A may form an MTJ layer 350A. A variable resistance layer may contain such an MTJ layer 350A.

[0055] refer to Figure 3G and Figure 3H A second interlayer insulating film 365 can be formed, covering the sidewalls of the offset offset layer 330A, spacer layer 340A, selector layer 360A, second electrode layer 361A, and MTJ layer 350A (including fixed layer 351A, tunnel barrier layer 352A, and free layer 353A). Subsequently, a second wiring 380 can be formed on top of the memory cell. For example, the second electrode layer 361A may contain at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a rare earth metal (e.g., lutetium, platinum, etc.).

[0056] Through the above-described process, a semiconductor device according to an embodiment of this disclosure can be formed. (See again...) Figure 3H According to one embodiment of the present disclosure, a semiconductor device may be formed having a substrate 300, a first wiring 310, a bottom electrode contact 320, a spacer 326, a first electrode layer 327, an offset cancellation layer 330A, a spacer layer 340A, a selector layer 360A, a second electrode layer 361A, a second wiring 380, and an MTJ layer 350A (including a fixed layer 351A, a tunnel barrier layer 352A, and a free layer 353A). The semiconductor device further includes a first interlayer insulating film 325 covering the sidewalls of the bottom electrode contact 320, and a second interlayer insulating film 365 covering the sidewalls of the offset cancellation layer 330A, the spacer layer 340A, the selector layer 360A, the second electrode layer 361A, and the MTJ layer 350A (including the fixed layer 351A, the tunnel barrier layer 352A, and the free layer 353A). In this embodiment, all the advantages described in the foregoing embodiments are obtained.

[0057] By placing the offset cancellation layer 330A at the bottom of the MTJ layer 350A, the semiconductor device of this embodiment can provide a lower synthetic antiferromagnetic (SAF) structure (i.e., Figure 3HThe structure (a) is formed by the offset cancellation layer 330A, the spacer layer 340A, and the fixed layer 351A in sequence to provide strong vertical magnetic anisotropy (PMA), thereby enhancing the exchange bias field (Hex). By placing the SAF structure at the bottom, this embodiment improves the stability against external magnetic fields, thereby improving the reliability of data storage.

[0058] Furthermore, in this embodiment, the semiconductor device replaces the conventional multilayer offset cancellation layer (SCL layer) with an offset cancellation layer 330A. The offset cancellation layer 330A comprises a Co alloy, Fe alloy, Ni alloy, or Mn alloy containing at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals; or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy containing one of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B. This replacement allows the MTJ layer 350A to undergo high-temperature heat treatment, thereby promoting crystallization and significantly improving magnetoresistance (MR). In proposed multilayer SCL structures, interdiffusion within the SCL layer during high-temperature heat treatment leads to a decrease in synthetic antiferromagnetic (SAF) performance. However, in this embodiment, the multilayer SCL structure can be replaced with specific alloys, such as ordered phase alloys with bulk magnetic anisotropy, rare earth-transition metal (RE-TM) alloys, or ternary or quaternary Co alloys, Fe alloys, or Ni alloys containing specific elements, to improve the thermal stability of the SAF. The offset cancellation layer 330A, made from these specific alloys, exhibits superior magnetic properties compared to the proposed [FM / NM]*n structure, which enhances the structure in which the fixed layer 351A, tunnel barrier layer 352A, and free layer 353A are arranged in sequence (i.e., Figure 3H The magnetoresistance (MR) of the structure (b) in the example is increased. Therefore, the read / write efficiency of the semiconductor device can be greatly improved. Thus, the offset cancellation layer 330A of this embodiment can realize a high-performance spintronic device by simultaneously achieving a combination of exchange bias field (Hex) enhancement and magnetoresistance (MR) increase, and provides a solution to overcome the limitations of high-temperature thermal processing in conventional technologies.

[0059] Figure 3H The process structure can be the same as the above. Figure 1C The basic process structures are the same. That is, the substrate 300, the first wiring 310, the bottom electrode contact 320, the first interlayer insulating film 325, the offset cancellation layer 330A, the spacer layer 340A, the MTJ layer 350A, the selector layer 360A, the second interlayer insulating film 365, and the second wiring 380 can respectively correspond to Figure 1CThe substrate 100, first wiring 110, bottom electrode contact 120, first interlayer insulating film 125, offset cancellation layer 130, spacer layer 140, MTJ layer 150, selector layer 160, second interlayer insulating film 165, and second wiring 180 are included. Therefore, [details omitted]. Figure 1C A detailed description of the process structure and its corresponding parts.

[0060] According to the aforementioned semiconductor device and its manufacturing method, a lower SAF structure is formed by providing an offset cancellation layer below the MTJ layer. Simultaneously, the multilayer SCL structure with [FM / NM]*n can be replaced with an offset cancellation layer formed of a specific alloy, such as an ordered phase alloy with bulk magnetic anisotropy, a rare-earth transition metal (RE-TM) alloy, or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy containing specific elements. Therefore, the semiconductor device of this embodiment can provide strong vertical magnetic anisotropy (PMA), which enhances the exchange bias field (Hex) and simultaneously increases the magnetoresistance (MR) of the MTJ layer. This significantly improves the read / write efficiency of the semiconductor device.

[0061] According to the above embodiments of the present disclosure, a semiconductor device and its manufacturing method prevent SAF performance degradation that may occur during high-temperature heat treatment by using a specific alloy to form an offset offset layer (SCL), which provides stable exchange coupling and achieves high exchange bias field (Hex) and magnetoresistance (MR) even at high temperatures.

[0062] While this disclosure has been described above with reference to specific embodiments, those skilled in the art will understand that various modifications and improvements can be made without departing from the spirit and scope defined by the claims of this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: Substrate; An interlayer insulating film disposed on the substrate and having a recess that exposes a portion of the substrate; The bottom electrode contact BEC is embedded in at least a portion of the recess; The MTJ layer includes a fixed layer with a fixed magnetization direction disposed on the interlayer insulating film and the bottom electrode contact, a free layer with a variable magnetization direction, and a tunnel barrier layer disposed between the free layer and the fixed layer; MTJ refers to a magnetic tunnel junction. An offset cancellation layer having a magnetization direction that is antiparallel to the fixed layer. The offset cancellation layer comprises a magnetic alloy selected from the group consisting of: (i) Cobalt-based alloys or iron-based alloys, comprising at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf) and rare earth metals; (ii) A nickel-based alloy or a manganese-based alloy, comprising at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf), and rare earth metals; and (iii) A ternary or quaternary alloy containing Co, Fe or Ni, further containing one of platinum (Pt) or palladium (Pd), and at least one element selected from the group consisting of chromium (Cr), aluminum (Al), terbium (Tb), silicon (Si) and boron (B).

2. The semiconductor device of claim 1, wherein, The offset offset layer is located between the bottom electrode contact and the MTJ layer.

3. The semiconductor device of claim 1, wherein, The offset offset layer comprises a cobalt-Co based alloy.

4. The semiconductor device of claim 1, wherein, The offset offset layer comprises an iron-Fe-based alloy or a cobalt-Co-based alloy containing rare earth metals.

5. The semiconductor device of claim 1, wherein, The offset offset layer comprises a nickel-based alloy or a manganese-based alloy.

6. The semiconductor device of claim 1, further comprising: The spacer layer between the fixed layer and the offset offset layer The fixed layer and the offset cancellation layer are antiferromagnetically exchange-coupled through the spacer layer to form a synthetic antiferromagnetic SAF structure.

7. The semiconductor device of claim 6, wherein, The spacer layer comprises ruthenium (Ru), Ir, Cr, or a combination thereof.

8. The semiconductor device according to claim 6, wherein, The spacer layer has a thickness of at least 0.5 nm.

9. The semiconductor device according to claim 1, further comprising: An intermediate layer located between the fixed layer and the tunnel barrier layer.

10. The semiconductor device according to claim 9, wherein, The intermediate layer includes Co, Fe, Ni, B, noble metals, or combinations thereof.

11. The semiconductor device according to claim 1, further comprising: An electrode layer, which is disposed above the bottom electrode contact and embedded in the upper part of the recess, and A spacer is formed on one side of the electrode layer.

12. A method for manufacturing a semiconductor device, the method comprising: An interlayer insulating film is formed on the substrate; The interlayer insulating film is selectively etched to form a recess that exposes a portion of the substrate; A bottom electrode contact is formed that is embedded in at least a portion of the recess; as well as An offset cancellation layer and a variable resistance element are formed on the bottom electrode contact. The offset cancellation layer comprises a magnetic alloy selected from the group consisting of: (i) Cobalt-based alloys or iron-based alloys, comprising at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf) and rare earth metals; (ii) A nickel-based alloy or a manganese-based alloy, comprising at least one element selected from the group consisting of aluminum (Al), gallium (Ga), boron (B), iridium (Ir), zirconium (Zr), hafnium (Hf), and rare earth metals; and (iii) A ternary or quaternary alloy containing Co, Fe or Ni, further containing one of platinum (Pt) or palladium (Pd), and at least one element selected from the group consisting of chromium (Cr), aluminum (Al), terbium (Tb), silicon (Si) and boron (B).

13. The method according to claim 12, wherein, The variable resistor element comprises: An MTJ layer is formed, the MTJ layer comprising a fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a free layer with a variable magnetization direction, which are stacked sequentially on the offset cancellation layer, wherein MTJ refers to a magnetic tunnel junction.

14. The method according to claim 13, wherein, The offset cancellation layer has a magnetization direction that is opposite to and parallel to the fixed layer.

15. The method according to claim 13, wherein, The offset offset layer comprises a cobalt-Co based alloy.

16. The method according to claim 12, wherein, The offset offset layer comprises an iron-Fe based alloy or a cobalt-Co based alloy containing rare earth metals.

17. The method according to claim 12, wherein, The offset offset layer comprises a nickel-based alloy or a manganese-based alloy.

18. The method of claim 13, further comprising: A spacer layer is formed on the offset offset layer before the MTJ layer is formed. The fixed layer and the offset cancellation layer are antiferromagnetically exchange-coupled through the spacer layer to form a synthetic antiferromagnetic SAF structure.

19. The method according to claim 18, wherein, The spacer layer comprises ruthenium (Ru), Ir, Cr, or a combination thereof.

20. The method according to claim 18, wherein, The spacer layer has a thickness of at least 0.5 nm.

21. The method of claim 13, further comprising: An intermediate layer is formed between the fixed layer and the tunnel barrier layer.

22. The method according to claim 21, wherein, The intermediate layer includes Co, Fe, Ni, B, noble metals, or combinations thereof.

23. The method of claim 12, further comprising: An electrode layer is formed in the upper part of the recess, above the bottom electrode contact.

Images