A low-stress nitride epi wafer, method of making and optoelectronic device

Abstract

This invention relates to a low-stress nitride epitaxial wafer, its fabrication method, and optoelectronic devices. The low-stress nitride epitaxial wafer comprises a substrate, an n-type nitride layer, an n-type nitride barrier layer, a composite light-emitting layer, and a p-type nitride structure, sequentially stacked. Nucleation aggregation regions are spaced apart on the surface of the n-type nitride barrier layer away from the substrate. The composite light-emitting layer includes spaced composite nanostructures and light-emitting structures disposed between the composite nanostructures. This invention achieves isolation of the light-emitting structure through the composite nanostructures, enabling the light-emitting structure to utilize the quantum size confinement effect to reduce QCSE, thereby reducing stress distribution, improving the radiative recombination efficiency of electrons and holes, thus improving the luminous efficiency and brightness of the epitaxial wafer, reducing the full width at half maximum (FWHM) of the emission wavelength, and improving color purity for display applications.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic device technology, and relates to an epitaxial wafer structure, particularly a low-stress nitride epitaxial wafer, its preparation method, and an optoelectronic device. Background Technology

[0002] Blue and green Micro-LEDs use nitride semiconductors, while red Micro-LEDs use phosphide semiconductors. Combining different semiconductor materials increases the production difficulty and cost of RGB full-color Micro-LEDs. Compared to nitrides, phosphides have higher diffusion coefficients and surface recombination rates. The higher surface recombination rate and larger carrier diffusion length exacerbate surface recombination in phosphide devices. Furthermore, phosphides have poor temperature characteristics, exhibiting severe performance degradation at high temperatures. Therefore, the fabrication of Micro-LEDs using nitride materials shows greater promise.

[0003] Nitride LEDs typically employ multi-period quantum well layers and quantum barrier layers as their active layers. To enhance carrier confinement, the quantum barrier layer requires a high potential barrier. However, this leads to a significant lattice mismatch between the quantum well and quantum barrier layers. This large lattice mismatch corresponds to high stress, which greatly increases nonradiative recombination in the active layer and exacerbates the quantum-confined Stark effect (QCSE), affecting the radiative recombination efficiency of carriers. Therefore, nitride LEDs face problems of low efficiency and limited spectral width. Summary of the Invention

[0004] The purpose of this invention is to provide a low-stress nitride epitaxial wafer, its preparation method, and an optoelectronic device. This low-stress nitride epitaxial wafer can reduce the Stark effect by utilizing the quantum size confinement effect, reduce the stress distribution in the light-emitting structure, and improve the radiative recombination efficiency of electrons and holes, thereby improving the luminous efficiency and brightness of the epitaxial wafer, reducing the full width at half maximum (FWHM) of the emission wavelength, and improving the color purity for display applications.

[0005] To achieve this objective, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a low-stress nitride epitaxial wafer, the low-stress nitride epitaxial wafer comprising:

[0007] Substrate.

[0008] An n-type nitride layer is disposed on the substrate.

[0009] An n-type nitride barrier layer is disposed on the n-type nitride layer; wherein, nucleation aggregation regions are distributed at intervals on the surface of the n-type nitride barrier layer away from the substrate, and the surface of the n-type nitride barrier layer away from the substrate where the nucleation aggregation regions are not distributed is a non-nucleation aggregation region.

[0010] Multiple spaced composite nanostructures are disposed on the nucleation and aggregation region of the n-type nitride barrier layer; wherein each composite nanostructure includes a semiconductor nanopillar and a nanostructure disposed on the semiconductor nanopillar.

[0011] Multiple spaced n-type nitride low-barrier structures cover the non-nucleation aggregation region.

[0012] Multiple spaced-apart light-emitting structures are disposed on the n-type nitride low-barrier structure.

[0013] Multiple p-type nitride structures are spaced apart and disposed on the light-emitting structure.

[0014] The low-stress nitride epitaxial wafer provided by this invention achieves the isolation of the light-emitting structure through the setting of a composite nano-segmentation structure with spaced distribution. This enables the reduction of QCSE by utilizing the quantum size confinement effect, thereby reducing stress distribution, improving the radiative recombination efficiency of electrons and holes, improving the luminous efficiency and brightness of the epitaxial wafer, reducing the half-width at half maximum (WHM) of the emission wavelength, and improving the color purity for display applications.

[0015] Preferably, the n-type nitride low-barrier structure corresponds one-to-one with the non-nucleation aggregation region.

[0016] The luminescent structure corresponds one-to-one with the low-barrier structure of the n-type nitride.

[0017] Preferably, the top surface of the composite nano-sparging structure is lower than the top surface of the p-type nitride structure.

[0018] Preferably, the top surface of the semiconductor nanopillar is higher than the top surface of the light-emitting structure.

[0019] Preferably, the barrier of the n-type nitride low barrier structure is smaller than the barrier of the n-type nitride barrier layer.

[0020] Preferably, the low-stress nitride epitaxial wafer further includes a p-type nitride top layer, which is conformally disposed to cover the surfaces of the p-type nitride structure and the nanostructure.

[0021] Preferably, the low-stress nitride epitaxial wafer further includes a nitride nucleation layer and a nitride buffer layer stacked together; the nitride nucleation layer is disposed on the substrate, and the nitride buffer layer is covered by the n-type nitride layer.

[0022] Preferably, the depth of the nucleation aggregation region is 1 nm to 2 nm, and the longitudinal and / or transverse width of the nucleation aggregation region is 0.5 μm to 1 μm.

[0023] Preferably, the semiconductor nanopillars are made of silicon.

[0024] Preferably, the height of the semiconductor nanopillars is 35 nm to 400 nm.

[0025] Preferably, the distance between any two adjacent composite nanostructures is 5 μm to 50 μm.

[0026] Preferably, the material of the nanostructure includes aluminum oxide.

[0027] Secondly, the present invention provides a method for preparing a low-stress nitride epitaxial wafer, the method comprising the following steps:

[0028] An n-type nitride layer and an n-type nitride barrier layer are sequentially prepared on the surface of a substrate; wherein, the n-type nitride barrier layer has nucleation aggregation regions distributed at intervals on the surface away from the substrate, and the n-type nitride barrier layer without nucleation aggregation regions is a non-nucleation aggregation region on the surface away from the substrate.

[0029] Multiple spaced composite nanostructures and multiple spaced n-type nitride low-barrier structures are fabricated on the n-type nitride barrier layer; wherein, the composite nanostructures are disposed on the nucleation and aggregation regions of the n-type nitride barrier layer, and each composite nanostructure includes a semiconductor nanopillar and a nanostructure disposed on the semiconductor nanopillar; the n-type nitride low-barrier structures cover the non-nucleation and aggregation regions.

[0030] A light-emitting structure was prepared on the n-type nitride low-barrier structure.

[0031] A p-type nitride structure is prepared on the surface of the light-emitting structure away from the substrate.

[0032] The low-stress nitride epitaxial wafer prepared by the second aspect of the present invention achieves the isolation of the light-emitting structure through the setting of a composite nano-segmentation structure, so that the light-emitting structure can reduce the QCSE by utilizing the quantum size confinement effect, thereby reducing the stress distribution, improving the radiative recombination efficiency of electrons and holes, thereby improving the luminous efficiency and luminous brightness of the epitaxial wafer, reducing the half-width at half maximum of the emission wavelength, and improving the color purity of display applications.

[0033] Preferably, the method for preparing the n-type nitride barrier layer includes:

[0034] An initial n-type nitride barrier layer is prepared on the substrate.

[0035] Silicon ion implantation is performed using an energy of 10keV to 50keV to form nucleation aggregation regions with a depth of 1nm to 2nm and a longitudinal and / or lateral width of 0.5μm to 1μm on the surface of the initial n-type nitride barrier layer away from the substrate, thereby obtaining the n-type nitride barrier layer.

[0036] Preferably, the preparation method includes:

[0037] The composite nanostructure is prepared on each nucleation aggregation region of the n-type nitride barrier layer.

[0038] The n-type nitride low barrier structure is prepared on each non-nucleation aggregation region of the n-type nitride barrier layer.

[0039] The luminescent structure is prepared on each of the n-type nitride low-barrier structures.

[0040] The p-type nitride structure is prepared on each of the light-emitting structures.

[0041] Preferably, the fabrication of the n-type nitride low-barrier structure on each non-nucleation aggregation region of the n-type nitride barrier layer includes:

[0042] Under conditions of temperature ranging from 1050°C to 1150°C and pressure ranging from 200 to 400 torr, Si doping concentration of 2 × 10⁻⁶ is grown on the surface of the non-nucleation aggregation region. 17 cm -3 Up to 8×10 17 cm -3 Low barrier n-type nitride structures with a thickness of 20 nm to 120 nm.

[0043] Preferably, the preparation method further includes: growing a p-type nitride top layer, such that the p-type nitride top layer conformally covers the surface of the p-type nitride structure and the nanostructure.

[0044] Preferably, the growth of the p-type nitride top layer includes: subjecting the nanostructure to nitriding at a temperature of 900°C to 1050°C and a pressure of 400 torr to 600 torr; and then growing a Mg doping concentration of 5 × 10⁻⁶ nm on the p-type nitride layer with a thickness of 100 nm to 300 nm on the p-type nitride layer at a temperature of 720°C to 850°C and a pressure of 400 torr to 600 torr. 19 cm -3 Up to 1×1021 cm -3 The top layer of the p-type nitride.

[0045] Preferably, the fabrication of the composite nanostructure on each nucleation and aggregation region of the n-type nitride barrier layer includes:

[0046] S1. An aluminum metal capping layer with a thickness of 10 nm to 200 nm is grown on the surface of the n-type nitride barrier layer; then, the aluminum metal capping layer is annealed for 60 s to 300 s at a temperature of 500 °C to 1000 °C and a pressure of 50 torr to 150 torr to form a microstructure in the nucleation and aggregation region.

[0047] S2. The microstructure is subjected to silicon heat treatment for 100s to 600s at a temperature of 500℃ to 1000℃ and a pressure of 200 torr to 600 torr to obtain a nanosphere structure.

[0048] S3. Semiconductor nanopillars are grown based on the nanosphere structure.

[0049] S4. Post-process the semiconductor nanopillars to obtain the composite nano-spacing structure.

[0050] Preferably, the material of the nanostructure includes aluminum oxide, and the post-processing of the semiconductor nanopillars to obtain the composite nanostructure includes:

[0051] S41. Under conditions of temperature of 400°C to 800°C and pressure of 200 to 600 tor, perform oxygen treatment for 60 to 120 seconds to form a nanostructure of aluminum oxide material on the top surface of the semiconductor nanopillar.

[0052] S42. Under conditions of temperature of 400°C to 800°C and pressure of 200 torr to 600 torr, perform hydrogen treatment for 20 to 60 seconds to decompose the oxygen element on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars.

[0053] The composite nano-segmentation structure is obtained by repeating S41 and S42 cyclically 20 to 100 times.

[0054] Preferably, the growth of semiconductor nanopillars based on the nanosphere structure includes:

[0055] S31. The nanosphere structure is heat-treated for 10s to 100s at a temperature of 500℃ to 1000℃ and a pressure of 200 torr to 600 torr.

[0056] S32. Interrupt the heat treatment for 10s to 180s.

[0057] S33. S31 and S32 are periodically and alternately executed 100 to 1000 times to obtain the semiconductor nanopillar.

[0058] Preferably, the method for preparing the light-emitting structure includes:

[0059] A1. Under conditions of temperature of 650℃ to 750℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a quantum well layer with a thickness of 0.5 nm to 3 nm.

[0060] A2. Under conditions of temperature of 750℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a quantum barrier layer with a thickness of 5 nm to 15 nm.

[0061] A3. The light-emitting structure is obtained by periodically alternating between A1 and A2 2 to 15 times.

[0062] Preferably, the preparation of the p-type nitride structure on each of the light-emitting structures includes:

[0063] Under conditions of 750°C to 950°C and 400 torr to 600 torr, a gallium source with a flow rate of 100 sccm to 1000 sccm and a nitrogen source with a flow rate of 20 slm to 80 slm are introduced to grow a nitride light-emitting layer with a thickness of 20 nm to 800 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 Up to 5×10 20 cm -3 The p-type nitride structure described above.

[0064] Preferably, the preparation method further includes:

[0065] A nitride nucleation layer is prepared on the surface of a substrate.

[0066] A nitride buffer layer is prepared on the surface of the nitride nucleation layer.

[0067] The n-type nitride layer is prepared on the nitride buffer layer.

[0068] Preferably, the preparation of the nitride nucleation layer on the surface of the substrate includes:

[0069] A nitride nucleation layer with a thickness of 10 nm to 200 nm is grown on the substrate under conditions of temperature of 500 °C to 900 °C and pressure of 200 torr to 600 torr.

[0070] Preferably, a nitride buffer layer is prepared on the surface of the nitride nucleation layer, comprising:

[0071] A nitride buffer layer with a thickness of 1 μm to 3 μm is grown on the nitride nucleation layer under conditions of temperature of 1050°C to 1150°C and pressure of 100 torr to 300 torr.

[0072] Preferably, the method for preparing the n-type nitride layer includes:

[0073] Under conditions of temperature from 1050°C to 1150°C and pressure from 100 to 300 torr, a silicon doping concentration of 1×10⁻⁶ is grown on the nitride buffer layer with a thickness of 2 μm to 5 μm. 18 cm -3 Up to 1×10 20 cm -3 The n-type nitride layer.

[0074] Preferably, the method for preparing the initial n-type nitride barrier layer includes:

[0075] Under conditions of temperature ranging from 1070℃ to 1200℃ and pressure ranging from 50 to 250 torr, a growth thickness of 2nm to 20nm and a silicon doping concentration of 5×10⁻⁶ were achieved. 17 cm -3 Up to 5×10 18 cm -3 The initial n-type nitride barrier layer.

[0076] Thirdly, the present invention provides an optoelectronic device, the optoelectronic device comprising the low-stress nitride epitaxial wafer described in the first aspect, or a low-stress nitride epitaxial wafer prepared by the preparation method described in the second aspect.

[0077] Preferably, the optoelectronic device includes a low-stress nitride epitaxial wafer and a P-electrode, wherein the upper surface of the low-stress nitride epitaxial wafer has multiple recessed regions, and the P-electrode is disposed within the recessed regions.

[0078] Compared with the prior art, the present invention has the following beneficial effects:

[0079] The low-stress nitride epitaxial wafer provided by this invention achieves the isolation of the light-emitting structure through the setting of a composite nano-segmentation structure with spaced distribution. This enables the reduction of QCSE by utilizing the quantum size confinement effect, thereby reducing stress distribution, improving the radiative recombination efficiency of electrons and holes, improving the luminous efficiency and brightness of the epitaxial wafer, reducing the half-width at half maximum (WHM) of the emission wavelength, and improving the color purity for display applications. Attached Figure Description

[0080] Figure 1 This is a schematic diagram of the structure of the optoelectronic device provided in Embodiment 1 of the present invention.

[0081] Figure 2 This is a schematic diagram of the structure of the optoelectronic device provided in Embodiment 2 of the present invention.

[0082] Wherein: 1, substrate; 2, nitride nucleation layer; 3, nitride buffer layer; 4, n-type nitride layer; 5, n-type nitride barrier layer; 6, nucleation aggregation region; 71, composite nanostructure; 72, nanostructure; 81, n-type nitride low barrier structure; 82, light-emitting structure; 83, p-type nitride structure; 9, p-type nitride top layer; 10, p-electrode. Detailed Implementation

[0083] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0084] An embodiment of the present invention provides a low-stress nitride epitaxial wafer, which includes: a substrate, an n-type nitride layer, an n-type nitride barrier layer, a plurality of spaced composite nanostructures, a plurality of spaced n-type nitride low barrier structures, a plurality of spaced light-emitting structures, and a plurality of spaced p-type nitride structures.

[0085] Substrate.

[0086] An n-type nitride layer is disposed on the substrate.

[0087] An n-type nitride barrier layer is disposed on an n-type nitride layer; wherein, nucleation aggregation regions are distributed at intervals on the surface of the n-type nitride barrier layer away from the substrate, and the surface of the n-type nitride barrier layer away from the substrate without nucleation aggregation regions is a non-nucleation aggregation region.

[0088] The composite nano-sparging structure is disposed on the nucleation and aggregation region of the n-type nitride barrier layer; wherein, each composite nano-sparging structure includes a semiconductor nanopillar and a nanostructure disposed on the semiconductor nanopillar.

[0089] n-type nitride low-barrier structures cover non-nucleation aggregation regions.

[0090] The light-emitting structure is set on an n-type nitride low-barrier structure.

[0091] The p-type nitride structure is set on the light-emitting structure.

[0092] The low-stress nitride epitaxial wafer provided by this invention achieves the isolation of the light-emitting structure through the setting of a composite nano-segmentation structure with spaced distribution. This enables the reduction of QCSE by utilizing the quantum size confinement effect, thereby reducing stress distribution, improving the radiative recombination efficiency of electrons and holes, improving the luminous efficiency and brightness of the epitaxial wafer, reducing the half-width at half maximum (WHM) of the emission wavelength, and improving the color purity for display applications.

[0093] In the low-stress nitride epitaxial wafer provided by this invention, the n-type nitride barrier layer plays a role in lateral diffusion and longitudinal blocking of electrons injected into the light-emitting structure, which improves the uniformity of electron injection distribution and slows down the electron injection rate, enabling electrons to effectively recombine with holes in the light-emitting structure to emit light.

[0094] In some embodiments, the n-type nitride low-barrier structure corresponds one-to-one with the non-nucleation aggregation region; the luminescent structure corresponds one-to-one with the n-type nitride low-barrier structure.

[0095] In some embodiments, the top surface of the composite nano-sparger structure is lower than the top surface of the p-type nitride structure.

[0096] In some embodiments, the top surface of the semiconductor nanopillar is higher than the top surface of the light-emitting layer.

[0097] This invention places the top surface of the semiconductor nanopillar above the top surface of the light-emitting structure, which avoids the electrodes directly connecting the p-type nitride structure and the n-type nitride low barrier layer, thus ensuring smooth light emission.

[0098] In some embodiments, the barrier of the n-type nitride low-barrier structure is smaller than the barrier of the n-type nitride barrier layer.

[0099] In this invention, the barrier of the n-type nitride barrier layer is higher than that of the n-type nitride low-barrier structure. The resulting high electron barrier serves to diffuse electron injection and also prevents electron injection backflow, improving electron injection uniformity. Furthermore, it utilizes dislocation coarse blocking to reduce the extension of dislocations from the n-type nitride layer into the light-emitting structure, thereby improving radiative recombination. The n-type nitride low-barrier structure acts as both a lateral diffuser and a longitudinal barrier to electrons injected into the light-emitting structure, improving the uniformity of electron injection distribution and slowing down the electron injection rate, allowing electrons to effectively recombine with holes in the light-emitting structure to emit light.

[0100] In some embodiments, the low-stress nitride epitaxial wafer further includes a p-type nitride top layer, which is conformally configured to cover the surface of the p-type nitride structure and the nanostructure.

[0101] In this invention, the arrangement of the n-type nitride low barrier structure, the light-emitting structure, and the p-type nitride structure enables the sidewalls of the p-type nitride top layer to cover the electrode when the electrode is formed on the low-stress nitride epitaxial wafer. This enhances the electrode's ability to extend the current of the p-type nitride top layer, improves the brightness of the device, and reduces the voltage.

[0102] In some embodiments, the low-stress nitride epitaxial wafer further includes a nitride nucleation layer and a nitride buffer layer stacked together; the nitride nucleation layer is disposed on the substrate, and the nitride buffer layer is covered by an n-type nitride layer.

[0103] In some embodiments, the depth of the nucleation aggregation region is 1 nm to 2 nm, and the longitudinal and / or lateral width of the nucleation aggregation region is 0.5 μm to 1 μm.

[0104] The depth of the nucleation and aggregation region is 1 nm to 2 nm, for example, it can be 1 nm, 1.2 nm, 1.5 nm, 1.8 nm or 2 nm; the longitudinal and / or transverse width of the nucleation and aggregation region is 0.5 μm to 1 μm, for example, it can be 0.5 μm, 0.6 μm, 0.8 μm, 0.9 μm or 1 μm.

[0105] In some embodiments, the semiconductor nanopillars are made of silicon.

[0106] In some embodiments, the height of the semiconductor nanopillars is from 35 nm to 400 nm, for example, it can be 35 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm or 400 nm.

[0107] In some embodiments, the distance between any two adjacent composite nanostructures is 5 μm to 50 μm, for example, it can be 5 μm, 10 μm, 20 μm, 30 μm, 40 μm or 50 μm.

[0108] In this invention, the distance between any two adjacent composite nanostructures refers to the distance between the nearest edges of any two adjacent composite nanostructures.

[0109] In some embodiments, the material of the nanostructure includes aluminum oxide, such as Al2O3.

[0110] An embodiment of the present invention provides a method for preparing a low-stress nitride epitaxial wafer, the method comprising the following steps:

[0111] S1: An n-type nitride layer and an n-type nitride barrier layer are sequentially prepared on the surface of a substrate; wherein, the surface of the n-type nitride barrier layer away from the substrate has nucleation aggregation regions distributed at intervals, and the surface of the n-type nitride barrier layer without nucleation aggregation regions is a non-nucleation aggregation region away from the substrate.

[0112] S2: Multiple spaced composite nano-segmentation structures and multiple spaced n-type nitride low-barrier structures are prepared on an n-type nitride barrier layer; wherein, the composite nano-segmentation structures are disposed on the nucleation and aggregation regions of the n-type nitride barrier layer, and each composite nano-segmentation structure includes a semiconductor nanopillar and a nanostructure disposed on the semiconductor nanopillar; the n-type nitride low-barrier structures cover the non-nucleation and aggregation regions.

[0113] S3: Prepare a light-emitting structure on an n-type nitride low-barrier structure.

[0114] S4: Prepare a p-type nitride structure on the surface of the light-emitting structure away from the substrate.

[0115] In some embodiments, the above preparation method further includes: preparing a nitride nucleation layer on the surface of a substrate; preparing a nitride buffer layer on the surface of the nitride nucleation layer; and preparing an n-type nitride layer on the nitride buffer layer.

[0116] In some embodiments, a nitride nucleation layer is prepared on the surface of the substrate, including:

[0117] Nitride nucleation layers with a thickness of 10 nm to 200 nm are grown on a substrate under conditions of temperature of 500 °C to 900 °C and pressure of 200 torr to 600 torr.

[0118] The temperature for growing the nitride nucleation layer is between 500℃ and 900℃, for example, it can be 500℃, 600℃, 700℃, 800℃ or 900℃.

[0119] The pressure for growing the nitride nucleation layer is 200 torr to 600 torr, for example, 200 torr, 300 torr, 400 torr, 500 torr or 600 torr.

[0120] The thickness of the nitride nucleation layer is 10 nm to 200 nm, for example, it can be 10 nm, 50 nm, 100 nm, 150 nm or 200 nm.

[0121] In some embodiments, a nitride buffer layer is prepared on the surface of the nitride nucleation layer, including: growing a nitride buffer layer with a thickness of 1 μm to 3 μm on the nitride nucleation layer at a temperature of 1050°C to 1150°C and a pressure of 100 torr to 300 torr.

[0122] The temperature for growing the nitride buffer layer is between 1050℃ and 1150℃, for example, it can be 1050℃, 1080℃, 1100℃, 1120℃ or 1150℃.

[0123] The pressure for growing the nitride buffer layer is 100 torr to 300 torr, for example, it can be 100 torr, 150 torr, 200 torr, 250 torr or 300 torr.

[0124] The thickness of the nitride buffer layer is 1 μm to 3 μm, for example, it can be 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm.

[0125] In some embodiments, the method for preparing the n-type nitride layer includes: growing a nitride buffer layer with a thickness of 2 μm to 5 μm and a silicon doping concentration of 1 × 10⁻⁶ on a nitride buffer layer at a temperature of 1050°C to 1150°C and a pressure of 100 torr to 300 torr. 18 cm -3 Up to 1×10 20 cm -3 The n-type nitride layer.

[0126] The temperature for growing the n-type nitride layer is between 1050℃ and 1150℃, for example, it can be 1050℃, 1080℃, 1100℃, 1120℃ or 1150℃.

[0127] The pressure for growing the n-type nitride layer is 100 torr to 300 torr, for example, it can be 100 torr, 150 torr, 200 torr, 250 torr or 300 torr.

[0128] The thickness of the n-type nitride layer is 2 μm to 5 μm, for example, it can be 2 μm, 3 μm, 4 μm or 5 μm.

[0129] The silicon doping concentration of the n-type nitride layer is 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 For example, it could be 1×10 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 5×10 19 cm -3 Or 1×10 20 cm -3 wait.

[0130] In some embodiments, the method for preparing an n-type nitride barrier layer includes: preparing an initial n-type nitride barrier layer on a substrate; and performing silicon ion implantation using an energy of 10 keV to 50 keV to form nucleation aggregation regions with a depth of 1 nm to 2 nm and a longitudinal and / or lateral width of 0.5 μm to 1 μm on the surface of the initial n-type nitride barrier layer away from the substrate, thereby obtaining an n-type nitride barrier layer.

[0131] Furthermore, the depth of the nucleation aggregation region is 1 nm to 2 nm, for example, it can be 1 nm, 1.2 nm, 1.5 nm, 1.8 nm or 2 nm; the longitudinal and / or transverse width of the nucleation aggregation region is 0.5 μm to 1 μm, for example, it can be 0.5 μm, 0.6 μm, 0.8 μm, 0.9 μm or 1 μm.

[0132] In one embodiment, the method for preparing the initial n-type nitride barrier layer includes: growing a thickness of 2 nm to 20 nm and a silicon doping concentration of 5 × 10⁻⁶ under conditions of a temperature of 1070 °C to 1200 °C and a pressure of 50 torr to 250 torr. 17 cm -3 Up to 5×10 18 cm -3 The initial n-type nitride barrier layer.

[0133] The temperature for preparing the initial n-type nitride barrier layer is between 1070℃ and 1200℃, for example, it can be 1070℃, 1100℃, 1120℃, 1150℃, 1180℃ or 1200℃.

[0134] The pressure for preparing the initial n-type nitride barrier layer is 50 torr to 250 torr, for example, it can be 50 torr, 100 torr, 150 torr, 200 torr or 250 torr.

[0135] The initial n-type nitride barrier layer has a thickness of 2 nm to 20 nm, for example, it can be 2 nm, 5 nm, 10 nm, 15 nm or 20 nm.

[0136] The initial silicon doping concentration of the n-type nitride barrier layer is 5 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 For example, it could be 5×10 17 cm -3 1×10 18 cm -3 2×10 18 cm -3 3×10 18 cm -3 4×1018 cm -3 Or 5×10 18 cm -3 wait.

[0137] In some embodiments, the above preparation method includes: preparing a composite nano-sparing structure on each nucleation aggregation region of the n-type nitride barrier layer; preparing an n-type nitride low barrier structure on each non-nucleation aggregation region of the n-type nitride barrier layer; preparing a luminescent structure on each n-type nitride low barrier structure; and preparing a p-type nitride structure on each luminescent structure.

[0138] In some embodiments, the fabrication of n-type nitride low-barrier structures on each non-nucleation aggregation region of the n-type nitride barrier layer includes: growing Si doping concentrations of 2 × 10⁻⁶ on the surface of the non-nucleation aggregation regions at a temperature of 1050°C to 1150°C and a pressure of 200 torr to 400 torr. 17 cm -3 Up to 8×10 17 cm -3 Low barrier n-type nitride structures with a thickness of 20 nm to 120 nm.

[0139] The temperature for preparing the n-type nitride low barrier structure is 1050℃ to 1150℃, for example, 1050℃, 1080℃, 1100℃, 1120℃ or 1150℃.

[0140] The pressure for preparing the low barrier structure of n-type nitride is 200 torr to 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0141] The Si doping concentration for the n-type nitride low-barrier structure is 2 × 10⁻⁶. 17 cm -3 Up to 8×10 17 cm -3 For example, it could be 2×10 17 cm -3 4×10 17 cm -3 5×10 17 cm -3 6×10 17 cm -3 Or 8×10 17 cm -3 wait.

[0142] The thickness of the n-type nitride low barrier structure is 20 nm to 120 nm, for example, it can be 20 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm or 120 nm.

[0143] In some embodiments, composite nanostructures are fabricated on each nucleation aggregation region of the n-type nitride barrier layer, including:

[0144] S1. An aluminum metal capping layer with a thickness of 10 nm to 200 nm is grown on the surface of an n-type nitride barrier layer; then, the aluminum metal capping layer is annealed for 60 s to 300 s at a temperature of 500 °C to 1000 °C and a pressure of 50 torr to 150 torr to form microstructures in the nucleation and aggregation regions.

[0145] The thickness of the aluminum metal coating ranges from 10nm to 200nm, for example, it can be 10nm, 50nm, 80nm, 100nm, 150nm or 200nm.

[0146] The temperature required for annealing is between 500°C and 1000°C, for example, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C.

[0147] The pressure required for annealing is between 50 torr and 150 torr, for example, 50 torr, 60 torr, 80 torr, 100 torr, 120 torr or 150 torr.

[0148] The annealing time for the aluminum metal coating is 60s to 300s, for example, 60s, 100s, 150s, 200s, 250s or 300s.

[0149] S2. Under conditions of 500℃ to 1000℃ and 200 torr to 600 torr, the microstructure is subjected to silicon heat treatment for 100s to 600s to obtain nanosphere structures.

[0150] The temperature required for silicon heat treatment is between 500°C and 1000°C, for example, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C.

[0151] The pressure required for silicon heat treatment is between 200 torr and 600 torr, for example, 200 torr, 300 torr, 400 torr, 500 torr or 600 torr.

[0152] The time specified in the conditions for silicon heat treatment is between 100s and 600s, for example, it can be 100s, 200s, 300s, 400s, 500s or 600s, etc.

[0153] S3. Semiconductor nanopillars grown based on nanosphere structure.

[0154] S4. Post-process the semiconductor nanopillars to obtain a composite nanostructure.

[0155] The present invention introduces silicon atoms on the surface of the microstructure through silicon heat treatment in step S2, and utilizes the solvent precipitation of silicon atoms in the microstructure, which is beneficial for the growth of semiconductor nanopillars.

[0156] In some embodiments, semiconductor nanopillars are grown based on nanosphere structures, including:

[0157] S31. The nanosphere structure is heat-treated for 10s to 100s at a temperature of 500℃ to 1000℃ and a pressure of 200 torr to 600 torr.

[0158] The required temperature for heat treatment is between 500°C and 1000°C, for example, 500°C, 600°C, 800°C, 900°C, or 1000°C.

[0159] The pressure required for heat treatment is between 200 torr and 600 torr, for example, 200 torr, 300 torr, 400 torr, 500 torr, or 600 torr.

[0160] The required time for heat treatment is between 10s and 100s, for example, it could be 10s, 30s, 50s, 60s, 80s, or 100s.

[0161] S32, interrupt heat treatment for 10s to 180s.

[0162] The interruption time for heat treatment can be 10s, 30s, 50s, 60s, 80s, 100s, 120s, 150s, or 180s, etc.

[0163] S33, and S31 and S32 are periodically and alternately executed 100 to 1000 times to obtain semiconductor nanopillars.

[0164] In step S31, the heat treatment is performed under conditions where a silicon source is introduced, and the silicon source can be SiH4. The number of times S31 and S32 are periodically and alternately executed is 100 to 1000 times, for example, 100 times, 300 times, 500 times, 600 times, 800 times, or 1000 times.

[0165] The raw materials Ga, N, Al, Si, Mg, and O required for the embodiments are not specifically limited. Commercially available mature precursor materials can meet the process requirements and are set according to actual conditions. In the process of growing semiconductor nanopillars based on nanosphere structures, the present invention interrupts the heat treatment to allow silicon atoms to fully dissolve and continuously and uniformly precipitate, resulting in semiconductor nanopillars with smooth surfaces. This avoids the diffusion of freely moving silicon atoms to the top p-type nitride structure, reduces nonradiative recombination of charge carriers, and improves the performance of low-stress nitride epitaxial wafers.

[0166] In some embodiments, the nanostructure is made of aluminum oxide, and the semiconductor nanopillars are post-processed to obtain a composite nanostructure, including:

[0167] S41. Under conditions of temperature of 400°C to 800°C and pressure of 200 to 600 tor, perform oxygen treatment for 60 to 120 seconds to form a nanostructure with aluminum oxide material on the top surface of the semiconductor nanopillar.

[0168] Temperatures can be 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, or 800℃, etc. Pressures can be 200 torr, 300 torr, 400 torr, 500 torr, or 600 torr, etc.

[0169] The oxygen treatment time can be 60s, 80s, 90s, 100s, or 120s, etc.

[0170] S42. Under conditions of 400°C to 800°C and 200 torr to 600 torr, perform hydrogen treatment for 20 to 60 seconds to decompose the oxygen element on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars.

[0171] Temperatures can be 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, or 800℃, etc. Pressures can be 200 torr, 300 torr, 400 torr, 500 torr, or 600 torr, etc.

[0172] The hydrogen treatment time can be 20s, 30s, 40s, 50s, or 60s, etc.

[0173] Hydrogen treatment decomposes oxygen elements on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars, preventing the formation of oxygen impurities in the n-type nitride barrier layer, reducing the light absorption of oxygen impurities, improving the crystal quality of the n-type nitride barrier layer, reducing the extension of dislocations into the light-emitting unit, and improving the radiative recombination efficiency in the light-emitting structure.

[0174] S43, S41 and S42 are periodically cyclically alternated 20 to 100 times to obtain a composite nano-sparing structure.

[0175] The number of cyclical alternations ranges from 20 to 100 times, for example, 20, 40, 50, 60, 80, or 100 times.

[0176] In some embodiments, the method for preparing the light-emitting structure includes:

[0177] A1. Under conditions of temperature of 650℃ to 750℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a quantum well layer with a thickness of 0.5 nm to 3 nm.

[0178] The temperature for growing the quantum well layer is 650°C to 750°C, for example, it can be 650°C, 680°C, 700°C, 720°C or 750°C.

[0179] The pressure for growing the quantum well layer is between 200 torr and 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0180] The gallium source flow rate is from 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm or 500 sccm.

[0181] The indium source flow rate is from 500 sccm to 2000 sccm, for example, it can be 500 sccm, 600 sccm, 800 sccm, 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm or 2000 sccm, etc.

[0182] The nitrogen source flow rate is 50 slm to 100 slm, for example, it can be 50 slm, 60 slm, 80 slm, 90 slm or 100 slm, etc.

[0183] The thickness of the quantum well layer is 0.5 nm to 3 nm, for example, it can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm.

[0184] A2. Under conditions of temperature of 750℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a quantum barrier layer with a thickness of 5 nm to 15 nm.

[0185] The temperature for growing the quantum barrier layer is between 750°C and 950°C, for example, it can be 750°C, 800°C, 850°C, 900°C or 950°C.

[0186] The pressure for growing the quantum barrier layer is between 200 torr and 400 torr, for example, it can be 200 torr, 250 torr, 300 torr, 350 torr or 400 torr.

[0187] The flow rate of the gallium source is from 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm or 500 sccm.

[0188] The flow rate of the nitrogen source is 50 slm to 100 slm, for example, it can be 50 slm, 60 slm, 80 slm, 90 slm or 100 slm, etc.

[0189] The thickness of the grown quantum barrier layer is 5nm to 15nm, for example, it can be 5nm, 8nm, 9nm, 10nm, 12nm or 15nm.

[0190] A3. Periodically and alternately execute A1 and A2 2 to 15 times to obtain the light-emitting structure.

[0191] The number of times A1 and A2 are executed alternately in a periodic cycle is 2 to 15 times, for example, 2, 4, 5, 6, 8, 10, 12 or 15 times.

[0192] In some embodiments, a p-type nitride structure is fabricated on each light-emitting structure, comprising: introducing a gallium source with a flow rate of 100 sccm to 1000 sccm and a nitrogen source with a flow rate of 20 slm to 80 slm at a temperature of 750°C to 950°C and a pressure of 400 torr to 600 torr, and growing a Mg doping concentration of 1 × 10⁻⁶ nm with a thickness of 20 nm to 800 nm on the surface of the nitride light-emitting layer. 19 cm -3 Up to 5×10 20 cm -3 The p-type nitride structure.

[0193] The temperature for preparing p-type nitride structures is between 750°C and 950°C, for example, 750°C, 800°C, 850°C, 900°C, or 950°C.

[0194] The pressure for preparing the p-type nitride structure is 400 torr to 600 torr, for example, 400 torr, 450 torr, 500 torr, 550 torr or 600 torr.

[0195] The gallium source flux for preparing p-type nitride structures is 100 sccm to 1000 sccm, for example, it can be 100 sccm, 300 sccm, 500 sccm, 800 sccm or 1000 sccm.

[0196] The nitrogen source flux for preparing p-type nitride structures is 20 slm to 80 slm, for example, it can be 20 slm, 40 slm, 50 slm, 60 slm or 80 slm.

[0197] The thickness of the prepared p-type nitride structure is 20 nm to 800 nm, for example, it can be 20 nm, 100 nm, 200 nm, 400 nm, 500 nm, 600 nm or 800 nm.

[0198] The Mg doping concentration of the prepared p-type nitride structure was 1×10⁻⁶. 19 cm -3 Up to 5×10 20 cm -3 For example, it could be 1×10 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 Or 5×10 20 cm -3 wait.

[0199] In the p-type nitride structure of the present invention, the Mg doping concentration is relatively low, which plays a role in the lateral expansion of current and can also reduce the absorption of light from the nitride light-emitting layer to the p-type nitride structure by the interstitial atoms of Mg impurities. Moreover, the relatively low doping concentration reduces the lattice distortion of the p-type nitride structure, interrupts the dislocation connectivity between the nitride light-emitting layer and the top p-type nitride, and improves ESD and leakage current performance.

[0200] In some embodiments, the above preparation method further includes: growing a p-type nitride top layer, such that the p-type nitride top layer conformally covers the surface of the p-type nitride structure and the nanostructure.

[0201] In some embodiments, growing the p-type nitride top layer includes: subjecting the nanostructure to nitriding at a temperature of 900°C to 1050°C and a pressure of 400 torr to 600 torr; and growing a Mg doping concentration of 5 × 10⁻⁶ nm on the p-type nitride layer with a thickness of 100 nm to 300 nm on a pressure of 400 torr to 600 torr. 19 cm -3 Up to 1×10 21 cm -3 The top layer of the p-type nitride.

[0202] Nitrogen thermal treatment nitrids the surface of the nanostructure to form an AlN nucleation layer, providing a growth template for the growth of the p-type nitride top layer. Nitrogen thermal treatment also reduces N vacancies on the p-type nitride surface, decreases N vacancy acceptor compensation, increases the hole concentration in the p-type nitride structure, and improves the uniformity of hole injection into the emissive layer. The p-type nitride top layer then provides excellent current injection.

[0203] The temperature of the nitrogen heat treatment is between 900℃ and 1050℃, for example, it can be 900℃, 950℃, 980℃, 1000℃, 1020℃ or 1050℃.

[0204] The pressure for nitrogen heat treatment is 400 torr to 600 torr, for example, 400 torr, 450 torr, 500 torr, 550 torr or 600 torr.

[0205] The temperature for growing the top layer of p-type nitride is between 720°C and 850°C, for example, it can be 720°C, 750°C, 780°C, 800°C, 820°C or 850°C.

[0206] The pressure for growing the p-type nitride top layer is 400 torr to 600 torr, for example, it can be 400 torr, 450 torr, 500 torr, 550 torr or 600 torr.

[0207] The Mg doping concentration in the top layer of the p-type nitride is 5 × 10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 For example, it could be 5×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 5×10 20 cm -3 8×1020 cm -3 Or 1×10 21 cm -3 wait.

[0208] The thickness of the p-type nitride top layer is 10 nm to 50 nm, for example, it can be 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0209] An embodiment of the present invention provides an optoelectronic device, which includes a low-stress nitride epitaxial wafer as described in any embodiment, or a low-stress nitride epitaxial wafer prepared by the preparation method provided in any embodiment.

[0210] In some embodiments, the optoelectronic device includes a low-stress nitride epitaxial wafer and a P-electrode. The upper surface of the low-stress nitride epitaxial wafer has multiple recessed regions, and the P-electrode is disposed within the recessed regions.

[0211] Example 1

[0212] This embodiment provides a method such as Figure 1 The optoelectronic device shown includes: a substrate 1, an n-type nitride layer 4, an n-type nitride barrier layer 5, multiple spaced composite nano-segmentation structures 71, multiple spaced n-type nitride low barrier structures 81, multiple spaced light-emitting structures 82, multiple spaced p-type nitride structures 83, a p-type nitride top layer 9, and a p-electrode 10.

[0213] The material of substrate 1 is sapphire substrate, and the size of substrate 1 is 4 inches.

[0214] An n-type nitride layer 4 is disposed on the substrate 1.

[0215] An n-type nitride barrier layer 5 is disposed on an n-type nitride layer 4; wherein, nucleation aggregation regions 6 are distributed at intervals on the surface of the n-type nitride barrier layer 5 away from the substrate 1, and the surface of the n-type nitride barrier layer 5 away from the substrate 1 where no nucleation aggregation regions 6 are distributed is a non-nucleation aggregation region 6.

[0216] A composite nanostructure 71 is disposed on the nucleation and aggregation region 6 of the n-type nitride barrier layer 5; wherein each composite nanostructure 71 includes a semiconductor nanopillar and a nanostructure 72 disposed on the semiconductor nanopillar. An n-type nitride low barrier structure 81 covers the non-nucleation and aggregation region 6. A light-emitting structure 82 is disposed on the n-type nitride low barrier structure 81. A p-type nitride structure 83 is disposed on the light-emitting structure 82.

[0217] The n-type nitride low barrier structure 81 corresponds one-to-one with the non-nucleation aggregation region 6; the luminescent structure 82 corresponds one-to-one with the n-type nitride low barrier structure 81; the top surface of the composite nano-sparging structure 71 is lower than the top surface of the p-type nitride structure 83; the top surface of the semiconductor nanopillar is higher than the top surface of the luminescent structure 82; the barrier of the n-type nitride low barrier structure 81 is lower than the barrier of the n-type nitride barrier layer 5.

[0218] The p-type nitride top layer 9 is conformally disposed on the surface of the p-type nitride structure 83 and the nanostructure 72; the upper surface of the p-type nitride top layer 9 has multiple recessed regions, and the p electrode 10 is disposed in the recessed regions.

[0219] The method for preparing low-stress nitride epitaxial wafers provided in this embodiment includes the following steps:

[0220] (1) Under the conditions of 1100℃ and 200 torr, a silicon doping concentration of 1×10⁻⁶ was grown on substrate 1 with a thickness of 4μm. 19 cm -3 The n-type nitride layer 4 is an n-type GaN layer.

[0221] (2) An n-type nitride barrier layer 5 was prepared on the surface of the n-type nitride layer 4: a thickness of 10 nm and a silicon doping concentration of 1×10⁻⁶ were grown at a temperature of 1150 °C and a pressure of 150 torr. 18 cm -3 An initial n-type nitride barrier layer 5 is formed, which is an initial n-type GaN barrier layer. Silicon ion implantation is performed using an energy of 30keV to form nucleation and aggregation regions 6 with a depth of 1.5nm and longitudinal and lateral widths of 0.8μm on the surface of the initial n-type nitride barrier layer 5 away from the substrate 1, thereby obtaining the n-type nitride barrier layer 5.

[0222] The surface of the n-type nitride barrier layer 5, which is far from the substrate 1, is the non-nucleation aggregation region 6.

[0223] (3) Semiconductor nanopillars are prepared on the nucleation and aggregation region 6 of the n-type nitride barrier layer 5, including the following steps:

[0224] A31. An aluminum metal capping layer with a thickness of 100 nm is grown on the surface of the n-type nitride barrier layer 5; then, the aluminum metal capping layer is annealed for 200 s at a temperature of 800 °C and a pressure of 100 torr to form a microstructure in the nucleation aggregation region 6.

[0225] A32. Under conditions of 800℃ and 400 torr, the microstructure was subjected to silicon heat treatment for 300s to obtain a nanosphere structure.

[0226] A33. The nanosphere structure was subjected to silicon heat treatment for 50 seconds at a temperature of 800℃ and a pressure of 400 torr.

[0227] A34, interrupt silicon heat treatment for 100 seconds.

[0228] A35, A33 and A34 are periodically and alternately executed 500 times to obtain semiconductor nanopillars with a height of 200 nm, and the distance between any two adjacent semiconductor nanopillars is 25 μm.

[0229] (4) Post-processing of the semiconductor nanopillars yields a composite nanostructure 71:

[0230] A41. Under conditions of 600°C and 400 torr, an oxygen treatment is performed for 90 seconds to form a nanostructure 72 on the top surface of the semiconductor nanopillars, the material of which includes aluminum oxide.

[0231] A42. Under conditions of 600℃ and 400 torr, hydrogen treatment is performed for 40s to decompose the oxygen element on the surface of the non-nucleation aggregation region 6 between adjacent semiconductor nanopillars.

[0232] A43, A41 and A42 are periodically cyclically alternated 60 times to obtain composite nano-spacing structure 71.

[0233] (5) Under conditions of 1100℃ and 300 torr, Si doping concentration of 5×10⁻⁶ was grown on the surface of the non-nucleation aggregation region 6. 17 cm -3 A low-barrier n-type nitride structure with a thickness of 50 nm 81.

[0234] (6) The light-emitting structure 82 is prepared on the n-type nitride low barrier structure 81, including the following steps:

[0235] A61. Under conditions of 700℃ and 300 torr, a quantum well layer with a thickness of 2nm is grown by introducing TMGa at a flow rate of 300 sccm, TMIn at a flow rate of 1200 sccm, and NH3 at a flow rate of 80 slm.

[0236] A62. Under conditions of 850℃ and 300 torr, a quantum barrier layer with a thickness of 10 nm is grown by introducing TMGa at a flow rate of 300 sccm and NH3 at a flow rate of 80 slm.

[0237] A63, A61 and A62 are periodically and alternately executed 8 times to obtain the light-emitting structure 82.

[0238] (7) Under conditions of 850℃ and 500 torr, TMGa with a flow rate of 500 sccm and NH3 with a flow rate of 50 slm were introduced to grow a 150 nm thick Mg doping concentration of 1×10 on the surface of the nitride light-emitting layer. 20 cm -3 The p-type nitride structure 83.

[0239] (8) The nanostructure 72 was subjected to nitrogen thermal treatment at a temperature of 950℃ and a pressure of 500 torr; then, a 200 nm thick Mg doping concentration of 1×10⁻⁶ was conformally grown on the p-type nitride structure 83 and the nanostructure 72 at a temperature of 800℃ and a pressure of 500 torr. 20 cm -3 The top layer of the p-type nitride is 9.

[0240] (9) A p electrode 10 is provided on the top layer 9 of the p-type nitride.

[0241] Example 2

[0242] This embodiment provides a method such as Figure 2 Compared with Example 1, the low-stress nitride epitaxial wafer shown in this embodiment further includes a nitride nucleation layer 2 and a nitride buffer layer 3 stacked together; the nitride nucleation layer 2 is disposed on the substrate 1, and the nitride buffer layer 3 is covered by an n-type nitride layer 4.

[0243] The method for preparing low-stress nitride epitaxial wafers provided in this embodiment includes the following steps:

[0244] (1) A nitride nucleation layer 2, a nitride buffer layer 3, and an n-type nitride layer 4 are sequentially prepared on the surface of substrate 1, including the following steps:

[0245] A11: A nitride nucleation layer 2 with a thickness of 100 nm is grown on substrate 1 under the conditions of 700℃ and 400 torr. The nitride nucleation layer 2 is a GaN nucleation layer.

[0246] A12: A nitride buffer layer 3 with a thickness of 2 μm was grown on the nitride nucleation layer 2 under the conditions of 1100℃ and 200 torr.

[0247] A13: A 4 μm thick silicon doping concentration of 1 × 10⁻⁶ was grown on nitride buffer layer 3 under conditions of 1100 °C and 200 torr. 19 cm -3 The n-type nitride layer 4 is an n-type GaN layer.

[0248] (2) Under the conditions of 1150℃ and 150 torr, a thickness of 10 nm and a silicon doping concentration of 1×10⁻⁶ were grown. 18 cm -3 An initial n-type nitride barrier layer 5 is formed, which is an initial n-type GaN barrier layer. Silicon ion implantation is performed using an energy of 30keV to form nucleation and aggregation regions 6 with a depth of 1.5nm and longitudinal and lateral widths of 0.8μm on the surface of the initial n-type nitride barrier layer 5 away from the substrate 1, thereby obtaining the n-type nitride barrier layer 5.

[0249] The surface of the n-type nitride barrier layer 5, which is far from the substrate 1, is the non-nucleation aggregation region 6.

[0250] (3) Semiconductor nanopillars are prepared on the nucleation and aggregation region 6 of the n-type nitride barrier layer 5, including the following steps:

[0251] A31. An aluminum metal capping layer with a thickness of 100 nm is grown on the surface of the n-type nitride barrier layer 5; then, the aluminum metal capping layer is annealed for 200 s at a temperature of 800 °C and a pressure of 100 torr to form a microstructure in the nucleation aggregation region 6.

[0252] A32. Under conditions of 800℃ and 400 torr, the microstructure was subjected to silicon heat treatment for 300s to obtain a nanosphere structure.

[0253] A33. The nanosphere structure was subjected to silicon heat treatment for 50 seconds at a temperature of 800℃ and a pressure of 400 torr.

[0254] A34, interrupt silicon heat treatment for 100 seconds.

[0255] A35, A33 and A34 are periodically and alternately executed 500 times to obtain semiconductor nanopillars with a height of 200 nm, and the distance between any two adjacent semiconductor nanopillars is 25 μm.

[0256] (4) Post-processing of the semiconductor nanopillars yields a composite nanostructure 71:

[0257] A41. Under conditions of 600°C and 400 torr, an oxygen treatment is performed for 90 seconds to form a nanostructure 72 on the top surface of the semiconductor nanopillars, the material of which includes aluminum oxide.

[0258] A42. Under conditions of 600℃ and 400 torr, hydrogen treatment is performed for 40s to decompose the oxygen element on the surface of the non-nucleation aggregation region 6 between adjacent semiconductor nanopillars.

[0259] A43, A41 and A42 are periodically cyclically alternated 60 times to obtain composite nano-spacing structure 71.

[0260] (5) Under conditions of 1100℃ and 300 torr, Si doping concentration of 5×10⁻⁶ was grown on the surface of the non-nucleation aggregation region 6. 17 cm -3 A low-barrier n-type nitride structure with a thickness of 50 nm 81.

[0261] (6) The light-emitting structure 82 is prepared on the n-type nitride low barrier structure 81, including the following steps:

[0262] A61. Under conditions of 700℃ and 300 torr, a quantum well layer with a thickness of 2nm is grown by introducing TMGa at a flow rate of 300 sccm, TMIn at a flow rate of 1200 sccm, and NH3 at a flow rate of 80 slm.

[0263] A62. Under conditions of 850℃ and 300 torr, a quantum barrier layer with a thickness of 10 nm is grown by introducing TMGa at a flow rate of 300 sccm and NH3 at a flow rate of 80 slm.

[0264] A63, A61 and A62 are periodically and alternately executed 8 times to obtain the light-emitting structure 82.

[0265] (7) Under conditions of 850℃ and 500 torr, TMGa with a flow rate of 500 sccm and NH3 with a flow rate of 50 slm were introduced to grow a 150 nm thick Mg doping concentration of 1×10 on the surface of the nitride light-emitting layer. 20 cm -3 The p-type nitride structure 83.

[0266] (8) The nanostructure 72 was subjected to nitrogen thermal treatment at a temperature of 950℃ and a pressure of 500 torr; then, a 200 nm thick Mg doping concentration of 1×10⁻⁶ was conformally grown on the p-type nitride structure 83 and the nanostructure 72 at a temperature of 800℃ and a pressure of 500 torr. 20 cm -3 The top layer of the p-type nitride is 9.

[0267] (9) A p electrode 10 is provided on the top layer 9 of the p-type nitride.

[0268] Example 3

[0269] This embodiment provides a low-stress nitride epitaxial wafer, and the structure of the low-stress nitride epitaxial wafer provided in this embodiment is the same as that in Embodiment 2.

[0270] The method for preparing low-stress nitride epitaxial wafers provided in this embodiment includes the following steps:

[0271] (1) A nitride nucleation layer, a nitride buffer layer, and an n-type nitride layer are sequentially prepared on the surface of a substrate, including the following steps:

[0272] A11: A nitride nucleation layer with a thickness of 10 nm is grown on a substrate under conditions of 500℃ and 200 torr. The nitride nucleation layer is a GaN nucleation layer.

[0273] A12: A nitride buffer layer with a thickness of 1 μm was grown on the nitride nucleation layer at a temperature of 1050℃ and a pressure of 100 torr.

[0274] A13: Under conditions of 1050℃ and 100 torr, a 2μm thick silicon doping concentration of 1×10⁻⁶ was grown on a nitride buffer layer. 18 cm -3 The n-type nitride layer is an n-type GaN layer.

[0275] (2) Under conditions of 1070℃ and 50 torr, a growth thickness of 2nm and a silicon doping concentration of 5×10⁻⁶ were achieved. 17 cm -3 An initial n-type nitride barrier layer is formed, which is an initial n-type GaN barrier layer. Silicon ion implantation is performed using an energy of 10keV to form nucleation and aggregation regions with a depth of 1nm and a longitudinal and lateral width of 0.5μm on the surface of the initial n-type nitride barrier layer away from the substrate, thereby obtaining an n-type nitride barrier layer.

[0276] The surface of the n-type nitride barrier layer far from the substrate, where no nucleation aggregation region is distributed, is the non-nucleation aggregation region.

[0277] (3) Fabricating spaced semiconductor nanopillars on the nucleation aggregation region of the n-type nitride barrier layer, including the following steps:

[0278] A31. An aluminum metal capping layer with a thickness of 10 nm is grown on the surface of an n-type nitride barrier layer; then, the aluminum metal capping layer is annealed for 60 s at a temperature of 500 °C and a pressure of 50 torr to form a microstructure in the nucleation and aggregation region.

[0279] A32. Under conditions of 500℃ and 200 torr, the microstructure was subjected to silicon heat treatment for 100s to obtain a nanosphere structure.

[0280] A33. The nanosphere structure was heat-treated for 10 seconds at a temperature of 500℃ and a pressure of 200 torr.

[0281] A34, interrupt heat treatment for 10 seconds.

[0282] A35, A33 and A34 are periodically and alternately executed 100 times to obtain semiconductor nanopillars with a height of 35 nm, and the distance between any two adjacent semiconductor nanopillars is 5 μm.

[0283] (4) Post-processing of the semiconductor nanopillars yields a composite nanostructure:

[0284] A41. Under conditions of 400°C and 200 torr, an oxygen treatment is performed for 60 seconds to form a nanostructure containing aluminum oxide on the top surface of the semiconductor nanopillar.

[0285] A42. Under conditions of 400℃ and 200 torr, hydrogen treatment is performed for 20s to decompose the oxygen element on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars.

[0286] A43, A41 and A42 are periodically cyclically alternated 20 times to obtain a composite nano-spacing structure.

[0287] (5) Under conditions of 1050℃ and 200 torr, Si doping concentration of 2×10⁻⁶ was grown on the surface of the non-nucleation aggregation region. 17 cm -3 A low-barrier n-type nitride structure with a thickness of 20 nm.

[0288] (6) The light-emitting structure is prepared on the low barrier structure of the n-type nitride, including the following steps:

[0289] A61. Under conditions of 650℃ and 200 torr, a quantum well layer with a thickness of 0.5 nm is grown by introducing TMGa at a flow rate of 100 sccm, TMIn at a flow rate of 500 sccm, and NH3 at a flow rate of 50 slm.

[0290] A62. Under conditions of 750℃ and 200 torr, a quantum barrier layer with a thickness of 5nm is grown by introducing TMGa at a flow rate of 100 sccm and NH3 at a flow rate of 50 slm.

[0291] A63, A61 and A62 are periodically and alternately executed twice to obtain the light-emitting structure.

[0292] (7) Under conditions of 750℃ and 400 torr, a gallium source with a flow rate of 100 sccm and a nitrogen source with a flow rate of 20 slm were introduced to grow a 20 nm thick Mg doping concentration of 1×10⁻⁶ on the surface of the nitride light-emitting layer. 19 cm -3 The p-type nitride structure.

[0293] (8) The nanostructure was subjected to nitrogen thermal treatment at a temperature of 900℃ and a pressure of 400 torr; then a p-type nitride top layer was grown, so that the p-type nitride top layer conformally covered the surface of the p-type nitride structure and the nanostructure:

[0294] Under conditions of 720℃ and 400 torr, a 10 nm thick Mg doping concentration of 5 × 10⁻⁶ was conformally grown on p-type nitride structures and nanostructures. 19 cm -3 The top layer of the p-type nitride.

[0295] (9) Set a p electrode on the top layer of p-type nitride.

[0296] Example 4

[0297] This embodiment provides a low-stress nitride epitaxial wafer, and the structure of the low-stress nitride epitaxial wafer provided in this embodiment is the same as that in Embodiment 2.

[0298] The method for preparing low-stress nitride epitaxial wafers provided in this embodiment includes the following steps:

[0299] (1) A nitride nucleation layer, a nitride buffer layer, and an n-type nitride layer are sequentially prepared on the surface of a substrate, including the following steps:

[0300] A11: A nitride nucleation layer with a thickness of 200 nm is grown on a substrate under conditions of 900℃ and 600 torr. The nitride nucleation layer is a GaN nucleation layer.

[0301] A12: A nitride buffer layer with a thickness of 3 μm was grown on the nitride nucleation layer at a temperature of 1150℃ and a pressure of 300 torr.

[0302] A13: A 5 μm thick silicon doping concentration of 1 × 10⁻⁶ was grown on a nitride buffer layer at a temperature of 1150 °C and a pressure of 300 torr. 20 cm -3 The n-type nitride layer is an n-type GaN layer.

[0303] (2) Under conditions of 1200℃ and 250 torr, a thickness of 20 nm and a silicon doping concentration of 5 × 10⁻⁶ were grown.18 cm -3 An initial n-type nitride barrier layer, which is an initial n-type GaN barrier layer, is obtained by silicon ion implantation using an energy of 50 keV to form nucleation aggregation regions with a depth of 2 nm and longitudinal and lateral widths of 1 μm on the surface of the initial n-type nitride barrier layer away from the substrate, thereby obtaining an n-type nitride barrier layer.

[0304] The surface of the n-type nitride barrier layer far from the substrate, where no nucleation aggregation region is distributed, is the non-nucleation aggregation region.

[0305] (3) Fabricating spaced semiconductor nanopillars on the nucleation aggregation region of the n-type nitride barrier layer, including the following steps:

[0306] A31. An aluminum metal capping layer with a thickness of 200 nm is grown on the surface of an n-type nitride barrier layer; then, the aluminum metal capping layer is annealed for 300 s at a temperature of 1000 °C and a pressure of 150 torr to form microstructures in the nucleation and aggregation regions.

[0307] A32. Under conditions of 1000℃ and 600 torr, the microstructure was subjected to silicon heat treatment for 600s to obtain a nanosphere structure.

[0308] A33. The nanosphere structure was subjected to silicon heat treatment for 100s at a temperature of 1000℃ and a pressure of 600 torr.

[0309] A34, interrupted silicon heat treatment for 180 seconds.

[0310] A35, A33 and A34 are periodically and alternately executed 1000 times to obtain semiconductor nanopillars with a height of 400 nm, and the distance between any two adjacent semiconductor nanopillars is 50 μm.

[0311] (4) Post-processing of the semiconductor nanopillars yields a composite nanostructure:

[0312] A41. Under conditions of 800°C and 600 torr, an oxygen treatment is performed for 120 seconds to form a nanostructure containing aluminum oxide on the top surface of a semiconductor nanopillar.

[0313] A42. Under conditions of 800℃ and 600 torr, hydrogen treatment is performed for 60s to decompose the oxygen element on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars.

[0314] A43, A41 and A42 are periodically cyclically alternated 100 times to obtain a composite nano-spacing structure.

[0315] (5) Under conditions of 1150℃ and 400 torr, Si doping concentration of 8×10⁻⁶ was grown on the surface of the non-nucleation aggregation region. 17 cm -3 A low-barrier n-type nitride structure with a thickness of 120 nm.

[0316] (6) The light-emitting structure is prepared on the low barrier structure of the n-type nitride, including the following steps:

[0317] A61. Under conditions of 750℃ and 400 torr, a quantum well layer with a thickness of 3nm is grown by introducing TMGa at a flow rate of 500 sccm, TMIn at a flow rate of 2000 sccm, and NH3 at a flow rate of 100 slm.

[0318] A62. Under conditions of 950℃ and 400 torr, a quantum barrier layer with a thickness of 15nm is grown by introducing TMGa at a flow rate of 500 sccm and NH3 at a flow rate of 100 slm.

[0319] A63, A61 and A62 are periodically and alternately executed 15 times to obtain the light-emitting structure.

[0320] (7) Under conditions of 900℃ and 600 torr, TMGa with a flow rate of 1000 sccm and NH3 with a flow rate of 80 slm were introduced to grow a nitride light-emitting layer with a thickness of 800 nm and a Mg doping concentration of 5 × 10⁻⁶. 20 cm -3 The p-type nitride structure.

[0321] (8) Under conditions of 850℃ and 600 torr, a 300 nm thick Mg doping concentration was conformally grown on the p-type nitride structure and nanostructure. 21 cm -3 The top layer of the p-type nitride.

[0322] (9) Set a p electrode on the top layer of p-type nitride.

[0323] Example 5

[0324] This embodiment provides a low-stress nitride epitaxial wafer. Except for step A34, which is not performed, semiconductor nanopillars are grown directly on the surface of the nanosphere structure. The rest is the same as in embodiment 2, and will not be described again here.

[0325] Comparative Example 1

[0326] This comparative example provides a low-stress nitride epitaxial wafer, which is the same as Example 2 except that an n-type nitride barrier layer is not provided and the nucleation aggregation region is located in the n-type nitride layer. It will not be described again here.

[0327] Comparative Example 2

[0328] This comparative example provides a low-stress nitride epitaxial wafer, which is the same as Example 2 except that it does not have nucleation and non-nucleation aggregation regions, and will not be described again here.

[0329] The method for preparing low-stress nitride epitaxial wafers provided in this comparative example includes:

[0330] (1) A nitride nucleation layer, a nitride buffer layer, and an n-type nitride layer are sequentially prepared on the surface of a substrate, including the following steps:

[0331] A11: A nitride nucleation layer with a thickness of 100 nm is grown on a substrate under the conditions of 700℃ and 400 torr. The nitride nucleation layer is a GaN nucleation layer.

[0332] A12: A nitride buffer layer with a thickness of 2 μm was grown on the nitride nucleation layer at a temperature of 1100℃ and a pressure of 200 torr.

[0333] A13: A 4 μm thick silicon doping concentration of 1 × 10⁻⁶ was grown on a nitride buffer layer at a temperature of 1100 °C and a pressure of 200 torr. 19 cm -3 The n-type nitride layer is an n-type GaN layer.

[0334] (2) Under the conditions of 1150℃ and 150 torr, a thickness of 10 nm and a silicon doping concentration of 1×10⁻⁶ were grown. 18 cm -3 The n-type nitride barrier layer is an n-type GaN barrier layer.

[0335] (3) Fabricating spaced semiconductor nanopillars on an n-type nitride barrier layer, comprising the following steps:

[0336] A31. An aluminum metal capping layer with a thickness of 100 nm is grown on the surface of an n-type nitride barrier layer; then, the aluminum metal capping layer is annealed for 200 s at a temperature of 800 °C and a pressure of 100 torr to form a microstructure.

[0337] A32. Under conditions of 800℃ and 400 torr, the microstructure was subjected to silicon heat treatment for 300s to obtain a nanosphere structure.

[0338] A33. The nanosphere structure was heat-treated for 50 seconds at a temperature of 800℃ and a pressure of 400 torr.

[0339] A34, interrupt silicon heat treatment for 100 seconds.

[0340] A35, A33 and A34 are periodically and alternately executed 500 times to obtain semiconductor nanopillars with a height of 200 nm, and the distance between any two adjacent semiconductor nanopillars is 25 μm.

[0341] (4) Post-processing of the semiconductor nanopillars yields a composite nanostructure:

[0342] A41. Under conditions of 600°C and 400 torr, an oxygen treatment is performed for 90 seconds to form a nanostructure containing aluminum oxide on the top surface of the semiconductor nanopillar.

[0343] A42. Under conditions of 600℃ and 400 torr, hydrogen treatment is performed for 40s to decompose the oxygen element on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars.

[0344] A43, A41 and A42 are periodically cyclically alternated 60 times to obtain a composite nano-spacing structure.

[0345] (5) Under the conditions of 1100℃ and 300 torr, Si with a doping concentration of 5×10⁻⁶ is grown. 17 cm -3 A low-barrier n-type nitride structure with a thickness of 50 nm.

[0346] (6) The light-emitting structure is prepared on the low barrier structure of the n-type nitride, including the following steps:

[0347] A61. Under conditions of 700℃ and 300 torr, a quantum well layer with a thickness of 2nm is grown by introducing TMGa at a flow rate of 300 sccm, TMIn at a flow rate of 1200 sccm, and NH3 at a flow rate of 80 slm.

[0348] A62. Under conditions of 850℃ and 300 torr, a quantum barrier layer with a thickness of 10 nm is grown by introducing TMGa at a flow rate of 300 sccm and NH3 at a flow rate of 80 slm.

[0349] A63, A61 and A62 are periodically and alternately executed 8 times to obtain the light-emitting structure.

[0350] (7) Under conditions of 850℃ and 500 torr, TMGa with a flow rate of 500 sccm and NH3 with a flow rate of 50 slm were introduced to grow a 150 nm thick Mg doping concentration of 1×10 on the surface of the nitride light-emitting layer. 20 cm -3 The p-type nitride structure.

[0351] (8) The nanostructure was subjected to nitrogen thermal treatment at a temperature of 950℃ and a pressure of 500 torr; then, a 30 nm thick Mg doping concentration of 1×10⁻⁶ was conformally grown on the p-type nitride structure and the nanostructure at a temperature of 800℃ and a pressure of 500 torr. 20 cm -3 The top layer of the p-type nitride.

[0352] (9) Set a p electrode on the top layer of p-type nitride.

[0353] Comparative Example 3

[0354] This comparative example provides a low-stress nitride epitaxial wafer. Compared with Example 2, the low-stress nitride epitaxial wafer provided in this comparative example does not have a composite nano-spacing structure.

[0355] The method for preparing low-stress nitride epitaxial wafers provided in this comparative example includes the following steps:

[0356] (1) A nitride nucleation layer, a nitride buffer layer, and an n-type nitride layer are sequentially prepared on the surface of a substrate, including the following steps:

[0357] A11: A nitride nucleation layer with a thickness of 100 nm is grown on a substrate under the conditions of 700℃ and 400 torr. The nitride nucleation layer is a GaN nucleation layer.

[0358] A12: A nitride buffer layer with a thickness of 2 μm was grown on the nitride nucleation layer at a temperature of 1100℃ and a pressure of 200 torr.

[0359] A13: A 4 μm thick silicon doping concentration of 1 × 10⁻⁶ was grown on a nitride buffer layer at a temperature of 1100 °C and a pressure of 200 torr. 19 cm -3 The n-type nitride layer is an n-type GaN layer.

[0360] (2) Under the conditions of 1150℃ and 150 torr, a thickness of 10 nm and a silicon doping concentration of 1×10⁻⁶ were grown. 18 cm -3An initial n-type nitride barrier layer, which is an n-type GaN barrier layer, is obtained. Silicon ion implantation is performed using an energy of 30keV to form a nucleation aggregation region with a depth of 1.5nm and a longitudinal and lateral width of 0.8μm on the surface of the initial n-type nitride barrier layer away from the substrate, thereby obtaining an n-type nitride barrier layer.

[0361] The surface of the n-type nitride barrier layer far from the substrate, where no nucleation aggregation region is distributed, is the non-nucleation aggregation region.

[0362] (3) Under conditions of 1100℃ and 300 torr, Si doping concentration of 5×10⁻⁶ was grown on the surface of the n-type nitride barrier layer. 17 cm -3 A low-barrier n-type nitride structure with a thickness of 50 nm.

[0363] (4) The light-emitting structure is prepared on the low barrier structure of the n-type nitride, including the following steps:

[0364] A41. Under conditions of 700℃ and 300 torr, a quantum well layer with a thickness of 2nm is grown by introducing TMGa at a flow rate of 300 sccm, TMIn at a flow rate of 1200 sccm, and NH3 at a flow rate of 80 slm.

[0365] A42. Under conditions of 850℃ and 300 torr, a quantum barrier layer with a thickness of 10 nm is grown by introducing TMGa at a flow rate of 300 sccm and NH3 at a flow rate of 80 slm.

[0366] A43, A41 and A42 are periodically and alternately executed 8 times to obtain the light-emitting structure.

[0367] (5) Under conditions of 850℃ and 500 torr, TMGa with a flow rate of 500 sccm and NH3 with a flow rate of 50 slm were introduced to grow a 150 nm thick Mg doping concentration of 1×10⁻⁶ on the surface of the nitride luminescent layer. 20 cm -3 The p-type nitride structure.

[0368] (6) Nitrogen heat treatment was performed at a temperature of 950℃ and a pressure of 500 torr; then, a conformal growth of 30 nm thickness with a Mg doping concentration of 1×10⁻⁶ was carried out on the p-type nitride structure at a temperature of 800℃ and a pressure of 500 torr. 20 cm -3 The top layer of the p-type nitride.

[0369] (7) A p electrode is placed on the top layer of the p-type nitride.

[0370] Performance Characterization

[0371] The long-wavelength red light (610nm±1nm) low-stress nitride epitaxial wafers obtained in the above embodiments and comparative examples were subjected to performance testing. The wavelength uniformity (std / nm) and full width at half maximum (HW / nm) of the epitaxial wafers prepared in the above embodiments and comparative examples were tested by photoluminescence (PL). Then, Micro-LEDs were fabricated using the same preparation process and tested using an LED optoelectronic performance tester, including luminous intensity (Lop / mW) under a 2mA current injection condition, leakage yield (IR) performance test under a reverse voltage of 7V, and peak luminous efficiency (PQE / %) in the current range of 1-5mA. The results are shown in Table 1.

[0372] Table 1

[0373] WLD / nm std / nm HW / nm Lop / mW / 2mA VF / V / 2mA IR / % PQE / % Example 1 615.1 0.72 53.7 13.7 2.81 99.9 15.1 Example 2 615.4 0.65 53.1 13.5 2.83 99.9 16.3 Example 3 615.1 0.78 53.6 13.7 2.82 99.8 14.4 Example 4 615.2 0.94 54.5 14.1 2.85 100 16.6 Example 5 615.7 1.36 56.1 11.1 2.88 96.7 12.5 Comparative Example 1 615.4 1.12 55.4 10.4 2.91 95.3 11.3 Comparative Example 2 615.2 2.01 58.6 9.1 3.01 94.6 10.9 Comparative Example 3 615.6 2.87 62.5 6.9 3.21 94.2 7.8

[0374] As shown in the table above, Examples 1-4 exhibit excellent photoelectric performance due to their low wavelength (std), low full width at half maximum (HW), high luminance (Lop), low voltage (VF), high leakage current (IR) yield, and high peak efficiency. Example 5, lacking Si interruption treatment, results in insufficient dissolution of silicon atoms during semiconductor nanopillar formation, leading to uneven silicon atom precipitation and difficulty in obtaining semiconductor nanopillars with smooth surfaces. This reduces the uniformity of the semiconductor nanopillars, thus affecting the uniformity of carrier distribution in the luminescent structure. Comparative Example 1 lacks an n-type nitride barrier layer, which reduces the effectiveness of the electron barrier, resulting in... The injection is uneven and cannot effectively block the extension of dislocations from the bottom layer to the light-emitting structure, resulting in more non-radiative recombination and leakage channels. Comparative Example 2 does not set up a nucleation aggregation region, so it cannot provide a uniform high-density distribution of atomic nucleation aggregation centers. It can only form a composite nanostructure with large differences in random discrete distribution, which cannot effectively reduce the stress distribution in the light-emitting structure, and the quantum size confinement effect is suppressed. In Comparative Example 3, it is also impossible to achieve the isolation of the light-emitting structure by setting up a composite nanostructure with interval distribution. The quantum size confinement effect and stress modulation effect cannot be reflected.

[0375] In summary, the low-stress nitride epitaxial wafer provided by this invention achieves the isolation of the light-emitting structure through the setting of a composite nano-segmentation structure with spaced distribution. This enables the reduction of QCSE by utilizing the quantum size confinement effect, thereby reducing stress distribution, improving the radiative recombination efficiency of electrons and holes, improving the luminous efficiency and brightness of the epitaxial wafer, reducing the half-width at half maximum (WHM) of the emission wavelength, and improving the color purity for display applications.

[0376] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A low-stress nitride epitaxial wafer, characterized in that, The low-stress nitride epitaxial wafer comprises: Substrate; An n-type nitride layer is disposed on the substrate; An n-type nitride barrier layer is disposed on the n-type nitride layer; wherein, nucleation aggregation regions are distributed at intervals on the surface of the n-type nitride barrier layer away from the substrate, and the surface of the n-type nitride barrier layer away from the substrate where the nucleation aggregation regions are not distributed is a non-nucleation aggregation region. Multiple spaced composite nanostructures are disposed on the nucleation and aggregation region of the n-type nitride barrier layer; wherein each composite nanostructure includes a semiconductor nanopillar and a nanostructure disposed on the semiconductor nanopillar. Multiple spaced n-type nitride low-barrier structures cover the non-nucleation aggregation region; Multiple spaced-apart light-emitting structures are disposed on the n-type nitride low-barrier structure; Multiple p-type nitride structures are spaced apart and disposed on the light-emitting structure.

2. The low-stress nitride epitaxial wafer according to claim 1, characterized in that, The n-type nitride low barrier structure corresponds one-to-one with the non-nucleation aggregation region; The light-emitting structure corresponds one-to-one with the n-type nitride low-barrier structure; Preferably, the top surface of the composite nanostructure is lower than the top surface of the p-type nitride structure; Preferably, the top surface of the semiconductor nanopillar is higher than the top surface of the light-emitting structure; Preferably, the barrier of the n-type nitride low barrier structure is smaller than the barrier of the n-type nitride barrier layer; Preferably, the low-stress nitride epitaxial wafer further includes a p-type nitride top layer, which is conformally disposed to cover the surfaces of the p-type nitride structure and the nanostructure; Preferably, the low-stress nitride epitaxial wafer further includes a nitride nucleation layer and a nitride buffer layer stacked together; the nitride nucleation layer is disposed on the substrate, and the nitride buffer layer is covered by the n-type nitride layer; Preferably, the depth of the nucleation and aggregation region is 1 nm to 2 nm, and the longitudinal and / or transverse width of the nucleation and aggregation region is 0.5 μm to 1 μm; Preferably, the semiconductor nanopillars are made of silicon; Preferably, the height of the semiconductor nanopillars is 35 nm to 400 nm; Preferably, the distance between any two adjacent composite nanostructures is 5 μm to 50 μm; Preferably, the material of the nanostructure includes aluminum oxide.

3. A method for preparing a low-stress nitride epitaxial wafer, characterized in that, The preparation method includes the following steps: An n-type nitride layer and an n-type nitride barrier layer are sequentially prepared on the surface of a substrate; wherein, the n-type nitride barrier layer has nucleation and aggregation regions distributed at intervals on the surface away from the substrate, and the n-type nitride barrier layer without the nucleation and aggregation regions is a non-nucleation and aggregation region on the surface away from the substrate. Multiple spaced-apart composite nanostructures and multiple spaced-apart n-type nitride low-barrier structures are fabricated on the n-type nitride barrier layer; wherein, the composite nanostructures are disposed on the nucleation and aggregation regions of the n-type nitride barrier layer, and each composite nanostructure includes a semiconductor nanopillar and a nanostructure disposed on the semiconductor nanopillar; the n-type nitride low-barrier structures cover the non-nucleation and aggregation regions; A light-emitting structure was prepared on the n-type nitride low-barrier structure; A p-type nitride structure is prepared on the surface of the light-emitting structure away from the substrate.

4. The preparation method according to claim 3, characterized in that, The method for preparing the n-type nitride barrier layer includes: An initial n-type nitride barrier layer is prepared on the substrate; Silicon ion implantation is performed using an energy of 10keV to 50keV to form nucleation aggregation regions with a depth of 1nm to 2nm and a longitudinal and / or lateral width of 0.5μm to 1μm on the surface of the initial n-type nitride barrier layer away from the substrate, thereby obtaining the n-type nitride barrier layer. Preferably, the preparation method includes: The composite nanostructure was prepared on each nucleation and aggregation region of the n-type nitride barrier layer; The n-type nitride low barrier structure is prepared on each non-nucleation aggregation region of the n-type nitride barrier layer; The luminescent structure is prepared on each of the n-type nitride low-barrier structures; The p-type nitride structure is prepared on each of the light-emitting structures.

5. The preparation method according to claim 4, characterized in that, The preparation of the n-type nitride low barrier structure on each non-nucleation aggregation region of the n-type nitride barrier layer includes: Under conditions of temperature ranging from 1050°C to 1150°C and pressure ranging from 200 to 400 torr, Si doping concentration of 2 × 10⁻⁶ is grown on the surface of the non-nucleation aggregation region. 17 cm -3 Up to 8×10 17 cm -3 n-type nitride low-barrier structures with a thickness of 20 nm to 120 nm; Preferably, the preparation method further includes: growing a p-type nitride top layer, such that the p-type nitride top layer conformally covers the surface of the p-type nitride structure and the nanostructure; Preferably, the growth of the p-type nitride top layer includes: subjecting the nanostructure to nitriding at a temperature of 900°C to 1050°C and a pressure of 400 torr to 600 torr; and then growing a Mg doping concentration of 5 × 10⁻⁶ nm on the p-type nitride layer with a thickness of 100 nm to 300 nm on the p-type nitride layer at a temperature of 720°C to 850°C and a pressure of 400 torr to 600 torr. 19 cm -3 Up to 1×10 21 cm -3 The top layer of the p-type nitride.

6. The preparation method according to claim 4, characterized in that, The fabrication of the composite nanofraction structure on each nucleation and aggregation region of the n-type nitride barrier layer includes: S1. An aluminum metal capping layer with a thickness of 10 nm to 200 nm is grown on the surface of the n-type nitride barrier layer; then, the aluminum metal capping layer is annealed for 60 s to 300 s at a temperature of 500 °C to 1000 °C and a pressure of 50 torr to 150 torr to form a microstructure in the nucleation and aggregation region. S2. The microstructure is subjected to silicon heat treatment for 100s to 600s at a temperature of 500℃ to 1000℃ and a pressure of 200 torr to 600 torr to obtain a nanosphere structure. S3. Semiconductor nanopillars are grown based on the nanosphere structure; S4. Post-process the semiconductor nanopillars to obtain the composite nano-spacing structure. Preferably, the material of the nanostructure includes aluminum oxide, and the post-processing of the semiconductor nanopillars to obtain the composite nanostructure includes: S41. Under conditions of temperature of 400°C to 800°C and pressure of 200 torr to 600 torr, perform oxygen treatment for 60 to 120 seconds to form a nanostructure of aluminum oxide material on the top surface of the semiconductor nanopillar. S42. Under conditions of temperature of 400°C to 800°C and pressure of 200 torr to 600 torr, perform hydrogen treatment for 20 to 60 seconds to decompose the oxygen element on the surface of the non-nucleation aggregation region between adjacent semiconductor nanopillars. S43, S41 and S42 are periodically cyclically alternated 20 to 100 times to obtain the composite nano-sparing structure; Preferably, the growth of semiconductor nanopillars based on the nanosphere structure includes: S31. The nanosphere structure is heat-treated for 10s to 100s at a temperature of 500℃ to 1000℃ and a pressure of 200 torr to 600 torr. S32. Interrupt the heat treatment for 10s to 180s; S33. S31 and S32 are periodically and alternately executed 100 to 1000 times to obtain the semiconductor nanopillar.

7. The preparation method according to claim 6, characterized in that, The method for preparing the light-emitting structure includes: A1. Under conditions of temperature of 650℃ to 750℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm, an indium source with a flow rate of 500 sccm to 2000 sccm, and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a quantum well layer with a thickness of 0.5 nm to 3 nm. A2. Under conditions of temperature of 750℃ to 950℃ and pressure of 200 torr to 400 torr, a gallium source with a flow rate of 100 sccm to 500 sccm and a nitrogen source with a flow rate of 50 slm to 100 slm are introduced to grow a quantum barrier layer with a thickness of 5 nm to 15 nm. A3. Periodically and alternately execute A1 and A2 2 to 15 times to obtain the light-emitting structure; Preferably, the preparation of the p-type nitride structure on each of the light-emitting structures includes: Under conditions of 750°C to 950°C and 400 torr to 600 torr, a gallium source with a flow rate of 100 sccm to 1000 sccm and a nitrogen source with a flow rate of 20 slm to 80 slm are introduced to grow a nitride light-emitting layer with a thickness of 20 nm to 800 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 Up to 5×10 20 cm -3 The p-type nitride structure described above.

8. The preparation method according to claim 3, characterized in that, The preparation method further includes: A nitride nucleation layer is prepared on the surface of the substrate; A nitride buffer layer is prepared on the surface of the nitride nucleation layer; The n-type nitride layer is prepared on the nitride buffer layer; Preferably, the preparation of the nitride nucleation layer on the surface of the substrate includes: A nitride nucleation layer with a thickness of 10 nm to 200 nm is grown on the substrate under conditions of temperature of 500 °C to 900 °C and pressure of 200 torr to 600 torr. Preferably, a nitride buffer layer is prepared on the surface of the nitride nucleation layer, comprising: A nitride buffer layer with a thickness of 1 μm to 3 μm is grown on the nitride nucleation layer under conditions of temperature of 1050℃ to 1150℃ and pressure of 100 torr to 300 torr. Preferably, the method for preparing the n-type nitride layer includes: Under conditions of temperature from 1050°C to 1150°C and pressure from 100 to 300 torr, a silicon doping concentration of 1×10⁻⁶ is grown on the nitride buffer layer with a thickness of 2 μm to 5 μm. 18 cm -3 Up to 1×10 20 cm -3 n-type nitride layer; Preferably, the method for preparing the initial n-type nitride barrier layer includes: Under conditions of temperature ranging from 1070℃ to 1200℃ and pressure ranging from 50 to 250 torr, a growth thickness of 2nm to 20nm and a silicon doping concentration of 5×10⁻⁶ were achieved. 17 cm -3 Up to 5×10 18 cm -3 The initial n-type nitride barrier layer.

9. An optoelectronic device, characterized in that, The optoelectronic device includes the low-stress nitride epitaxial wafer as described in claim 1 or 2, or the low-stress nitride epitaxial wafer prepared by the preparation method described in any one of claims 3 to 9.

10. The optoelectronic device according to claim 9, characterized in that, The optoelectronic device includes a low-stress nitride epitaxial wafer and a P-electrode. The upper surface of the low-stress nitride epitaxial wafer has multiple recessed regions, and the P-electrode is disposed in the recessed regions.

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