Display device

Abstract

This disclosure relates to a display device that can reduce the level of the boundary between a user-perceived normal area and an optical area by correcting image data based on a gamma curve selected based on a region in which sub-pixels to be provided with image data are disposed, among a first gamma curve for a first driving area, a second gamma curve for a second driving area, and a third gamma curve for a boundary driving area, and outputting corrected image data.

Description

[0001] This application is a divisional application of the original invention patent application No. 202311579944.4 (filed on November 23, 2023, invention title: display device, gamma correction circuit and display driving method). Technical Field

[0002] This disclosure generally relates to electronic devices including displays, and more specifically to display devices, gamma correction circuits, and display driving methods. Background Technology

[0003] With advancements in display technology, display devices can offer additional functionalities such as image capture and sensing capabilities, as well as image display capabilities. To provide these functionalities, display devices may need to include one or more optical and electronic devices, such as cameras and sensors for detecting images.

[0004] In order to receive light transmitted through the front surface of a display device, it may be desirable for such optical electronics to be located in an area of ​​the display device capable of increasingly receiving and detecting incident light from the front surface. To achieve this, in typical display devices, the optical electronics are designed to be located at the front of the display device, allowing cameras, sensors, etc., which are optical electronics, to be increasingly exposed to incident light. To mount the optical electronics in the display device in this way, the bezel area of ​​the display device may be enlarged, or it may be necessary to form notches or holes in the display area of ​​the associated display panel.

[0005] Therefore, when a display device requires optical electronics to receive or detect incident light and perform its intended function, the size of the bezel in the front of the display device may increase, or substantial disadvantages may be encountered when designing the front of the display device. Summary of the Invention

[0006] In addition to the technical challenges involved in integrating optoelectronic devices into display devices, the structure within the display device can also unintentionally degrade image quality and potentially impair the performance of the optoelectronic devices. For example, in the case where the optoelectronic device is a camera, the quality of images acquired by the camera may be reduced.

[0007] To address these issues, one or more embodiments of this disclosure may provide a display device comprising: a transmission and display structure in which one or more optical electronic devices configured to receive light are disposed below or at the lower portion of a display panel, and a display area of ​​the display panel overlapping with one or more optical electronic devices (hereinafter referred to as an optical area) is configured to serve as an image display and a light transmission path.

[0008] One or more embodiments of this disclosure can provide a display device, a gamma correction circuit, and a display driving method capable of reducing the level of the boundary between the user-perceived normal area and the optical area.

[0009] One or more embodiments of this disclosure can provide a display device, a gamma correction circuit, and a display driving method capable of reducing the color difference between the normal area and the optical area perceived by the user.

[0010] One or more embodiments of this disclosure can provide a display device, gamma correction circuit, and display driving method capable of preventing display artifacts such as brightness differences at the boundary between normal and optical areas.

[0011] According to various aspects of this disclosure, a display device may be provided, the display device comprising: a substrate including a display area for displaying an image, the display area including a first driving area, a second driving area and a boundary driving area between the first driving area and the second driving area; and a plurality of pixels including a plurality of first pixels disposed in the first driving area, a plurality of second pixels disposed in the second driving area and a plurality of third pixels disposed in the boundary driving area.

[0012] The number of pixels per unit area in the second driving region can be less than the number of pixels per unit area in the first driving region.

[0013] Each of the plurality of first pixels may have a first brightness for a first gray level according to a first gamma curve, each of the plurality of second pixels may have a second brightness for a first gray level according to a second gamma curve, and each of the plurality of third pixels may have a third brightness for a first gray level according to a third gamma curve.

[0014] All curves in the first gamma curve, the second gamma curve, and the third gamma curve can be different from each other, and all brightness levels in the first brightness level, the second brightness level, and the third brightness level can be different from each other.

[0015] The second driving region may include one or more transmission regions that allow light to pass through.

[0016] The display device may also include a gamma correction circuit for correcting the image data (e.g., performing digital gamma correction on the image data) based on the gamma curve among the first, second, and third gamma curves that corresponds to the position where the image data is provided, and outputting the corrected image data.

[0017] According to various aspects of this disclosure, a gamma correction circuit can be provided, comprising: a region identifier configured to identify a region in which sub-pixels to be provided with image data are disposed as one of a first driving region, a second driving region, and a boundary driving region between the first and second driving regions; a gamma curve selector configured to select a gamma curve corresponding to the identified region from a first gamma curve for the first driving region, a second gamma curve for the second driving region, and a third gamma curve for the boundary driving region; and a gamma correction processor configured to correct the image data based on the selected gamma curve (e.g., perform digital gamma correction on the image data) and output the corrected image data.

[0018] When the subpixel to be provided with image data is included in a plurality of first pixels set in the first driving region, the gamma correction processor can correct the image data according to the first gamma curve (e.g., perform digital gamma correction on the image data) and output the corrected image data.

[0019] When the subpixel to be provided with image data is included in a plurality of second pixels set in the second driving region, the gamma correction processor can correct the image data according to the second gamma curve (e.g., perform digital gamma correction on the image data) and output the corrected image data.

[0020] When the subpixel to be provided with image data is included in a plurality of third pixels set in the boundary driving region, the gamma correction processor can multiply the image data by a gain (e.g., a second gain), then correct the adjusted image data obtained by multiplication according to the third gamma curve (e.g., perform digital gamma correction on the adjusted image data), and output the corrected image data.

[0021] When the subpixel to be provided with image data is included in a plurality of fourth pixels set in the boundary driving region, the gamma correction processor can multiply the image data by another gain (e.g., a first gain), then correct the adjusted image data obtained by multiplication according to a third gamma curve (e.g., perform digital gamma correction on the adjusted image data), and output the corrected image data.

[0022] According to various aspects of this disclosure, a display driving method may be provided, comprising the steps of: identifying a region in which sub-pixels to be provided with image data are disposed as one of a first driving region, a second driving region, and a boundary driving region between the first driving region and the second driving region; and correcting the image data based on a gamma corresponding to the identified region among a first gamma for the first driving region, a second gamma for the second driving region, and a third gamma for the boundary driving region (e.g., performing digital gamma correction on the image data).

[0023] Among the first brightness at the first gray level according to the first gamma, the second brightness at the first gray level according to the second gamma, and the third brightness at the first gray level according to the third gamma, the second brightness can be the highest, and the third brightness can be higher than the first brightness and lower than the second brightness.

[0024] According to one or more embodiments of the present disclosure, a display device may be provided, the display device including a transmission and display structure, wherein one or more optical electronic devices required for receiving light are disposed below or at the lower part of a display panel, and the display area of ​​the display panel overlapping with one or more optical electronic devices is configured to serve as an image display and a light transmission path.

[0025] According to one or more embodiments of this disclosure, a display device, gamma correction circuit, and display driving method can be provided that can reduce the user's perception of the boundary between the normal area and the optical area by applying different gammas to the boundary between the normal area and the optical area.

[0026] According to one or more embodiments of this disclosure, a display device, a gamma correction circuit, and a display driving method can be provided that are capable of reducing the color difference between a user-perceived normal area and an optical area by using a separate gamma for each area.

[0027] According to one or more embodiments of the present disclosure, a display device, gamma correction circuit, and display driving method may be provided that can prevent display artifacts such as brightness differences at the boundary between the normal and optical regions by designing pixels to be arranged in the same layout at each location in the boundary between the normal and optical regions.

[0028] According to one or more embodiments of this disclosure, a display device, gamma correction circuit, and display driving method can be provided that can reduce power consumption, perform efficient driving, and achieve low-power design by using a gamma suitable for each region. Attached Figure Description

[0029] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated in and forming part of this disclosure, illustrate various aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings: Figure 1A , Figure 1B and Figure 1C Example display devices according to various aspects of this disclosure are shown; Figure 2 An example system configuration of a display device according to various aspects of this disclosure is shown; Figure 3 Example display panels according to various aspects of this disclosure are shown; Figure 4 An example first type of optical region and an example normal region surrounding the first type of optical region are schematically shown in a display panel according to various aspects of the present disclosure. Figure 5 and Figure 6 An example light-emitting element and an example pixel circuit for driving the light-emitting element are shown, which are arranged in a normal area, an optical bezel area and an optical area in a display panel according to various aspects of the present disclosure; Figure 7 This is an example plan view of the normal area, optical bezel area, and optical area included in a display panel according to various aspects of this disclosure; Figure 8 and Figure 9 These are example cross-sectional views of a display panel according to various aspects of this disclosure, as well as cross-sectional views of the optical bezel area and the optical area of ​​the display panel; Figure 10 An example of a second type of optical region and an example of a normal region surrounding the second type of optical region are shown in a display panel according to various aspects of this disclosure; Figure 11 This is an example plan view of a second type of optical region in a display panel according to various aspects of this disclosure; Figure 12 This is an example cross-sectional view of a second type of optical region in a display panel according to various aspects of this disclosure; Figure 13 An example structure of a display device according to various aspects of this disclosure is shown; Figure 14 An example corresponding pixel arrangement in each of the normal area and optical area of ​​a display device according to various aspects of this disclosure is shown; Figure 15 An example irregular pixel arrangement at the boundary between the normal area and the optical area in a display device according to various aspects of this disclosure is shown; Figure 16An example of a triple gamma-based boundary awareness level reduction drive in a display device according to various aspects of this disclosure is shown. Figure 17 An example pixel arrangement in the normal area, optical area, and boundary drive area of ​​a display device according to various aspects of this disclosure is shown; Figure 18 An example triple gamma curve for a triple gamma-based boundary awareness level reduction drive in a display device according to various aspects of this disclosure is shown. Figure 19 An example of each pixel in a display device according to various aspects of this disclosure is shown, driven by a triple gamma-based reduction in boundary awareness level. Figure 20 and Figure 21 The illustration shows example corresponding pixel brightness in each of the first driving region, the boundary driving region, and the second driving region when a triple gamma-based boundary awareness level reduction drive is performed in a display device according to aspects of the present disclosure. Figure 22 Nine example types of pixel arrangement patterns in the boundary driving region are shown when a triple gamma-based boundary awareness level reduction drive is performed in a display device according to various aspects of this disclosure. Figure 23 This is an example block diagram of a triple gamma-based gamma correction circuit in a display device according to various aspects of this disclosure; and Figure 24 This is an example block diagram of a display controller for a display device according to various aspects of the present disclosure. Detailed Implementation

[0030] Implementations of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings.

[0031] In the following description, the structures, implementations, methods, and operations described herein are not limited to one or more specific examples set forth herein and may be varied as is known in the art, unless otherwise stated. Unless otherwise stated, the same reference numerals always denote the same elements. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from the names used in actual products. The advantages and features of this disclosure and its implementation methods will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be considered as limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete enough to assist those skilled in the art in fully understanding the scope of this disclosure. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of this disclosure. The shapes, dimensions, ratios, angles, quantities, etc., shown in the drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. When using terms such as “comprising,” “having,” “containing,” “including,” “consisting of,” “composed of,” “formed by,” etc., one or more additional elements may be added unless a term such as “only” is used. Unless the context clearly indicates otherwise, elements described in the singular are intended to include multiple elements, and vice versa.

[0032] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0033] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be understood that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0034] When describing positional relationships, such as when using terms like "above," "over," "below," "over," "beside," or "near" to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately adjacent," "directly," or "closely neighboring" are used. For example, if one element or layer is positioned "above" another element or layer, a third element or layer may be inserted therebetween. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "above," and "below" refer to any frame of reference.

[0035] Furthermore, when referring to any size, relative size, etc., even without a specific description, it should be assumed that the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) include the tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "may".

[0036] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, for ease of description, the scale of each element shown in the drawings may differ from the actual scale. Therefore, the elements shown are not limited to the specific scales they are shown in the drawings.

[0037] Figure 1A , Figure 1B and Figure 1C Example display devices according to various aspects of this disclosure are shown.

[0038] Reference Figure 1A , Figure 1B and Figure 1C In one or more embodiments, the display device 100 according to various aspects of this disclosure may include a display panel 110 for displaying one or more images and one or more optical electronic devices (11 and / or 12). Hereinafter, the optical electronic devices may be referred to as light detectors, light receivers, or light sensing devices. The optical electronic devices may include one or more of a camera, camera lens, sensor, sensor for detecting images, etc.

[0039] The display panel 110 may include a display area DA in which one or more images can be displayed and a non-display area NDA in which no images are displayed. Multiple sub-pixels may be arranged in the display area DA, and various types of signal lines for driving the multiple sub-pixels may be arranged in the display area DA.

[0040] The non-display area NDA can refer to the area outside the display area DA. Various types of signal lines can be arranged in the non-display area NDA, and various types of drive circuits can be connected to various types of signal lines. At least a portion of the non-display area NDA can be bent to be invisible from the front surface of the display device 100, or it can be covered by the housing or casing (not shown) of the display device 100. The non-display area NDA can also be referred to as a bezel or bezel area.

[0041] Reference Figure 1A , Figure 1B and Figure 1C In one or more embodiments, in the display device 100 according to various aspects of the present disclosure, one or more optical electronic devices (11 and / or 12) may be fabricated independently of the display panel 110 and mounted in the display panel 110, and located below or in the lower part of the display panel 110 (on the side opposite to the viewing surface of the display panel 110).

[0042] Light can enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optoelectronic devices (11 and / or 12) located below or on the lower part of the display panel 110 (on the side opposite to the viewing surface). The light transmitted through the display panel 110 may include, for example, visible light, infrared light, or ultraviolet light.

[0043] One or more optical electronic devices (11 and / or 12) may be devices capable of receiving or detecting light transmitted through the display panel 110 and performing predefined functions based on the received light. For example, one or more optical electronic devices (11 and / or 12) may include one or more of the following: an image capturing device such as a camera (image sensor); or a sensor such as a proximity sensor, an illuminance sensor, etc. Such a sensor may be, for example, an infrared sensor capable of detecting infrared light.

[0044] Reference Figure 1A , Figure 1B and Figure 1C In one or more embodiments, the display area DA of the display panel 110 according to various aspects of this disclosure may include one or more optical areas (OA1 and / or OA2) and a normal area NA. Hereinafter, the term "normal area" NA may refer to an area present in the display area DA that does not overlap with one or more optoelectronic devices (11 and / or 12), and may also be referred to as a non-optical area. One or more optical areas (OA1 and / or OA2) may be one or more areas that overlap with one or more optoelectronic devices (11 and / or 12) respectively in a cross-sectional view of the display panel 110.

[0045] according to Figure 1A For example, the display area DA may include a first optical area OA1 and a normal area NA. In this example, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11.

[0046] according to Figure 1B For example, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA. In this example, a portion of the normal area NA may exist between the first optical area OA1 and the second optical area OA2. At least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0047] according to Figure 1C For example, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA. In this example, the normal area NA may not exist between the first optical area OA1 and the second optical area OA2. For example, the first optical area OA1 and the second optical area OA2 may be in contact with each other (e.g., in direct contact). In this example, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0048] In the display panel 110 or display device 100 according to various aspects of this disclosure, it may be desirable to implement both an image display structure and a light transmission structure in one or more optical regions (OA1 and / or OA2). For example, since one or more optical regions (OA1 and / or OA2) are part of the display area DA, it may be desirable to have the light-emitting region of the sub-pixel for displaying one or more images disposed in one or more optical regions (OA1 and / or OA2). Furthermore, in order for light to be able to transmit through one or more optoelectronic devices (11 and / or 12), it may be desirable to implement a light transmission structure in one or more optical regions (OA1 and / or OA2).

[0049] It should be noted that even if one or more optoelectronic devices (11 and / or 12) are devices that need to receive light, one or more optoelectronic devices (11 and / or 12) may be located on the back of the display panel 110 (e.g., on the side opposite to the viewing surface of the display panel 110), so that they can receive light that has passed through the display panel 110. For example, one or more optoelectronic devices (11 and / or 12) may not be exposed in the front surface (viewing surface) of the display panel 110 or the display device 100. Therefore, when the user is facing the front surface of the display device 100, one or more optoelectronic devices (11 and / or 12) are positioned so that they are not visible to the user.

[0050] The first optical electronic device 11 may be, for example, a camera, and the second optical electronic device 12 may be, for example, a sensor. The sensor may be a proximity sensor, an illumination sensor, an infrared sensor, etc. In one or more embodiments, the camera may be a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor, and the sensor may be an infrared sensor capable of detecting infrared light. In another embodiment, the first optical electronic device 11 may be a sensor, and the second optical electronic device 12 may be a camera.

[0051] In the following description, for ease of reference to the optical electronics (11 and 12), the first optical electronics 11 is considered as a camera, and the second optical electronics 12 is considered as an infrared sensor. However, it should be understood that the scope of this disclosure includes examples in which the first optical electronics 11 is an infrared sensor and the second optical electronics 12 is a camera. A camera may be, for example, a camera lens, an image sensor, or a unit that includes at least one of a camera lens and an image sensor.

[0052] In an example where the first optical electronic device 11 is a camera, the camera may be located on the back of the display panel 110 (e.g., below or in the lower part of the display panel 110) and is a front-facing camera capable of capturing objects or images in the frontal direction of the display panel 110. Therefore, a user can capture images or objects that are not visible on the viewing surface while viewing the viewing surface of the display panel 110.

[0053] Despite Figure 1A , Figure 1B and Figure 1CEach of the display areas DA in the diagram includes a normal area NA and one or more optical areas (OA1 and / or OA2) that are areas where images are allowed to be displayed. The normal area NA is an area that does not require the implementation of a light transmission structure, but the one or more optical areas (OA1 and / or OA2) are areas that require the implementation of a light transmission structure. Therefore, in one or more embodiments, the normal area NA is an area that does not have or include a light transmission structure, and the one or more optical areas (OA1 and / or OA2) are areas that have or include a light transmission structure.

[0054] Therefore, one or more optical regions (OA1 and / or OA2) may have a transmittance greater than or equal to a selected or predetermined level, such as a relatively high transmittance, and the normal region NA may have a transmittance less than a selected predetermined level, or may have no transmittance.

[0055] For example, one or more optical regions (OA1 and / or OA2) may have different resolutions, subpixel arrangement structures, number of subpixels per unit area, electrode structures, line structures, electrode arrangement structures, line arrangement structures, etc., than the normal region NA.

[0056] In one implementation, the number of subpixels per unit area in one or more optical regions (OA1 and / or OA2) may be less than the number of subpixels per unit area in the normal region NA. For example, the resolution of one or more optical regions (OA1 and / or OA2) may be lower than the resolution of the normal region NA. In this example, the number of subpixels per unit area can have the same meaning as resolution, pixel density, or pixel integration. For example, the unit for the number of subpixels per unit area may be pixels per inch (PPI), which represents the number of pixels per inch.

[0057] exist Figure 1A , Figure 1B and Figure 1C In the example, the number of sub-pixels per unit area in the first optical region OA1 can be less than the number of sub-pixels per unit area in the normal region NA. Figure 1B and Figure 1C In the example, the number of sub-pixels per unit area in the second optical region OA2 can be greater than or equal to the number of sub-pixels per unit area in the first optical region OA1, and less than the number of sub-pixels per unit area in the normal region NA.

[0058] In one or more embodiments, as a method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, a pixel density differentiation design scheme as described above can be applied, in which differences in pixel (or sub-pixel) density or pixel (or sub-pixel) integration can be generated between the first optical region OA1, the second optical region OA2, and the normal region NA. According to the pixel density differentiation design scheme, in one embodiment, the display panel 110 can be configured or designed such that the number of sub-pixels per unit area of ​​at least one of the first optical region OA1 and the second optical region OA2 is greater than the number of sub-pixels per unit area of ​​the normal region NA.

[0059] In one or more embodiments, as another method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, a pixel size differentiation design scheme can be applied, in which a difference in pixel (or sub-pixel) size can be created between the first optical region OA1, the second optical region OA2, and the normal region NA. According to the pixel size differentiation design scheme, the display panel PNL can be configured or designed such that when the number of sub-pixels per unit area of ​​at least one of the first optical region OA1 and the second optical region OA2 is equal to or similar to the number of sub-pixels per unit area of ​​the normal region NA, the size of each sub-pixel in at least one of the first optical region OA1 and the second optical region OA2 (e.g., the size of the corresponding light-emitting area) is smaller than the size of each sub-pixel in the normal region NA (e.g., the size of the corresponding light-emitting area).

[0060] In one or more aspects, for ease of description, the following discussion is provided based on a pixel density differentiation design scheme among two schemes (e.g., a pixel density differentiation design scheme and a pixel size differentiation design scheme) for increasing the respective transmittance of at least one of the first optical region OA1 and the second optical region OA2, unless otherwise explicitly stated. Therefore, it should be understood that in the following description, a small number of subpixels per unit area can be considered to correspond to small-sized subpixels, while a large number of quantum pixels per unit area can be considered to correspond to large-sized subpixels.

[0061] exist Figure 1A , Figure 1B and Figure 1C In the example, the first optical region OA1 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. Figure 1B and Figure 1CIn the example, the second optical region OA2 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. The first optical region OA1 and the second optical region OA2 can have the same or substantially the same or nearly the same shape, or different shapes.

[0062] Reference Figure 1C In examples where the first optical region OA1 and the second optical region OA2 are in contact with each other (e.g., in direct contact), the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. In the following description, for ease of reference to the shapes of the optical regions (OA1 and OA2), each of the first optical region OA1 and the second optical region OA2 is considered to have a circular shape. However, it should be understood that the scope of this disclosure includes examples where at least one of the first optical region OA1 and the second optical region OA2 has a shape other than a circular shape.

[0063] According to one or more aspects of this disclosure, when a display device 100 has a structure in which a first optical electronic device 11, such as a camera, is located below or in the lower part of the display panel 110 and is not exposed to the outside, such a display device may be referred to as a display that implements under-display camera (UDC) technology.

[0064] The display device 100 implementing this under-display camera (UDC) technology offers the advantage of preventing a reduction in the area or size of the display area DA because it eliminates the need to form a notch or camera hole in the display panel 110 for exposing the camera. In fact, since it eliminates the need to form a notch or camera hole in the display panel 110 for camera exposure, the display device 100 offers the further advantage of reducing the size of the bezel area and increasing design freedom, as this limitation on design is eliminated.

[0065] Although one or more optoelectronic devices (11 and / or 12) are located on the back of the display panel 110 of the display device 100 (e.g., below or in the lower part of the display panel 110) (e.g., hidden or not exposed to the outside), it is expected that one or more optoelectronic devices (11 and / or 12) can perform their normal predefined functions by receiving or detecting light.

[0066] Furthermore, although one or more optoelectronic devices (11 and / or 12) are located on the back side of the display panel 110 (e.g., below or in the lower part of the display panel 110) to be hidden and thus positioned to overlap with the display area DA, it is desirable that the display device 100 be able to normally display one or more images in one or more optical areas (OA1 and / or OA2) overlapping with one or more optoelectronic devices (11 and / or 12) in the display area DA. Therefore, even if one or more optoelectronic devices (11 and / or 12) are located on the back side of the display panel, the display device 100 according to various aspects of this disclosure can also be configured to display images in a normal manner (e.g., without degrading image quality) in one or more optical areas (OA1 and / or OA2) overlapping with one or more optoelectronic devices (11 and / or 12) in the display area DA.

[0067] Since the first optical region OA1 is configured or designed as an optical transmission region, the image display quality in the first optical region OA1 may differ from the image display quality in the normal region NA.

[0068] Furthermore, when the first optical region OA1 is designed for the purpose of improving image display quality, the transmittance of the first optical region OA1 may sometimes decrease.

[0069] To address these issues, in one or more aspects, the first optical region OA1 included in the display device 100 or display panel may be configured with or include a structure capable of preventing image quality differences (e.g., non-uniformity) between the first optical region OA1 and the normal region NA and improving the transmittance of the first optical region OA1.

[0070] Furthermore, in addition to the first optical region OA1, the second optical region OA2 included in the display device 100 or display panel 110 according to various aspects of this disclosure may also be configured with or include structures that can improve the image quality of the second optical region OA2 and improve the transmittance of the second optical region OA2.

[0071] It should also be noted that the first optical region OA1 and the second optical region OA2 included in the display device 100 or display panel 110 according to various aspects of this disclosure may be implemented differently or have different application examples, while having similarities in terms of optical transmission area. Taking into account such differences, the structures of the first optical region OA1 and the second optical region OA2 in the display device 100 according to various aspects of this disclosure may be configured or designed differently from each other.

[0072] Figure 2 An example system configuration of a display device 100 according to various aspects of this disclosure is shown.

[0073] Reference Figure 2 The display device 100 may include a display panel 110 and a display driving circuit as components for displaying one or more images.

[0074] The display driving circuit may be a circuit for driving the display panel 110, and includes a data driving circuit 220, a gating driving circuit 230, a display controller 240 and other circuit components.

[0075] Display panel 110 may include a display area DA in which one or more images can be displayed and a non-display area NDA in which no images are displayed. The non-display area NDA may be an area outside the display area DA and may also be referred to as an edge area or border area. All or at least a portion of the non-display area NDA may be an area visible from the front surface of display device 100, or an area that is bent out of the front surface of display device 100 and is not visible. Display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Display panel 110 may also include various types of signal lines to drive the plurality of sub-pixels SP.

[0076] In one or more embodiments, the display device 100 according to aspects of the present disclosure may be a liquid crystal display device or a self-emissive display device that emits light from the display panel 110 itself. In an example where the display device 100 according to aspects of the present disclosure is implemented as a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element. For example, the display device 100 according to aspects of the present disclosure may be an organic light-emitting display device implemented using one or more organic light-emitting diodes (OLEDs). In another example, the display device 100 according to aspects of the present disclosure may be an inorganic light-emitting display device implemented using one or more light-emitting diodes based on inorganic materials. In yet another example, the display device 100 according to aspects of the present disclosure may be a quantum dot display device implemented using quantum dots, where quantum dots are self-emissive semiconductor crystals.

[0077] The structure of each of the plurality of subpixels SP can be configured or designed differently depending on the type of display device 100. For example, in an example where the display device 100 is a self-emissive display device including self-emissive subpixels SP, each subpixel SP may include a self-emissive light-emitting element, one or more transistors, and one or more capacitors.

[0078] In one or more embodiments, various types of signal lines arranged in the display device 100 may include, for example, multiple data lines DL for carrying data signals (which may be referred to as data voltage or image signals), multiple gating lines GL for carrying gating signals (which may be referred to as scan signals), etc.

[0079] Multiple data lines (DL) and multiple gating lines (GL) can intersect each other. Each of the multiple data lines (DL) can extend in a first direction. Each of the multiple gating lines (GL) can extend in a second direction different from the first direction. For example, the first direction can be a column or vertical direction, while the second direction can be a row or horizontal direction. In another example, the first direction can be a row or horizontal direction, while the second direction can be a column or vertical direction.

[0080] The data driving circuit 220 can be a circuit for driving multiple data lines DL, and can provide data signals to the multiple data lines DL. The gating driving circuit 230 can be a circuit for driving multiple gating lines GL, and can provide gating signals to the multiple gating lines GL.

[0081] The display controller 240 can be a device for controlling the data drive circuit 220 and the gating drive circuit 230, and can control the driving time of multiple data lines DL and the driving time of multiple gating lines GL.

[0082] The display controller 240 can provide a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and provide a gating drive control signal GCS to the gating drive circuit 230 to control the gating drive circuit 230.

[0083] The display controller 240 can receive input image data (which may be referred to as image signal) from the host system 250 and provide image data Data to the data drive circuit 220 based on the input image data.

[0084] For example, the input image data (or image signal) received by the display controller 240 from the host system 250 may include red signal values, green signal values, and blue signal values.

[0085] The data drive circuit 220 can receive digital image data Data from the display controller 240, convert the received image data Data into an analog data signal, and output the obtained analog data signal to multiple data lines DL.

[0086] The gating drive circuit 230 can receive a first gating voltage corresponding to the on-level voltage and a second gating voltage corresponding to the off-level voltage, as well as various gating drive control signals GCS, generate gating signals, and provide the generated gating signals to multiple gating lines GL.

[0087] In one or more embodiments, the data drive circuit 220 may be connected to the display panel 110 in a tape auto-bonding (TAB) type, or to conductive pads such as bonding pads of the display panel 110 in a chip-on-glass (COG) type or chip-on-panel (COP) type, or to the display panel 110 in a chip-on-film (COF) type.

[0088] In one or more embodiments, the gate drive circuit 230 may be connected to the display panel 110 in a tape auto-bonding (TAB) type, or to conductive pads such as bonding pads on the display panel 110 in a chip-on-glass (COG) or chip-on-panel (COP) type, or to the display panel 110 in a chip-on-film (COF) type. In another embodiment, the gate drive circuit 230 may be disposed in the non-display area NDA of the display panel 110 in a gate-in-panel (GIP) type. The gate drive circuit 230 may be disposed on the substrate or connected to the substrate. That is, in the case of the GIP type, the gate drive circuit 230 may be disposed in the non-display area NDA of the substrate. In the case of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., the gate drive circuit 230 may be connected to the substrate.

[0089] In one or more embodiments, at least one of the data driving circuit 220 and the gating driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gating driving circuit 230 may be configured such that it does not overlap with sub-pixel SP, or is configured such that it overlaps with one or more or all of the sub-pixels of sub-pixel SP, or overlaps with at least one or more corresponding portions of one or more sub-pixels.

[0090] The data driving circuit 220 may be located and / or electrically connected to, but not limited to, only one side or portion of the display panel 110 (e.g., the upper edge or the lower edge). In one or more embodiments, depending on the driving scheme, panel design, etc., the data driving circuit 220 may be located and / or electrically connected to, but not limited to, at least two of the four sides or portions of the display panel 110 (e.g., the upper edge and the lower edge) or four of the four sides or portions of the display panel 110 (e.g., the upper edge, the lower edge, the left edge, and the right edge).

[0091] The gating drive circuit 230 may be located and / or electrically connected to, but not limited to, only one side or portion of the display panel 110 (e.g., the left edge or the right edge). In one or more embodiments, depending on the driving scheme, panel design, etc., the gating drive circuit 230 may be located and / or electrically connected to, but not limited to, two sides or portions of the display panel 110 (e.g., the left edge and the right edge) or at least two of the four sides or portions of the display panel 110 (e.g., the top edge, the bottom edge, the left edge, and the right edge).

[0092] The display controller 240 can be implemented as a component separate from the data drive circuit 220, or it can be incorporated into the data drive circuit 220 and thus implemented as an integrated circuit.

[0093] Display controller 240 may be a timing controller used in typical display technologies, or it may be a controller or control device capable of performing control functions other than those of a typical timing controller. In one or more embodiments, display controller 140 may be a controller or control device different from the timing controller, or may be circuitry or components included in a controller or control device. Display controller 240 may be implemented using various circuitry or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0094] The display controller 240 can be mounted on a printed circuit board, flexible printed circuit, etc., and is electrically connected to the gating drive circuit 230 and the data drive circuit 220 through the printed circuit board, flexible printed circuit, etc.

[0095] The display controller 240 can send signals to and receive signals from the data driver circuit 220 via one or more predefined interfaces. For example, such interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc.

[0096] In one or more embodiments, to further provide touch sensing and image display functions, the display device 100 according to various aspects of the present disclosure may include at least one touch sensor and a touch sensing circuit, which can detect whether a touch object such as a finger or pen has triggered a touch event by sensing the touch sensor, or can detect the corresponding touch position (or touch coordinates).

[0097] The touch sensing circuit may include: a touch driver circuit 260 capable of generating and providing touch sensing data by driving and sensing a touch sensor; a touch controller 270 capable of using the touch sensing data to detect the occurrence of a touch event or to detect the touch position (or touch coordinates); and one or more other components.

[0098] The touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to the touch driver circuit 260.

[0099] The touch sensor can be implemented externally as a touch panel on the display panel 110, or integrated internally within the display panel 110. In the example where the touch sensor is implemented externally as a touch panel on the display panel 110, this type of touch sensor can be referred to as an add-on type. In the example where an add-on type touch sensor is disposed in the display device 100, the touch panel and the display panel 110 can be manufactured separately and combined in an assembly process. The add-on type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0100] In an example where the touch sensor is integrated inside the display panel 110, the touch sensor can be formed on the substrate SUB along with signal lines and electrodes associated with display driving during the manufacturing process of the display panel 110.

[0101] The touch driving circuit 260 can provide a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0102] Touch sensing circuits can use self-capacitance sensing technology or mutual capacitance sensing technology to perform touch sensing.

[0103] In an example where the touch sensing circuit uses self-capacitance sensing technology to perform touch sensing, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.). According to self-capacitance sensing technology, each of the plurality of touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or one or more of the plurality of touch electrodes and sense all or one or more of the plurality of touch electrodes.

[0104] In an example where touch sensing is performed using mutual capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing technology, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0105] The touch driving circuit 260 and touch controller 270 included in the touch sensing circuit can be implemented as separate devices or as a single device. Furthermore, the touch driving circuit 260 and data driving circuit 220 can be implemented as separate devices or as a single device.

[0106] The display device 100 may also include a power supply circuit for providing various types of power to the display driving circuit and / or touch sensing circuit.

[0107] The display device 100 according to various aspects of this disclosure may represent, but is not limited to, mobile terminals such as smartphones, tablets, etc., or monitors, televisions (TVs), etc. Embodiments of this disclosure are not limited thereto. In one or more embodiments, the display device 100 may be a display device of various types, sizes, and shapes for displaying information or images, or may include a monitor.

[0108] As mentioned above, such as Figure 1A , Figure 1B and Figure 1C As shown, the display area DA of the display panel 110 may include a normal area NA and one or more optical areas (OA1 and / or OA2). The normal area NA and one or more optical areas (OA1 and / or OA2) may be areas capable of displaying images. It should be noted that the normal area NA may be an area that does not require the implementation of a light transmission structure, and the one or more optical areas (OA1 and / or OA2) may be areas that require the implementation of a light transmission structure.

[0109] As mentioned above Figure 1A , Figure 1B and Figure 1C As discussed in the examples, although the display area DA of the display panel 110 may include one or more optical areas (OA1 and / or OA2) and a normal area NA, for ease of description, the following discussion will be based on the following example, in which the display area DA includes a first optical area OA1 and a second optical area OA2 (e.g., Figure 1A , Figure 1B and Figure 1C The first optical region OA1, and Figure 1B and Figure 1C The second optical region OA2) and both and the normal region NA (e.g., Figure 1A , Figure 1B and Figure 1C The normal region NA).

[0110] Figure 3 An example system configuration of a display device 100 according to various aspects of this disclosure is shown.

[0111] Reference Figure 3 Multiple subpixels SP can be disposed within the display area DA of the display panel 110. Multiple subpixels SP can be disposed within the normal area (e.g.,) included in the display area DA of the display panel 110. Figure 1A , Figure 1B and Figure 1C The normal area), the first optical area (e.g., Figure 1A , Figure 1B and Figure 1C The first optical region OA1) and the second optical region (e.g., Figure 1B and Figure 1C In the second optical region OA2).

[0112] Each of the multiple sub-pixels SP may include a light-emitting element ED and a pixel circuit SPC configured to drive the light-emitting element FD. The pixel circuit SPC may include a driving transistor DT for driving the light-emitting element ED, a scanning transistor ST for transmitting a data voltage Vdata to a first node N1 of the driving transistor DT, a storage capacitor Cst for maintaining the voltage at an approximately constant level during a frame, etc.

[0113] The driving transistor DT may include a first node N1 to which a data voltage is applied, a second node N2 electrically connected to a light-emitting element ED, and a third node N3 to which a driving voltage ELVDD is applied via a driving voltage line DVL. In the driving transistor DT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. For ease of description, the following description will be provided based on examples where the first, second, and third nodes (N1, N2, and N3) of the driving transistor DT are respectively gate nodes, source nodes, and drain nodes, unless otherwise explicitly stated. However, it should be understood that the scope of this disclosure includes examples where the first, second, and third nodes (N1, N2, and N3) of the driving transistor DT are respectively gate nodes, drain nodes, and source nodes.

[0114] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​may represent a pixel electrode disposed in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DT of each sub-pixel SP. The cathode electrode CE may represent a common electrode disposed in multiple sub-pixels SP, and a basic voltage ELVSS, such as a low-level voltage or ground voltage, may be applied to the cathode electrode CE.

[0115] For example, the anode electrode AE ​​can be a pixel electrode, and the cathode electrode CE can be a common electrode. In another example, the anode electrode AE ​​can be a common electrode, and the cathode electrode CE can be a pixel electrode. For ease of description, unless explicitly stated otherwise, the following discussion will be based on the example where the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode. However, it should be understood that the scope of this disclosure includes the example where the anode electrode AE ​​is a common electrode and the cathode electrode CE is a pixel electrode.

[0116] A light-emitting element (ED) may include a light-emitting region (EA) having a predetermined size or area. The light-emitting region (EA) of the light-emitting element (ED) may be defined, for example, as the area where the anode electrode (AE), the light-emitting layer (EL), and the cathode electrode (CE) overlap with each other.

[0117] The light-emitting element (ED) can be, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting element, etc. In the example where an organic light-emitting diode (OLED) is used as the light-emitting element (ED), its light-emitting layer (EL) can include an organic light-emitting layer containing organic materials.

[0118] The scanning transistor ST can be turned on and off by the scanning signal SCAN, which is a gating signal applied by the gating line GL. The scanning transistor ST can be electrically connected between the first node N1 of the driving transistor DT and the data line DL.

[0119] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

[0120] like Figure 3 As shown, the pixel circuit SPC can be configured with two transistors (2T: DRT and SCT) and one capacitor (1C: CST) (which can be referred to as "2T1C structure"), and in one or more implementations, it may also include one or more transistors and / or one or more capacitors.

[0121] In one or more embodiments, the storage capacitor Cst, which may exist between the first node N1 and the second node N2 of the driving transistor DT, may be an external capacitor intentionally configured or designed to be located outside the driving transistor DT, rather than an internal capacitor such as a parasitic capacitor (e.g., gate-to-source capacitance Cgs, gate-to-drain capacitance Cgd, etc.). Each of the driving transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.

[0122] Since the circuit elements included in each sub-pixel SP (specifically, light-emitting elements ED implemented using organic light-emitting diodes comprising organic materials) are susceptible to external moisture or oxygen, an encapsulation layer ENCAP can be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into these circuit elements. The encapsulation layer ENCAP can be configured to cover the light-emitting element ED.

[0123] In the following text, for ease of description, the term "optical region OA" will be used instead of distinguishing between the first optical region OA1 and the second optical region OA2 described above. Therefore, it should be noted that the optical region described below may refer to any one or both of the first optical region OA1 and the second optical region OA2 described above, unless otherwise expressly stated.

[0124] Similarly, for ease of description, the term "optical electronic device" is used instead of distinguishing between the first optical electronic device 11 and the second optical electronic device 12 described above. Therefore, it should be noted that the optical electronic device described below may refer to any one or both of the first optical electronic device 11 and the second optical electronic device 12 described above, unless otherwise expressly stated.

[0125] In the following text, reference will be made to Figures 4 to 9 Describe the optical region OA of the first type of example, and refer to Figures 10 to 12 Example description of optical region OA of type 2.

[0126] The first type of optical region OA and the second type of optical region OA are briefly described as follows.

[0127] In the case of the first type of optical region OA, one or more pixel circuits SPC used to drive one or more light-emitting elements ED disposed in the optical region OA can be disposed in a region outside the optical region OA, rather than disposed in the optical region OA.

[0128] In the case of the second type of optical region OA, one or more pixel circuits SPC for driving one or more light-emitting elements ED disposed in the optical region OA can be disposed in the optical region OA.

[0129] Figure 4 An example first type optical region OA and an example normal region NA surrounding the first type optical region OA are schematically shown in a display panel 110 according to various aspects of the present disclosure.

[0130] Reference Figure 4In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may include a display area (e.g., the display area DA in the above figures) capable of displaying one or more images and a non-display area (e.g., the non-display area NDA in the above figures) not displaying images.

[0131] Reference Figure 4 The display area DA may include an optical area OA through which light can pass and a normal area NA surrounding the optical area OA. The optical area OA may have a first type of structure. Therefore, in an example of implementing the optical area OA in the first type, an optical border area OBA may be disposed outside the optical area OA. In one or more embodiments, the optical border area OBA may represent a portion of the normal area NA.

[0132] In other words, when the optical region OA is implemented in the first type, the display region DA may include the optical region OA, the normal region NA located outside the optical region OA, and the optical border region OBA between the optical region OA and the normal region NA.

[0133] Reference Figure 4 The optical region OA can be an area overlapping with an optoelectronic device, and can be a transmission region through which light used for the operation of the optoelectronic device can be transmitted. Light transmitted through the optical region OA can include light of a single wavelength or light of various wavelengths. For example, the optical region OA can be configured to allow, but is not limited to, the transmission of at least one of visible light, infrared light, ultraviolet light, etc.

[0134] An optical electronic device disposed in an optical region OA can receive light transmitted through the optical region OA and use the received light to perform a predefined operation. The light received by the optical electronic device through the optical region OA can include at least one of visible light, infrared light, and ultraviolet light.

[0135] For example, in an example where the optical electronics is a camera, the light that has passed through the optical region OA for a predefined operation of the optical electronics may include visible light. In another example, where the optical electronics is an infrared sensor, the light that has passed through the optical region OA for a predefined operation of the optical electronics may include infrared radiation (also known as infrared light).

[0136] Reference Figure 4 The optical border region OBA can represent the area outside the optical region OA. The normal region NA can represent the area outside the optical border region OBA. The optical border region OBA can be set between the optical region OA and the normal region NA.

[0137] For example, the optical border region OBA can be set outside only a portion of the edge of the optical region OA, or outside the entire edge of the optical region OA.

[0138] In an example where the optical border region OBA is positioned outside the entire edge of the optical region OA, the optical border region OBA can have a ring-shaped form surrounding the optical region OA. For example, the optical region OA can have various shapes such as circular, elliptical, polygonal, irregular, etc. The optical border region OBA can have various ring-shaped forms (e.g., circular ring, elliptical ring, polygonal ring, irregular ring, etc.) surrounding the optical region OA, which has various shapes.

[0139] Reference Figure 4 The display area DA can include multiple light-emitting areas EA. Since the optical area OA, the optical bezel area OBA, and the normal area NA are included in the display area DA, each of the optical area OA, the optical bezel area OBA, and the normal area NA can include multiple light-emitting areas EA.

[0140] For example, multiple light-emitting regions EA may include a first-color light-emitting region that emits light of a first color, a second-color light-emitting region that emits light of a second color, and a third-color light-emitting region that emits light of a third color.

[0141] At least one of the first color emitting region, the second color emitting region, and the third color emitting region may have an area or size different from the remaining one or more emitting regions.

[0142] The first color, the second color, and the third color can be different colors from each other, and can be various colors. For example, the first color, the second color, and the third color can be red, green, and blue, respectively.

[0143] In the following text, for ease of description, the first color, the second color, and the third color will be considered as red, green, and blue, respectively. However, the embodiments of this disclosure are not limited thereto.

[0144] In the example where the first, second, and third colors are red, green, and blue, respectively, the area of ​​the blue emitting region EA_B can be larger than the area of ​​the red emitting region EA_R and the area of ​​the green emitting region EA_G.

[0145] The light-emitting element ED located in the red light-emitting region EA_R may include a light-emitting layer EL that emits red light. The light-emitting element ED located in the green light-emitting region EA_G may include a light-emitting layer EL that emits green light. The light-emitting element ED located in the blue light-emitting region EA_B may include a light-emitting layer EL that emits blue light.

[0146] The organic materials included in the blue light-emitting layer (EL) may be more prone to degradation than the corresponding organic materials included in the red light-emitting layer (EL) and the green light-emitting layer (EL).

[0147] In one or more embodiments, since the blue emitting region EA_B is configured or designed to have the largest area or size, the current density supplied to the light-emitting element ED disposed in the blue emitting region EA_B can be the smallest. Therefore, the degree of degradation of the light-emitting element ED disposed in the blue emitting region EA_B can be similar to the degree of degradation of the light-emitting element ED disposed in the red emitting region EA_R and the degree of degradation of the light-emitting element ED disposed in the green emitting region ER_G.

[0148] As a result, the degradation differences between the light-emitting elements ED in the red light-emitting region EA_R, the light-emitting elements ED in the green light-emitting region EA_G, and the light-emitting elements ED in the blue light-emitting region EA_B can be reduced or minimized (or, in some cases, eliminated). Therefore, the display device 100 or display panel 110 according to various aspects of the present disclosure can provide the advantage of improved image quality. Furthermore, since the degradation differences between the light-emitting elements ED in the red light-emitting region EA_R, the light-emitting elements ED in the green light-emitting region EA_G, and the light-emitting elements ED in the blue light-emitting region EA_B are eliminated or reduced, the display device 100 or display panel 110 according to various aspects of the present disclosure can provide the advantage of reduced lifespan differences between the light-emitting elements ED in the red light-emitting region EA_R, the light-emitting elements ED in the green light-emitting region EA_G, and the light-emitting elements ED in the blue light-emitting region EA_B.

[0149] Reference Figure 4 The optical region OA, which serves as the optical transmission region, is expected to have high transmittance. To meet this requirement, the cathode electrode (e.g., Figure 3 The cathode electrode (CE) may include multiple cathode holes (CH) in the optical region OA. In other words, the cathode electrode CE may include multiple cathode holes (CH) in the optical region OA.

[0150] Reference Figure 4 In one or more embodiments, the cathode electrode CE may not include the cathode hole CH in the normal region NA. That is, in the normal region NA, the cathode electrode CE may not include the cathode hole CH.

[0151] In one or more embodiments, the cathode electrode CE may not include the cathode hole CH in the optical frame region OBA. That is, the cathode electrode CE may not include the cathode hole CH in the optical frame region OBA.

[0152] In the optical region OA, the multiple cathode holes CH formed in the cathode electrode CE can be referred to as multiple transmission regions TA or multiple openings. Although Figure 4 It is shown that each cathode hole CH has a corresponding circular shape. One or more cathode holes CH can have various shapes other than circular shapes, such as elliptical shapes, polygonal shapes, irregular shapes, etc.

[0153] Figure 5 An example configuration of a display panel 110 according to various aspects of this disclosure is shown. For example... Figure 5 As shown, the display panel 110 may include light-emitting elements (ED1, ED2, ED3 and ED4) disposed in the normal area NA, the optical bezel area OBA and the optical area OA, as well as pixel circuits (SPC1, SPC2, SPC3 and SPC4) for driving the light-emitting elements (ED1, ED2, ED3 and ED4).

[0154] It should be understood here that, for example Figure 3 As shown, each of the pixel circuits (SPC1, SPC2, SPC3, and SPC4) may include transistors (DT and ST), storage capacitors Cst, etc. However, it should be noted that, for ease of description, each of the pixel circuits (SPC1, SPC2, SPC3, and SPC4) is simply represented as the corresponding driving transistor (DT1, DT2, DT3, and DT4).

[0155] Reference Figure 5 The normal region NA, the optical region OA, and the optical border region OBA can have structural and positional differences.

[0156] As an example of this structural difference, one or more pixel circuits (SPC1, SPC2, SPC3, and / or SPC4) can be placed in the optical border region OBA and the normal region NA, but pixel circuits can be omitted from the optical region OA. For example, the optical border region OBA and the normal region NA can be configured to allow one or more transistors (DT1, DT2, DT3, and / or DT4) to be placed therein, but the optical region OA can be configured to disallow transistors to be placed therein.

[0157] The transistors and storage capacitors included in the pixel circuits (SPC1, SPC2, SPC3, and SPC4) can be components that lead to a decrease in transmittance. Therefore, since the pixel circuits (e.g., SPC1, SPC2, SPC3, or SPC4) are not located in the optical region OA, the transmittance of the optical region OA can be further improved.

[0158] In one or more embodiments, although the pixel circuits (SPC1, SPC2, SPC3 and SPC4) may be disposed only in the normal region NA and the optical border region OBA, the light-emitting elements (ED1, ED2, ED3 and ED4) may also be disposed in the normal region NA, the optical border region OBA and the optical region OA.

[0159] Reference Figure 5 Although the first light-emitting element ED1 can be located in the optical region OA, the first pixel circuit SPC1 used to drive the first light-emitting element ED1 may not be located in the optical region OA.

[0160] Reference Figure 5 The first pixel circuit SPC1, which drives the first light-emitting element ED1 located in the optical region OA, can be located in the optical border region OBA, instead of in the optical region OA.

[0161] The normal region NA, optical region OA, and optical border region OBA will be described in more detail below.

[0162] Reference Figure 5 In one or more embodiments, the plurality of light-emitting regions EA included in the display panel 110 according to various aspects of the present disclosure may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. In these embodiments, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be included in an optical region OA, an optical bezel region OBA, and a normal region NA, respectively. Hereinafter, it is assumed that the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are regions that emit light of the same color.

[0163] Reference Figure 5 In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may include: a first light-emitting element ED1 disposed in an optical region OA1 and having a first light-emitting region EA1; a second light-emitting element ED2 disposed in an optical border region OBA1 and having a second light-emitting region EA2; and a third light-emitting element ED3 disposed in a normal region NA and having a third light-emitting region EA3.

[0164] Reference Figure 5 In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include a first pixel circuit SPC1 configured to drive a first light-emitting element ED1, a second pixel circuit SPC2 configured to drive a second light-emitting element ED2, and a third pixel circuit SPC3 configured to drive a third light-emitting element ED3.

[0165] Reference Figure 5 The first pixel circuit SPC1 may include a first driving transistor DT1. The second pixel circuit SPC2 may include a second driving transistor DT2. The third pixel circuit SPC3 may include a third driving transistor DT3.

[0166] Reference Figure 5 In one or more embodiments, in the display panel 110 according to various aspects of the present disclosure, the second pixel circuit SPC2 may be located in the optical bezel area OBA in which a second light-emitting element ED2 corresponding to the second pixel circuit SPC2 is provided, and the third pixel circuit SPC3 may be located in the normal area NA in which a third light-emitting element ED3 corresponding to the third pixel circuit SPC3 is provided.

[0167] Reference Figure 5 In one or more embodiments, in the display panel 110 according to various aspects of the present disclosure, the first pixel circuit SPC1 may not be located in the optical region OA where the first light-emitting element ED1 corresponding to the first pixel circuit SPC1 is disposed. Instead, the first pixel circuit SPC1 may be located in the optical bezel region OBA, which is located outside the optical region OA. As a result, the transmittance of the optical region OA can be improved.

[0168] Reference Figure 5 In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include an anode extension line AEL that electrically connects a first light-emitting element ED1 disposed in an optical region OA to a first pixel circuit SPC1 disposed in an optical bezel region OBA.

[0169] The anode extension line AEL can electrically extend or connect the anode electrode AE ​​of the first light-emitting element ED1 to the second node N2 of the first driving transistor DT1 in the first pixel circuit SPC1.

[0170] As described above, in the display panel 110 according to various aspects of this disclosure, the first pixel circuit SPC1 for driving the first light-emitting element ED1 disposed in the optical region OA can be disposed in the optical bezel region OBA, rather than in the optical region OA. Such a configuration or structure can be referred to as an anode extension structure. Similarly, the first type of optical region OA can also be referred to as an anode extension type.

[0171] In embodiments of the display panel 110 according to various aspects of the present disclosure having such an anode extension structure, all or at least a portion of the anode extension line AEL can be disposed in the optical region OA, and the anode extension line AEL can include a transparent material, or can be a transparent line, or include a transparent line. Therefore, even when the anode extension line AEL for connecting the first pixel circuit SPC1 to the first light-emitting element ED1 is disposed in the optical region OA, the display device or display panel 110 according to various aspects of the present disclosure can prevent a decrease in the transmittance of the optical region OA.

[0172] Reference Figure 5 The multiple light-emitting regions EA may also include a fourth light-emitting region EA4 that emits light of the same color as the first light-emitting region EA1 and is included in the optical region OA.

[0173] Reference Figure 5 The fourth light-emitting area EA4 can be set adjacent to the first light-emitting area EA1 along the row or column direction.

[0174] Reference Figure 5 In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include a fourth light-emitting element ED4 disposed in an optical region OA and having a fourth light-emitting region EA4, and a fourth pixel circuit SPC4 configured to drive the fourth light-emitting element ED4.

[0175] Reference Figure 5 The fourth pixel circuit SPC4 may include a fourth driving transistor DT4. For ease of description, from Figure 5 The scanning transistor ST and storage capacitor Cst included in the fourth pixel circuit SPC4 are omitted.

[0176] Reference Figure 5 Although the fourth pixel circuit SPC4 is used to drive the fourth light-emitting element ED4 located in the optical region OA, the fourth pixel circuit SPC4 can also be located in the optical border region OBA.

[0177] Reference Figure 5 In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include an anode extension line AEL for electrically connecting the fourth light-emitting element ED4 to the fourth pixel circuit SPC4.

[0178] All or at least a portion of the anode extension line AEL can be disposed in the optical region OA, and the anode extension line AEL may include transparent material, or may be a transparent line, or may include a transparent line.

[0179] As described above, the first pixel circuit SPC1 located in the optical frame region OBA can be configured to drive a light-emitting element ED1 located in the optical region OA. Such a circuit connection scheme can be referred to as a one-to-one (1:1) circuit connection scheme.

[0180] As a result, the number of pixel circuits (SPCs) disposed in the optical frame area (OBA) can be significantly increased. Furthermore, the structure of the OBA may become more complex, and the aperture area of ​​the OBA may be reduced. In this paper, the aperture area may be referred to as the light-emitting area, and may also be referred to as the aperture ratio or aperture size ratio.

[0181] In order to increase the opening area of ​​the optical frame area (OBA) while having an anode extension structure, in one or more embodiments, the display device 100 according to various aspects of the present disclosure may be configured with a 1:N (where N is 2 or greater) circuit connection scheme.

[0182] According to the 1:N circuit connection scheme, the first pixel circuit SPC1 set in the optical frame region OBA can be configured to drive the two light-emitting elements ED set in the optical region OA simultaneously or together.

[0183] For ease of description, Figure 6 A 1:2 circuit connection scheme is shown as an example. In this example, the first pixel circuit SPC1, located in the optical frame region OBA, can be configured to simultaneously or together drive two or more light-emitting elements (ED1 and ED4) located in the optical region OA.

[0184] In one or more embodiments, reference is made to Figure 6 The light-emitting elements (ED1, ED2, ED3 and ED4) and the pixel circuits (SPC1, SPC2 and SPC3) for driving the light-emitting elements (ED1, ED2, ED3 and ED4) are disposed in the normal area NA, the optical bezel area OBA and the optical area OA, respectively, and can be disposed in the display panel 110.

[0185] Reference Figure 6 The fourth light-emitting element ED4, located in the optical region OA, can be driven by the first pixel circuit SPC1, which drives the first light-emitting element ED1 located in the optical region OA. That is, the first pixel circuit SPC1, located in the optical frame region OBA, can be configured to drive the first light-emitting element ED1 and the fourth light-emitting element ED4 located in the optical region OA together or substantially simultaneously.

[0186] Therefore, even when the display panel 110 has an anode extension structure, the number of pixel circuits SPCs provided in the optical bezel area OBA can be significantly reduced, thereby increasing the opening area and light-emitting area of ​​the optical bezel area OBA.

[0187] exist Figure 6 In the example, the first light-emitting element ED1 and the fourth light-emitting element ED4, driven together by the first pixel circuit SPC1 located in the optical border region OBA, can be light-emitting elements that emit light of the same color and are adjacent to each other in the row or column direction.

[0188] Reference Figure 6 The anode extension line AEL connects the first light-emitting element ED1 and the fourth light-emitting element ED4 disposed in the optical region OA to the first pixel circuit SPC1 disposed in the optical frame region OBA. Specifically, the anode extension line AEL extending from the first light-emitting element ED1 to the first pixel circuit SPC1 disposed in the optical frame region OBA can be referred to as the first anode extension line FAEL. A separate second anode extension line SAEL can extend from the first anode extension line FAEL to connect to the fourth light-emitting element ED4 disposed in the optical region OA. As shown in the figure, the second anode extension line SAEL is also electrically connected to the first pixel circuit SPC1.

[0189] In one embodiment, the second anode extension line SAEL completely overlaps with the optical region OA.

[0190] In one embodiment, the node intersecting the first anode extension line FAEL and the second anode extension line SAEL can be located in the optical region OA. However, embodiments of this disclosure are not limited to those described above. Figure 6 The embodiment shown. In another embodiment, the electrical connection between the first anode extension line FAEL and the second anode extension line SAEL can be made in the optical frame region OBA.

[0191] Figure 7 This is an example plan view of the normal area NA, the optical bezel area OBA, and the optical area OA in the display panel 110 according to various aspects of this disclosure.

[0192] Reference Figure 7 In one or more embodiments, in the display panel 110 according to various aspects of the present disclosure, a plurality of light-emitting regions EA disposed in each of the normal region NA, the optical bezel region OBA, and the optical region OA may include a red light-emitting region EA_R, a green light-emitting region EA_G, and a blue light-emitting region EA_B.

[0193] Reference Figure 7In one or more embodiments, in the display panel 110 according to various aspects of the present disclosure, the cathode electrode (e.g., Figure 3 The cathode electrode (CE) can be set together in the normal region NA, the optical frame region OBA, and the optical region OA.

[0194] The cathode electrode CE may include multiple cathode holes CH, and the multiple cathode holes CH of the cathode electrode CE may be disposed in the optical region OA.

[0195] The normal region NA and the optical frame region OBA can be regions through which light cannot pass, while the optical region OA can be regions through which light can pass. Therefore, the transmittance of the optical region OA can be higher than that of the optical frame region OBA and the normal region NA.

[0196] All optical regions OA can be regions through which light can be transmitted, and the multiple cathode holes CH of optical region OA can be transmission regions TA through which light can be transmitted more effectively. For example, the remaining region of optical region OA other than the multiple cathode holes CH can be regions through which light can be transmitted, and the transmittance of each of the multiple cathode holes CH in optical region OA can be higher than the transmittance of the remaining region of optical region OA other than the multiple cathode holes (CH).

[0197] In another example, the multiple cathode holes CH in the optical region OA can be a transmission region TA through which light can pass, and the remaining region in the optical region OA other than the multiple cathode holes CH can be a region through which light cannot pass.

[0198] Reference Figure 7 The arrangement of the light-emitting region EA in the optical region OA, the arrangement of the light-emitting region EA in the optical frame region OBA, and the arrangement of the light-emitting region EA in the normal region NA can be the same as each other.

[0199] Reference Figure 7 Multiple light-emitting regions EA may include a first light-emitting region EA1 contained in an optical region OA, a second light-emitting region EA2 contained in an optical border region OBA and emitting light of the same color as the first light-emitting region EA1, and a third light-emitting region EA3 contained in a normal region NA and emitting light of the same color as the first light-emitting region EA1.

[0200] Reference Figure 7 The multiple light-emitting regions EA may also include a fourth light-emitting region EA4, which is contained in the optical region OA and emits light of the same color as the first light-emitting region EA1.

[0201] Reference Figure 7In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may include a first anode electrode AE1 disposed in the optical region OA, a second anode electrode AE2 disposed in the optical bezel region OBA, a third anode electrode AE3 disposed in the normal region NA, and a fourth anode electrode AE4 disposed in the optical region OA.

[0202] In one or more embodiments, the display panel 110 according to various aspects of this disclosure may further include a cathode electrode (e.g., commonly disposed in the normal region NA, the optical bezel region OBA, and the optical region OA) Figure 3 The cathode electrode CE in the middle.

[0203] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may include a first light-emitting layer EL1 disposed in an optical region OA, a second light-emitting layer EL2 disposed in an optical border region OBA, a third light-emitting layer EL3 disposed in a normal region NA, and a fourth light-emitting layer EL4 disposed in the optical region OA.

[0204] The first light-emitting layers EL1 to the fourth light-emitting layers EL4 can be light-emitting layers that emit light of the same color. In these embodiments, the first light-emitting layers EL1 to the fourth light-emitting layers EL4 can be set as separate light-emitting layers or integrated into a single light-emitting layer.

[0205] Reference Figure 7 According to various aspects of this disclosure, the light-emitting elements of the display panel 110 can be configured such that: a first light-emitting element ED1 is provided with a first anode electrode AE1, a first light-emitting layer EL1 and a cathode electrode CE; a second light-emitting element ED2 is provided with a second anode electrode AE2, a second light-emitting layer EL2 and a cathode electrode CE; a third light-emitting element ED3 is provided with a third anode electrode AE3, a third light-emitting layer EL3 and a cathode electrode CE; and a fourth light-emitting element ED4 is provided with a fourth anode electrode AE4, a fourth light-emitting layer EL4 and a cathode electrode CE.

[0206] In the following text, reference will be made to Figure 8 and Figure 9 A more detailed discussion along Figure 7 The cross-sectional structure of the line XY.

[0207] Depend on Figure 7 The XY line in the diagram indicates the portion of the optical frame region OBA1 and the portion of the optical region OA1 relative to the boundary between the optical frame region OBA1 and the optical region OA1.

[0208] Depend on Figure 7The portion indicated by the XY line may include a first emitting region EA1 and a fourth emitting region EA4 contained in the optical region OA, and a second emitting region EA2 contained in the optical frame region OBA. The first emitting region EA1, the fourth emitting region EA4, and the second emitting region EA2 may represent emitting regions EA that emit light of the same color.

[0209] Figure 8 An example cross-sectional view of a display panel 110 according to various aspects of this disclosure is shown, and more specifically, example cross-sectional views of the optical bezel region OBA and optical region OA of the display panel 110 are shown. It should be noted here that... Figure 8 It shows an application-based approach, such as Figure 5 The cross-sectional view of the 1:1 circuit connection scheme shown.

[0210] Reference Figure 8 In terms of stacked configuration, the display panel 110 may include a transistor forming section, a light-emitting element forming section, and a packaging section.

[0211] The transistor forming section may include a substrate SUB, a first buffer layer BUF1 on the substrate SUB, various types of transistors DT1 and DT2 formed on the first buffer layer BUF1, a storage capacitor Cst, and various electrodes and signal lines.

[0212] The substrate SUB may include, for example, a first substrate SUB1 and a second substrate SUB2, and may include an intermediate layer INTL interposed between the first substrate SUB1 and the second substrate SUB2. In this example, the intermediate layer INTL may be an inorganic layer and may be used to prevent moisture penetration.

[0213] The lower shielding metal BSM can be disposed on the substrate SUB. The lower shielding metal BSM can be located below the first active layer ACT1 of the first driving transistor DT1.

[0214] The first buffer layer BUF1 may include a single-layer stack or a multi-layer stack. In an example where the first buffer layer BUF1 includes a multi-layer stack, the first buffer layer BUF1 may include a multi-buffer layer MBUF and an active buffer layer ABUF.

[0215] Various types of transistors (DT1, DT2, etc.), at least one storage capacitor Cst, and various electrodes or signal lines can be disposed on the first buffer layer BUF1.

[0216] For example, transistors DT1 and DT2 formed on the first buffer layer BUF1 may comprise the same material and may reside in one or more identical layers. In another example, such as Figure 8As shown, the first driving transistor DT1 and the second driving transistor DT2 in the transistors (DT1, DT2, etc.) may include different materials and be located in different layers.

[0217] Reference Figure 8 The first driving transistor DT1 can represent the driving transistor DT used to drive the first light-emitting element ED1 included in the optical region OA, and the second driving transistor DT2 can represent the driving transistor DT used to drive the second light-emitting element ED2 included in the optical frame region OBA.

[0218] For example, the first driving transistor DT1 may represent a driving transistor included in the first pixel circuit SPC1 for driving the first light-emitting element ED1 included in the optical region OA, and the second driving transistor DT2 may represent a driving transistor included in the second pixel circuit SPC2 for driving the second light-emitting element ED2 included in the optical frame region OBA.

[0219] The stacked configuration of the first driving transistor DT1 and the second driving transistor DT2 will be described below.

[0220] The first driving transistor DT1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0221] The second driving transistor DT2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0222] The second active layer ACT2 of the second driving transistor DT2 can be located higher in the stack configuration than the first active layer ACT1 of the first driving transistor DT1.

[0223] The first buffer layer BUF1 can be located below the first active layer ACT1 of the first driving transistor DT1, and the second buffer layer BUF2 can be located below the second active layer ACT2 of the second driving transistor DT2.

[0224] For example, the first active layer ACT1 of the first driving transistor DT1 can be located on the first buffer layer BUF1, and the second active layer ACT2 of the second driving transistor DT2 can be located on the second buffer layer BUF2. In this case, the second buffer layer BUF2 can be placed at a higher position than the first buffer layer BUF1.

[0225] The first active layer ACT1 of the first driving transistor DT1 can be disposed on the first buffer layer BUF1, and the first gate insulating layer GI1 can be disposed on the first active layer ACT1 of the first driving transistor DT1. The first gate electrode G1 of the first driving transistor DT1 can be disposed on the first gate insulating layer GI1, and the first interlayer insulating layer ILD1 can be disposed on the first gate electrode G1 of the first driving transistor DT1.

[0226] In this embodiment, the first active layer ACT1 of the first driving transistor DT1 may include a first channel region overlapping with the first gate electrode G1, a first source connection region on one side of the first channel region, and a first drain connection region on the other side of the first channel region.

[0227] The second buffer layer BUF2 can be placed on the first interlayer insulation layer ILD1.

[0228] The second active layer ACT2 of the second driving transistor DT2 can be disposed on the second buffer layer BUF2, and the second gate insulating layer GI2 can be disposed on the second active layer ACT2. The second gate electrode G2 of the second driving transistor DT2 can be disposed on the second gate insulating layer GI2, and the second interlayer insulating layer ILD2 can be disposed on the second gate electrode G2.

[0229] In this embodiment, the second active layer ACT2 of the second driving transistor DT2 may include a second channel region overlapping with the second gate electrode G2, a second source connection region on one side of the second channel region, and a second drain connection region on the other side of the second channel region.

[0230] The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 can be disposed on the second interlayer insulating layer ILD2. The second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2 can also be disposed on the second interlayer insulating layer ILD2.

[0231] The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 can be connected to the first source connection region and the first drain connection region of the first active layer ACT1, respectively, through vias formed in the second interlayer insulating layer ILD2, the second gate insulating layer GI2, the second buffer layer BUF2, the first interlayer insulating layer ILD1 and the first gate insulating layer GI1.

[0232] The second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2 can be connected to the second source connection region and the second drain connection region of the second active layer ACT2, respectively, through vias formed in the second interlayer insulating layer ILD2 and the second gate insulating layer GI2.

[0233] It should be understood that, Figure 8 Only the second driving transistor DT2 and the storage capacitor Cst, which are included in the circuit components of the second pixel circuit SPC2, are shown, and other components such as one or more transistors are omitted. It should also be understood that... Figure 8 Only the first driving transistor DT1 among the circuit components included in the first pixel circuit SPC1 is shown, and other components such as one or more transistors, storage capacitors, etc. are omitted.

[0234] Reference Figure 8 The storage capacitor Cst included in the second pixel circuit SPC2 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0235] The first capacitor electrode PLT1 can be electrically connected to the second gate electrode G2 of the second driving transistor DT2, and the second capacitor electrode PLT2 can be electrically connected to the second source electrode S2 of the second driving transistor DT2.

[0236] In one or more embodiments, reference is made to Figure 8 The lower metal layer BML can be disposed below the second active layer ACT2 of the second driving transistor DT2. The lower metal layer BML can overlap with all or at least a portion of the second active layer ACT2.

[0237] The lower metal BML can be electrically connected to, for example, the second gate electrode G2. In another example, the lower metal BML can be used as a light shield to block light propagating from a position lower than the lower metal BML. In this embodiment, the lower metal BML can be electrically connected to the second source electrode S2.

[0238] Even if the first driving transistor DT1 is a transistor used to drive the first light-emitting element ED1 located in the optical region OA, the first driving transistor DT1 can also be located in the optical frame region OBA instead of in the optical region OA.

[0239] The second driving transistor DT2 is a transistor used to drive the second light-emitting element ED2 disposed in the optical frame region OBA, and can be disposed in the optical frame region OBA.

[0240] Reference Figure 8 The display panel 110 may include at least one planarization layer PLN disposed on the first driving transistor DT1 and the second driving transistor DT2.

[0241] Reference Figure 8For example, at least one planarization layer PLN may include a first planarization layer PLN1. For example, the first planarization layer PLN1 may be disposed on the first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 and the second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2.

[0242] Reference Figure 8 The first relay electrode RE1 and the second relay electrode RE2 can be disposed on the first planarization layer PLN1.

[0243] The first relay electrode RE1 can represent an electrode used to relay the electrical interconnection between the first source electrode S1 of the first driving transistor DT1 and the first anode electrode AE1 of the first light-emitting element ED1. The second relay electrode RE2 can represent an electrode used to relay the electrical interconnection between the second source electrode S2 of the second driving transistor DT2 and the second anode electrode AE2 of the second light-emitting element ED2.

[0244] The first relay electrode RE1 can be electrically connected to the first source electrode S1 of the first driving transistor DT1 through a hole formed in the first planarization layer PLN1. The second relay electrode RE2 can be electrically connected to the second source electrode S2 of the second driving transistor DT2 through another hole formed in the first planarization layer PLN1.

[0245] Reference Figure 8 The first relay electrode RE1 and the second relay electrode RE2 can be set in the optical frame area OBA.

[0246] Reference Figure 8 The anode extension line AEL can be connected to the first relay electrode RE1 and extends from the optical frame region OBA to the optical region OA.

[0247] In one or more embodiments, reference is made to Figure 8 The anode extension line AEL can be a metal layer disposed on the first relay electrode RE1 and includes a transparent material.

[0248] Reference Figure 8 At least one planarization layer PLN disposed on the display panel 110 may also include a second planarization layer PLN2 on the first planarization layer PLN1.

[0249] For example, the second planarization layer PLN2 can be configured such that the second planarization layer PLN2 covers the first relay electrode RE1, the second relay electrode RE2 and the anode extension line AEL located on the first planarization layer PLN1.

[0250] although Figure 8An example is shown where at least one planarization layer PLN includes a first planarization layer PLN1 and a second planarization layer PLN2, but embodiments of this disclosure are not limited thereto. For example, the planarization layer PLN may also include at least one planarization layer PLN.

[0251] Reference Figure 8 The light-emitting element forming portion can be located on the second planarization layer PLN2.

[0252] Reference Figure 8 The light-emitting element forming section may include a first light-emitting element ED1, a second light-emitting element ED2 and a fourth light-emitting element ED4 disposed on the second planarization layer PLN2.

[0253] Reference Figure 8 The first light-emitting element ED1 and the fourth light-emitting element ED4 can be set in the optical region OA, and the second light-emitting element ED2 can be set in the optical frame region OBA.

[0254] exist Figure 8 In the example, the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 can be light-emitting elements that emit light of the same color. The individual light-emitting layers EL of the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 can be formed independently of each other. However, for ease of explanation in the following discussion, it is assumed that the individual light-emitting layers EL of the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 collectively form a common light-emitting layer.

[0255] Reference Figure 8 The first light-emitting element ED1 may be configured (e.g., constructed) in the region where the first anode electrode AE1, the light-emitting layer EL, and the cathode electrode CE overlap. The second light-emitting element ED2 may be configured (e.g., constructed) in the region where the second anode electrode AE2, the light-emitting layer EL, and the cathode electrode CE overlap. The fourth light-emitting element ED4 may be configured (e.g., constructed) in the region where the fourth anode electrode AE4, the light-emitting layer EL, and the cathode electrode CE overlap.

[0256] Reference Figure 8 The first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 can be disposed on the second planarization layer PLN2.

[0257] The second anode electrode AE2 can be connected to the second relay electrode RE2 through a hole formed in the second planarization layer PLN2.

[0258] The first anode electrode AE1 can be connected to the anode extension line AEL, which extends from the optical frame region OBA to the optical region OA, through another hole formed in the second planarization layer PLN2.

[0259] The fourth anode electrode AE4 can be connected to another anode extension line AEL extending from the optical frame region OBA to the optical region OA through another hole formed in the second planarization layer PLN2.

[0260] Reference Figure 8 The embankment BK can be set on the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4.

[0261] The dam section BK may include multiple dam section holes, and corresponding portions of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 may be exposed through the corresponding dam section holes. That is, the multiple dam section holes formed in the dam section BK may overlap with the corresponding portions of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4, respectively.

[0262] Reference Figure 8 The light-emitting layer EL can be disposed on the embankment BK. The light-emitting layer EL can contact the corresponding portions of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 through multiple embankment holes.

[0263] Reference Figure 8 At least one spacer SPCR may be present between the luminescent layer EL and the embankment BK.

[0264] Reference Figure 8 The cathode electrode CE can be disposed on the light-emitting layer EL. The cathode electrode CE may include multiple cathode holes CH. The multiple cathode holes CH formed in the cathode electrode CE can be disposed in the optical region OA.

[0265] Figure 8 The cathode hole CH shown can represent a cathode hole located between the first light-emitting region EA1 and the fourth light-emitting region EA4.

[0266] Reference Figure 8 The encapsulation portion may be located on the cathode electrode CE. The encapsulation portion may include an encapsulation layer ENCAP disposed on the cathode electrode CE.

[0267] Reference Figure 8 The encapsulation layer ENCAP can be used to prevent moisture or oxygen from penetrating into the light-emitting elements (ED1, ED2, and ED4) disposed beneath the encapsulation layer ENCAP. Specifically, the encapsulation layer ENCAP may comprise an organic material or a film and can be used to prevent moisture or oxygen from penetrating into the light-emitting layer EL. In one or more embodiments, the encapsulation layer ENCAP may comprise a single-layer stack or a multi-layer stack.

[0268] Reference Figure 8The encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0269] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be inorganic material layers, and the second encapsulation layer PCL can be an organic material layer. Because the second encapsulation layer PCL is implemented using an organic material, it can be used as a planarization layer.

[0270] In one or more embodiments, according to aspects of the present disclosure, the touch sensor may be integrated into the display panel 110. In these embodiments, the display panel 110 according to aspects of the present disclosure may include a touch sensor layer TSL disposed on the encapsulation layer ENCAP.

[0271] Reference Figure 8 The touch sensor layer (TSL) may include a touch sensor metal (TSM) and a bridging metal (BRG), and may also include one or more insulating layers, such as a sensor buffer layer (S-BUF), an interlayer insulating layer (S-ILD), and a sensor protective layer (S-PAC). For example, the interlayer insulating layer (S-ILD) may include one or more insulating layers.

[0272] The sensor buffer layer S-BUF can be disposed on the encapsulation layer ENCAP. The bridging metal BRG can be disposed on the sensor buffer layer S-BUF, and the sensor interlayer insulating layer S-ILD can be disposed on the bridging metal BRG.

[0273] The touch sensor metal TSM can be disposed on the sensor interlayer insulating layer S-ILD. One or more touch sensor metal TSMs can be connected to one or more corresponding bridging metal BRGs through one or more corresponding holes formed in the sensor interlayer insulating layer S-ILD.

[0274] Reference Figure 8 The touch sensor metal TSM and bridging metal BRG can be set in the optical frame area OBA. The touch sensor metal TSM and bridging metal BRG can be set so as not to overlap with the second light-emitting area EA2 of the optical frame area OBA.

[0275] Multiple touch sensor metal TSMs can be configured as a single touch electrode (or a single touch electrode line). For example, multiple touch sensor metal TSMs can be arranged in a grid pattern and thus electrically connected to each other. One or more touch sensor metal TSMs and the remaining one or more touch sensor metal TSMs can be electrically connected through one or more corresponding bridging metal BRGs, thereby being configured as a single touch electrode (or a single touch electrode line).

[0276] The sensor protective layer S-PAC can be configured to cover the touch sensor metal TSM and the bridging metal BRG.

[0277] In an embodiment where the touch sensor is integrated into the display panel 110, at least one of the touch sensor metal TSMs located on the encapsulation layer ENCAP, or at least a portion of at least one of the touch sensor metal TSMs, may extend along an inclined surface formed in the edge of the encapsulation layer ENCAP and be electrically connected to a pad located in the edge of an inclined surface of the display panel 110 further away from the edge of the encapsulation layer ENCAP. The pad may be disposed in the non-display area NDA and may be a metal pattern electrically connected to the touch driving circuitry 260.

[0278] The display panel 110 according to various aspects of this disclosure may include a dam BK disposed on a first anode electrode AE1 and having a dam hole that exposes a portion of the first anode electrode AE1, and a light-emitting layer EL disposed on the dam BK and in contact with the portion of the first anode electrode AE1 exposed through the dam hole.

[0279] The dam holes formed in the dam section BK may not overlap with the multiple cathode holes CH. For example, where multiple cathode holes CH are present, the dam section BK may not be recessed or perforated (e.g., it may remain flat). Therefore, where multiple cathode holes CH are present, the second planarization layer PLN2 and the first planarization layer PLN1 located below the dam section BK may also not be recessed or perforated (e.g., they may remain flat).

[0280] The flatness of the corresponding portion of the upper surface of the embankment BK located below any one of the multiple cathode holes CH may mean one or more insulating layers or one or more metal patterns (e.g., one or more electrodes, one or more lines, etc.), or that the light-emitting layer EL located below any one of the multiple cathode holes CH has not been damaged by the process of forming the multiple cathode holes CH in the cathode electrode CE.

[0281] The process for forming cathode holes CH in a cathode electrode CE is briefly described below. Specific mask patterns can be deposited at various locations where cathode holes CH are to be formed, and then cathode electrode material can be deposited on these mask patterns. Therefore, cathode electrode material can be deposited only in areas where a specific mask pattern is not present, thereby forming a cathode electrode CE including cathode holes CH. The specific mask pattern can include, for example, organic materials. The cathode electrode material can include a magnesium-silver (Mg-Ag) alloy.

[0282] In one or more embodiments, after forming a cathode electrode CE with a cathode hole CH, the display panel 110 may be in a state where a particular mask pattern is completely removed, partially removed (where a portion of the particular mask pattern is retained), or not removed (where all the particular mask patterns are retained and not removed).

[0283] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may include a first driving transistor DT1 and a second driving transistor DT2, wherein the first driving transistor DT1 is disposed in an optical bezel region OBA to drive a first light-emitting element ED1 disposed in an optical region OBA, and the second driving transistor DT2 is disposed in the optical bezel region OBA to drive a second light-emitting element ED2 disposed in the optical bezel region OBA.

[0284] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include a first planarization layer PLN1 disposed on the first driving transistor DT1 and the second driving transistor DT2, a first relay electrode RE1 disposed on the first planarization layer PLN1 and electrically connected to the first source electrode S1 of the first driving transistor DT1 through a hole formed in the first planarization layer PLN1, a second relay electrode RE2 disposed on the first planarization layer PLN1 and electrically connected to the second source electrode S2 of the second driving transistor DT2 through another hole formed in the first planarization layer PLN1, and a second planarization layer PLN2 disposed on the first relay electrode RE1 and the second relay electrode RE2.

[0285] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include an anode extension line (e.g., an anode extension line AEL) that interconnects the first relay electrode RE1 and the first anode electrode AE1 and is located on the first planarization layer PLN1.

[0286] The second anode electrode AE2 can be electrically connected to the second relay electrode RE2 through a hole formed in the second planarization layer PLN2, and the first anode electrode AE1 can be electrically connected to the anode extension line AEL through another hole formed in the second planarization layer PLN2.

[0287] All or at least a portion of the anode extension line AEL can be disposed in the optical region OA, and the anode extension line AEL may include transparent material, or may be a transparent line, or may include a transparent line.

[0288] The first pixel circuit SPC1 may include a first driving transistor DT1 for driving the first light-emitting element ED1, and the second pixel circuit SPC2 may include a second driving transistor DT2 for driving the second light-emitting element ED2.

[0289] The first active layer ACT1 of the first driving transistor DT1 can be located in a different layer than the second active layer ACT2 of the second driving transistor DT2.

[0290] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include a substrate SUB, a first buffer layer BUF1 disposed between the substrate SUB and the first driving transistor DT1, and a second buffer layer BUF2 disposed between the first driving transistor DT1 and the second driving transistor DT2.

[0291] The first active layer ACT1 of the first driving transistor DT1 may include a different semiconductor material than the second active layer ACT2 of the second driving transistor DT2.

[0292] For example, the second active layer ACT2 of the second driving transistor DT2 may include an oxide semiconductor material. Such an oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), cadmium oxide (CdO), indium oxide (InO), zinc tin oxide (ZTO), zinc indium tin oxide (ZITO), etc.

[0293] For example, the first active layer ACT1 of the first driving transistor DT1 may include a different semiconductor material than the second active layer ACT2 of the second driving transistor DT2.

[0294] For example, the first active layer ACT1 of the first driving transistor DT1 may include a silicon-based semiconductor material. For example, the silicon-based semiconductor material may include low-temperature polycrystalline silicon (LTPS), etc.

[0295] In one or more embodiments, the display panel 110 according to various aspects of the present disclosure may further include an encapsulation layer ENCAP on the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3, and a touch sensor metal TSM on the encapsulation layer ENCAP.

[0296] The touch sensor metal TSM can be disposed in the normal region NA and the optical bezel region OBA. For example, the touch sensor metal TSM may not be disposed in the optical region OA. In another example, the touch sensor metal TSM can be disposed in the optical region OA, the normal region NA, and the optical bezel region OBA, such that the optical region OA has a lower touch sensor metal density than each of the normal region NA and the optical bezel region OBA.

[0297] Reference Figure 8The optical region OA may overlap with the optoelectronic device. The optical frame region OBA may not overlap with the optoelectronic device. In one or more embodiments, a portion of the optical frame region OBA may overlap with the optoelectronic device.

[0298] Optoelectronic devices overlapping with the optical region OA can be those discussed above. Figure 1A , Figure 1B and Figure 1C The first optical electronic device 11 and / or the second optical electronic device 12 are included. For example, the optical electronic device may include a camera, an infrared sensor, an ultraviolet sensor, etc. For example, the optical electronic device may be a device capable of receiving visible light and performing a selected operation, or a device capable of receiving light other than visible light (e.g., infrared light and / or ultraviolet light) and performing a selected operation.

[0299] Reference Figure 8 The cross-sectional structure of the normal region NA can be substantially the same as or nearly the same as the cross-sectional structure of the optical frame region OBA. It should be noted that the first pixel circuit SPC1, which is located in the optical frame region OBA to drive the first light-emitting element ED1 located in the optical region OA, may not be located in the normal region NA.

[0300] Figure 9 An example cross-sectional view of a display panel 110 according to various aspects of this disclosure is shown, and more specifically, example cross-sectional views of the optical bezel region OBA and optical region OA of the display panel 110 are shown. It should be noted here that... Figure 9 It shows an application-based approach, such as Figure 6 The example cross-sectional view of the 1:2 circuit connection scheme is shown.

[0301] Figure 9 cross-sectional view and Figure 8 The cross-sectional views are basically the same. It should be noted here that... Figure 8 and Figure 9 One difference between the cross-sectional views is that Figure 8 Adopting such Figure 5 The 1:1 circuit connection scheme shown is as follows: Figure 9 Adopting such Figure 6 The 1:2 circuit connection scheme is shown. Given their similarities, the following discussion will focus on... Figure 8 Different features of the cross-sectional structure to provide for Figure 9 Description of the cross-sectional structure.

[0302] Reference Figure 9The first light-emitting element ED1 and the fourth light-emitting element ED4, which are disposed in the optical region OA, can be driven together or substantially simultaneously by the first driving transistor DT1 disposed in the optical frame region OBA.

[0303] Therefore, as Figure 9 As shown, the anode extension line AEL (e.g., Figure 8 The anode extension line AEL can be further electrically connected to a fourth anode electrode AE4, which is different from the first anode electrode AE1, as well as the first anode electrode AE1. Therefore, the anode extension line AEL can be electrically connected to both the first anode electrode AE1 of the first light-emitting element ED1 and the fourth anode electrode AE4 of the fourth light-emitting element ED4.

[0304] Reference Figure 9 The anode extension line AEL can overlap with the cathode hole CH located between the first light-emitting element ED1 and the fourth light-emitting element ED4 among the multiple cathode holes CH.

[0305] Reference Figure 9 The first light-emitting region EA1 configured by the first light-emitting element ED1 and the fourth light-emitting region EA4 configured by the fourth light-emitting element ED4 can be light-emitting regions that emit light of the same color.

[0306] For example, in the optical region OA, the area other than the multiple cathode holes CH that serve as the transmission region TA can be a region through which light cannot be transmitted. In another example, in the optical region OA, the area other than the multiple cathode holes CH that serve as the transmission region TA can be a region through which light can be transmitted with low transmittance (or low transmittance).

[0307] Therefore, in the optical region OA, the transmittance (or transmittance) of the region other than the multiple cathode holes CH can be lower than the transmittance of the multiple cathode holes CH. In one or more embodiments, the transmittance (or transmittance) of the region OA other than the multiple cathode holes CH can be higher than the transmittance of the normal region NA.

[0308] Figure 10 An example second type optical region OA and an example normal region NA surrounding the second type optical region OA are schematically shown in a display panel 110 according to various aspects of this disclosure.

[0309] Reference Figure 10 The display area DA may include an optical area OA. The optical area OA may have a second type of structure. In an example of implementing the second type of optical area OA, the optical area OA may include multiple transmission areas TA and low transmission areas LTA. The second type may be referred to as an aperture type.

[0310] Reference Figure 10 In the optical region OA, the low-transmission region LTA, in addition to the multiple transmission regions TA, may include multiple light-emitting regions EA. In the optical region OA, multiple light-emitting elements ED for the multiple light-emitting regions EA can be disposed in the low-transmission region LTA, in addition to the multiple transmission regions TA.

[0311] Furthermore, multiple pixel circuits (SPCs) for driving multiple light-emitting elements (EDs) can be disposed in the low-transmission region (LTA). That is, multiple pixel circuits (SPCs) can be disposed in the optical region (OA). This differs from situations where multiple pixel circuits (SPCs) are not disposed in the optical region (OA). Figures 4 to 9 The optical region OA of the first type (e.g., the anode extension type) in the example is different.

[0312] In one embodiment, the low-transmission region LTA in the optical region OA can be a region through which light cannot be transmitted. In another embodiment, the low-transmission region LTA in the optical region OA can be a region through which light can be transmitted with low transmittance (or low transmittance).

[0313] In the optical region OA, the transmittance (or transmittance) of the low-transmission region LTA can be lower than that of the transmission region TA. In one or more embodiments, the transmittance (or transmittance) of the low-transmission region LTA in the optical region OA can be higher than that of the normal region NA.

[0314] Reference Figure 10 The arrangement of the light-emitting region EA in the optical region OA can be the same as the arrangement of the light-emitting region EA in the normal region NA.

[0315] In one or more embodiments, reference is made to Figure 10 The corresponding region of each of the multiple light-emitting regions EA included in the optical region OA may be the same as, substantially the same as or nearly the same as, or different within a predetermined range from the corresponding region of each of the multiple light-emitting regions EA included in the normal region NA.

[0316] Furthermore, the corresponding regions of each of the multiple light-emitting regions EA included in the optical region OA may be the same or different within a predetermined range.

[0317] Cathode electrode (e.g., Figure 3 The cathode electrode (CE) can be disposed together in the normal region NA and the optical region OA, and can include multiple cathode holes CH in the optical region OA. The multiple cathode holes CH of the cathode electrode CE can each correspond to the transmission region TA of the optical region OA.

[0318] Since the optical region OA includes multiple transmission regions TA, the optical region OA can have a higher transmittance than the normal region NA.

[0319] All or at least part of the optical region OA may overlap with the optoelectronic device.

[0320] Optoelectronic devices overlapping with the optical region OA can be those discussed above. Figure 1A , Figure 1B and Figure 1C The first optical electronic device 11 and / or the second optical electronic device 12 are included. For example, the optical electronic device may include a camera, an infrared sensor, an ultraviolet sensor, etc. For example, the optical electronic device may be a device capable of receiving visible light and performing a selected operation, or a device capable of receiving light other than visible light (e.g., infrared light and / or ultraviolet light) and performing a selected operation.

[0321] Figure 11 It is a second type of optical region OA in the display panel 110 according to various aspects of this disclosure (e.g., as Figure 10 Example floor plan (configuration).

[0322] Reference Figure 11 In an example where the optical region OA is implemented in the second type, the optical region OA may include one or more transmission regions TA and low transmission regions LTA in addition to one or more transmission regions.

[0323] The low-transmittance region (LTA) can include multiple luminescent regions (EA).

[0324] Each light-emitting element ED can be set in each of the multiple light-emitting areas EA.

[0325] Multiple pixel circuits (SPCs) used to drive multiple light-emitting elements (EDs) can be set in the low-transmission region (LTA).

[0326] In the second type of optical region OA, the light-emitting element ED and the pixel circuit SPC can partially overlap each other.

[0327] In the case of the second type of optical region OA, the data lines (DL1, DL2 and DL3) and the gate lines (GL1, GL2, GL3 and GL4) can extend across the optical region OA.

[0328] In the optical region OA, the data lines (DL1, DL2 and DL3) can be arranged along the row direction (or column direction) while avoiding one or more transmission regions TA corresponding to one or more corresponding cathode holes CH.

[0329] In the optical region OA, the gate lines (GL1, GL2, GL3 and GL4) can be arranged along the column direction (or row direction) while avoiding one or more transmission regions TA corresponding to one or more corresponding cathode holes CH.

[0330] Data lines (DL1, DL2 and DL3) and gate lines (GL1, GL2, GL3 and GL4) can be connected to pixel circuits (SPC1, SPC2 and SPC3) located in the optical area OA.

[0331] For example, four light-emitting elements (EDr, Edg1, Edg2, and Edb) can be disposed in the portion of the low-transmission region LTA located between four adjacent transmission regions TA. The four light-emitting elements (Edr, Edg1, Edg2, and Edb) may include one red light-emitting element Edr, two green light-emitting elements Edg1 and Edg2, and one blue light-emitting element Edb.

[0332] For example, pixel circuit SPC1, used to drive a red light-emitting element EDR, can be connected to the first data line DL1 and the first gating line GL1. Pixel circuit SPC2, used to drive two green light-emitting elements Edg1 and Edg2, can be connected to the second data line DL2, the second gating line GL2, and the third gating line GL3. Pixel circuit SPC3, used to drive a blue light-emitting element Edb, can be connected to the third data line DL3 and the fourth gating line GL4.

[0333] Figure 12 It is a second type of optical region OA in the display panel 110 according to various aspects of this disclosure (e.g., Figure 10 and Figure 11 Example cross-sectional view of the configuration.

[0334] Figure 12 The metal and insulating layers in the cross-sectional structure can be combined with Figure 8 and Figure 9 The metal and insulating layers in the cross-sectional structure are the same, substantially the same, or nearly the same. Considering their similarities, the focus will be on... Figure 8 and Figure 9 Different features of the cross-sectional structure to provide for Figure 12 Discussion of the cross-sectional structure.

[0335] Reference Figure 12 The optical electronic device can be configured such that it overlaps with all or at least a portion of the optical region OA. The optical electronic device can be as discussed above. Figure 1A , Figure 1B and Figure 1C The first optical electronic device 11 and / or the second optical electronic device 12 in the middle.

[0336] Reference Figure 12 The first light-emitting element ED1 and the second light-emitting element ED2 can be disposed in the optical region OA. The first light-emitting region EA1 configured by the first light-emitting element ED1 and the second light-emitting region EA2 configured by the second light-emitting element ED2 can be light-emitting regions that emit light of the same color.

[0337] Reference Figure 12 The area where the first light-emitting element ED1 and the second light-emitting element ED2 are disposed can be a low-transmission region LTA, and a transmission region TA can exist between the first light-emitting element ED1 and the second light-emitting element ED2. That is, the transmission region TA can exist between the first light-emitting region EA1 disposed by the first light-emitting element ED1 and the second light-emitting region EA2 disposed by the second light-emitting element ED2.

[0338] The pixel circuit SPC can be configured to drive the first light-emitting element ED1 and is set to overlap with all or at least a portion of the first light-emitting element ED1 in the optical region OA.

[0339] Reference Figure 12 The pixel circuit SPC used to drive the first light-emitting element ED1 may include a first driving transistor DT1, a first scanning transistor ST1, and a first storage capacitor Cst1.

[0340] The pixel circuit SPC can be configured to drive the second light-emitting element ED2 and is set to overlap with all or at least a portion of the second light-emitting element ED2 in the optical region OA.

[0341] Reference Figure 12 The pixel circuit SPC used to drive the second light-emitting element ED2 may include a second driving transistor DT2, a second scanning transistor ST2, and a second storage capacitor Cst2.

[0342] Reference Figure 12 The first driving transistor DT1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0343] The first light-emitting element ED1 can be configured (e.g., constructed) in the region where the first anode electrode AE1, the light-emitting layer (e.g., the light-emitting layer EL discussed above), and the cathode electrode (e.g., the cathode electrode CE discussed above) overlap with each other.

[0344] The first source electrode S1 of the first driving transistor DT1 can be connected to the first anode electrode AE1 via the first relay electrode RE1.

[0345] The first storage capacitor Cst1 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0346] The first source electrode S1 of the first driving transistor DT1 can be connected to the second capacitor electrode PLT2 of the first storage capacitor Cst1.

[0347] The first gate electrode G1 of the first driving transistor DT1 can be connected to the first capacitor electrode PLT1 of the first storage capacitor Cst1.

[0348] The active layer ACT1s of the first scanning transistor ST1 can be located on the first buffer layer BUF1 and at a position lower than the first active layer ACT1 of the first driving transistor DT1.

[0349] The semiconductor material included in the active layer ACT1s of the first scanning transistor ST1 may be different from the semiconductor material included in the first active layer ACT1 of the first driving transistor DT1. For example, the semiconductor material included in the first active layer ACT1 of the first driving transistor DT1 may be an oxide semiconductor material, while the semiconductor material included in the active layer ACT1s of the first scanning transistor ST1 may be a silicon-based semiconductor material (e.g., low-temperature polycrystalline silicon (LTPS)).

[0350] Reference Figure 12 The second driving transistor DT2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0351] The second light-emitting element ED2 can be configured (e.g., formed) in the region where the second anode electrode AE2, the light-emitting layer EL, and the cathode electrode CE overlap with each other.

[0352] The second source electrode S2 of the second driving transistor DT2 can be connected to the second anode electrode AE2 via the second relay electrode RE2.

[0353] The second storage capacitor Cst2 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0354] The second source electrode S2 of the second driving transistor DT2 can be connected to the second capacitor electrode PLT2 of the second storage capacitor Cst2.

[0355] The second gate electrode G2 of the second driving transistor DT2 can be connected to the first capacitor electrode PLT1 of the second storage capacitor Cst2.

[0356] The active layer ACT2s of the second scanning transistor ST2 can be located on the first buffer layer BUF1 and at a position lower than the second active layer ACT2 of the second driving transistor DT2.

[0357] The semiconductor material included in the active layer ACT2s of the second scanning transistor ST2 may be different from the semiconductor material included in the second active layer ACT2 of the second driving transistor DT2. For example, the semiconductor material included in the second active layer ACT2 of the second driving transistor DT2 may be an oxide semiconductor material, while the semiconductor material included in the active layer ACT2s of the second scanning transistor ST2 may be a silicon-based semiconductor material (e.g., low-temperature polycrystalline silicon (LTPS)).

[0358] The cathode electrode CE may not include a cathode hole CH, or may include multiple cathode holes CH.

[0359] In an example where the cathode electrode CE includes multiple cathode holes CH, the cathode holes CH formed in the cathode electrode CE can be positioned to correspond to the respective transmission regions TA of the optical region OA.

[0360] The dam hole formed in the dam BK may not overlap with any of the cathode holes CH.

[0361] The upper surface of the embankment BK, located below the cathode hole CH, can be flat without being recessed or etched. For example, where the cathode hole CH is present, the embankment BK may not be recessed or perforated (e.g., it remains flat). Therefore, where the cathode hole CH is present, the second planarization layer PLN2 and the first planarization layer PLN1, located below the embankment BK, may also not be recessed or perforated (e.g., they remain flat).

[0362] The flatness of the various portions of the upper surface of the embankment BK located below the cathode hole CH may mean one or more insulating layers or one or more metal patterns (e.g., one or more electrodes, one or more lines, etc.), or that the light-emitting layer EL located below the cathode electrode CE has not been damaged by the process of forming the cathode hole CH in the cathode electrode CE.

[0363] The process for forming cathode holes CH in a cathode electrode CE is briefly described below. Specific mask patterns can be deposited at various locations where cathode holes CH are to be formed, and then cathode electrode material can be deposited on these mask patterns. Therefore, cathode electrode material can be deposited only in areas where specific mask patterns are not present, thereby forming a cathode electrode CE including cathode holes CH.

[0364] Specific mask patterns may include, for example, organic materials. Cathode electrode materials may include magnesium-silver (Mg-Ag) alloys.

[0365] In one or more embodiments, after forming a cathode electrode CE with a cathode hole CH, the display panel 110 may be in a state where a particular mask pattern is completely removed, partially removed (where a portion of the particular mask pattern is retained), or not removed (where all the particular mask patterns are retained and not removed).

[0366] As discussed above, although transistors (e.g., DT and / or ST) and storage capacitors Cst can be unlike Figures 4 to 9 In the example, they are set in the optical region OA configured in the first type (e.g., anode extension type), but transistors (e.g., DT and / or ST) and one or more storage capacitors Cst can be set as shown. Figures 10 to 12 As in the example, it is set in the optical region OA configured with the second type (e.g., aperture type).

[0367] exist Figures 4 to 9 In the first type (e.g., the anode extension type), two or more light-emitting elements ED can be provided in the optical region OA, and two or more light-emitting elements ED can also be provided in the optical frame region OBA, which is located outside the optical region OA. Furthermore, in the first type (e.g., the anode extension type), transistors (e.g., DT and / or ST) and storage capacitors Cst may not be provided in the optical region OA, and transistors (e.g., DT and / or ST) and one or more storage capacitors Cst may be provided in the optical frame region OBA located outside the optical region OA.

[0368] Reference Figures 10 to 12 In the second type (e.g., aperture type), two or more light-emitting elements ED can be arranged in the optical region OA. That is, in the second type (e.g., aperture type) optical region OA, two or more light-emitting elements ED can be arranged in the low-transmission region LTA of the optical region OA. Furthermore, in the second type (e.g., aperture type), transistors (e.g., DT and / or ST) and one or more storage capacitors Cst can be arranged in the optical region OA. That is, in the second type (e.g., aperture type) optical region OA, transistors (e.g., DT and / or ST) and one or more storage capacitors Cst can be arranged in the low-transmission region LTA of the optical region OA.

[0369] Figure 13 An example structure of a display device 100 according to various aspects of this disclosure is shown.

[0370] Reference Figure 13In one or more embodiments, in the display device 100 according to various aspects of the present disclosure, one or more optoelectronic devices (11 and / or 12) that need to receive external light (e.g., visible light, infrared light, ultraviolet light, etc.) to perform predefined operations may be located below or in the lower part of the display panel 110 and may be positioned to overlap with the optical region OA, which is a portion of the display area DA of the display panel 110. In these embodiments, by receiving external light transmitted through the optical region OA, one or more optoelectronic devices (11 and / or 12) may perform predefined operations (e.g., camera operation, sensing operation, etc.) based on the received light (e.g., visible light, infrared light, ultraviolet light, etc.).

[0371] Reference Figure 13 Although one or more optoelectronic devices (11 and / or 12) are placed at specific locations on the display device 100, these devices need to receive external light normally through the display panel 110. Furthermore, even when one or more optoelectronic devices (11 and / or 12) are configured to overlap with an optical area OA, which is a portion of the display area DA of the display panel 110, the display panel 110 still needs to perform image display normally.

[0372] Therefore, the optical region OA in the display area DA of the display panel 110 needs to have light transmission and display structures. In one or more embodiments, the boundary region adjacent to the optical region OA in the normal area NA of the display area DA of the display panel 110 may have light transmission and display structures.

[0373] Reference Figure 13 Briefly describe the stacked configuration of the display panel 110. The display panel 110 may include a substrate SUB, a thin film transistor forming layer 1310, a light-emitting element forming layer 1320, an encapsulation layer ENCAP, etc.

[0374] The thin-film transistor forming layer 1310 may be located on the substrate SUB and may be a vertical region (e.g., a stack comprising one or more layers) in which a plurality of thin-film transistors (TFTs) and a plurality of capacitors are disposed. The plurality of thin-film transistors (TFTs) may include transistors (DT and ST) disposed in each sub-pixel SP. The plurality of capacitors may include a storage capacitor Cst disposed in each sub-pixel SP.

[0375] The thin-film transistor forming layer 1310 may include at least one metal layer, at least one semiconductor material layer (which may also be referred to as an active layer), and multiple insulating layers.

[0376] The light-emitting element forming layer 1320 may be located on the thin-film transistor forming layer 1310, and may be a vertical region therein in which multiple light-emitting elements ED are disposed (e.g., a stack of one or more layers).

[0377] The light-emitting element forming layer 1320 may include a plurality of anode electrodes AE, at least one light-emitting layer EL, and a cathode electrode CE. A light-emitting region EA may be formed in a region where the anode electrode AE ​​overlaps with the light-emitting layer EL and the cathode electrode CE.

[0378] Multiple light-emitting regions EA can be formed in the light-emitting element forming layer 1320. The multiple light-emitting regions EA may include one or more red light-emitting regions EA_R for emitting red light, one or more green light-emitting regions EA_G for emitting green light, and one or more blue light-emitting regions EA_B for emitting blue light.

[0379] Reference Figure 13 Multiple light-emitting regions EA can be densely arranged in the normal area NA of the display area DA. Conversely, multiple light-emitting regions EA can be arranged less densely in the optical area OA of the display area DA. Therefore, the number of pixels per unit area in the optical area OA can be less than the number of pixels per unit area in the normal area NA.

[0380] The reason why multiple light-emitting areas EA are not densely arranged in the optical area OA of the display area DA is to provide space for light to be transmitted effectively.

[0381] In the optical region OA of the display region DA, the space where the light-emitting region EA is not located can be used for light transmission. This space for light transmission can also be referred to as the transmission region TA. Metals that are not allowed to transmit light may not be located in the transmission region TA. In one or more embodiments, one or more insulating layers may be partially etched into the transmission region TA to increase light transmittance.

[0382] Reference Figure 13 In the optical region OA of the display area DA, pixels P can be spaced apart from each other, each pixel P includes sub-pixels grouped together from multiple sub-pixels SP, and the transmission region TA can be set between pixels P.

[0383] Multiple subpixels SP may include one or more red subpixels SP for emitting red light, one or more green subpixels SP for emitting green light, and one or more blue subpixels SP for emitting blue light.

[0384] For example, a pixel P may include a red subpixel SP, a green subpixel SP, and a blue subpixel SP.

[0385] For example, a pixel P can include a red subpixel SP, two green subpixels SP, and a blue subpixel SP.

[0386] In this paper, the luminous region EA can also be described as sub-pixel SP, and the red luminous region EA_R, the green luminous region EA_G, and the blue luminous region EA_B can be described as red sub-pixel SP, green sub-pixel SP, and blue sub-pixel, respectively. Furthermore, all luminous regions EA of sub-pixels SP included in pixel P can be collectively referred to as one pixel P.

[0387] In one or more embodiments, the display panel 110 according to various aspects of this disclosure may further include a color filter layer. The color filter layer may include color filters disposed on a plurality of light-emitting elements ED and a black matrix BM disposed between the color filters.

[0388] In the example where a color filter layer is added to the display panel 110, multiple light-emitting elements (EDs) can emit light of the same color. For example, when a color filter layer is added, multiple EDs can emit the same white light. In another example, multiple EDs can emit the same blue light.

[0389] For example, a color filter may include a red color filter, a green color filter, and a blue color filter. In another example, a color filter may include a red color filter and a green color filter, but may not include a blue color filter.

[0390] For example, the color filter layer can be placed on the encapsulation layer ENCAP.

[0391] For example, a color filter layer can be disposed on the touch sensor layer TSL located on the encapsulation layer ENCAP. In another example, the color filter and black matrix BM can be disposed between the encapsulation layer ENCAP and the touch sensor layer TSL.

[0392] In one or more embodiments, the display panel 110 according to various aspects of this disclosure may further include a color conversion layer. The color conversion layer may be disposed below or above the color filter layer. For example, the color conversion layer may include quantum dots.

[0393] As described above, since the display panel 110 of the display device 100 according to various aspects of the present disclosure has a light transmission and display structure in the optical region OA, even when one or more optical electronic devices (11 and / or 12) are located below the substrate SUB of the display panel 110 and overlap with the optical region OA, one or more optical electronic devices (11 and / or 12) can normally receive light transmitted through the optical region OA and perform normal operation based on the received light.

[0394] Reference Figure 13 In the display device 100 according to various aspects of this disclosure, the number of pixels per unit area in the optical region OA may be less than the number of pixels per unit area in the normal region NA, which may result in image differences between the normal region NA and the optical region OA. Specifically, such image differences can be significantly perceived in the boundary region between the normal region NA and the optical region OA.

[0395] Figure 14 An example corresponding pixel arrangement in each of the normal region NA and the optical region OA in a display device 100 according to various aspects of the present disclosure is shown.

[0396] Reference Figure 14 A pixel P can include a red sub-pixel SP_R, two green sub-pixels SP_G, and a blue sub-pixel SP_B.

[0397] Reference Figure 14 The luminous area of ​​a pixel P can include a red luminous area EA_R of a red sub-pixel SP_R, two green luminous areas EA_G of two green sub-pixels SP_G, and a blue luminous area EA_B of a blue sub-pixel SP_B.

[0398] according to Figure 14 For example, the number of pixels per unit area UA in the normal region NA can be four, and the number of pixels per unit area UA in the optical region OA can be one. That is, the ratio of the number of pixels per unit area UA in the normal region NA to the number of pixels per unit area UA in the optical region OA can be 4:1.

[0399] The luminous area ratio (m) between the normal region NA and the optical region OA can be obtained by dividing the number of pixels per unit area UA in the normal region NA by the number of pixels per unit area UA in the optical region OA. According to this definition, Figure 14 The luminous area ratio (m) in the example is 4.

[0400] Figure 15 An example irregular pixel arrangement at the boundary between the normal region NA and the optical region OA in a display device 100 according to various aspects of this disclosure is shown.

[0401] Reference Figure 15 Multiple pixels P are disposed in each of the normal area NA and the optical area OA included in the display area DA of the display panel 110. The number of pixels per unit area UA in the optical area OA may be less than the number of pixels per unit area UA in the normal area NA.

[0402] like Figure 15 As shown, depending on the shape of the optical region OA, the boundary line 1500 between the normal region NA and the optical region OA may include a horizontal portion, a vertical portion, an inclined portion, and / or a bent portion. In this implementation, pixels surrounding the boundary line 1500 between the normal region NA and the optical region OA can be arranged differently depending on their position along the boundary line.

[0403] Reference Figure 15 In the region 1510 adjacent to the first position in the boundary line 1500, the blank area without a pixel P can be relatively wide. As a result, the region 1510 adjacent to the first position in the boundary line 1500 can be a low-brightness region.

[0404] Reference Figure 15 In region 1520 adjacent to the second position in boundary line 1500, pixels P of normal region NA and pixels P of optical region OA can be arranged to contact each other, thereby the blank area where pixels P are absent can be relatively narrow. As a result, region 1520 adjacent to the second position in boundary line 1500 can be a high-brightness region.

[0405] As described above, the irregularity in the arrangement of individual pixels at the location of the boundary line 1500 between the normal region NA and the optical region OA can lead to brightness differences. As a result, dark or bright lines may appear, and color perception may vary depending on the pixel location due to color fringing.

[0406] In other words, because brightness is simply controlled for each line, the pixel layout (e.g., pixel arrangement) may differ at different locations (e.g., top, bottom, left, and / or right) along the boundary between the normal region NA and the optical region OA. Therefore, differences in color perception still occur at these boundary locations due to color fringing. This can cause corresponding areas to appear as dark and / or bright lines in monochrome driving.

[0407] The display characteristics of the boundary region (1500, 1510 and / or 1520) between the normal region NA and the optical region OA may differ from the display characteristics of the normal region NA and the optical region OA.

[0408] Because the gamma curve is an exponential function, it may be difficult to fit precisely to the desired gamma curve (e.g., the gamma curve in 2.2) even when a predefined gain is applied, and therefore differences between gray levels may occur.

[0409] Figure 16 An example of a triple gamma-based boundary awareness level reduction drive is shown in a display device 100 according to various aspects of this disclosure. Figure 17An example pixel arrangement in the normal region NA, optical region OA, and boundary drive region BA of a display device 100 according to various aspects of the present disclosure is shown. Figure 18 An example triple gamma curve for a triple gamma-based boundary awareness level reduction drive is shown in a display device 100 according to various aspects of this disclosure.

[0410] In one or more embodiments, the display device 100 according to various aspects of the present disclosure may include a substrate SUB, the substrate SUB including a display area DA for displaying an image and a plurality of pixels P arranged in the display area DA.

[0411] Reference Figure 16 and Figure 17 The display area DA may include a first driving area A1, a second driving area A2, and a boundary driving area BA between the first driving area A1 and the second driving area A2.

[0412] Reference Figure 16 and Figure 17 The second driving region A2 may be included within the optical region OA, which is configured to facilitate the transmission of light. Therefore, the second driving region A2 may include a transmission region that facilitates the transmission of light.

[0413] Reference Figure 16 and Figure 17 The first driving region A1 may be included in the normal region NA, which is different from the optical region OA.

[0414] Reference Figure 16 and Figure 17 The boundary driving region BA between the first driving region A1 and the second driving region A2 may be included in the normal region NA, or in the optical border region OBA between the normal region NA and the optical region OA.

[0415] In the optical region OA, it is configured as follows: Figure 4 In the example of the first type (e.g., anodized extension type) shown, the boundary-driven region BA can be included within the optical frame region OBA. In the optical region OA configured as follows... Figure 10 In the example of the second type (e.g., hole type) shown, the boundary-driven region BA can be included in the normal region NA.

[0416] Reference Figure 16 and Figure 17 The multiple pixels P may include multiple first pixels P1 set in the first driving region A1, multiple second pixels P2 set in the second driving region A2, and multiple third pixels P3 set in the boundary driving region BA.

[0417] Reference Figure 16and Figure 17 Multiple pixels P may also include multiple fourth pixels P4 set in the boundary driving region BA.

[0418] For example, such as Figure 17 As shown, each of the first to fourth pixels (P1, P2, P3, and P4) can include four sub-pixels SP. Figure 17 In this diagram, each of the multiple circles represents a subpixel SP. A pixel can be configured with four subpixels SP, and a unit area can be configured with four pixels.

[0419] Reference Figure 17 The number of pixels per unit area UA in the second driving region A2 can be less than the number of pixels per unit area UA in the first driving region A1. For example, as Figure 14 As shown, the ratio of the number of pixels per unit area UA in the first driving region A1 to the number of pixels per unit area UA in the second driving region A2 can be 4:1.

[0420] Reference Figure 16 The display device 100 according to various aspects of this disclosure can provide a drive for reducing the perception level of the boundary between the normal region NA and the optical region OA (hereinafter referred to as boundary perception level reduction drive).

[0421] In one or more embodiments, the display device 100 according to various aspects of this disclosure can use triple gamma for boundary awareness level reduction drive.

[0422] Reference Figure 16 and Figure 18 In one or more embodiments, the display device 100 according to various aspects of the present disclosure may use a first gamma (gamma 1) for a first driving region A1, a second gamma (gamma 2) for a second driving region A2, and a third gamma (gamma 3) for a boundary driving region BA.

[0423] Reference Figure 16 and Figure 18 The first gamma (Gamma 1), the second gamma (Gamma 2), and the third gamma (Gamma 3) can be different from each other.

[0424] Reference Figure 16 and Figure 18In the triple gamma-based boundary awareness reduction drive according to the embodiments of the present disclosure, each of the plurality of first pixels P1 disposed in the first driving region A1 can represent a first brightness L1 for a first gray level G1 according to a first gamma curve GC1, each of the plurality of second pixels P2 disposed in the second driving region A2 can represent a second brightness L2 for a first gray level G1 according to a second gamma curve GC2, and each of the plurality of third pixels P3 disposed in the boundary driving region BA can represent a third brightness L3 for a first gray level G1 according to a third gamma curve GC3.

[0425] Reference Figure 16 and Figure 18 The first gamma curve GC1, the second gamma curve GC2, and the third gamma curve GC3 can be different from each other, and the first brightness L1 of each first pixel P1 in the first driving region A1, the second brightness L2 of each second pixel P2 in the second driving region A2, and the third brightness L3 of each third pixel P3 in the boundary driving region BA can be different from each other.

[0426] Reference Figure 16 and Figure 18 Each of the plurality of fourth pixels P4 disposed in the boundary driving region BA can represent a fourth luminance for the first gray level G1 according to the third gamma curve GC3. For example, the fourth luminance of each fourth pixel P4 disposed in the boundary driving region BA can be different from the first luminance L1 of each first pixel P1 in the first driving region A1, the second luminance L2 of each second pixel P2 in the second driving region A2, and the third luminance L3 of each third pixel P3 in the boundary driving region BA.

[0427] Reference Figure 18 The first gamma curve GC1 can have a first slope at the first gray level G1, the second gamma curve GC2 can have a second slope at the first gray level G1, and the third gamma curve GC3 can have a third slope at the first gray level G1.

[0428] Reference Figure 18 The second slope can be greater than the first slope and the third slope, and the third slope can be greater than the first slope and less than the second slope.

[0429] As described above, the display area DA may include an optical area OA that facilitates light transmission and a normal area NA that is different from the optical area OA. A first driving area A1 may be included in the normal area NA, a second driving area A2 may be included in the optical area OA, and a boundary driving area BA may be included in the normal area NA or in an optical border area OBA between the normal area NA and the optical area OA.

[0430] The optical region OA may overlap with one or more optoelectronic devices (11 and / or 12) located below the substrate SUB.

[0431] One or more optoelectronic devices (11 and / or 12) can perform predefined operations by receiving light transmitted through the optical region OA.

[0432] One or more optoelectronic devices (11 and / or 12) may include a first optoelectronic device 11 (e.g., the one discussed above). Figure 1A , Figure 1B , Figure 1C and Figure 13 The first optical electronic device 11) and the second optical electronic device 12 (e.g., the one discussed above) Figure 1A , Figure 1B , Figure 1C and Figure 13 The first optical electronic device 11 is configured to perform a predefined operation by receiving light (e.g., visible light) having a first wavelength range (e.g., the wavelength of visible light) that is transmitted through the optical region OA, and the second optical electronic device 12 is configured to perform a predefined operation by receiving light (e.g., infrared light) having a second wavelength range (e.g., the wavelength of infrared light) that is transmitted through the optical region OA.

[0433] Reference Figure 17 Since the boundary driving region BA has the same rendering pixel structure as the first driving region A1, the same pixel layout can be achieved at each position in the boundary driving region BA.

[0434] Therefore, it is possible to prevent or reduce brightness differences caused by the irregular arrangement of individual pixels at the boundary between the normal region NA and the optical region OA, thereby preventing or reducing differences in color perception.

[0435] like Figure 17 As shown, for example, the number of pixels per unit area UA of the boundary driving region BA can be the same as the number of pixels per unit area UA of the first driving region A1.

[0436] In another example, the number of pixels per unit area UA of the boundary driving region BA can be greater than the number of pixels per unit area UA of the second driving region A2, and can be less than the number of pixels per unit area UA of the first driving region A1.

[0437] Figure 19 An example of a triple gamma-based boundary awareness level reduction drive is shown for each pixel in a display device 100 according to various aspects of this disclosure. Figure 20 and Figure 21 This illustrates the first driving region A1, the boundary driving region BA, and the second driving region A2 (see [reference]) when a triple gamma-based boundary perception level reduction drive is performed in the display device 100 according to various aspects of this disclosure. Figure 17 The example in each of the examples corresponds to the pixel brightness.

[0438] Reference Figure 19 , Figure 20 and Figure 21 The image data to be provided to each of the plurality of first pixels P1 disposed in the first driving region A1 may be image data obtained by correcting the first original image data according to the first gamma curve GC1 (e.g., by correcting using digital gamma correction), and the image data to be provided to each of the plurality of second pixels P2 disposed in the second driving region A2 may be image data obtained by correcting the second original image data according to the second gamma curve GC2 (e.g., by correcting using digital gamma correction).

[0439] In this paper, the term "gamma" can refer to an indicator representing the relationship between the gray levels of an input image and the brightness of an output image, and can be defined as a gamma curve. The term "gamma correction" can refer to the processing of changing the brightness of a corresponding gray level to a brightness according to the corresponding gamma, and can be achieved by processing the image data to correct (change) according to the gamma curve. In this paper, gamma correction can refer to digital gamma correction, which is implemented digitally.

[0440] Reference Figure 19 , Figure 20 and Figure 21 The image data to be provided to each of the plurality of fourth pixels P4 set in the boundary driving region BA can be image data that has been corrected according to the third gamma curve GC3 after multiplying the fourth original image data by a first gain (gain 1) (e.g., corrected using digital gamma correction).

[0441] Reference Figure 19 , Figure 20 and Figure 21 The image data to be provided to each of the plurality of third pixels P3 set in the boundary driving region BA can be image data that has been corrected according to the third gamma curve GC3 after multiplying the third original image data by a second gain (gain 2) different from the first gain (gain 1). (e.g., corrected using digital gamma correction).

[0442] Reference Figure 19 , Figure 20 and Figure 21In one or more embodiments, according to the triple gamma-based boundary awareness level reduction drive, among the corresponding first brightness of each first pixel P1 in the first driving region A1, the corresponding second brightness of each second pixel P2 in the second driving region A2, and the corresponding third brightness of each third pixel P3 in the boundary driving region BA, the second brightness can be the highest, and the third brightness can be higher than the first brightness and lower than the second brightness (e.g., second brightness > third brightness > first brightness).

[0443] Reference Figure 19 , Figure 20 and Figure 21 In one or more embodiments, according to the triple gamma-based boundary awareness level reduction drive, among the corresponding first brightness of each first pixel P1 in the first driving region A1, the corresponding second brightness of each second pixel P2 in the second driving region A2, the corresponding third brightness of each third pixel P3 in the boundary driving region BA, and the corresponding fourth brightness of each fourth pixel P4 in the boundary driving region BA, the second brightness can be the highest, the third brightness can be higher than the first brightness and lower than the second brightness, and the fourth brightness can be lower than the first brightness (e.g., second brightness > third brightness > first brightness > fourth brightness).

[0444] Reference Figure 19 , Figure 20 and Figure 21 Based on the triple gamma-based boundary awareness level reduction drive according to the embodiments of this disclosure, the first gain (gain 1) can be set to be less than the second gain (gain 2). Therefore, among the plurality of third pixels P3 and the plurality of fourth pixels P4 disposed in the boundary driving region BA, each of the plurality of fourth pixels P4 can emit a dimmer light than each of the plurality of third pixels P3.

[0445] Reference Figure 19 , Figure 20 and Figure 21 Each of the plurality of fourth pixels P4 can emit light dimmer than each of the plurality of first pixels P1 disposed in the first driving region A1. Each of the plurality of third pixels P3 can emit light dimmer than each of the plurality of second pixels P2 disposed in the second driving region A2.

[0446] Reference Figure 19 , Figure 20 and Figure 21 The first gain (gain 1) can be set such that each of the plurality of fourth pixels P4 can emit light dimmer than each of the plurality of third pixels P3, and also emit light dimmer than each of the plurality of first pixels P1 set in the first driving region A1.

[0447] Reference Figure 19 , Figure 20 and Figure 21 The second gain (gain 2) can be set such that each of the plurality of third pixels P3 can emit brighter light than each of the plurality of fourth pixels P4, and emit darker light than each of the plurality of second pixels P2 set in the second driving region A2.

[0448] Reference Figure 21 The driving of the pixels (P3 and P4) set in the boundary driving region BA can be generated by both a driving (A1') for enabling the emission of light that is dimmer than that of the first pixel P1 set in the first driving region A1 and an additional driving (A2') for enabling the emission of light that is dimmer than that of the second pixel P2 set in the second driving region A2.

[0449] Based on the above discussion, although there are brightness differences between the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4, the total brightness of the first driving region A1, the total brightness of the second driving region A2, and the total brightness of the boundary driving region BA can be the same. Therefore, based on the triple gamma-based boundary perception level reduction drive according to the embodiments of this disclosure, although there may be brightness differences between pixels, there may be no difference in brightness between regions. As a result, differences in color perception by the user can be eliminated or reduced. That is, during operation, the brightness of the first driving region A1, the brightness of the second driving region A2, and the brightness of the boundary driving region BA can be perceived by the user as being the same due to the gamma correction function (e.g., the triple gamma-based boundary perception level reduction drive).

[0450] Figure 22 Nine example types of pixel arrangement patterns (cases 1 to 9) of four pixels (e.g., a third pixel P3 and three fourth pixels P4) per unit area UA in the boundary driving region BA are shown when a triple gamma-based boundary awareness level reduction drive is performed in a display device 100 according to aspects of the present disclosure.

[0451] For example, a unit area UA can include four pixels P. The four pixels P can include a third pixel P3 and three fourth pixels P4. In a unit area UA, the four pixels P can be arranged in two rows and two columns.

[0452] For example, each of the four pixels P can include four subpixels SP. For example, the four subpixels SP can include one red subpixel, two green subpixels, and one blue subpixel.

[0453] When representing a unit area UA based on subpixels SP, the unit area UA can include 16 subpixels SP arranged in four rows and four columns.

[0454] According to the nine types of pixel arrangement patterns (cases 1 to 9), the third pixel P3, including the four sub-pixels SP arranged in two rows and two columns, can be located in the nine types of patterns.

[0455] The circuit elements used to perform the triple gamma-based boundary awareness level reduction drive according to embodiments of the present disclosure will now be briefly described.

[0456] Figure 23 This is an example block diagram of a triple gamma-based gamma correction circuit in a display device 100 according to various aspects of the present disclosure.

[0457] Reference Figure 23 In one or more embodiments, the display device 100 according to various aspects of the present disclosure may include a gamma correction circuit 2300, which is configured to perform digital gamma correction on the image data based on the gamma curve corresponding to the position where the image data is provided, among the first gamma curve GC1, the second gamma curve GC2, and the third gamma curve GC3, and output the corrected image data.

[0458] Reference Figure 23 In one or more embodiments, the triple gamma-based gamma correction circuit 2300 may include a region identification circuit 2310 (also referred to as “region identifier 2310”), a gamma curve selection circuit 2320 (also referred to as “gamma curve selector 2320”) and a gamma correction processor 2330.

[0459] The region recognizer 2310 can be configured to recognize a region in which sub-pixels to be provided with image data are set as one of a first driving region A1, a second driving region A2, and a boundary driving region BA between the first driving region A1 and the second driving region A2.

[0460] The gamma curve selector 2320 can be configured to select a gamma curve corresponding to the identified region from a first gamma curve GC1 for the first driving region A1, a second gamma curve GC2 for the second driving region A2, and a third gamma curve GC3 for the boundary driving region BA.

[0461] The gamma correction processor 2330 can perform digital gamma correction on image data based on a selected gamma curve and output corrected image data.

[0462] The first gamma curve GC1 can have a first slope at the first gray level, the second gamma curve GC2 can have a second slope at the first gray level, and the third gamma curve GC3 can have a third slope at the first gray level.

[0463] In one or more embodiments, the second slope may be greater than the first slope and the third slope, and the third slope may be greater than the first slope and less than the second slope.

[0464] In one or more embodiments, data on each of the first gamma curve GC1 for the first driving region A1, the second gamma curve GC2 for the second driving region A2, and the third gamma curve GC3 for the boundary driving region BA can be generated by an optical compensation process during the panel manufacturing process and stored in the memory of the display device 100.

[0465] The gamma correction circuit 2300 can identify the data on the first gamma curve to the third gamma curve (GC1, GC2 and GC3) by accessing a memory that stores data on the first gamma curve to the third gamma curve (GC1, GC2 and GC3).

[0466] When the sub-pixels to be provided with image data are included in a plurality of first pixels P1 set in the first driving region A1, the gamma correction processor 2330 can correct the image data according to the first gamma curve (e.g., perform digital gamma correction on the image data) and output the corrected image data.

[0467] When the sub-pixel to be provided with image data is included in a plurality of second pixels P2 set in the second driving region A2, the gamma correction processor 2330 can correct the image data according to the second gamma curve (e.g., perform digital gamma correction on the image data) and output the corrected image data.

[0468] When the subpixel to be provided with image data is included in a plurality of third pixels P3 set in the boundary driving region BA, the gamma correction processor 2330 can multiply the image data by a gain (e.g., a second gain), then correct the adjusted image data obtained by multiplication according to the third gamma curve (e.g., perform digital gamma correction on the adjusted image data), and output the corrected image data.

[0469] When the subpixel to be provided with image data is included in a plurality of fourth pixels P4 set in the boundary driving region BA, the gamma correction processor 2330 can multiply the image data by another gain (e.g., a first gain), then correct the adjusted image data obtained by multiplication according to a third gamma curve (e.g., perform digital gamma correction on the adjusted image data), and output the corrected image data.

[0470] In one or more embodiments, the triple gamma-based gamma correction circuit 2300 may be configured inside or outside the display controller 240.

[0471] In an example where the triple gamma-based gamma correction circuit 2300 is configured outside the display controller 240, the gamma correction circuit 2300 can be configured between the host system 250 and the display controller 240, or it can be configured between the display controller 240 and the data drive circuit 220.

[0472] The following describes an example of a triple gamma-based gamma correction circuit 2300 configured inside a display controller 240.

[0473] Figure 24 This is an example block diagram of the display controller 240 of the display device 100 according to various aspects of the present disclosure.

[0474] Reference Figure 24 In one or more embodiments, the display controller 240 of the display device 100 according to various aspects of the present disclosure may include a data input unit 2410, a gamma correction circuit 2300 (e.g., Figure 23 The gamma correction circuit 2300 and the data output unit 2420 are configured to receive image data, the data input unit 2410 is configured to perform digital gamma correction on the image data based on the gamma curve corresponding to the position where the image data is provided and provide the corrected image data, and the data output unit 2420 is configured to output the corrected image data obtained from the digital gamma correction.

[0475] In one or more embodiments, the display controller 240 may be a timing controller. That is, the gamma correction circuit 2300 may be included in the timing controller. However, as previously described, in other embodiments, the gamma correction circuit 2300 is operatively connected to the timing controller but located externally to the timing controller.

[0476] The data output unit 2420 can provide the corrected image data obtained from digital gamma correction to the data drive circuit 220.

[0477] The gamma curve corresponding to the location where image data is provided may include a first gamma curve GC1 for a first driving region A1, a second gamma curve GC2 for a second driving region A2 including one or more transmission regions, and a third gamma curve GC3 for the boundary driving region BA between the first driving region A1 and the second driving region A2.

[0478] like Figure 23As shown, the gamma correction circuit 2300 may include a region identifier 2310, a gamma curve selector 2320, and a gamma correction processor 2330.

[0479] The driving method of the triple gamma-based display device 100 according to the above embodiment will be briefly described below.

[0480] In one or more embodiments, a method for driving a display device 100 based on triple gamma may include: identifying a region in which sub-pixels to be provided with image data are disposed as one of a first driving region A1, a second driving region A2, and a boundary driving region BA between the first driving region A1 and the second driving region A2 (which may be referred to as a region identification step); and correcting the image data based on a gamma or a gamma curve that corresponds to the identified region among a first gamma (gamma 1) or a first gamma curve GC1 that defines the first gamma (gamma 1) for the first driving region A1, a second gamma (gamma 2) or a second gamma curve GC2 that defines the second gamma (gamma 2) for the second driving region A2, and a third gamma (gamma 3) or a third gamma curve GC3 that defines the third gamma (gamma 3) for the boundary driving region BA (e.g., performing digital gamma correction on the image data), and outputting the corrected image data (which may be referred to as a gamma correction processing step).

[0481] A first gamma curve GC1 may have a first slope at a first gray level G1, a second gamma curve GC2 may have a second slope at the first gray level G1, and a third gamma curve GC3 may have a third slope at the first gray level G1. In one or more embodiments, the second slope may be greater than the first slope and the third slope, and the third slope may be greater than the first slope and less than the second slope (e.g., second slope > third slope > first slope). The term "slope" may also include the meaning of a tangent or a simple tangent at the first gray level G1.

[0482] The first gamma curve GC1 defines the first brightness at the first gray level G1, the second gamma curve GC2 defines the second brightness at the first gray level G1, and the third gamma curve GC3 defines the third brightness at the first gray level G1. The second brightness can be the highest, and the third brightness can be higher than the first brightness but lower than the second brightness.

[0483] Among the first brightness at the first gray level G1 according to the first gamma (gamma 1), the second brightness at the first gray level G1 according to the second gamma (gamma 2), and the third brightness at the first gray level G1 according to the third gamma (gamma 3), the second brightness can be the highest, and the third brightness can be higher than the first brightness and lower than the second brightness.

[0484] The first driving region A1 and the second driving region A2 can have different numbers of pixels per unit area UA.

[0485] The first driving region A1 may be a region that does not include the transmission region TA, and the second driving region A2 may be a region that includes one or more transmission regions TA.

[0486] The first driving region A1 can be a region included in the normal region NA, and the second driving region A2 can be a region included in the optical region OA.

[0487] The first driving region A1 may be a region that does not overlap with one or more optical electronic devices (11 and / or 12), and the second driving region A2 may be a region that overlaps with one or more optical electronic devices (11 and / or 12).

[0488] For example, the number of pixels per unit area UA of the boundary driving region BA between the first driving region A1 and the second driving region A2 can be equal to or similar to the number of pixels per unit area UA of the first driving region A1.

[0489] In another example, the number of pixels per unit area UA of the boundary driving region BA between the first driving region A1 and the second driving region A2 can be greater than the number of pixels per unit area UA of the second driving region A2, and less than or equal to the number of pixels per unit area UA of the first driving region A1.

[0490] In an example where the optical region OA is configured in a second type (e.g., aperture type), the boundary driving region BA between the first driving region A1 and the second driving region A2 can be included in the normal region NA.

[0491] In an example where the optical region OA is configured in a first type (e.g., anodized extension type), the boundary driving region BA between the first driving region A1 and the second driving region A2 may be included in the optical border region OBA.

[0492] According to the embodiments described herein, a display device 100 may be provided, the display device 100 including a transmission and display structure in which one or more optical electronic devices required for receiving light are disposed below or at the lower part of a display panel, and the display area of ​​the display panel overlapping with one or more optical electronic devices is configured to serve as an image display and a light transmission path.

[0493] According to the embodiments described herein, a display device 100, a gamma correction circuit 2300, and a display driving method can be provided that can reduce the level of user perception of the boundary between the normal area and the optical area by applying different gammas to the boundary between the normal area and the optical area.

[0494] According to the embodiments described herein, a display device 100, a gamma correction circuit 2300, and a display driving method can be provided that can reduce the color difference between a user-perceived normal area and an optical area by using a separate gamma for each area. In other words, by reducing the color difference between the normal area and the optical area in which optoelectronic devices are disposed, the user may be unable to perceive the boundary between the normal area and the optical area.

[0495] According to the embodiments described herein, a display device 100, a gamma correction circuit 2300, and a display driving method can be provided that are able to prevent display artifacts such as brightness differences at the boundary between the normal and optical regions by designing pixels to be arranged in the same layout for each location at the boundary between the normal and optical regions.

[0496] According to the embodiments described herein, a display device 100, a gamma correction circuit 2300, and a display driving method can be provided that can reduce power consumption, perform efficient driving, and achieve low-power design by using a gamma suitable for each region.

[0497] The above description is provided to enable any person skilled in the art to make, use, and practice the technical features of this disclosure, and is given as an example in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and accompanying drawings provide examples of the technical features of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of this disclosure.

[0498] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in and / or listed in the application data sheets are incorporated herein by reference in their entirety. If necessary, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide further embodiments.

[0499] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents conferred by those claims. Therefore, the claims are not limited to this disclosure.

[0500] Cross-references to related applications

[0501] This application claims priority to Korean Patent Application No. 10-2023-0011943, filed with the Korean Intellectual Property Office on January 30, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A display device, the display device comprising: A substrate having a display area for displaying an image, the display area including: a normal area, an optical area, and an optical border area between the normal area and the optical area, wherein the optical area is configured to overlap with an optoelectronic device; and A first light-emitting element disposed in the optical region, a second light-emitting element disposed in the optical frame region, and a third light-emitting element disposed in the normal region; A first pixel circuit electrically connected to the first light-emitting element, a second pixel circuit electrically connected to the second light-emitting element, and a third pixel circuit electrically connected to the third light-emitting element; and A first anode extension line extends from the first pixel circuit located in the optical frame region to be electrically connected to the first light-emitting element located in the optical region.

2. The display device according to claim 1, wherein the display device comprises: A fourth light-emitting element is disposed in the optical region; as well as The second anode extension line extends from the fourth light-emitting element and is electrically connected to the first anode extension line. Wherein, the second anode extension line overlaps with the optical region, and The second pixel circuit is located in the optical frame region, and the third pixel circuit is located in the normal region.

3. The display device according to claim 1, wherein the display device comprises: A fourth light-emitting element is disposed in the optical region; as well as The second anode extension line extends from the fourth light-emitting element and is electrically connected to the fourth pixel circuit. Wherein, the second anode extension line overlaps with the optical region, and The fourth pixel circuit is located in the optical frame area.

4. The display device according to claim 1, wherein The first anode extension line is any one of transparent material, transparent line, or line including a transparent portion.

5. The display device according to claim 1, wherein the display device comprises: At least one planarization layer, the at least one planarization layer being located between the first pixel circuit and the first light-emitting element, wherein the at least one planarization layer comprises: A first planarization layer, wherein a relay electrode electrically connected to the first pixel circuit and the first anode extension line is disposed on the first planarization layer; and A second planarization layer is located between the first planarization layer and the first light-emitting element. The first anode extension line is electrically connected to the relay electrode in the optical frame region, extends into the optical region, and is electrically connected to the first light-emitting element in the optical region.

6. The display device of claim 5, wherein, The relay electrode is electrically connected to the first pixel circuit in the optical frame region through the contact hole of the first planarization layer, and the first anode extension line is electrically connected to the first light-emitting element in the optical region through the contact hole of the second planarization layer.

7. The display device according to claim 1, wherein Each of the first light-emitting element, the second light-emitting element, and the third light-emitting element includes: Cathode electrode; Anode electrode; and A light-emitting layer is provided between the cathode electrode and the anode electrode. The cathode electrode includes multiple cathode holes only in the optical region and not in the normal region or the optical frame region.

8. The display device according to claim 1, wherein A first pixel disposed in the normal region has a first brightness for a first gray level according to a first gamma curve, a second pixel disposed in the optical region has a second brightness for the first gray level according to a second gamma curve, and a third pixel disposed in the optical border region has a third brightness for the first gray level according to a third gamma curve. Among them, all curves in the first gamma curve, the second gamma curve, and the third gamma curve are different from each other, and all brightness levels in the first brightness, the second brightness, and the third brightness are different from each other.

9. The display device of claim 8, wherein, Among the first brightness, the second brightness, and the third brightness, the second brightness is the highest, and the third brightness is higher than the first brightness but lower than the second brightness.

10. The display device of claim 8, wherein, The first gamma curve has a first slope at the first gray level, the second gamma curve has a second slope at the first gray level, and the third gamma curve has a third slope at the first gray level. Among the first slope, the second slope, and the third slope, the second slope is the largest, and the third slope is greater than the first slope and less than the second slope.

11. The display device of claim 8, wherein, A fourth pixel is disposed in the optical border region, and the fourth pixel has a fourth brightness for the first gray level according to the third gamma curve. The fourth brightness is different from all the brightnesses in the first brightness, the second brightness, and the third brightness.

12. The display device of claim 11, wherein, Among the first brightness, the second brightness, the third brightness, and the fourth brightness, the second brightness is the highest, the third brightness is higher than the first brightness but lower than the second brightness, and the fourth brightness is lower than the first brightness. Among the third and fourth pixels disposed in the optical frame area, the fourth pixel emits a darker light than the third pixel.

13. The display device of claim 11, wherein, The image data to be provided to the first pixel located in the normal area is image data obtained by correcting the first original image data according to the first gamma curve; The image data to be provided to the second pixel located in the optical region is image data obtained by correcting the second original image data according to the second gamma curve; The image data to be provided to the fourth pixel located in the optical frame region is image data corrected according to the third gamma curve after multiplying the fourth original image data by a first gain; and The image data to be provided to the third pixel located in the optical frame region is image data corrected according to the third gamma curve after multiplying the third original image data by a second gain different from the first gain.

14. The display device according to claim 8, wherein the display device comprises: A gamma correction circuit is configured to perform digital gamma correction on the image data based on a first gamma curve, a second gamma curve, and a third gamma curve corresponding to the position where the image data is provided, and to output corrected image data based on the digital gamma correction. The number of pixels per unit area in the optical region is less than the number of pixels per unit area in the normal region. The gamma correction circuit reduces the color difference between the normal area and the optical area by using a separate gamma for each area, making it impossible for the user to identify the boundary between the normal area and the optical area.

15. The display device of claim 14, wherein, The gamma correction circuit includes: A region recognition circuit, configured to identify a region in which pixels to be provided with image data are disposed as one of the normal region, the optical region, and the optical border region; A gamma curve selection circuit configured to select, from a first gamma curve, a second gamma curve, and a third gamma curve, a gamma curve corresponding to the identified region; and A gamma correction processor is used to correct the image data based on a selected gamma curve and output the corrected image data.

Images