Integrated circuit device and method of diagnosing a fault in an integrated circuit device

Abstract

An integrated circuit device includes a scan chain and a device circuit. The scan chain includes a plurality of sequential elements and a diagnostic hardware circuit. The sequential elements are connected in series and grouped into a plurality of sections. The diagnostic hardware circuit includes a plurality of circuit components, each connected to one sequential element of a respective section. The diagnostic hardware circuit identifies a defective section of the scan chain during a diagnostic mode. During the diagnostic mode, test pattern data is serially shifted through the scan chain to isolate a faulty sequential element in the defective section. The device circuit is connected to the scan chain, performs one or more circuit functions during a functional mode, and generates functional data that is sequentially shifted through the scan chain. Embodiments of the present application also disclose methods for diagnosing faults in an integrated circuit device.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for diagnosing faults in integrated circuit devices. Background Technology

[0002] Integrated circuits (ICs) can employ scan chains to facilitate fault detection of their own flip-flops. For example, a scan chain may include multiple multiplexers, each connected to a corresponding flip-flop. The flip-flops and multiplexers constitute the scan chain, enabling the IC to operate in two distinct modes: a functional mode for normal circuit operation and a diagnostic mode that helps isolate one or more faulty flip-flops. In functional mode, the flip-flops sequentially shift functional data generated by the device circuitry, propagating through their data inputs in the scan chain. This functional data is then provided as an output for further processing. During diagnostic mode, a test sequence (a predefined data sequence) is transferred through the scan inputs of the flip-flops into the scan chain. The resulting responses are output and analyzed to determine whether each flip-flop is functioning correctly. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, an integrated circuit device is provided, configured to operate in a functional mode and a diagnostic mode. The integrated circuit device includes: an input terminal configured to receive test mode data provided by a diagnostic software tool; an output terminal configured to provide diagnostic output data; and a scan chain connected between the input terminal and the output terminal. The scan chain includes: a plurality of sequential elements connected in series and grouped into a plurality of segments; and diagnostic hardware circuitry including a plurality of circuit components, each circuit component connected to a sequential element of a corresponding segment, wherein: the diagnostic hardware circuitry is configured to identify defective segments of the scan chain during diagnostic mode; and during diagnostic mode, test mode data is serially shifted through the scan chain to isolate faulty sequential elements in the defective segments. The integrated circuit device also includes device circuitry connected to the scan chain and configured to perform one or more circuit functions during functional mode and generate functional data sequentially shifted through the scan chain.

[0004] According to another aspect of the embodiments of this application, an integrated circuit device is provided, configured to operate in a functional mode and a diagnostic mode. The integrated circuit device includes: an input terminal configured to receive test mode data; an output terminal configured to provide diagnostic output data; and a bidirectional scan chain connected between the input terminal and the output terminal. The bidirectional scan chain includes: a plurality of sequence elements connected in series and grouped into a plurality of segments, wherein the plurality of segments include a first segment and a second segment following the first segment; and diagnostic hardware circuitry, the diagnostic hardware circuitry including: a plurality of circuit components respectively connected to a sequence element of a corresponding segment; and a feedback loop connecting the output of the second segment to the input of the first segment, wherein the diagnostic hardware circuitry is configured to perform: forward shift diagnostics for transferring test mode data from the first sequence element to the last sequence element of the scan chain during diagnostic mode to identify defective segments of the scan chain; and reverse shift diagnostics for transferring test mode data from the last sequence element to the first sequence element during diagnostic mode to isolate faulty sequence elements in the defective segments. The integrated circuit device also includes device circuitry connected to the scan chain and configured to perform one or more circuit functions during a functional mode and generate functional data that is sequentially shifted through the scan chain.

[0005] According to another aspect of the embodiments of this application, a method for diagnosing faults in an integrated circuit device is provided. The method includes: performing coarse-grained diagnostics on a scan chain of the integrated circuit device to identify defective segments, wherein the scan chain includes: a plurality of sequence elements grouped into segments; and diagnostic hardware circuitry including a plurality of circuit components, each circuit component connected to a first sequence element in a corresponding segment. The method further includes: performing fine-grained diagnostics on the identified defective segments to indicate one or more faulty sequence elements in the defective segments by serially shifting through test mode data of the scan chain. Attached Figure Description

[0006] Various aspects of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings:

[0007] Figure 1 This is a schematic block diagram illustrating exemplary devices according to various embodiments of the present disclosure;

[0008] Figure 2 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0009] Figure 3 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0010] Figure 4 This is a schematic block diagram / circuit diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0011] Figure 5 This is a schematic block diagram / circuit diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0012] Figure 6 This is a schematic block diagram / circuit diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0013] Figure 7 This is a flowchart of an exemplary method for diagnosing fixed faults in a device according to various embodiments of the present disclosure;

[0014] Figure 8 This is a flowchart of an exemplary method for diagnosing switching delay faults in a device according to various embodiments of the present disclosure;

[0015] Figure 9 This is a schematic block diagram / circuit diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0016] Figure 10 This is a schematic block diagram / circuit diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0017] Figure 11 This is a schematic block diagram / circuit diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0018] Figure 12 This is a flowchart of an exemplary method for diagnosing fixed faults in a device according to various embodiments of the present disclosure;

[0019] Figure 13 This is a flowchart of an exemplary method for diagnosing switching delay faults according to various embodiments of the present disclosure;

[0020] Figure 14 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0021] Figure 15 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0022] Figure 16 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0023] Figure 17 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0024] Figure 18 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure; and

[0025] Figure 19 This is a flowchart illustrating exemplary methods for manufacturing a device according to various embodiments of the present disclosure. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Devices, such as integrated circuits (ICs), can employ hardware diagnostic solutions, which in some cases may be entirely or primarily hardware-based. In some examples, bidirectional scan chains include diagnostic hardware circuitry components (e.g., multiplexers), each connected to a corresponding flip-flop of the IC, resulting in an equal number of flip-flops and multiplexers. This approach can lead to a significant cell area overhead, e.g., from about 2% to about 3%, adversely affecting power, performance, and area (PPA). To address these issues, some systems and methods described herein implement a hybrid diagnostic approach that combines hardware and software solutions to reduce the number of multiplexers to fewer than the number of flip-flops. For example, the sequential elements of the scan chain (e.g., flip-flops) can be segmented or grouped into multiple sections, with diagnostic hardware circuitry components (e.g., multiplexers) connected to one (e.g., the first) flip-flop in each section. This approach can significantly reduce the area overhead to, for example, about 1%, minimizing the impact on PPA without compromising fault isolation accuracy.

[0028] Figure 1 This is a schematic block diagram illustrating an exemplary device 100 according to various embodiments of the present disclosure. Figure 1 In this example, device 100 includes an input terminal 110, one or more scan chains 120, device circuitry 130, and an output terminal 140. In some embodiments, device 100 is an integrated circuit (IC), such as a central processing unit (CPU), a memory device (e.g., random access memory or RAM), an analog IC (e.g., an operational amplifier, voltage regulator, analog-to-digital converter, etc.), a packaged IC (e.g., a system-on-a-chip or SoC, an application-specific IC or ASIC, any other suitable packaged IC, or a combination thereof).

[0029] Input and output terminals 110 and 140 are externally accessible to device 100, allowing device 100 to interact with external test devices or other devices. A scan chain 120 is connected between input terminals 110 and output terminals 140 and includes a plurality of sequence elements 150 and diagnostic hardware circuitry 160. The sequence elements 150 are connected serially and sequentially shift data to output terminals 140. Data can be received from input terminals 110 or device circuitry 130. In this exemplary embodiment, the sequence elements 150 are organized into multiple segments, each segment including a predetermined number of sequence elements. In some embodiments, the sequence elements 150 are in the form of storage elements, such as D-type flip-flops, JK-type flip-flops, SR-type flip-flops, or T-type flip-flops, latches, shift registers, RAM (random access memory) cells, or any other suitable storage element, or combinations thereof.

[0030] Diagnostic hardware circuitry 160 helps identify one or more faulty sequence elements in scan chain 120. Diagnostic hardware circuitry 160 includes multiple circuit components, each connected to a sequence element in a corresponding segment, such as the first sequence element. These circuit components manage the data flow through scan chain 120, ensuring correct operation in functional and diagnostic modes. In some embodiments, the circuit components include multiplexers. In other embodiments, different configurations of the circuit components are envisioned.

[0031] Device circuitry 130 is connected to scan chain 120 and performs one or more circuit functions during the normal (or functional) mode of device 100, generating functional data that is sequentially shifted through scan chain 120 as part of normal circuit operation. In some embodiments, device circuitry 130 includes various logic circuits that perform core operations of device 100, such as data processing, signal routing, or arithmetic calculations. These operations support the overall functionality and performance of device 100, while scan chain 120 provides test access to sequential elements during diagnostic mode.

[0032] As described above, since each circuit component (e.g., a multiplexer) is connected to a (e.g., the first) sequential element in the corresponding segment of scan chain 120, area overhead is significantly reduced. Software-based tools, such as Automated Test Pattern Generation (ATPG), further analyze scan chain patterns to improve diagnostic resolution. This hybrid approach minimizes the impact of PPAs while maintaining a high level of fault isolation accuracy, which will be further described below.

[0033] In at least one embodiment, device 100 may include more than one scan chain. For example, Figure 2 This is a schematic block diagram illustrating another exemplary device 200 according to various embodiments of the present disclosure. Figure 2 In this example, device 200 (e.g., device 100) includes an input terminal 210, multiple scan chains 220-260, and an output terminal 270. Each scan chain (e.g., scan chain 210) is connected between the input and output terminals (e.g., 210, 270) and includes multiple sequential elements (e.g., FF1-FF6) and diagnostic hardware circuitry (e.g., ...). Figure 1 The diagnostic hardware circuit 160. Sequence elements are connected serially, and data is sequentially shifted from one sequence element to the next within each clock cycle, thus propagating data from the first sequence element of the scan chain to the last. In this exemplary embodiment, the sequence elements of each scan chain 220-260 are divided (or grouped) into multiple segments (e.g., 280a, 280b), each segment including a predetermined number of sequence elements (e.g., three).

[0034] The diagnostic hardware circuit 160 helps identify faulty sequential elements, in a manner that will be described in further detail below. It includes multiple circuit components, each connected to the first sequential element (e.g., FF1, FF4) of the corresponding segment (e.g., 280a, 280b).

[0035] Although the scan chain of device 200, taking segments 280a and 280b as examples, has three sequential elements in each segment (e.g., FF1-FF3, FF4-FF6), it should be understood that, upon reading this disclosure, the number of sequential elements in a scan chain segment can be increased or decreased as needed. For example, Figure 3 This is a schematic block diagram illustrating another exemplary device 300 according to various embodiments of the present disclosure. Figure 3 In this example, device 300 (e.g., device 100) includes multiple scan chains (e.g., 310-350), each scan chain including multiple sequence elements (e.g., FF1-FF4). The sequence elements of each scan chain 310-350 are connected serially and data is shifted sequentially, with data transferred from one sequence element to the next in each clock cycle. In this exemplary embodiment, the sequence elements of scan chains 310-350 are grouped into multiple segments. In this exemplary embodiment, at least one segment includes four sequence elements (FF1-FF4).

[0036] Figure 4 This is a schematic block diagram / circuit diagram illustrating another exemplary device 400 according to various embodiments of the present disclosure. Figure 4In the example device 400 (e.g., device 100-300), first, second, and third input terminals 410-430, one or more scan chains (e.g., scan chain 440), device circuitry 450, and output terminal 460 are included. The input and output terminals 410-430, 460 are externally accessible to device 400.

[0037] Scan chain 440 is connected between input and output terminals 410-430, 460, and includes multiple sequential elements (FF1-FF9) and diagnostic hardware circuitry (e.g., Figure 1 The diagnostic hardware circuit 160. Sequence elements (FF1-FF9) are connected serially, allowing data to move sequentially from one sequence element to the next in each clock cycle, propagating from the first sequence element to the last. The scan chain receives a scan-insignal from input terminal 410 or a data signal (DIN) from device circuitry 450. In this exemplary embodiment, the scan chain 440 is divided into multiple segments (e.g., segments 440a-440d). In some embodiments, at least two of segments 440a-440d have the same number of sequence elements. In other embodiments, the number of sequence elements between segments 440a-440d may differ.

[0038] The diagnostic hardware circuit 160 helps identify faulty sequential elements. For example, the diagnostic hardware circuit 160 includes multiple circuit components (MUX1-MUX4), each connected to one of the sequential elements in a corresponding segment (440a-440d), such as the first sequential element (FF1, FF3, FF6, FF9). Specifically, circuit component (MUX1) is connected between input terminal 410 and the sequential element (FF1). Similarly, circuit components (MUX2-MUX4) connect the last sequential element (FF2, FF5, FF8) of one segment to the first sequential element (e.g., FF3, FF6, FF9) of the next segment.

[0039] Device circuitry 450 is connected to scan chain 440 and performs one or more circuit functions during the normal (or functional) mode of device 400. It generates a data signal (DIN), which is serially shifted through scan chain 440 as part of normal circuit operation. In some embodiments, device circuitry 450 includes various logic components that perform core functions such as data processing, signal routing, or arithmetic calculations. These functions support the overall operation of device 400, while scan chain 440 is able to access sequential elements (FF1-FF9) during diagnostic mode.

[0040] In the exemplary design of device 400, sequential elements (FF1-FF9) are connected to each other in a serial manner to form scan chain 400. Scan chain 440 is then grouped into multiple segments (e.g., segments 440a-440d). The first sequential element of each segment is connected to a corresponding circuit component (MUX1-MUX4) of diagnostic hardware circuitry 160.

[0041] In the exemplary normal (or functional) mode, the data signal (DIN) generated by device circuitry 450 is received at the data input terminals (D) of the sequential elements (FF1-FF9), latched on the rising edge of the clock signal, and serially shifted through their outputs (Q). The output (DOUT) is provided at output terminal 460 for further processing, such as amplification and decoding.

[0042] In the exemplary first diagnostic mode, diagnostic hardware circuitry 160 performs coarse-grained diagnostics to identify defective segments of scan chain 440. Once a defective segment is identified, diagnostic software tools perform finer-grained diagnostics to pinpoint the faulty sequence element identified as a defective segment by diagnostic hardware circuitry 160. For example, during coarse-grained diagnostics, each circuit component (MUX1-MUX4) receives a select signal (SEL) with, for example, a logic high level ('1') from input terminal 420, enabling device 400 to perform coarse-grained diagnostics. A set / reset value is applied to input terminal 430 and serially shifted through scan chain 440 via scan inputs (SI) of sequence elements (FF1-FF9). The set / reset value is then latched in sequence elements (FF1-FF9) and propagated through their outputs (Q). The propagated set / reset value is provided at output terminal 460 for further analysis or observation.

[0043] For example, if the set / reset values ​​at input terminal 430 are all logic "0" (for detecting a stuck-at-1 fault) or all logic "1" (for detecting a stuck-at-0 fault), and if all sequence elements (FF1-FF9) are functioning correctly, the set / reset values ​​remain unchanged as they propagate through scan chain 440. As a result, the output signal (DOUT) at output terminal 460 matches the expected pattern. However, if one or more sequence elements (FF1-FF9) fail, the set / reset values ​​will be altered as they propagate through scan chain 440. For example, Figure 5 This is a schematic block diagram / circuit diagram illustrating another exemplary device 500 according to various embodiments of the present disclosure. Figure 5In this configuration, the sequence element (FF7) is fixed at -1, thus producing a logic "1" output (Q) regardless of its scan input (SI). This results in a changed output at output terminal 460 (e.g., DOUT = 000000111).

[0044] The presence and location of a faulty bit (e.g., logic '1') in the output mode (DOUT) indicates a defective segment (e.g., segment 440c) and that one or more of its sequential elements (FF7, FF8) may be faulty. For example, the output signal (DOUT) indicates that sequential element (FF7) is locked at logic "1", and sequential element (FF8) may also be faulty, making it a candidate for further diagnostics.

[0045] To isolate faulty sequence elements in section 440c, diagnostic software tools then perform fine-grained diagnostics on the candidate sequence elements (FF7, FF8) identified through coarse-grained diagnostics. For example, Figure 6 This is a schematic block diagram / circuit diagram illustrating another exemplary device 600 according to various embodiments of the present disclosure. Figure 6 In this circuit, each circuit component (MUX1-MUX4) receives a select signal (SEL) (e.g., a logic low level "0"), and the diagnostic software tool generates a scan input signal (or test mode data) fed to input terminal 410. The test mode data is sequentially shifted through scan chain 440 via scan inputs (SI) of sequential elements (FF1-FF9) and provided as data output (DOUT) at output terminal 460.

[0046] If sequence element (FF8) produces the expected output, i.e., its output (Q) matches its scan input (SI), it is identified as functional, and sequence element (FF7) is the only faulty sequence element. Otherwise, if sequence element (FF8) produces an unexpected output (DOUT), both sequence elements (FF7 and FF8) are confirmed to be faulty.

[0047] In the exemplary second diagnostic mode, similar hardware-software coordination is used to diagnose transition delay faults, such as slow rise (STR) and slow fall (STF) faults. For example, diagnostic hardware circuitry 160 performs coarse-grained diagnostics to identify defective segments of scan chain 440, while diagnostic software tools perform fine-grained diagnostics to pinpoint faulty sequence elements within the defective segments. In this mode, each circuit component (MUX1-MUX4) receives a select signal (SEL) with logic "1" from input terminal 420. A set / reset value is applied at input terminal 430 and serially shifted through scan chain 440 via scan inputs (SI) of sequence elements (FF1-FF9). The set / reset value is latched in the sequence elements and propagated serially to output terminal 460 via their outputs (Q).

[0048] If all sequence elements (FF1-FF9) function correctly, the transitions in the set / reset values ​​will propagate through scan chain 440 without delay, producing an output (DOUT) that matches the expected pattern. However, if one or more sequence elements (FF1-FF9) exhibit transition delays, such as STR or STF failures, the set / reset values ​​may not propagate in time. For example, as... Figure 5 As shown, the sequence element (FF7) exhibits a STR failure. That is, although it receives a logic "0" to "1" transition at its scan input (SI), its output (Q) fails to rise to logic "1" within the expected time window. This delay results in a damaged output at output terminal 460 (e.g., DOUT = 00000011).

[0049] Delayed transitions in the output mode help identify faulty segments (e.g., 440c) and one or more faulty sequence elements (e.g., FF7, FF8). Specifically, a delayed output of sequence element (FF7) indicates that it has an STR fault, while sequence element (FF8) is identified as a candidate for further diagnostics.

[0050] To isolate faulty components in section 440c, diagnostic software tools perform fine-grained diagnostics on candidates identified by coarse-grained hardware diagnostics (e.g., FF7, FF8). For example, as Figure 6 As shown, the scan input signal (or test mode data) is applied to the input terminal 410, sequentially shifted through the scan chain 440 via the scan input (SI) of the sequence element, and analyzed at the output terminal 460 to check whether the conversion occurs as expected.

[0051] If sequence element (FF8) is functioning correctly (i.e., its output Q matches its scan input (SI), then sequence element (FF7) is confirmed to be the only faulty sequence element exhibiting an STR fault. However, if sequence element (FF8) also produces an unexpected output, then both sequence elements (FF7, FF8) are identified as faulty, each exhibiting a transition delay fault (e.g., STR or STF).

[0052] In this exemplary embodiment, the diagnostic software tool includes an automated test device (ATE) and an ATPG installed in the ATE, the ATPG generating scan signals (or test mode data) during fine-grained diagnostics.

[0053] Figure 7 This is a flowchart of an exemplary method 700 for diagnosing fixed-type faults (i.e., STR and STF) in devices (e.g., 100-600) according to various embodiments of the present disclosure. Further reference will now be made to facilitate understanding. Figures 1-6Describe example method 700. It should be understood that method 700 applies to... Figures 1-6 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 700, additional operations may be provided before, during, and after method 700, and some of the operations described below may be replaced or eliminated.

[0054] In operation 710, coarse-grained diagnostics are performed using diagnostic hardware circuitry 160 to identify defective segments of scan chain 440. For example, each circuit component (e.g., MUX1-MUX4) receives a select signal (SEL), such as a logic "1", from input terminal 420, placing scan chain 440 into a hardware-based diagnostic mode. A scan input signal (or test mode data) is then applied at input terminal 410 and serially shifted through the scan inputs (SI) of sequence elements (FF1-FF9). Each sequence element (FF1-FF9) latches the test mode data at its scan input (SI) and shifts it to the next sequence element via its output (Q) each clock cycle. The test mode data is passed to output terminal 460 as a data output (DOUT) for observation.

[0055] The output data (DOUT) can be analyzed to determine whether the test pattern data has been altered as it propagates through scan chain 440. For example, if the test pattern consists entirely of logic "0" (for a fixed-1 test) or logic "1" (for a fixed-0 test), and if all sequence elements are functioning correctly, the data remains unchanged, and the output (DOUT) matches the input pattern, for example, a string of logic "0" or "1".

[0056] However, if one or more sequence elements fail, the test pattern data will be corrupted during propagation. The altered output (DOUT) can then be used to identify the defective segment. For example, if sequence element (FF7) is fixed at -1, it generates a constant logic "1" at output (Q) regardless of whether a logic "0" is received at scan input (SI). This results in an unexpected change in output observed at output terminal 460 (e.g., DOUT = 000000111). The transition position in the output pattern (DOUT) indicates that segment 440c is defective. Subsequent sequence elements in the same segment (e.g., FF8) may also be considered faulty or require further diagnostics.

[0057] In operation 720, fine-grained diagnostics are performed using diagnostic software tools to further evaluate candidate sequence elements (e.g., FF7, FF8) identified in the hardware-based coarse-grained stage. For example, each circuit component (e.g., MUX1-MUX4) receives a selection signal (SEL), such as logic "0," from input terminal 420, placing scan chain 440 into a software-based diagnostic mode. The diagnostic software tools generate setting / reset values ​​configured to evaluate the behavior of each candidate sequence element (FF7, FF8). This mode is applied at input terminal 430, shifted in scan chain 440 via scan input (SI), and the result output (DOUT) is analyzed at terminal 460 to determine the faulty sequence element.

[0058] If a candidate sequence element (e.g., FF8) produces the expected output, i.e., its output (Q) matches its scan input (SI), then the sequence element (FF8) is considered to be working properly, confirming that the sequence element (FF7) is the only faulty sequence element. Conversely, if the sequence element (FF8) produces an unexpected output, it is confirmed to be faulty, indicating that both sequence elements (FF7 and FF8) are defective.

[0059] As described above, the diagnostic mode combines coarse-grained hardware diagnostics with fine-grained software-based analysis to detect and locate fixed faults in scan chain 440. This hybrid diagnostic approach provides accurate fault isolation while minimizing additional hardware overhead.

[0060] Figure 8 This is a flowchart of an exemplary method 800 for diagnosing switching delay faults (e.g., slow rise (STR) faults or slow fall (STF) faults) in devices (e.g., devices 100-600) according to various embodiments of the present disclosure. Further reference will now be made to facilitate understanding. Figures 1-6 Describe example method 800. It should be understood that method 800 applies to... Figures 1-6 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 800, additional operations may be provided before, during, and after method 800, and some of the operations described below may be replaced or eliminated.

[0061] In operation 810, diagnostic hardware circuitry 160 performs coarse-grained diagnostics on device 400 to identify defective segments of scan chain 440. For example, each circuit component (MUX1-MUX4) receives a select signal (SEL), such as a logic "1", from input terminal 420, switching scan chain 440 to a hardware-based diagnostic mode. A scan input signal (or test mode data) is applied at input terminal 410 and serially shifted through the scan inputs (SI) of sequence elements (FF1-FF9). Each sequence element latches the test mode data at its scan input (SI) and propagates it to the next sequence element through its output (Q). The propagated test mode data is then observed at output terminal 460 as a data output (DOUT). In this exemplary embodiment, the test mode data causes a transition (e.g., a "0" to "1" transition or a "1" to "0" transition) configured to detect transition delay faults.

[0062] The output data (DOUT) can be analyzed to determine if there is a delay or failure in the conversion as the test pattern data propagates through scan chain 440. For example, if all sequence elements (FF1-FF9) are functioning correctly, the conversion will occur without delay, and the output (DOUT) at output terminal 460 will match the expected pattern.

[0063] However, if a sequence element malfunctions, the expected transition may be delayed or fail to occur. The altered or delayed output (DOUT) can then be analyzed to identify the defective segment of scan chain 440. For example, if sequence element (FF7) experiences an STR fault, it may receive a logic "1" at its scan input (SI) but fail to transition from logic "0" to "1" at its output (Q). This delay or fault results in an incorrect output pattern at output terminal 460, such as 000000011. Similarly, if sequence element (FF7) experiences an STF fault, it may fail to transition from logic "1" to "0" at its output (Q), resulting in an incorrect output pattern (e.g., DOUT = 111111100). The location of the erroneous transition in the output (DOUT) indicates that the error originates in segment 440c. Other sequence elements in the same segment (e.g., sequence element (FF8)) may also be faulty.

[0064] In operation 820, a diagnostic software tool is used to perform fine-grained diagnostics to evaluate candidate sequence elements (FF7, FF8) identified during coarse-grained diagnostics, in order to pinpoint the faulty sequence element. For example, each circuit component (MUX1-MUX4) receives a selection signal (SEL), such as logic "0", from input terminal 420, switching scan chain 440 to a software-based diagnostic mode. The diagnostic software tool generates set / reset values ​​(or test mode data) to induce a transition in the candidate sequence elements (e.g., FF7, FF8). The test mode data is applied to input terminal 430, sequentially shifted via scan input (SI) through scan chain 440, and observed at output terminal 460.

[0065] If a candidate sequence element (e.g., FF8) produces the expected output, i.e., it completes the expected transition ("0" to "1" or "1" to "0") within the expected time window, it is determined to be functioning correctly, confirming that the previous sequence element (e.g., FF7) is the only faulty sequence element. Conversely, if the sequence element (FF8) exhibits a delayed or incorrect transition, both sequence elements (FF7, FF8) are diagnosed as faulty.

[0066] As described above, method 800 combines coarse-grained hardware diagnostics with fine-grained software analysis to identify and locate STR and STF transition faults in the scan chain. This hybrid approach ensures accurate fault location with minimal hardware burden.

[0067] Figure 9 This is a schematic block diagram / circuit diagram illustrating another exemplary device 900 according to various embodiments of the present disclosure. Figure 9 In the example device 900 (e.g., device 100-300), first and second input terminals 910, 920, one or more scan chains (e.g., scan chain 930), device circuitry 940, multiple feedback loops 950, 960, and output terminal 970 are included. The input and output terminals 910, 920, 970 are accessible externally to the device 900.

[0068] In at least one embodiment, scan chain 930 is a bidirectional scan chain. For example, scan chain 930 is connected between input and output terminals 910, 920, 970 and includes multiple sequential elements (FF1-FF9) and diagnostic hardware circuitry (e.g., Figure 1The diagnostic hardware circuit 160. Sequence elements (FF1-FF9) are connected serially and data is sequentially shifted from one sequence element to the next in each clock cycle, propagating from the first sequence element of the scan chain 930 to the last sequence element (FF1-FF9) or performing a forward shift operation. The scan chain 930 is grouped into multiple segments (e.g., segments 930a-930c). In some embodiments, at least two of segments 930a-930c have the same number of sequence elements. In other embodiments, they may have different numbers of sequence elements.

[0069] The diagnostic hardware circuit 160 helps identify faulty sequential elements. For example, the diagnostic hardware circuit 160 includes multiple circuit components (MUX1-MUX3), each connected to one of the sequential elements (e.g., the first sequential element) in a corresponding segment 930a-930c. Specifically, circuit component (MUX1) is connected between input terminal 910 and the first sequential element (FF1). Similarly, circuit components (MUX2, MUX3) connect the last sequential element (FF3, FF6) of segments 930a, 930b to the first sequential element (FF4, FF7) of the next segment 930b, 930c. In this exemplary embodiment, the diagnostic hardware circuit 160 also includes a circuit component (MUX4) connected between the last sequential element (FF9) and output terminal 970.

[0070] Feedback loops 950 and 960 are connected between the outputs of segments 930a and 930b and the inputs of the preceding segments 933a and 930a, enabling the scan chain 930 to perform a reverse shift operation. For example, feedback loop 950 connects the output (Q) of the sequence element (FF6) to the input of the circuit assembly (MUX1), while feedback loop 960 connects the output Q of the sequence element FF9 to the input of the circuit assembly MUX2.

[0071] Device circuitry 940 is connected to scan chain 930, performs one or more circuit functions during the functional mode of device 900, and generates functional data (DIN) serially shifted through scan chain 930. In some embodiments, device circuitry 940 includes one or more logic circuits (e.g., logic gates, arithmetic circuits, multiplexers / demultiplexers, encoders / decoders, comparators, any other data generators, or combinations thereof) that support the overall functionality and operation of device 900.

[0072] In the exemplary design of device 900, the sequential elements (FF1-FF9) of each scan chain 930 are connected to each other serially. The scan chains 930 are then divided or grouped into multiple segments 930a-930c. Next, each circuit component (MUX1-MUX3) is connected to one (e.g., the first) sequential element (FF1, FF4, FF7) of the corresponding segment 930a-930c. Finally, feedback loops 950 and 960 are connected between the outputs of segments 930a and 930b and the inputs of the preceding segments 933a and 930a.

[0073] In the exemplary normal (or functional) mode, the functional data (DIN) generated by device circuitry 940 is propagated through scan chain 930. In this mode, each circuit component (MUX1-MUX3) receives a select signal (SEL), such as logic "0", from input terminal 920, enabling device 900 to operate in functional mode. The functional data (DIN) is received at the data input terminals (D) of the sequential elements (FF1-FF9), latched on the clock edge, and propagated serially through their outputs (Q). The obtained data is then provided at output terminal 970 for further processing, such as amplification and / or decoding.

[0074] In the exemplary first diagnostic (test) mode, diagnostic hardware circuitry 160 performs forward shift diagnostics to identify defective segments in the bidirectional scan chain 930. Reverse shift diagnostics are then performed to locate faulty sequential elements within the defective segments identified during the forward shift diagnostics. During the forward shift diagnostics, each circuit component (MUX1-MUX4) receives a selection signal (SEL), such as a logic "1," from input terminal 920, enabling device 900 to operate in the forward shift fault diagnostic mode. A scan input signal (or test mode data) is applied at input terminal 910 and serially shifted in the scan chain 930 via the scan inputs (SI) of the sequential elements (FF1-FF9). The test mode data is latched in the sequential elements (FF1-FF9) and sequentially shifted via their outputs (Q). The resulting data is then provided to output terminal 970 for observation and analysis.

[0075] When the scan input signal at input terminal 910 is all logic '0' (to test for a fixed -1 fault) and all sequential elements (FF1-FF9) are functioning correctly, the test mode data remains intact as it propagates through the sequential elements (FF1-FF9). As a result, the output signal (DOUT) at output terminal 970 matches the input, for example, all logic "0".

[0076] However, if one or more sequence elements (FF1-FF9) fail, the test pattern data may change as it propagates through scan chain 930. For example, Figure 10 This is a schematic block diagram / circuit diagram illustrating another exemplary device 1000 according to various embodiments of the present disclosure. Figure 10 In this configuration, sequence element (FF5) can be fixed at -1 and output a logic "1" regardless of its scan input (SI). This results in a changed output at output terminal 970 (e.g., DOUT = 000011111). The presence of an unexpected logic "1" and its position in the output (DOUT) indicates a defect in segment 930b, and that one or more of its sequence elements (FF5, FF6) may be defective. Specifically, the output pattern (DOUT) indicates that sequence element (FF5) is fixed at -1, and sequence element (FF6) may also be a candidate for further diagnostics.

[0077] To isolate the fault sequence elements in section 930c, reverse shift diagnosis is performed on the candidate sequence elements (FF5, FF6) identified by forward shift diagnosis. For example, Figure 11 This is a schematic block diagram / circuit diagram illustrating another exemplary device 1100 according to various embodiments of the present disclosure. Figure 11 In this circuit, each circuit component (MUX1-MUX4) receives a select signal (SEL), such as a logic "1", enabling device 900 to operate in reverse shift diagnostic mode. A scan input signal (or test mode data) is applied at input terminal 910. The circuit components (MUX1-MUX4) and associated feedback loops 950, 960 redirect the test mode data to the last sequence element (FF9) of the scan chain 930. This redirection initiates the reverse shift operation, i.e., the test mode data propagates from the last sequence element to the first sequence element. In each clock cycle, the output (Q) of the sequence element becomes the scan input (SI) of the previous sequence element.

[0078] As the reverse shift proceeds, the test mode data moves toward the first sequence element (FF1). The circuit components (MUX1-MUX4), in conjunction with feedback loops 950 and 960, route the final result from the first sequence element (FF1) to output terminal 970 for evaluation. If sequence element (FF6) produces the expected output, i.e., its output (Q) matches its scan input (SI), then sequence element (FF6) is determined to be functioning correctly, confirming that sequence element (FFT5) is the only faulty sequence element. Otherwise, if sequence element (FF6) produces an unexpected output (DOUT), then both sequence elements (FF5, FF6) are identified as faulty.

[0079] In the exemplary second diagnostic mode, diagnostic hardware circuitry 160 performs forward shift diagnostics to identify defective segments of the bidirectional scan chain 930, and then performs reverse shift diagnostics to isolate faulty sequence elements in the segments determined to be defective by the forward shift diagnostics. During forward shift diagnostics, each circuit element (MUX1-MUX4) receives a selection signal (SEL), such as logic "1", switching device 900 to diagnostic mode. A scan input signal (or test mode data) is applied at input terminal 910 and serially shifted through the scan chain via the scan inputs (SI) of the sequence elements (FF1-FF9). The test mode data is latched in the sequence elements and serially propagated to output terminal 970 via their outputs (Q).

[0080] If all sequence elements (FF1-FF9) function correctly, the transitions in the test pattern data propagate through the scan chain 930 without delay, resulting in an output pattern (DOUT) matching the expected pattern at output terminal 970. However, if one or more sequence elements (FF1-FF9) experience a transition delay fault, such as a STR or STF fault, the test pattern data will not propagate as expected. For example, if... Figure 10 As shown, the sequence element (FF5) exhibits an STR fault. Although a logic "0" to "1" transition is received at its scan input (SI), the output (Q) of the sequence element (FF7) fails to rise to logic "1" within the expected time. This transition delay results in an incorrect output pattern at output terminal 970 (e.g., DOUT = 000000011).

[0081] The incorrect output pattern (DOUT) and the location of the delayed transition indicate a defect in segment 930b, which includes sequence element (FF5), and may include one or more faulty sequence elements (e.g., FF6). Specifically, the delayed transition at sequence element (FF5) indicates the presence of an STR fault, and sequence element (FF6) can also be considered a candidate for further diagnostics.

[0082] To isolate faulty sequence elements in defective segment 930b, the diagnostic hardware circuitry reconfigures device 1000 to perform reverse shift diagnostics. For example, as... Figure 11As shown, device 1100 receives a scan input signal (or test mode data) at its input terminal 910 to evaluate the transitions at sequential elements (FF5, FF6). Circuit components (MUX1-MUX4) and feedback loops 950, 960 redirect the test mode data to the last sequential element (FF9), initiating reverse data propagation. The test mode data then propagates backward from sequential element (FF9) to sequential element (FF1), with the output (Q) of each sequential element used as the input (SI) of the previous sequential element. The test mode data then reaches sequential element (FF1) and is routed to output terminal 970 for evaluation.

[0083] If sequence element (FF6) produces the expected output, i.e., its output (Q) matches its scan input (SI), then sequence element (FF6) is determined to be functioning correctly, and sequence element (FF5) is identified as the only faulty sequence element, exhibiting a STR fault. Conversely, if sequence element (FF6) produces an unexpected output, then both sequence elements (FF5, FF6) are identified as faulty, each exhibiting a transition delay fault (STR or STF).

[0084] Figure 12 This is a flowchart illustrating an exemplary method for diagnosing fixed faults in devices (e.g., 100-300, 900-1100) according to various embodiments of the present disclosure. Further reference will now be made to facilitate understanding. Figures 1-3 and Figures 9-11 Describe example method 1200. It should be understood that method 1200 is applicable to... Figures 1-3 and Figures 9-11 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 1200, additional operations may be provided before, during, and after method 1200, and some of the operations described below may be replaced or eliminated.

[0085] In operation 1210, forward shift diagnostics are performed on device 900 to identify defective segments of scan chain 930. For example, each circuit component (MUX1-MUX4) receives a select signal (SEL), such as logic "1", from input terminal 920, switching scan chain 930 to forward shift diagnostic mode. A scan input signal (or test mode data) is applied at input terminal 910 and serially shifted through the scan input (SI) of the sequence elements (FF1-FF9). Each sequence element (FF1-FF9) latches the test mode data and propagates it to the next sequence element through its output (Q). The resulting data is then provided as a data output (DOUT) at output terminal 970 via the last circuit component (MUX4).

[0086] The output data (DOUT) can be analyzed to detect any changes in the test pattern data as it propagates through scan chain 930. For example, if the test pattern data is all logic "0" (for a fixed -1 test) or logic "1" (for a fixed -0 test), and if all sequence elements (FF1-FF9) are functioning correctly, the test pattern data (DIN2) remains intact or unchanged. This results in the expected data output (DOUT) pattern appearing at output terminal 970, such as all logic "0".

[0087] However, if a sequence element is faulty, the test pattern data will change as it propagates through scan chain 930. The resulting output (DOUT) can be analyzed to identify the defective segment of scan chain 930. For example, if a sequence element (FF5) is fixed at -1, it will output a logic "1" even if a logic "0" is received at its scan input (SI). This results in a changed output pattern (DOUT) at output terminal 970, such as 000011111. The presence and location of the unexpected logic "1" in the output (DOUT) indicates that the fault is located in segment 930b. Furthermore, other sequence elements (FF6) in segment 930b may also be faulty.

[0088] In operation 1220, a reverse shift diagnosis is performed on the candidate sequence elements (e.g., FF5, FF6) identified during forward shift diagnosis to isolate the exact faulty sequence element. For example, each circuit component (MUX1-MUX4) receives a selection signal (SEL), such as logic "0", from input terminal 920, switching scan chain 930 to reverse shift diagnosis mode. A scan input signal (or test mode data) is applied at input terminal 910. Diagnostic hardware circuitry 160 reconfigures scan chain 930 for reverse shift operation. Circuit components (e.g., MUX1-MUX4) and feedback loops 950 and 960 reroute the test mode data to the last sequence element (FF9). The test mode data then propagates backward through scan chain 930, i.e., from FF9 to FF1, where the output (Q) of each sequence element is used as the scan input (SI) of the previous sequence element. Once the data reaches sequence element (FF1), it is routed to output terminal 970 for analysis.

[0089] If a candidate sequence element (e.g., FF6) produces the expected output, i.e., its output (Q) matches its scan input (SI), then it is determined that it is functioning correctly. This confirms that sequence element (FF5) is the only faulty sequence element. Conversely, if candidate sequence element (FF6) produces an unexpected output, then both sequence elements (FF5, FF6) are confirmed to be faulty.

[0090] By combining forward and reverse shift diagnostics, method 1200 identifies and locates faults in scan chain 930. Forward shift diagnostics provides coarse-grained localization by identifying defective segments, while reverse shift diagnostics enables precise isolation of faulty sequence elements. This dual approach ensures accurate fault localization with minimal hardware burden.

[0091] Figure 13 This is a flowchart of an exemplary method 1300 for diagnosing switching delay faults (e.g., STR faults or STF faults) in devices 100-300, 900-1100 according to various embodiments of the present disclosure. Further reference will now be made to facilitate understanding. Figures 1-3 and Figures 9-11 Describe example method 1300. It should be understood that method 1300 is applicable to... Figures 1-3 and Figures 9-11 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 1300, additional operations may be provided before, during, and after method 1300, and some of the operations described below may be replaced or eliminated.

[0092] In operation 1310, forward shift diagnostics are performed on device 900 to identify defective segments of scan chain 930. For example, each circuit component (MUX1-MUX4) receives a select signal (SEL), such as logic "1", from input terminal 920, switching scan chain 930 to forward shift diagnostic mode. A scan input signal (or test mode data) is applied at input terminal 910 and serially shifted through the scan input (SI) of sequence elements (FF1-FF9). Each sequence element latches the test mode data and propagates it to the next sequence element through its output (Q). The resulting data is then provided as a data output (DOUT) at output terminal 970 via circuit component (MUX4). In this exemplary embodiment, the test mode data causes transitions (e.g., "0" to "1" for STR testing or "1" to "0" for STF testing).

[0093] The output data (DOUT) can be analyzed to detect delays or failures in the expected conversion as the test pattern data propagates through scan chain 930. For example, if all sequence elements (FF1-FF9) are functioning correctly, the resulting conversion propagates without timing violations, resulting in an unchanged output (DOUT) at output terminal 970. However, if a conversion delay fault occurs in a sequence element, the output pattern (DOUT) will be altered or delayed.

[0094] The altered data output (DOUT) can be analyzed to identify defective segments in scan chain 930. For example, if sequence element (FF5) has an STR fault, although it receives a "1" at its scan input SI, it fails to transition from "0" to "1" at output Q. This results in an incorrect pattern (e.g., DOUT = 000000011). Similarly, if sequence element (FF7) has an STF fault, it fails to transition from "1" to "0," resulting in an output (DOUT) such as 111111100. The location of the failed transition in the output (DOUT) helps to locate faulty segments, such as segment 930b. Other elements in this segment, such as sequence element (FF6), can also be considered as candidate elements for further analysis.

[0095] In operation 1320, reverse shift diagnostics are performed on candidate sequence elements (e.g., FF5, FF6) identified by forward shift diagnostics. For example, each circuit component (MUX1-MUX4) receives a selection signal (SEL), such as logic "0", from input terminal 920, switching scan chain 930 to reverse shift diagnostic mode. A scan input signal (or test pattern data) is applied at input terminal 910. Diagnostic hardware circuitry 160 reconfigures scan chain 930 to enable reverse shift mode by routing the test data pattern through circuit components (e.g., MUX1-MUX4) and feedback loops 950, 960 to the last sequence element (FF9). The reverse shift operation propagates test pattern data from the last sequence element (FF9) to the first sequence element (FF1), with the output (Q) of each sequence element used as the scan input (SI) of the previous element. Once the test pattern data (DIN3) arrives at sequence element (FF1), it is routed as data output (DOUT) to output terminal 970 for evaluation.

[0096] If a candidate sequence element (e.g., FF6) produces the expected output, i.e., its output (Q) matches its scan input (SI), then it is determined to be functioning correctly. This confirms that sequence element (FF5) is the only faulty sequence element, exhibiting a transition delay fault such as STR or STF. Conversely, if sequence element (FF6) produces an unexpected output, then both sequence elements (FF5 and FF6) are confirmed to be faulty.

[0097] By combining forward and reverse shift diagnostics, method 1300 identifies and locates slow rise and slow fall faults in a bidirectional scan chain 930. Forward shift diagnostics provides coarse-grained localization by identifying defective segments, while reverse shift diagnostics enables fine-grained isolation of elements in the exact fault sequence. This dual diagnostic approach ensures accurate fault localization with minimal hardware overhead.

[0098] Figure 14This is a schematic block diagram illustrating another exemplary device 1400 according to various embodiments of the present disclosure. Figure 14 In the example device 1400, multiple scan chains 1410-1450 and diagnostic hardware circuitry (e.g., Figure 1 The diagnostic hardware circuit 160 includes multiple sequence elements (e.g., sequence elements FF1-FF6) in each scan chain (e.g., scan chain 1410). These sequence elements are grouped into multiple segments (e.g., segments 1460, 1470). The diagnostic hardware circuit 160 includes multiple circuit components (e.g., Figure 4 and Figure 9 Multiplexers MUX1-MUX4, each component is connected to a sequence element (e.g., sequence element FF1, FF4) of the corresponding segment (1460, 1470).

[0099] In this exemplary embodiment, one or more sequence elements are assigned at least one user-defined constraint. These constraints are applied to maintain the timing dependency, logical order, or placement constraints of scan chains 1410-1450. For example, as indicated by the forward arrows, sequence elements (FF2, FF3, FF1) following sequence elements (FF1, FF2, FF7) can be designated as "immovable" sequence elements. This constraint specifies that the position of sequence elements (e.g., FF2, FF3, FF1) remains unchanged within scan chains 1410, 1430.

[0100] Similarly, as indicated by the reverse arrows, sequence elements (FF9, FF12) preceding other sequence elements (e.g., FF10, F11) can also be designated as "immovable" sequence elements. This restriction specifies that the positions of sequence elements (FF9, FF12) in scan chains 1420, 1430 remain unchanged. Furthermore, as indicated by the double-headed arrows, sequence elements preceding and following sequence elements (FF12-FF14) can also be designated as "immovable" sequence elements. This restriction specifies that the positions of these "immovable" sequence elements remain fixed in scan chains 1430-1450.

[0101] In the exemplary design of device 1400, one or more sequential elements (e.g., FF1-FF14) are designated as “non-movable” sequential elements to maintain specific timing, logic, or placement constraints. Following this, the sequential elements of each scan chain 1410-1450 are grouped into multiple segments based on an area budget (e.g., approximately 1% of the total area). This area budget determines the segment length, for example, the number of sequential elements in each segment. The circuitry of diagnostic hardware circuitry 160 is then connected to the first sequential element in each segment of scan chains 1410-1450.

[0102] Figure 15 This is a schematic block diagram illustrating another exemplary device 1500 according to various embodiments of the present disclosure. Figure 15 In the example device 1500, multiple scan chains 1510-1550 and diagnostic hardware circuitry (e.g., Figure 1 The diagnostic hardware circuit 160 includes multiple sequence elements (e.g., sequence elements FF1-FF6) in each scan chain. These sequence elements are grouped into multiple segments (e.g., segments 1560, 1570). The diagnostic hardware circuit 160 includes multiple circuit components (e.g., Figure 4 and Figure 9 The multiplexer MUXn, each component is connected to the first sequence element (e.g., sequence element FF1, FF4) of the corresponding segment (1560, 1570).

[0103] In this exemplary embodiment, one or more sequence elements are specified with at least one user-defined constraint, for example, to maintain the timing dependencies, logical order, and / or placement constraints of scan chains 1510-1550. For example, sequence elements (FF7-FF17) may be specified as “untouchable” sequence elements. This constraint specifies that sequence elements (FF7-FF17) remain unconnected to circuit components of diagnostic hardware circuitry 160.

[0104] In the exemplary design of device 1500, one or more sequence elements (e.g., FF7-FF17) are designated as “untouchable” sequence elements. The sequence elements of each scan chain 1510-1550 are then grouped into multiple segments based on an area budget (e.g., 1%). This area budget determines the segment length, i.e., the number of sequence elements in each segment. In some embodiments, circuit components of diagnostic hardware circuitry 160 are connected to the first sequence element in each segment of scan chains 1510-1550, except that the first sequence elements (e.g., FF13-FF15, FF17) are “untouchable” sequence elements. In this particular embodiment, the diagnostic connection is omitted to comply with limitations.

[0105] Figure 16 This is a schematic block diagram illustrating another exemplary device 1600 according to various embodiments of the present disclosure. Figure 16 In the example device 1600, multiple scan chains 1610-1650 and diagnostic hardware circuitry (e.g., Figure 1 The diagnostic hardware circuit 160 includes multiple sequence elements (e.g., sequence elements FF1-FF6) in each scan chain. These sequence elements are grouped into multiple segments (e.g., segments 1660, 1670). The diagnostic hardware circuit 160 includes multiple circuit components (e.g., Figure 4 and Figure 9The multiplexer MUXn, each component is connected to the first sequence element (e.g., sequence element FF1, FF4) of the corresponding segment (1660, 1670).

[0106] In this exemplary embodiment, one or more sequence elements are specified with at least one user-defined constraint, for example, to maintain the timing dependencies, logical order, and / or placement constraints of scan chains 1610-1650. For example, sequence elements (FF7-FF17) may be specified as “untouchable” sequence elements. This constraint specifies that sequence elements (FF7-FF17) remain unconnected to circuit components of diagnostic hardware circuitry 160.

[0107] In the exemplary design of device 1600, one or more sequential elements (e.g., FF7-FF17) are designated as “untouchable” sequential elements. The sequential elements of each scan chain 1610-1650 are then grouped into multiple segments based on an area budget (e.g., 1% of the total area). This area budget determines the segment length, i.e., the number of sequential elements in each segment. If the first sequential element of a segment is designated as an “untouchable” sequential element, it will be swapped with another unrestricted sequential element. The replacement can come from the same segment, a different segment of the same scan chain, or from a different scan chain. The circuitry of diagnostic hardware circuitry 160 is then connected to the (new) first sequential element of each segment in scan chains 1610-1650.

[0108] Figure 17 This is a schematic block diagram illustrating another exemplary device 1700 according to various embodiments of the present disclosure. Figure 17 In the example device 1700, multiple scan chains 1710-1750 and diagnostic hardware circuitry (e.g., Figure 1 The diagnostic hardware circuit 160 includes multiple sequence elements (e.g., sequence elements FF1-FF6) in each scan chain (e.g., scan chain 1710). These sequence elements are grouped into multiple segments (e.g., segments 1760, 1770). The diagnostic hardware circuit 160 includes multiple circuit components (e.g., Figure 4 and Figure 9 The multiplexer MUXn, each component is connected to the first sequential element (e.g., FF1, FF4) of the corresponding segment (1760, 1770).

[0109] In this exemplary embodiment, one or more sequence elements are assigned at least one user-defined constraint. These constraints are applied to maintain the timing dependencies, logical ordering, or placement constraints of scan chains 1710-1750. For example, as indicated by the forward arrows, sequence elements (FF1-FF3) following sequence elements (FF7, FF1, FF2) can be designated as "immovable" sequence elements. This constraint specifies that the position of the sequence elements (e.g., FF1-FF3) within scan chain 1710 remains unchanged.

[0110] Similarly, as indicated by the reverse arrow, the sequence element (FF8) preceding the sequence element (FF9) can also be designated as a "non-movable" sequence element. This restriction specifies that the position of the sequence element (FF8) remains unchanged in scan chain 1720. Furthermore, as indicated by the double-headed arrow, the sequence elements preceding and following the sequence elements (FF11, FF18, FF19) can also be designated as "non-movable" sequence elements. This restriction specifies that the positions of these "non-movable" sequence elements remain unchanged in scan chains 1730-1750.

[0111] In the exemplary design of device 1700, one or more sequence elements (e.g., FF7-FF17) are designated as “untouchable” and “non-movable” sequence elements. Based on an area budget (e.g., 1% of the total area), the sequence elements of each scan chain 1710-1750 are grouped into multiple segments. This area budget determines the segment length, i.e., the number of sequence elements in each segment. If the first sequence element of a segment of a scan chain is designated as an “untouchable” sequence element, it is exchanged with another sequence element, such as a sequence element from the same segment, a different segment of the same scan chain, or a sequence element from a different scan chain that is not designated as “untouchable” or “non-movable,” unless the replacement sequence element is marked as “non-movable.” The circuitry of diagnostic hardware circuitry 160 is then connected to the (new) first sequence element of each segment in scan chains 1710-1750.

[0112] Figure 18 This is a schematic block diagram illustrating another exemplary device 1800 according to various embodiments of the present disclosure. Figure 18 In the example device 1800, a scan chain 1810 and device circuitry 1820 are included. The scan chain 1810 includes a plurality of sequential elements (e.g., A, B, C) and diagnostic hardware circuitry (e.g., ...). Figure 1 The diagnostic hardware circuit 160). The sequence elements are grouped into multiple segments (e.g., 1830, 1840).

[0113] In this exemplary embodiment, although the physical scan chain order is that sequence element (B) precedes sequence element (A) and sequence element (C) follows sequence element (A), the functional data path differs from the scan order. For example, the output of sequence element (C) is connected to the input of sequence element (A), while the output of sequence element (A) is connected to the input of sequence element (B). This arrangement avoids placing functionally dependent sequence elements (A, B) in the same segment, while also ensuring that sequence element (B) appears after sequence element (A) in the scan chain. That is, in the functional logic, the output of sequence element (A) drives the input of sequence element (B), but in the scan chain order, sequence element (B) precedes sequence element (A).

[0114] This reordering addresses the limitations of software-based diagnostics. For example, when two functionally dependent sequence elements are assigned to the same segment, signal propagation between them can mask the actual fault location, making it difficult for software-based diagnostics to identify the faulty element. By placing the driven sequence element (B) before the driven sequence element A in the scan chain and assigning them to different segments 1830 and 1840, erroneous fault candidate sequence elements are minimized, and fault isolation is further improved.

[0115] Diagnostic hardware circuitry 160 applied to the first sequence of elements in each segment helps identify the faulty segment and fault type (e.g., a fixed fault or a switching delay fault). The hardware may include, for example, a multiplexer (e.g., Figure 4 and Figure 9 The logic components (MUX1-MUX4) are connected to the scan chain 1810 and operate during normal mode to generate functional data. By combining hardware-based coarse-grained diagnostics with scan-mode-driven software analysis, this approach balances diagnostic resolution and area cost, enabling accurate fault location even in cases of complex logical dependencies between sequential elements.

[0116] Figure 19 This is a flowchart illustrating an exemplary method 1900 for manufacturing a device (e.g., device 1400-1800) according to various embodiments of the present disclosure. Further reference will now be made for ease of understanding. Figures 1-18 Describe example method 1900. It should be understood that method 1900 is applicable to... Figures 1-18 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 1900, additional operations may be provided before, during, and after method 1900, and some of the operations described below may be replaced or eliminated.

[0117] In operation 1910, the device fabrication system assigns at least one user-defined constraint to the sequence of elements (FF1-FF17). In some embodiments, these constraints include a "non-movable" constraint that maintains the position of the sequence of elements in the scan chain (e.g., 1710-1750) and a constraint that prevents the sequence of elements from being connected to diagnostic hardware circuitry (e.g., Figure 1 The diagnostic hardware circuit 160) has an "untouchable" restriction.

[0118] Next, in operation 1920, the device fabrication system groups the sequential elements of each scan chain 1710-1750 into multiple segments (e.g., segments 1760, 1770) based on an area budget, such as 1% of the total area, defined by the segment length (i.e., the number of sequential elements in each segment). Subsequently, in operation 1930, the device fabrication system adjusts the arrangement of sequential elements within the scan chain. For example, if the first sequential element of a segment has a "non-touchable" restriction, it will be swapped with another sequential element. The swapped sequential element can come from the same segment, a different segment of the same scan chain, or a sequential element in a different scan chain that has not been assigned a "non-movable" or "non-touchable" restriction. After adjustment, in operation 1940, the device fabrication system connects circuit components of the diagnostic hardware circuitry 160 (e.g., multiplexers MUX1-MUX4) to the first sequential element of each segment in the scan chain, unless these sequential elements are specified with a "non-movable" or "non-touchable" restriction. In operation 1950, the device manufacturing system then processed the device circuitry (e.g., Figure 1 The device circuit 130) is connected to the scan chain. Finally, in operation 1960, the device manufacturing system manufactures devices 1400-1800.

[0119] In one embodiment, the device is configured to operate in a functional mode and a diagnostic mode. The device includes input and output terminals, a scan chain, and device circuitry. The input terminals are configured to receive test mode data provided by diagnostic software tools. The output terminals are configured to provide diagnostic output data. A scan chain is connected between the input and output terminals and includes multiple sequential elements and diagnostic hardware circuitry. The sequential elements are connected in series and grouped into multiple segments. The diagnostic hardware circuitry includes multiple circuit components, each connected to a sequential element in a corresponding segment. The diagnostic hardware circuitry is configured to identify defective segments of the scan chain during diagnostic mode. During diagnostic mode, test mode data is serially shifted through the scan chain to isolate faulty sequential elements in the defective segments. The device circuitry is connected to the scan chain and configured to perform one or more circuit functions during functional mode and generate functional data that is sequentially shifted through the scan chain.

[0120] In some embodiments, the sequence element is the first sequence element.

[0121] In some embodiments, the diagnostic hardware circuitry is configured to diagnose a fixed-1 fault in one or more sequential elements in a scan chain during a diagnostic mode; test mode data includes a sequence of logic lows serially shifted through the scan chain; a predicted output mode is compared with an actual output mode at an output terminal; and the difference between the predicted output mode and the actual output mode indicates the presence of a fixed-1 fault in one or more sequential elements.

[0122] In some embodiments, the diagnostic hardware circuitry is configured to diagnose a transition delay fault in one or more sequential elements in a scan chain during a diagnostic mode; the test mode data is serially shifted through the scan chain to introduce an upward transition into the scan chain; the expected transition is captured and compared with the actual transition at the output terminal; and it is determined whether the sequential element exhibits a delayed response indicating a transition delay fault.

[0123] In some embodiments, the diagnostic hardware circuitry is configured to diagnose a fixed-0 fault in one or more sequence elements of a scan chain during a diagnostic mode; test mode data includes a sequence of logic highs serially shifted through the scan chain; a predicted output mode is compared with an actual output mode at an output terminal; and the difference between the predicted output mode and the actual output mode indicates the presence of a fixed-0 fault in one or more sequence elements.

[0124] In some embodiments, the diagnostic hardware circuitry is configured to diagnose a transition delay fault in one or more sequential elements of a scan chain during a diagnostic mode; test mode data is serially shifted through the scan chain to introduce a droop transition into the scan chain; the expected transition is captured and compared with the actual transition at the output terminal; and it is determined whether the sequential element exhibits a delayed response indicating a transition delay fault.

[0125] In some embodiments, the scan chain is configured to switch between functional and diagnostic modes in response to a selection signal.

[0126] In another embodiment, the device is configured to operate in a functional mode and a diagnostic mode. The device includes input terminals and output terminals, a bidirectional scan chain, and device circuitry. The input terminals are configured to receive test mode data. The output terminals are configured to provide diagnostic output data. The bidirectional scan chain is connected between the input and output terminals and includes multiple sequence elements and diagnostic hardware circuitry. The multiple sequence elements are connected in series and grouped into multiple segments. The multiple segments include a first segment and a second segment following the first segment. The diagnostic hardware circuitry includes multiple circuit components and a feedback loop. Each circuit component is connected to a sequence element in a corresponding segment. The feedback loop connects the output of the second segment to the input of the first segment. The diagnostic hardware circuitry is configured to perform forward shift diagnostics and reverse shift diagnostics. For transferring test mode data from the first sequence element to the last sequence element of the scan chain during diagnostic mode to identify defective segments of the scan chain. For transferring test mode data from the last sequence element to the first sequence element during diagnostic mode to isolate faulty sequence elements in defective segments. The device circuitry is connected to the scan chain and configured to perform one or more circuit functions during the functional mode, and to generate functional data that is sequentially shifted through the scan chain.

[0127] In some embodiments, a sequence element is the first sequence element.

[0128] In some embodiments, forward shift diagnostics is configured to identify defective segments in the scan chain; test pattern data is serially shifted from the first sequence element to the last sequence element of the scan chain; an output terminal captures the response generated by the scan chain; the expected output pattern is compared with the actual output pattern to detect a difference; and the defective segment is identified when the difference indicates a deviation from the expected propagation of the test pattern data through the scan chain.

[0129] In some embodiments, a reverse shift diagnostic is performed after the defective segment is identified; test pattern data is serially shifted from the last sequence element of the scan chain to the first sequence element in reverse order; diagnostic hardware circuitry isolates the faulty sequence element in the defective segment by analyzing the response at the output terminal; and if the actual output response of the sequence element deviates from the expected test pattern data during the reverse shift, the sequence element is determined to be faulty.

[0130] In some embodiments, the diagnostic hardware circuitry is configured to diagnose fixed faults.

[0131] In some embodiments, the diagnostic hardware circuitry is configured to diagnose switching delay faults.

[0132] In some embodiments, the scan chain is configured to switch between functional and diagnostic modes in response to a selection signal.

[0133] In another embodiment, a method for diagnosing faults in an integrated circuit device includes: performing coarse-grained diagnostics on a scan chain of the integrated circuit device to identify defective segments, and performing fine-grained diagnostics on the identified defective segments to pinpoint one or more faulty sequence elements within the defective segments by serially shifting test pattern data through the scan chain. The scan chain includes a plurality of sequence elements and diagnostic hardware circuitry. The sequence elements are grouped into segments. The diagnostic hardware circuitry includes a plurality of circuit components, each connected to a first sequence element in a corresponding segment. Fine-grained diagnostics are performed on the identified defective segments to pinpoint one or more faulty sequence elements within the defective segments by serially shifting test pattern data through the scan chain.

[0134] In some embodiments, performing the coarse-grained diagnostics includes serially shifting first test mode data through the scan chain, and performing the fine-grained diagnostics includes serially shifting second test mode data through the scan chain.

[0135] In some embodiments, performing coarse-grained diagnostics includes serially shifting first test mode data from the first sequence element of the scan chain to the last sequence element, and performing fine-grained diagnostics includes serially shifting second test mode data from the last sequence element to the first sequence element.

[0136] In some embodiments, the method further includes serial shift function data through a scan chain.

[0137] In some embodiments, the method further includes diagnosing whether a fixed fault exists in the scan chain.

[0138] In some embodiments, the method further includes diagnosing whether a transition delay fault exists in the scan chain.

[0139] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device configured to operate in a functional mode and a diagnostic mode, the device comprising: The input terminal is configured to receive test mode data provided by diagnostic software tools; The output terminal is configured to provide diagnostic output data; A scan chain, connected between the input terminal and the output terminal, the scan chain comprising: Multiple sequential elements, connected in series and grouped into multiple segments; and The diagnostic hardware circuitry comprises multiple circuit components, each connected to a sequence of elements in a corresponding segment, wherein: The diagnostic hardware circuitry is configured to identify defective segments of the scan chain during diagnostic mode; and During the diagnostic mode, the test mode data is serially shifted through the scan chain to isolate fault sequence elements in the defective segment; and The device circuitry is connected to the scan chain and configured to perform one or more circuit functions during the functional mode and generate functional data that is sequentially shifted through the scan chain.

2. The integrated circuit device according to claim 1, wherein, The sequence element is the first sequence element.

3. The integrated circuit device according to claim 1, wherein, The diagnostic hardware circuitry is configured to diagnose a fixed-1 fault in one or more sequence elements in the scan chain during the diagnostic mode. The test mode data includes a logical low sequence serially shifted through the scan chain; The expected output mode is compared with the actual output mode at the output terminal; as well as The difference between the expected output pattern and the actual output pattern indicates a fixed-1 fault in one or more sequence elements.

4. The integrated circuit device according to claim 1, wherein, The diagnostic hardware circuitry is configured to diagnose transition delay faults of one or more sequence elements in the scan chain during the diagnostic mode. The test mode data is serially shifted through the scan chain to introduce an up transition into the scan chain; Capture the expected conversion and compare the expected conversion with the actual conversion at the output terminal; and Determine whether the sequence element exhibits a delayed response that indicates a switching delay fault.

5. The integrated circuit device according to claim 1, wherein, The diagnostic hardware circuitry is configured to diagnose a fixed-0 fault in one or more sequence elements in the scan chain during the diagnostic mode. The test mode data includes a logical high sequence serially shifted through the scan chain; The expected output mode is compared with the actual output mode at the output terminal; as well as The difference between the expected output mode and the actual output mode indicates a fixed -0 fault in one or more sequence elements.

6. The integrated circuit device according to claim 1, wherein, The diagnostic hardware circuitry is configured to diagnose transition delay faults in one or more sequence elements in the scan chain during the diagnostic mode. The test mode data is serially shifted through the scan chain to introduce a descent transition into the scan chain; Capture the expected conversion and compare the expected conversion with the actual conversion at the output terminal; and Determine whether the sequence element exhibits a delayed response that indicates a switching delay fault.

7. An integrated circuit device configured to operate in a functional mode and a diagnostic mode, the integrated circuit device comprising: The input terminal is configured to receive test mode data; The output terminal is configured to provide diagnostic output data; A bidirectional scan chain, connected between the input terminal and the output terminal, the scan chain comprising: Multiple sequence elements are connected in series and grouped into multiple segments, wherein the multiple segments include a first segment and a second segment following the first segment; and Diagnostic hardware circuitry, the diagnostic hardware circuitry comprising: Multiple circuit components, each connected to a sequence element in a corresponding segment; and A feedback loop connects the output of the second segment to the input of the first segment, wherein the diagnostic hardware circuit is configured to perform: Forward shift diagnostics, used to transfer test mode data from the first sequence element to the last sequence element of the scan chain during diagnostic mode to identify defective segments of the scan chain; and Reverse shift diagnostics, used to transfer test mode data from the last sequence element to the first sequence element during the diagnostic mode to isolate faulty sequence elements in the defective segment; and The device circuitry is connected to the scan chain and configured to perform one or more circuit functions during the functional mode and generate functional data that is sequentially shifted through the scan chain.

8. The integrated circuit device according to claim 7, wherein, The scan chain is configured to switch between the functional mode and the diagnostic mode in response to a selection signal.

9. A method for diagnosing faults in an integrated circuit device, the method comprising: Coarse-grained diagnostics are performed on the scan chain of the integrated circuit device to identify defective segments, wherein the scan chain includes: Multiple sequence elements are grouped into segments; and Diagnostic hardware circuitry, comprising multiple circuit components, each said circuit component being connected to a first sequential element in a corresponding segment; and Fine-grained diagnostics are performed on the identified defective sections to pinpoint one or more fault sequence elements within the defective sections by serially shifting through test pattern data from the scan chain.

10. The method according to claim 9, wherein, Performing the coarse-grained diagnostics includes serially shifting first test mode data from the first sequence element of the scan chain to the last sequence element, and performing the fine-grained diagnostics includes serially shifting second test mode data from the last sequence element to the first sequence element.

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