Chip hardware code generation method based on large model code enhancement and self-reflection
By leveraging code-to-code enhancement and self-reflection mechanisms, the shortcomings of open-source large language models in RTL code generation are addressed, enabling high-quality code generation and self-correction, improving the automation level of hardware design, and protecting privacy and intellectual property.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2024-12-23
- Publication Date
- 2026-06-23
AI Technical Summary
Existing open-source large language models are inadequate in generating high-quality RTL code and lack self-reflection capabilities. They also pose privacy and security issues, making it difficult to meet the needs of hardware design.
We employ a code-to-code enhancement approach to redescribe and generate open-source code. Combined with a self-reflection mechanism, we improve dataset quality and achieve self-correction capabilities through an iterative self-reflection process and a dual LoRA model architecture.
It generates high-quality RTL code with self-reflection capabilities, improves the automation level of hardware design, protects privacy and intellectual property, and significantly improves the reliability and efficiency of code generation.
Smart Images
Figure CN122263753A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design automation technology, specifically to a register-transfer-level (RTL) hardware code generation method that utilizes large models for code enhancement and self-reflection. Background Technology
[0002] In recent years, Large Language Models (LLMs) have demonstrated remarkable capabilities in natural language understanding and generation. Research shows that LLMs also exhibit considerable proficiency in code generation tasks. Commercial LLMs (such as GPT-4 and Claude3-Opus) have demonstrated the ability to generate high-quality software code, significantly improving coding efficiency. Furthermore, LLMs have shown impressive capabilities in hardware code generation, particularly register-transfer-level (RTL) code.
[0003] Generating RTL code from natural language instructions offers an innovative approach to improving hardware development efficiency. This method has the potential to revolutionize existing HDL coding workflows by alleviating the heavy workload of designers in hardware description language (HDL) coding. Similar to High-Level Synthesis (HLS), LLM can simplify complex hardware design tasks by generating code from high-level specifications, thereby streamlining the design process.
[0004] However, the application of commercial LLMs in generating RTL code often raises privacy and security concerns. These issues are particularly critical in the field of hardware design, as RTL code typically contains valuable intellectual property. Furthermore, the closed-source nature of these LLMs limits researchers' ability to conduct in-depth analysis and customization, hindering further fine-tuning of the model for specific domains, such as hardware design. In contrast, open-source models offer better privacy and security, while also facilitating further improvement and customization.
[0005] Open-source models (such as StarCoder2, DeepSeek-Coder, and CodeQwen-V1.5) have demonstrated encouraging results in code generation for common programming languages (such as Python and C / C++). However, they still lag behind GPT-3.5 in RTL code generation. This performance gap highlights the urgent need to develop an open-source LLM specifically for RTL code generation.
[0006] Furthermore, compared to other popular programming languages, high-quality, large-scale RTL code datasets are significantly scarce. This shortage poses a major challenge to achieving satisfactory results in RTL generation tasks. To address this issue, some research focuses on collecting open-source code snippets. Verigen (VeriGen: A Large Language Model for VerilogCodeGeneration) collected a comprehensive hardware description language Verilog dataset from open-source repositories on GitHub and various textbooks. Nevertheless, the performance of its optimal fine-tuned model still falls short of GPT-3.5, primarily due to the inconsistent quality of the collected open-source code, which was neither filtered nor processed.
[0007] Existing work, including the VerilogEval (Evaluating Large Language Models for Verilog Code Generation) and RTLCoder (Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique), recognizes the importance of dataset quality and employs data synthesis methods based on commercial LLMs to improve it. VerilogEval uses GPT-3.5 to add descriptions to each code snippet in the filtered VeriGen dataset. This approach enables LLMs trained on the dataset to not only learn Verilog syntax but also understand the correspondence between Verilog code and natural language. However, due to the low average quality of the code in the dataset, VerilogEval's performance still lags behind GPT-3.5. RTLCoder employs a synthesis method to generate RTL code from natural language specifications, but its reliance on a limited set of keywords restricts further dataset expansion and may limit the size and complexity of the generated RTL code.
[0008] Self-reflection is another key factor in RTL code generation. In this context, self-reflection refers to the model's ability to evaluate its generated code based on feedback from the hardware compiler and simulator. Existing open-source LLMs primarily focus on code generation, often neglecting the compilation and simulation interactions indispensable in hardware design methodologies. Some works have integrated self-reflection methods into their frameworks, but these methods mostly rely on commercial LLMs for self-reflection or perform poorly due to limited training data.
[0009] Therefore, the chip hardware design field urgently needs an open-source solution that can generate high-quality RTL code, possess self-reflective capabilities, and protect privacy and intellectual property. On one hand, this solution should be able to effectively acquire high-quality, large-scale RTL code datasets, while the trained model should be able to generate high-quality RTL code and possess self-reflective capabilities similar to commercial LLMs, thereby providing more reliable and efficient support for hardware design. Summary of the Invention
[0010] To address the problems existing in the prior art, this invention provides a method for generating RTL hardware code based on a large model. It aims to overcome the limitations of existing open-source large language models in RTL code generation through code enhancement and self-reflection mechanisms, thereby improving the quality and reliability of the generated code.
[0011] The core of this invention is to overcome the shortcomings of existing open-source large language models in register-transfer level RTL hardware code generation by employing innovative code-to-code enhancement technology and a self-reflective mechanism. To address the limitations of existing work, this invention mainly makes the following improvements:
[0012] 1) A code-to-code enhancement method is proposed: Unlike existing traditional methods that directly use open-source code or generate code based on keywords, this invention utilizes a large commercial language model to re-describe and generate open-source code, i.e., a code-to-code enhancement method, which significantly improves the quality and diversity of the dataset. The specific steps for re-describing and generating open-source code using the code-to-code enhancement method include:
[0013] 11) Strictly filter open-source RTL code samples to ensure code quality and standardization.
[0014] 12) Utilize large language models (such as Claude3-Haiku) to generate detailed code descriptions.
[0015] 13) Regenerate the RTL code based on the generated code description and verify it using an open-source hardware compiler (such as IcarusVerilog).
[0016] 14) Iterate and correct any code that fails to compile until it compiles successfully or the maximum number of iterations is reached.
[0017] 2) Constructing a dedicated error correction dataset: By collecting and filtering error samples from the code generation process, a high-quality error correction dataset was constructed. Model training was then performed on this dataset, enabling the large language model to learn stronger self-reflection capabilities. This specifically includes the following steps:
[0018] 21) Collect failed compilation samples and their corrected versions generated during the code enhancement process.
[0019] 22) Filter and retain samples that are modified only within the main body of the hardware module to ensure the consistency of the hardware module declaration.
[0020] The module contains input / output interface definitions (module declaration) and specific implementation logic (module body). This step only retains error-fixing samples where the modifications made do not involve the interface definitions and only correct the internal implementation logic.
[0021] 23) Construct a high-quality dataset containing error codes, hardware compiler error messages, natural language instructions, and correction codes.
[0022] 3) An iterative self-reflection process was implemented: a closed-loop code generation-verification-correction process was designed, enabling the large language model to continuously improve the generated code based on feedback from the hardware compiler.
[0023] This invention uses an existing, open-source large language model as its backbone, and trains two independent LoRA (Low-Rank Adaptation) adapters on top of it. The advantage of this structure is that it maintains the generality of the base model while achieving task-specific optimization through lightweight LoRA adapters. Specifically, it includes the following steps:
[0024] We employ a base large language model and two specially trained LoRA (low-rank adapter) models: a generative model and a repair model. By separating these two models, we can avoid the performance degradation caused by encountering erroneous code when training in a single model.
[0025] The generative model is responsible for generating the initial RTL code, while the repair model is used for syntax error correction. An iterative self-reflective process is implemented to analyze hardware compiler error messages, identify, and fix the code. The iterative self-reflective code generation process includes several steps: Initial code generation: First, the generative model generates initial RTL code based on the input natural language design task; Compilation and verification: The generated code is submitted to the compiler for verification; Error handling: If compilation fails, the error message, erroneous code, and design task are submitted to the repair model for analysis, and the code is regenerated. This process is repeated until the code compiles successfully or the maximum number of iterations (set to 5) is reached; Finally, the successfully compiled RTL code is output.
[0026] 4) Development of the VerilogFixEval benchmark set for benchmarking: A benchmark set specifically designed to evaluate the self-reflection and correction capabilities of RTL code was created, filling a gap in existing evaluation methods. Specifically, VerilogFixEval is a benchmark set containing code samples that fail to compile, natural language instructions, and compiler error messages, used to evaluate the model's self-reflection and improvement capabilities.
[0027] By following the steps above, code enhancement and self-reflective chip hardware code generation based on a large model can be achieved.
[0028] Compared with the prior art, the beneficial technical effects of the present invention are as follows:
[0029] This invention proposes a dataset construction method based on code-to-code augmentation, which improves the quality of training data by re-describing and generating open-source code through a large model. It innovatively proposes a dual LoRA model architecture that separates code generation and error correction, avoiding the negative impact of training with faulty samples on code generation capabilities. A complete self-reflective loop mechanism is designed, enabling the model to continuously improve the generated code through compilation feedback. A dedicated error correction evaluation benchmark is constructed, providing a standardized evaluation method for related research. Attached Figure Description
[0030] Figure 1 The flowchart of the code-to-code enhancement process provided by this invention includes: filtering open-source RTL code, performing code description, regenerating the code, evaluating it using a hardware compiler, correcting errors if it fails, and re-evaluating until it passes. The RTL code that passes the evaluation is added to the enhanced RTL code dataset, and the error samples that failed and their correction information are used to construct an error correction dataset.
[0031] Figure 2 The flowchart of the iterative self-reflective code generation provided by this invention is as follows: The design task in natural language form is input into the generation model and the repair model. The generated RTL code is evaluated by the compiler. If it fails, an error sample is returned to the repair model for correction, forming a self-reflective loop until the generated RTL code passes the compiler evaluation.
[0032] Figure 3 This is a flowchart of the VerilogFixEval evaluation set construction method provided by the present invention; Starting from the VerilogEval evaluation set, RTL code is generated through the GPT-3.5 model. After evaluation by the compiler, the failed error samples are collected and used to construct the VerilogFixEval evaluation set. Detailed Implementation
[0033] The present invention will be further illustrated below with reference to the accompanying drawings and embodiments.
[0034] This invention provides a method for RTL hardware code generation based on a large model, comprising three main parts: code-to-code enhancement, error correction dataset construction, and a self-reflective loop. The following section combines... Figure 1 , Figure 2 and Figure 3 The embodiments of the present invention will be described in detail.
[0035] 1) Regenerate RTL code through a code-to-code enhancement process;
[0036] Code-to-code enhancement implementation methods, such as Figure 1 As shown, the code-to-code enhancement process of this invention includes the following specific steps:
[0037] 11) Filtering of open-source RTL code datasets; this part corresponds to... Figure 1 After the RTL code is filtered, it is input into the closed-source large model. The specific implementation includes:
[0038] Code samples with more than 300 lines or 1536 characters of tokens were removed;
[0039] Exclude non-standard code that averages more than 30 tokens (approximately 90 characters) per line;
[0040] Keyword filtering requires code to contain the keywords "module" and "endmodule," and must include at least one of either "always" (including variants such as "always_comb," "always_ff," and "always_latch") or "assign." Keyword filtering filters code based on the basic syntax requirements of the hardware description language, ensuring the completeness and validity of the code samples. The keywords "module" and "endmodule" are necessary markers for defining a complete hardware module. "always" blocks and "assign" statements are two basic ways to describe hardware behavior: "always" is used to describe sequential logic (such as flip-flops) and combinational logic, while "assign" is used to describe simple combinational logic connections. This keyword filtering ensures that the code samples contain the basic hardware design structure, avoiding the collection of incomplete or invalid code snippets, thereby improving the quality of the training data.
[0041] Remove all comments to avoid interfering with the code description;
[0042] 12) Code description generation, this part corresponds to Figure 1The closed-source large model is the stage for generating code descriptions from the filtered code. The closed-source large model used here is Claude3-Haiku. The closed-source large model description should include: module functional specifications, input / output port definitions, key signal and timing specifications, and a description of the main behavioral logic.
[0043] 13) Code regeneration and verification, such as Figure 1 As shown, this stage mainly includes the following steps:
[0044] 131) Based on the regenerated description, code generation is performed. The large model generates corresponding RTL code again based on the description generated in the previous steps. The generated code is then compiled and verified using the Icarus Verilog open-source compiler.
[0045] 132) Compilation Verification and Error Handling
[0046] If the code passes compilation verification, it is marked as qualified RTL code; otherwise, the error correction process is initiated to regenerate the code.
[0047] like Figure 1 As shown, the error correction process first requires collecting error samples and error information. This includes RTL code generated by the large model that failed compilation checks, compiler error messages, and descriptions of the code generated by the large model in previous steps. Subsequently, this information is fed back into the large model to request it to correct any syntax errors. The above checking process is then performed on the regenerated RTL from the large model. If the regenerated code still fails to compile, the above steps continue to repeat until it passes or the preset limit of 5 iterations is reached.
[0048] 2) Dataset construction: Two types of datasets are constructed in this stage: an enhanced RTL code dataset and a bug correction dataset.
[0049] Building an enhanced RTL code dataset involves the following steps:
[0050] Collect all RTL code that has passed compilation verification, and pair each RTL code with its corresponding code description;
[0051] Ensure that the code description is complete and covers the module's functionality, interface definitions, and key logic;
[0052] The steps to construct the error correction dataset are as follows.
[0053] To build an error sample collection, we first collect all RTL code that failed compilation checks during the code-to-code enhancement process, which forms the basis of the dataset. Each data sample includes a description of the original code, the error code, compiler error messages, and the corrected version of the code that compiles successfully after correction.
[0054] Sample screening: To ensure the quality of the error correction dataset, the collected samples need to be screened, including:
[0055] Remove samples that correct errors by modifying module declarations, as this may change the module's interface specification. Ensure that the corrections in the retained samples are limited to logical modifications within the module body.
[0056] Partial filtering of recurring error types can prevent certain errors from accounting for an excessively high proportion in the dataset.
[0057] 3) Implementation method of iterative self-reflective code generation, such as Figure 2 As shown, it contains two trained models: a generative model and a repair model. The specific implementation process is as follows:
[0058] 31) Model Training
[0059] The generative model is trained on an enhanced RTL code dataset, which contains natural language descriptions and their corresponding correct RTL code pairs.
[0060] The repair model is built on top of the generative model and further trained on an error correction dataset, specifically designed to analyze compilation error information and propose correction schemes.
[0061] 32) Iterative self-reflective code generation process, this part is as follows: Figure 2 As shown, it includes the following steps:
[0062] Initial code generation: First, a generative model is used to generate initial RTL code based on the input natural language design task;
[0063] Compilation and verification: Submit the generated code to the compiler for verification;
[0064] Error loop handling: If compilation fails, the error message, error code and design task are submitted to the repair model for analysis and code regeneration. The above process is repeated until the code compiles successfully or the maximum number of iterations (set to 5) is reached.
[0065] Finally, the compiled RTL code is output.
[0066] 4) VerilogFixEval benchmark construction, such as Figure 3As shown, this invention also constructs a benchmark dataset, VerilogFixEval, specifically for evaluating the model's error correction capabilities. The construction process involves collecting error samples, which include:
[0067] Design problems using the VerilogEval evaluation set;
[0068] Generate RTL code using a model with performance comparable to GPT-3.5;
[0069] Collect code samples that fail to compile, along with their corresponding code descriptions and compiler error messages;
[0070] Filter out erroneous samples to ensure a relatively balanced distribution of different error types;
[0071] The evaluation components, for each problem in the evaluation set, include error samples collected in the process described above, as well as the testbench (a code framework used to test and verify the correctness of hardware design functions) in the VerilogEval evaluation set, used to check whether the fixed code has passed the functional tests.
[0072] Through the above technical solution, the present invention achieves high-quality automatic generation of RTL hardware code and has strong error detection and self-correction capabilities, significantly improving the automation level of hardware design.
[0073] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
Claims
1. A chip hardware code generation method based on large-model code enhancement and self-reflection, characterized in that, Includes the following steps: 1) Design a code-to-code enhancement method to re-describe open-source code and generate register-transfer level code, and verify it through an open-source hardware compiler; 2) By collecting and filtering error samples during the code generation process, an error correction dataset is constructed to enable the model to learn strong self-reflection capabilities; the error correction dataset includes error codes, hardware compiler error messages, natural language instructions, and correction codes; 3) Through an iterative self-reflective process, including a closed-loop code generation-verification-correction process, the large language model continuously improves the generated code based on feedback from the hardware compiler; including: A basic large language model and two pre-trained low-rank adapter models are used as the generation model and the repair model, respectively. The generation model is responsible for generating the initial RTL code, and the repair model is used for correcting syntax errors. Separating the generation model and the repair model avoids performance degradation caused by erroneous code during training in a single model. Through an iterative self-reflection process, compiler error information is analyzed to identify and repair the code. 4) Create a benchmark set, perform benchmark tests, and evaluate the self-reflection and improvement capabilities of the model's register-transfer level code; the benchmark set includes code samples that failed to compile, natural language instructions, and compiler error messages; Through the above steps, code enhancement and self-reflective chip hardware code generation based on large models can be achieved.
2. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 1, characterized in that, Step 1) specifically involves using a large language model to re-describe and generate the open-source code, including the following steps: 11) Strictly filter open-source register transfer level code samples; 12) Generate detailed code descriptions using large language models; 13) Regenerate the register transfer level code based on the generated detailed code description and verify it using an open-source hardware compiler; 14) Iterate and correct any code that fails to compile until it compiles successfully or the maximum number of iterations is reached.
3. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 2, characterized in that, The large language model uses Claude3-Haiku; the open-source hardware compiler uses Icarus Verilog.
4. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 1, characterized in that, Step 2) Construct the error correction dataset, including: 21) Collect failed compilation samples and their corrected versions generated during the code enhancement process; 22) Filter and retain samples that are modified only within the main body of the chip hardware module to ensure the consistency of the module declaration.
5. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 1, characterized in that, Step 1) The code-to-code enhancement method includes the following steps: 11) Filter the open-source register transfer level code dataset; 12) Generate code description; the closed-source large model is Claude3-Haiku; the content of the closed-source large model description includes: module function description, input and output port definition, key signal and timing description, and main behavioral logic description; 13) Code regeneration and verification, this stage includes the following steps: 131) Code generation is performed based on the regenerated description. The large model generates the corresponding RTL code again based on the description generated in the previous steps. The generated code is then compiled and verified by an open-source compiler. 132) Compilation verification and error handling: If the code passes compilation verification, it is marked as qualified register-transfer level code; Otherwise, initiate the error correction process and regenerate the code; 133) Construct two types of datasets: an enhanced register-transfer level code dataset and an error correction dataset; Building the enhanced RTL code dataset includes: collecting all register-transfer level code that has passed compilation verification, and pairing each register-transfer level code with its corresponding code description; the register-transfer level code description fully covers the module function, interface definition and key logic; Building the bug fix dataset involves: first, collecting all register-transfer level code that failed compilation checks during the code-to-code enhancement process, which serves as the basis for the dataset; for each data sample, the dataset includes the corresponding original code description, bug code, compiler error message, and the corrected version of the code that compiles successfully after correction. Sample screening includes: removing samples that correct errors by modifying module declarations, ensuring that the corrections in the retained samples are limited to logical modifications within the module body; and partially filtering duplicate error types to avoid errors accounting for too high a proportion in the dataset.
6. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 5, characterized in that, Step 11) Filter the open-source register transfer level code dataset, including: Code samples with more than 300 lines or 1536 characters of tags were removed; Exclude non-standard code that averages more than 30 tokens and approximately 90 characters per line; By filtering by keywords, the code must contain the keywords "module" and "endmodule", and must contain at least one of "always" or "assign". Remove all comments to avoid interfering with the generation of code descriptions.
7. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 5, characterized in that, In step 132), the error correction process is as follows: First, collect error samples and error messages, including register transfer level code generated by the large model that failed the compilation check, compiler error messages and code descriptions generated by the large model in previous steps; Subsequently, the erroneous samples and error messages are input back into the large model to correct the syntax errors. Perform the above detection process on the register-transfer level code regenerated from the large model; if the regenerated code still fails to compile, continue the above steps until it passes or reaches the preset number of loops.
8. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 1, characterized in that, Step 3) The implementation process of iterative self-reflective code generation includes: 31) Perform model training, including: The generative model is trained on an enhanced register-transfer level code dataset, which contains natural language descriptions and corresponding correct register-transfer level code pairs. A repair model is built based on the generative model and trained on the error correction dataset to analyze compilation error information and propose correction schemes; 32) The iterative self-reflective code generation process includes the following steps: Initial code generation: First, a generative model is used to generate initial register-transfer level code based on the input natural language design task; Compilation and verification: Submit the generated code to the compiler for verification; Error loop handling: If compilation fails, the error message, error code, and design task are submitted to the repair model for analysis and code regeneration; repeat the above process until the code compiles successfully or the maximum number of iterations is reached; Finally, the compiled register-transfer level code is output.
9. The chip hardware code generation method based on large model code enhancement and self-reflection as described in claim 1, characterized in that, Step 4) Construct a benchmark dataset to evaluate the model's error correction capabilities; The methods for collecting error samples include: Design problems using the VerilogEval evaluation set; Generate register-transfer level code using a model with performance comparable to GPT-3.5; Collect code samples that fail to compile, along with their corresponding code descriptions and compiler error messages; Filter out erroneous samples to ensure a relatively balanced distribution of different error types; Evaluation components: For each problem in the evaluation set, it includes collected error samples and a code framework (testbench) from the VerilogEval evaluation set used to test and verify the functional correctness of the hardware design, and to check whether the fixed code has passed the functional tests.