Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

A semiconductor storage device having high reliability is provided. The semiconductor storage device includes: a laminate having conductive layers and insulating layers alternately laminated in a first direction; a plurality of memory pillars extending in the first direction within the laminate; and a structure body partitioning the plurality of memory pillars and extending in the first direction within the laminate. The structure body includes: a crystalline conductor extending in the first direction within the laminate; a first insulating film provided between the laminate and the crystalline conductor; a crystalline semiconductor film provided between the crystalline conductor and the first insulating film and containing silicon; and a second insulating film provided between the crystalline semiconductor film and a side surface of the crystalline conductor and containing silicon and oxygen. The crystalline conductor includes: a first crystalline region in contact with the crystalline semiconductor film and containing germanium; and a second crystalline region provided on the first crystalline region and in contact with the second insulating film in a second direction perpendicular to the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0002] Semiconductor storage devices, such as NAND flash memory, are known to have storage cells arranged in three dimensions on a semiconductor wafer. Summary of the Invention

[0003] One of the technical problems that the invention aims to solve is to provide a semiconductor memory device with high reliability.

[0004] The semiconductor memory device of the embodiment includes: a stack having a conductive layer and an insulating layer, the conductive layer and the insulating layer being alternately stacked in a first direction; a plurality of memory pillars extending in the stack along the first direction; and a structure dividing the plurality of memory pillars and extending in the stack along the first direction.

[0005] The structure comprises: a crystalline conductor extending in a first direction within a laminate; a first insulating film disposed between the laminate and the crystalline conductor; a crystalline semiconductor film disposed between the crystalline conductor and the first insulating film, and containing silicon; and a second insulating film disposed between the crystalline semiconductor film and the side surface of the crystalline conductor, and containing silicon and oxygen. The crystalline conductor comprises: a first crystalline region in contact with the crystalline semiconductor film and containing germanium; and a second crystalline region disposed above the first crystalline region and in contact with the second insulating film in a second direction perpendicular to the first direction. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example of memory configuration.

[0007] Figure 2 This is a circuit diagram showing the circuit configuration of a memory cell array.

[0008] Figure 3 This is a cross-sectional schematic diagram showing an example of the construction of a semiconductor memory device.

[0009] Figure 4 This is an enlarged schematic diagram showing a portion of the cross-section of a semiconductor memory device.

[0010] Figure 5 This is a planar schematic diagram showing an example of the planar layout of the storage column MP and the structure BS.

[0011] Figure 6 This is a cross-sectional schematic diagram showing a construction example of a storage column MP.

[0012] Figure 7This is a cross-sectional schematic diagram showing a construction example of the structure BS.

[0013] Figure 8 This is a diagram illustrating an example of the cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0014] Figure 9 This is a diagram illustrating an example of the cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0015] Figure 10 This is a diagram illustrating an example of the cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0016] Figure 11 This is a diagram illustrating an example of the cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0017] Figure 12 This is a diagram illustrating an example of the cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0018] Figure 13 This is a diagram illustrating an example of the cross-sectional structure during the manufacturing process of a semiconductor memory device.

[0019] Figure 14 This is a cross-sectional schematic diagram used to illustrate a construction example of a conventional BS structure.

[0020] Figure 15 This is a cross-sectional schematic diagram illustrating a construction example of the structure BS in the semiconductor memory device of this embodiment.

[0021] Figure 16 This is a cross-sectional schematic diagram used to illustrate the first modified example of the structure BS.

[0022] Figure 17 This is a cross-sectional schematic diagram used to illustrate the second variant of the structure BS.

[0023] Figure 18 This is a cross-sectional schematic diagram used to illustrate a construction example of a conventional BS structure.

[0024] Figure 19 This is a cross-sectional schematic diagram used to illustrate the third variant of the structure BS. Detailed Implementation

[0025] The embodiments will now be described with reference to the accompanying drawings. The relationships between the thickness and planar dimensions of each component, and the proportions of the thicknesses of each component shown in the drawings, may sometimes differ from the actual object. Furthermore, in the embodiments, substantially identical components are labeled with the same reference numerals, and descriptions are appropriately omitted.

[0026] Unless otherwise specified, the term "connection" in this specification includes not only physical connections but also electrical connections.

[0027] An example of the configuration of a semiconductor memory device will be described. Figure 1 This is a block diagram illustrating an example of memory configuration. The memory includes a memory cell array 1, a command register 2, an address register 3, a sequencer 4, a driver 5, a row decoder 6, and a sense amplifier 7.

[0028] Storage cell array 1 contains multiple blocks BLK (BLK0~BLK(L-1) (L is a natural number greater than 2)). A block BLK is a collection of multiple storage cells that store data.

[0029] Command register 2 holds command signals CMD received from the memory controller. Command signals CMD may contain, for example, command data that causes sequencer 4 to perform read, write, and erase operations.

[0030] Address register 3 holds the address signal ADD received from the memory controller. The address signal ADD includes, for example, the block address BA, page address PA, and column address CA. For example, the block address BA, page address PA, and column address CA are used for the selection of the block BLK, word line WL, and bit line BL, respectively.

[0031] The sequencer 4 controls the operation of the memory. For example, the sequencer 4 controls the driver 5, the line decoder 6, and the sense amplifier 7 based on the command signal CMD held in the command register 2, and performs operations such as read, write, and erase.

[0032] Driver 5 generates voltages used in read, write, and erase operations. Driver 5 includes, for example, a DA converter. Furthermore, driver 5 applies the generated voltage to the signal line corresponding to the selected word line WL, for example, based on the page address PA held in address register 3.

[0033] The row decoder 6 selects one block BLK within the corresponding memory cell array 1 based on the block address BA held in the address register 3. Furthermore, the row decoder 6, for example, transmits the voltage applied to the signal line corresponding to the selected word line WL to the selected word line WL within the selected block BLK.

[0034] During the write operation, the sense amplifier 7 applies the desired voltage to each bit line BL based on the write data DAT received from the memory controller. Conversely, during the read operation, the sense amplifier 7 determines the data stored in the memory cell based on the voltage of the bit line BL, and transmits the determination result as read data DAT to the memory controller.

[0035] Communication between the memory and the memory controller supports, for example, the NAND interface standard. This communication utilizes, for instance, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, the ready / busy signal RBn, and input / output (I / O) signals.

[0036] The command latch enable signal CLE indicates that the received I / O signal from the memory is the command signal CMD. The address latch enable signal ALE indicates that the received I / O signal is the address signal ADD. The write enable signal WEn is the signal that commands the memory to perform I / O. The read enable signal REn is the signal that commands the memory to perform I / O.

[0037] The Ready / Busy signal RBn is a signal that informs the memory controller whether the memory is in a ready state (accepting commands from the memory controller) or a busy state (not accepting commands).

[0038] Input / output (I / O) signals are, for example, 8-bit wide signals, and may include command signals (CMD), address signals (ADD), write data signals (DAT), etc.

[0039] The memory and memory controller described above can be combined to form a semiconductor memory device. Examples of such semiconductor memory devices include memory cards like SD cards and solid-state drives (SSDs).

[0040] Next, an example of the circuit configuration of the memory cell array 1 will be described. Figure 2 This is a circuit diagram showing the circuit configuration of the memory cell array 1. Figure 2 Block BLK0 is shown as an example, but the structure of other blocks BLK is the same.

[0041] Block BLK contains multiple string units SU. Each string unit SU contains multiple NAND strings NS. Additionally, Figure 2 The diagram shows three string units SU (SU0~SU2), but the number of string units SU is not particularly limited.

[0042] Each NAND string NS is connected to one of multiple bit lines BL (BL0 to BL(N-1), where N is a natural number greater than 2). Each NAND string NS contains, for example, a storage transistor MT, a select transistor ST1, and a select transistor ST2. The storage transistor MT constitutes a memory cell MC. Each NAND string NS has multiple memory cells connected in series.

[0043] The storage transistor MT includes a control gate and a charge storage layer, enabling it to retain data non-volatilely. Furthermore, the storage transistor MT can be a MONOS type, where an insulating film is used in the charge storage layer, or an FG type, where a conductive layer is used in the charge storage layer. In the following implementation, the MONOS type will be used as an example.

[0044] The control gate of the storage transistor MT is connected to the corresponding word line WL. One of the source and drain of one of the storage transistors MT is connected to the other of the source and drain of another storage transistor MT. Figure 2 The diagram shows multiple storage transistors MT (MT0 to MT(M-1) (M is a natural number greater than 2)), but the number of storage transistors MT is not particularly limited.

[0045] Transistor ST1 is selected for the selection of the string unit SU during various operations. There is no particular limitation on the number of transistors ST1 selected.

[0046] Transistor ST2 is selected for the selection of the string unit SU during various operations. There is no particular limitation on the number of transistors ST2 selected.

[0047] In each NAND string NS, the drain of select transistor ST1 is connected to the corresponding bit line BL. The source of select transistor ST1 is connected to one end of the series-connected storage transistor MT. The other end of the series-connected storage transistor MT is connected to the drain of select transistor ST2.

[0048] Within the same block BLK, the source of select transistor ST2 is connected to source line SL. The gate of select transistor ST1 in each string cell SU is connected to its corresponding select gate line SGD. The gate of storage transistor MT is connected to its corresponding word line WL. The gate of select transistor ST2 is connected to its corresponding select gate line SGS.

[0049] Multiple NAND strings NS, assigned the same column address CA, are connected to the same bit line BL across multiple blocks BLK. Source lines SL are connected across multiple blocks BLK.

[0050] Figure 3 This is a cross-sectional schematic diagram illustrating a construction example of a semiconductor memory device according to an embodiment. Figure 4 This is an enlarged schematic diagram showing a portion of a cross-section of a semiconductor memory device according to an embodiment. Figure 3 as well as Figure 4The diagram shows an X-axis direction that is substantially parallel to the surface of the semiconductor substrate 11, a Y-axis direction that is substantially perpendicular to the X-axis along the surface, and a Z-axis direction that intersects the surface substantially perpendicularly. "Substantially parallel" includes not only parallel directions but may also include directions deviating from the parallel direction by ±10 degrees. "Substantially perpendicular" includes not only vertical directions but may also include directions deviating from the vertical direction by ±10 degrees. The Z-axis direction is, for example, the thickness direction of the semiconductor substrate 11.

[0051] The semiconductor memory device has a circuit region 10 and an array region 20. Circuit region 10 includes peripheral circuitry such as a command register 2, an address register 3, a sequencer 4, a driver 5, a row decoder 6, and a sense amplifier 7. The peripheral circuitry can be constructed, for example, using CMOS circuitry. Array region 20 includes a memory cell array 1.

[0052] A semiconductor memory device is formed, for example, by bonding a circuit wafer W1 containing a circuit region 10 with an array wafer W2 containing an array region 20. Figure 3 The mating surface B between circuit region 10 and array region 20 is shown.

[0053] The circuit region 10 includes a semiconductor substrate 11, a transistor 12, an interlayer insulating film 13, a contact plug 14, a wiring layer 15 containing multiple wirings, a through-hole plug 16, and a metal pad 17.

[0054] The array region 20 includes an interlayer insulating film 21, a metal pad 22, a via plug 23, a wiring layer 24 containing multiple wirings, a contact plug 25, a stack 26, a memory pillar MP, a structure BS, a source layer 28, and an insulating film 29. Figure 3 One of a plurality of contact plugs 25 is shown.

[0055] The semiconductor substrate 11 is, for example, a Si (silicon) substrate or other semiconductor substrate. A transistor 12 is disposed on the semiconductor substrate 11 and includes a gate insulating film 12a and a gate electrode 12b. The transistor 12, for example, constitutes the CMOS circuit described above. An interlayer insulating film 13 is disposed on the semiconductor substrate 11 to cover the transistor 12. The interlayer insulating film 13 is, for example, a laminate containing a SiO2 film (silicon oxide film), or a SiO2 film and other insulating films.

[0056] Contact plugs 14, wiring layers 15, via plugs 16, and metal pads 17 are formed within the interlayer insulating film 13. Specifically, contact plugs 14 are disposed on the semiconductor substrate 11 or on the gate electrode 12b of the transistor 12. Figure 3In this configuration, contact plugs 14 on the semiconductor substrate 11 are disposed on the source and drain regions (not shown) of the transistor 12. A wiring layer 15 is disposed on the contact plugs 14. A via plug 16 is disposed on the wiring layer 15. A metal pad 17 is disposed on the via plug 16 above the semiconductor substrate 11. The metal pad 17 is, for example, a Cu (copper) layer.

[0057] Interlayer insulating film 21 is formed on interlayer insulating film 13. Interlayer insulating film 21 is, for example, a laminate containing a SiO2 film, or a SiO2 film and other insulating films.

[0058] Metal pads 22, via plugs 23, wiring layers 24, and contact plugs 25 are formed within the interlayer insulating film 21. Specifically, the metal pads 22 are disposed on metal pads 17 above the semiconductor substrate 11. The metal pads 22 are, for example, Cu layers. The via plugs 23 are disposed on the metal pads 22. The wiring layers 24 are disposed on the via plugs 23. Figure 3 One of a plurality of wirings within wiring layer 24 is shown, which functions, for example, as a bit line BL. Contact plug 25 is configured on wiring layer 24.

[0059] The laminate 26 is disposed on the interlayer insulating film 21 and includes a plurality of conductive layers 31 and a plurality of insulating layers 32 alternately stacked in a generally parallel direction along the Z-axis. The conductive layers 31 are, for example, metal layers containing tungsten (W) layers, functioning as word lines WL. The insulating layers 32 are, for example, SiO2 films. In this embodiment, the plurality of conductive layers 31 and the plurality of insulating layers 32 have the same thickness. However, the uppermost insulating layer 32 may be thicker than the other insulating layers 32.

[0060] The source layer 28 comprises a semiconductor layer 37 and a metal layer 38 sequentially formed on the stack 26, the memory pillar MP, and the structure BS, and functions as the source line SL. The metal layer 38 is formed directly on the semiconductor layer 37. The semiconductor layer 37 is, for example, a polycrystalline semiconductor layer such as a polycrystalline silicon layer. The metal layer 38 comprises, for example, a W layer, a Cu layer, or an Al (aluminum) layer. The semiconductor layer 37 may contain P (phosphorus) atoms and H (hydrogen) atoms as impurity atoms.

[0061] An insulating film 29 is formed on the source layer 28. The insulating film 29 is, for example, a SiO2 film.

[0062] like Figure 3 As shown, circuit region 10 also includes a wiring layer 15a containing multiple wirings and a wiring layer 15b containing multiple wirings. Figure 3In the circuit region 10, a wiring layer 15a is provided on the wiring layer 15, a wiring layer 15b is provided on the wiring layer 15a, and a through-hole plug 16 is provided on the wiring layer 15b. Figure 3 The circuit has three wiring layers 15, 15a, and 15b, but the number of wiring layers in the circuit region 10 can also be more than three.

[0063] like Figure 3 As shown, array region 20 also has a wiring layer 24a containing multiple wirings. Figure 3 In the array region 20, a wiring layer 24a is provided on the through-hole plug 23, and a wiring layer 24 is provided on the wiring layer 24a. Figure 3 The array has two wiring layers 24 and 24a, but the number of wiring layers in the array region 20 can also be more than two.

[0064] The array region 20 also has a memory cell array 1 disposed within the interlayer insulating film 21 and under the insulating film 29. The memory cell array 1 includes a stack 26, memory pillars MP, a structure BS, a source layer 28, etc. Each conductive layer 31 within the stack 26 functions as a word line WL, and the source layer 28 functions as a source line SL.

[0065] The memory cell array 1 includes a stepped structure 42. Each word line WL is electrically connected to the word routing layer 44 via a contact plug 43. On the other hand, each memory cylinder MP is electrically connected to the bit line BL via a contact plug 25, and is also electrically connected to the source line SL. In this embodiment, the word routing layer 44 and the bit line BL are contained within the routing layer 24.

[0066] The array region 20 also has a plurality of through-hole plugs 45, metal pads 46 and passivation film 47. The plurality of through-hole plugs 45 are disposed on the wiring layer 24, the metal pads 46 are disposed on the through-hole plugs 45 and the insulating film 29, and the passivation film 47 is disposed on the metal pads 46 and the insulating film 29.

[0067] The metal pad 46 is, for example, a Cu layer or an Al layer, and functions as an external connection pad (bonding pad) for the semiconductor memory device of this embodiment. The passivation film 47 is, for example, an insulating film such as a SiO2 film, and has an opening P that exposes the upper surface of the metal pad 46. The metal pad 46 can be electrically connected to a mounting substrate or other device via the opening P through bonding wires, solder balls, metal bumps, etc.

[0068] The memory columns MP extend within the stack 26 in a direction approximately parallel to the Z-axis. The stack 26 and the multiple memory columns MP form the memory cell array 1.

[0069] Multiple storage columns (MPs) are divided into multiple groups by a structure (BS). The structure (BS) can also be a contact embedded in the stack 26, for example. The structure (BS) can extend through the stack 26 in a direction approximately parallel to the Z-axis and connect to the source layer 28.

[0070] Figure 5 This is a planar schematic diagram showing an example of the planar layout of the storage column MP and the structure BS. Figure 5 Multiple memory pillars (MPs) and multiple structures (BSs) are shown. The multiple structures (BSs) are arranged, for example, along a direction substantially parallel to the Y-axis of the semiconductor substrate 11 and extending along a direction substantially parallel to the X-axis. Multiple memory pillars (MPs) are disposed between the multiple structures (BSs). Furthermore, the number of memory pillars (MPs) is not limited to [specific number]. Figure 5 The quantity shown.

[0071] Figure 6 This is a cross-sectional schematic diagram showing a construction example of the storage column MP. Additionally, in Figure 6 For simplicity, the vertical orientation of the storage column MP is shown relative to its horizontal position. Figure 3 , Figure 4 The image shows the inverted state of the memory column MP. The memory column MP is divided into multiple layers, including a first layer T1 and a second layer T2 disposed above the first layer T1. In each layer, the memory column MP extends in a manner that narrows towards the semiconductor layer 37 in the Y-axis direction. The number of multiple layers can also be more than two.

[0072] The storage column MP has a barrier insulating film 201, a charge storage film 202, a tunnel insulating film 203, a semiconductor layer 204, a core insulating layer 205, and a capping layer 206. The barrier insulating film 201, charge storage film 202, tunnel insulating film 203, semiconductor layer 204, and core insulating layer 205 extend in a direction substantially parallel to the Z-axis. One storage column corresponds to one NAND string NS. The storage column MP has a storage layer. The storage layer has a barrier insulating film 201, a charge storage film 202, and a tunnel insulating film 203. The storage layer extends through the laminate 26 in a direction substantially parallel to the Z-axis. A portion of the storage layer may also extend within the semiconductor layer 37 in a direction substantially parallel to the Z-axis.

[0073] The barrier insulating film 201 and the core insulating layer 205 may contain, for example, oxygen and silicon. The charge storage film 202 may contain, for example, nitrogen and silicon. The tunnel insulating film 203 may contain, for example, oxygen and silicon. In addition, the barrier insulating film 201 and the tunnel insulating film 203 may also contain, for example, nitrogen.

[0074] More specifically, a hole is formed that penetrates multiple conductive layers 31 and corresponds to a storage pillar MP. A barrier insulating film 201, a charge storage film 202, and a tunnel insulating film 203 are sequentially stacked on the sides of the hole. Then, a semiconductor layer 204 is formed such that the sides of the semiconductor layer 204 are in contact with the tunnel insulating film 203.

[0075] Semiconductor layer 204 extends within the stack 26 in each of the first layer T1 and the second layer T2 in a direction substantially parallel to the Z-axis. Semiconductor layer 204 has channel formation regions for selection transistor ST1, selection transistor ST2, and storage transistor MT. Therefore, semiconductor layer 204 functions as a signal line connecting the current paths of selection transistor ST1, selection transistor ST2, and storage transistor MT.

[0076] Semiconductor layer 204 is in contact with the surface of tunnel insulating film 203 in each of the first layer T1 and the second layer T2. Semiconductor layer 204 may comprise, for example, a polycrystalline semiconductor layer such as polycrystalline silicon. Semiconductor layer 204 may also be formed, for example, by crystallizing an amorphous silicon film. Semiconductor layer 204 also extends inside and is in contact with semiconductor layer 37. That is, semiconductor layer 204 is exposed from tunnel insulating film 203, semiconductor layer 37 is directly in contact with semiconductor layer 204, and source layer 28 is electrically connected to the channel formation region of each memory pillar MP. A portion of semiconductor layer 204 may also extend within semiconductor layer 37 in a direction substantially parallel to the Z-axis.

[0077] The core insulating layer 205 is disposed inside the semiconductor layer 204 in each of the first layer T1 and the second layer T2. The core insulating layer 205 extends within the laminate 26 in a direction substantially parallel to the Z-axis. The core insulating layer 205 is surrounded by the semiconductor layer 204 in the XY plane.

[0078] A capping layer 206 is disposed above the core insulating layer 205 and is in contact with the semiconductor layer 204. The capping layer 206 may contain, for example, oxygen and silicon, or polycrystalline silicon containing N-type impurity elements. For example, when the capping layer 206 contains oxygen and silicon, the diffusion of impurity elements can be suppressed. When the capping layer 206 is an insulating layer, N-type impurity elements such as phosphorus and arsenic may be implanted onto the surface of the capping layer 206. The capping layer 206 is connected to the contact plug 25.

[0079] Figure 7 This is a cross-sectional schematic diagram showing a construction example of structure BS. Additionally, in Figure 7 For simplicity, the top and bottom of the structure BS are shown relative to each other. Figure 3 , Figure 4The diagram shows the inverted state of the structure BS. The structure BS is divided into multiple layers, including a first layer T1 and a second layer T2 disposed above the first layer T1. In each of the first layer T1 and the second layer T2, the structure BS extends in a manner where its width in the Y-axis direction narrows toward the semiconductor layer 37. The number of multiple layers can also be more than two.

[0080] The structure BS has a crystalline conductor 301, an insulating film 302, a crystalline semiconductor film 303, and an insulating film 304.

[0081] In each of the first layer T1 and the second layer T2, the width of the crystalline conductor 301 in a direction substantially parallel to the Y-axis narrows toward the semiconductor layer 37, and extends within the stack 26 in a manner that tapers towards its leading edge relative to a direction substantially parallel to the Z-axis. The crystalline conductor 301 contains germanium. The crystalline conductor 301 may also contain at least one metallic element selected from tungsten and molybdenum. The crystalline conductor 301 preferably does not contain silicon. In the absence of silicon, as described later, a gas without fluorine atoms can be used as a raw material for forming the crystalline conductor 301. Examples of the crystalline conductor 301 include a conductor layer primarily composed of germanium. Here, "primary component" refers to the component with the highest concentration among the constituent elements. Not limited thereto, the crystalline conductor 301 may also be, for example, a stack of a conductor layer primarily composed of germanium and a conductor layer primarily composed of a metallic element.

[0082] An insulating film 302 is disposed between the laminate 26 and the crystalline conductor 301. The insulating film 302 prevents the plurality of conductive layers 31 from being electrically connected to the crystalline conductor 301. The insulating film 302 may contain, for example, silicon and oxygen. Examples of the insulating film 302 include, for example, a silicon oxide film.

[0083] A crystalline semiconductor film 303 is disposed between the insulating film 302 and the crystalline conductor 301. The crystalline semiconductor film 303 is disposed such that it overlaps with the inner bottom surface BT of the slit ST (described later) in the Z-axis direction. The crystalline semiconductor film 303 contains silicon. Examples of the crystalline semiconductor film 303 include polycrystalline silicon films.

[0084] An insulating film 304 is disposed between the side surface of the crystalline semiconductor film 303 and the crystalline conductor 301. The insulating film 304 is in contact with the side surface of the crystalline semiconductor film 303 in a direction substantially parallel to the Y-axis. The insulating film 304 is not disposed between the crystalline semiconductor film 303 and the crystalline conductor 301 in the Z-axis direction. Furthermore, in this embodiment, the insulating film 304, for example, is not disposed between the crystalline semiconductor film 303 and the crystalline conductor 301 in the direction substantially parallel to the Y-axis of the first layer T1, except for the portion that tapers at the leading edge of the second layer T2. The insulating film 304 contains silicon and oxygen. Examples of the insulating film 304 include a silicon oxide film.

[0085] In addition, the crystalline conductor 301 has a crystalline region 301A and a crystalline region 301B.

[0086] Crystalline region 301A contains germanium. Preferably, germanium is the main component of crystalline region 301A. Crystalline region 301A does not contact the insulating film 304 in a direction substantially parallel to the Y-axis, but is in contact with the crystalline semiconductor film 303 in a direction substantially parallel to the Z-axis. Crystalline region 301A may also be in contact with the crystalline semiconductor film 303 in directions substantially parallel to the X-axis and substantially parallel to the Y-axis. Crystalline region 301A may, for example, be polycrystalline.

[0087] Crystallized region 301B is disposed above crystalline region 301A and contacts insulating film 304 in a direction substantially parallel to the Y-axis. Crystallized region 301B contains germanium or at least one metallic element. The at least one metallic element is selected, for example, from tungsten and molybdenum. Crystallized region 301B is preferably composed mainly of germanium or at least one metallic element. Crystallized region 301B may, for example, be polycrystalline.

[0088] Crystallization region 301B may contain at least one element composed of silicon, oxygen, carbon, and nitrogen. The concentration of at least one element is preferably 1 × 10⁻⁶. 20 / cm 3 Above and 1×10 22 / cm 3 Therefore, the Young's modulus can be increased, thereby improving the flexural strength. The concentration of each element can be determined, for example, by energy-dispersive X-ray spectroscopy (EDX). Furthermore, when silicon is contained in the crystalline region 301B, it is preferable that the silicon concentration in the crystalline conductor 301 is lower than the germanium concentration in the crystalline region 301A.

[0089] The interface between crystalline region 301A and crystalline region 301B is sometimes not visually discernible. In such cases, crystalline region 301A and crystalline region 301B can be distinguished, for example, based on differences in composition determined by elemental analysis. This is not a limitation; for example, the portion that connects to the crystalline semiconductor film 303 in a direction substantially parallel to the Y-axis may be designated as crystalline region 301A, and the portion that connects to the insulating film 304 in a direction substantially parallel to the Y-axis may be designated as crystalline region 301B.

[0090] Next, for Figure 3 A manufacturing method for the semiconductor memory device shown will be described. Here, in particular, a series of manufacturing processes related to the formation of the structure BS will be described, and the cross-sectional structure of the array wafer W2 during manufacturing will be shown. Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 . Figures 8 to 13 This is a cross-sectional schematic diagram illustrating an example of a semiconductor memory device manufacturing method. Furthermore, the semiconductor substrate 11, the laminate 26, the interlayer insulating film 21, and other portions of the circuit region 10 and array region 20, such as the memory pillars MP, can be formed using known methods, therefore, descriptions are omitted here.

[0091] like Figure 8 As shown, a slit ST is formed. The slit ST extends through the stack 26 containing the memory pillars MP in a direction generally parallel to the Z-axis. The slit ST divides the stack 26 into multiple memory pillars MP that extend in a manner that tapers along the leading edge of the Z-axis. The slit ST has an inner bottom surface BT and an inner wall surface SW. The slit ST can be formed, for example, by locally etching the stack 26 multiple times in a direction generally parallel to the Z-axis using etching methods such as reactive ion etching (RIE).

[0092] Next, as Figure 9 As shown, an insulating film 302 is formed. The insulating film 302 is formed on the inner bottom surface BT and the inner wall surface SW of the slit ST. The insulating film 302 can be formed, for example, by forming a silicon oxide film using low-pressure chemical vapor deposition (LP-CVD).

[0093] Next, as Figure 10 As shown, a crystalline semiconductor film 303 is formed. The crystalline semiconductor film 303 is formed on the inner bottom surface BT and the inner wall surface SW, separated by an insulating film 302. The crystalline semiconductor film 303 can be formed, for example, by forming a silicon film using LP-CVD.

[0094] Next, as Figure 11 As shown, an insulating film 304 is formed. The insulating film 304 is formed on the crystalline semiconductor film 303 such that it covers at least a portion of a first portion of the crystalline semiconductor film 303 that overlaps with the inner wall surface SW in a direction substantially parallel to the X-axis and in a direction substantially parallel to the Y-axis, and exposes a second portion of the crystalline semiconductor film 303 that overlaps with the inner bottom surface BT in a direction substantially parallel to the Z-axis. A portion of the first portion of the crystalline semiconductor film 303 adjacent to the inner bottom surface BT can be exposed from the insulating film 304. In this embodiment, for example, the crystalline semiconductor film 303 on the side and bottom surfaces of the first layer T1 is exposed from the insulating film 304. Additionally, the crystalline semiconductor film 303 on the side surfaces of the second layer T2 is covered by the insulating film 304. The insulating film 304 can be formed, for example, by forming a silicon oxide film using an ALD (Alternating Deposition) process. The insulating film 304 can cover at least a portion of the first part of the crystalline semiconductor film 303 and expose the second part of the crystalline semiconductor film 303 by adjusting conditions such as pressure, temperature, and time during film formation.

[0095] Next, as Figure 12 As shown, an amorphous body 301a is formed on the second portion of the crystalline semiconductor film 303. The amorphous body 301a is in contact with the crystalline semiconductor film 303 in a direction substantially parallel to the Z-axis. The amorphous body 301a may also be in contact with the crystalline semiconductor film 303 in directions substantially parallel to the X-axis and in directions substantially parallel to the Y-axis. The amorphous body 301a contains germanium. The amorphous body 301a can be formed, for example, by depositing germanium using CVD. The amorphous body 301a may also be composed of multiple particles, for example.

[0096] The germanium-containing amorphous body 301a does not form on the surface of the insulating film 304, which is a silicon oxide film, but only on the surface of the crystalline semiconductor film 303. This is believed to be because the oxygen atoms present on the surface of the silicon oxide film are bonded to silicon atoms, and therefore cannot bond to germanium atoms.

[0097] The amorphous material 301a is preferably formed at a temperature of 300°C or higher and 900°C or lower. This, for example, can suppress the degradation of the insulating film and word lines of the memory cell.

[0098] Amorphous material 301a can also be formed by LP-CVD using GeH4 and an amino compound in the raw materials. This allows for film formation at temperatures, for example, below 900°C.

[0099] The amorphous body 301a is preferably formed in an atmosphere containing hydrogen. This, for example, can improve the embeddability of the amorphous body 301a.

[0100] Next, as Figure 13 As shown, an electrical conductor 301b is formed on top of an amorphous body 301a, and the amorphous body 301a is crystallized to become a crystalline body 301a1, which is then subjected to crystalline growth (epitaxial growth), thereby forming a crystalline conductor with crystalline regions 301A and 301B as shown in the figure. The amorphous body 301a is crystallized, for example, in the environment in which the electrical conductor 301b is formed.

[0101] Electrical conductor 301b is a semiconductor or a conductor. Electrical conductor 301b contains germanium or at least one metallic element. Electrical conductor 301b can, for example, be a metal layer containing tungsten, tungsten carbide, or molybdenum as the main component. Electrical conductor 301b can, for example, be formed by depositing raw materials using CVD.

[0102] When the electrical conductor 301b contains silicon, it is preferably formed by LP-CVD, which, for example, uses at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and a second compound selected from the group consisting of Si2H6, SiH4, SiH2Cl2, SiHCl3, Si2Cl6, SiCl4 and amino compounds containing Si in the raw materials. This allows for film formation with good coverage (step coverage), for example.

[0103] When the electrical conductor 301b contains oxygen, the electrical conductor 301b is preferably formed by LP-CVD, which, for example, uses at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and at least one third compound selected from the group consisting of O2, O3, N2O, NO, and CO in the raw materials. Thus, oxygen can be added, for example, without the parent material becoming an oxide film.

[0104] When the electrical conductor 301b contains nitrogen, the electrical conductor 301b is preferably formed by LP-CVD, which, for example, uses at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and at least one fourth compound selected from the group consisting of NH3, N2O, and NO in the raw materials. Thus, nitrogen can be added, for example, without the parent compound becoming a nitride.

[0105] Then, through chemical dry etching, such as Figure 7 As shown, for example, back etching is performed along a direction approximately parallel to the Z-axis until the surface of the insulating layer 32 is exposed. The above process can form the structure BS.

[0106] As described above, in the method for manufacturing a semiconductor memory device according to this embodiment, an amorphous body 301a is formed on a silicon-containing crystalline semiconductor film 303 at the bottom of the slit ST, an electrical conductor 301b is formed above the amorphous body 301a, and the amorphous body 301a is crystallized to become a crystalline body 301a1, thereby forming a crystalline structure. Figure 7 The crystalline conductor 301 shown has crystalline regions 301A and crystalline regions 301B. This enables the suppression of decreased reliability in semiconductor memory devices.

[0107] The semiconductor memory device of this embodiment is adapted, for example, to form a structure BS in a slit ST with a high aspect ratio.

[0108] Figure 14 This is a cross-sectional schematic diagram used to illustrate a construction example of a conventional BS structure. For example... Figure 14As shown, when the structure BS is divided into a first level T1 and a second level T2, and a lower slit LST corresponding to the first level T1 and an upper slit UST corresponding to the second level T2 are formed, the structure BS is formed by forming an insulating film 302 on the inner wall surfaces of both the lower slit LST and the upper slit UST, and embedding a crystalline conductive material 301 such as silicon on the insulating film 302. The structure BS, for example, has a narrow arcuate shape at both ends in the Z-axis direction, with a width that is approximately parallel to the X-axis or Y-axis. The structure BS does not have a crystalline semiconductor film 303 or an insulating film 304. In this case, the width of the lower slit LST and the upper slit UST sometimes narrows in the direction approximately parallel to the Y-axis as they advance along the depth direction, thus easily generating voids S in the crystalline semiconductor film 303 formed in the lower slit LST. This is believed to be because, since the crystalline semiconductor film 301 is formed starting from the sidewall of the lower slit LST, voids are easily generated near the center of the lower slit LST. Furthermore, because the width of the lower slit LST, the upper slit UST, or the portion of the joint between the lower slit LST and the upper slit UST narrows in a direction approximately parallel to the Y-axis, the area near the entrance of the lower slit LST becomes blocked before the crystalline conductor 301 fills the central area of ​​the lower slit LST. If the continuous length of the void S increases, the bending strength of the crystalline conductor 301 may decrease. For example, when the continuous length of the void S is 2 μm or more, the bending strength decreases by more than 20% compared to when the continuous length of the void S is 0 μm or more but less than 1 μm. This contributes to the reduced reliability of the semiconductor memory device.

[0109] Furthermore, in conventional semiconductor memory devices, a crystalline conductor 301 is typically formed by silicon deposition using CVD. However, fluorine atoms contained in the raw material can easily remain within the voids S. At this time, fluorine atoms diffuse above or below the structure BS, thereby easily damaging, for example, the semiconductor layer 37 located below the structure BS and the interlayer insulating film 21 located above the structure BS. This contributes to the reduced reliability of the semiconductor memory device.

[0110] In contrast, Figure 15 This is a cross-sectional schematic diagram illustrating a structural example of the structure BS in the semiconductor memory device of this embodiment. For example... Figure 15As shown, when a lower slit LST and an upper slit UST are formed in the laminate 26, a crystalline semiconductor film 303 is first formed on the side and bottom surfaces of the insulating film 302 in the first layer T1, and on the side surfaces of the insulating film 302 in the second layer T2. Furthermore, an insulating film 304 is formed on the side surfaces of the insulating film 303 in the second layer T2. Thus, an amorphous body 301a is not formed on the insulating film 304, but is formed on the first layer T1, exposing the silicon-containing crystalline semiconductor film 303. For example, it is formed on the inner bottom surface BT of the slit ST. Then, the amorphous body 301a in contact with the crystalline semiconductor film 303 is crystallized to become a crystalline body 301a1, and its crystal growth is achieved, thereby forming crystalline regions 301A and crystalline regions 301B from the lower slit LST of the slit ST toward the upper slit UST. This reduces or eliminates the void S in the lower slit LST, thereby improving the embedding properties of the crystalline conductor 301. Consequently, it suppresses the decrease in bending strength. Therefore, it suppresses the decrease in the reliability of the semiconductor memory device.

[0111] Furthermore, by crystallizing and growing an amorphous body 301a that replaces silicon and is mainly composed of germanium to form a crystalline conductor 301, a feed gas containing germanium and free of fluorine can be selected, thus preventing damage to the source layer 28 and the interlayer insulating film 21 by fluorine atoms. Therefore, the decrease in the reliability of the semiconductor memory device can be suppressed.

[0112] (The first variation of the BS construct)

[0113] In the above embodiments, examples of crystalline regions 301A and 301B containing germanium have been described, but the structure BS may also have other crystalline regions containing at least one metal element above the crystalline regions containing germanium.

[0114] Figure 16 This is an enlarged schematic diagram showing a cross-section of the first deformed example of the structure BS. (and) Figure 7 Similarly, the structure BS shown is divided into multiple levels, including a first level T1 and a second level T2 disposed above the first level T1. The following will discuss... Figure 7 The different parts of the shown structure BS will be explained. For other parts, appropriate references can be made. Figure 7 Description of the shown construct BS.

[0115] Figure 16 The shown structure BS and Figure 7Compared to the structure BS shown, it differs in at least the following ways: the crystalline conductor 301 has crystalline regions 301A1, crystalline regions 301B1 and crystalline regions 301C1, and the insulating film 304 is in contact with the side of the crystalline semiconductor film 303 in the first layer T1 and the second layer T2.

[0116] Crystalline region 301A1 contains germanium. Preferably, crystalline region 301A1 is predominantly composed of germanium. Crystalline region 301A1 does not contact the insulating film 304 in a direction substantially parallel to the Y-axis, but is in contact with the crystalline semiconductor film 303 in a direction substantially parallel to the Z-axis. Crystalline region 301A1 may also be in contact with the crystalline semiconductor film 303 in directions substantially parallel to the X-axis and substantially parallel to the Y-axis. Crystalline region 301A1 may, for example, be polycrystalline. Further descriptions of crystalline region 301A1 can be appropriately referenced from the description of crystalline region 301A.

[0117] Crystallized region 301B1 is disposed above crystalline region 301A1 in the first layer T1 and is in contact with insulating film 304 in a direction substantially parallel to the Y-axis. Crystallized region 301B1 contains at least one metallic element. The at least one metallic element is selected, for example, from tungsten and molybdenum. Crystallized region 301B1 is preferably composed mainly of at least one metallic element. Crystallized region 301B1 may, for example, be polycrystalline.

[0118] Crystallized region 301C1 is disposed above crystalline region 301B1 in the second layer T2 and is in contact with insulating film 304 in a direction substantially parallel to the Y-axis. Crystallized region 301C1 contains at least one metallic element. The at least one metallic element is selected, for example, from tungsten and molybdenum. Crystallized region 301C1 is preferably composed mainly of at least one metallic element. Crystallized region 301C1 may, for example, be polycrystalline. Crystallized region 301C1 may also have the same metallic element as crystalline region 301B1.

[0119] Crystallized regions 301A1, 301B1, and 301C1 can be formed, for example, in the same manner as in the above-described embodiments, by forming an amorphous body 301a with germanium as the main component on a silicon-containing crystalline semiconductor film 303, forming an electrical conductor 301b with at least one of the above-described metal elements as the main component on top of the amorphous body 301a, and crystallizing the amorphous body 301a to become a crystalline body 301a1, thereby allowing it to crystallize and grow (epitaxial growth).

[0120] As described above, the second variation of the structure BS can reduce the resistance of the crystalline conductor 301 by having crystalline regions 301B1 and 301C1 containing metallic elements above the crystalline region 301A1.

[0121] Furthermore, in the first layer T1 and the second layer T2, the insulating film 304 is in contact with the side of the crystalline semiconductor film 303, so that at the portion where the crystalline semiconductor film 303 overlaps with the insulating film 304 in a direction approximately parallel to the Y-axis, the germanium-based amorphous material 301a will not form on the insulating film 304. Therefore, when the amorphous material 301a is crystallized to become a crystalline material 301a1 and crystal growth (epitaxy growth) is performed, crystal growth will not proceed at the portion where the crystalline semiconductor film 303 overlaps with the insulating film 304 in a direction approximately parallel to the Y-axis, thus crystal growth can be easily performed from the crystalline material 301a1.

[0122] (Second variation of the BS construct)

[0123] Figure 17 This is an enlarged schematic diagram of a cross-section showing a second modified example of the structure BS. In this second modified example of the structure BS, at least the following differences exist: the insulating film 304 has a gap G at the seam between the first layer T1 and the second layer. At the gap G, the insulating film 304 is not formed, and the crystalline semiconductor film 303 contacts the crystalline conductor 301. Hereinafter, [the following will discuss the...] Figure 7 The different parts of the shown structure BS will be explained. For other parts, appropriate references can be made. Figure 7 Description of the shown construct BS.

[0124] The gap G is provided, for example, near the entrance of the first layer T1. For example, at the seam between the first layer T1 and the second layer, the width of the slit ST in the second layer T2 in the direction approximately parallel to the Y-axis is narrower than the width of the slit ST in the first layer T1 in the direction approximately parallel to the Y-axis, making it difficult to form the insulating film 304, and thus sometimes forming the gap G. However, even when the gap G is formed, at the seam between the first layer T1 and the second layer, the width of the slit ST in the second layer T2 in the direction approximately parallel to the Y-axis is narrower than the width of the slit ST in the first layer T1 in the direction approximately parallel to the Y-axis, making it difficult to form an amorphous substance 301a on the crystalline semiconductor film 303 facing the gap G. Therefore, in the second variation of the structure BS, by connecting the insulating film 304 to a portion of the side surface of the crystalline semiconductor film 303 in the second layer T2, when the amorphous body 301a is crystallized to become a crystalline body 301a1 and crystal growth (epitaxial growth) is performed, crystal growth will not proceed at the portion of the crystalline semiconductor film 303 that overlaps with the insulating film 304 in a direction approximately parallel to the Y-axis. Therefore, crystal growth can be easily performed from the crystalline body 301a1.

[0125] (The third variation of the BS construct)

[0126] In the above embodiments, an example of a structure BS being divided into multiple layers including a first level T1 and a second level T2 has been described, but the structure BS may also not have multiple levels.

[0127] Figure 18 This is a cross-sectional schematic diagram used to illustrate a construction example of a conventional BS structure. For example... Figure 18 As shown, in the case where the structure BS does not have multiple layers, the structure BS is formed by forming an insulating film 302 on the inner wall surface of the slit ST and embedding a crystalline conductor 301 such as silicon on the insulating film 302. The structure BS does not have a crystalline semiconductor film 303 or an insulating film 304. In this case, the slit ST sometimes narrows in width in a direction approximately parallel to the Y-axis as it advances along the depth direction, thus easily generating voids S within the crystalline semiconductor film 303 formed in the slit ST. This is believed to be because, since the crystalline semiconductor film 303 is formed from the side wall surface of the slit ST, voids are easily generated near the center of the slit ST, and because the width narrows near the entrance of the slit ST, the entrance is blocked before being embedded near the center of the slit ST.

[0128] Furthermore, in conventional semiconductor memory devices, a crystalline conductor 301 is typically formed by silicon deposition using CVD. However, fluorine atoms contained in the raw material can easily remain within the voids S. At this time, fluorine atoms diffuse above or below the structure BS, thereby easily damaging, for example, the source layer 28 located below the structure BS and the interlayer insulating film 21 located above the structure BS. This contributes to the reduced reliability of the semiconductor memory device.

[0129] In contrast, Figure 19 This is a cross-sectional schematic diagram illustrating a structural example of the structure BS in the semiconductor memory device of this embodiment. For example... Figure 19 As shown, in the slit ST, with Figure 7Similarly, the structure BS shown includes a crystalline semiconductor film 303 connected to the side of the insulating film 302, an insulating film 304 connected to the crystalline semiconductor film 303 in a direction approximately parallel to the Y-axis, an amorphous body 301a connected to the crystalline semiconductor film 303 in the Z-axis direction, an electrical conductor 301b formed above the amorphous body 301a, and crystallized to become a crystalline body 301a1, which is then allowed to grow (epitaxial growth), thereby forming crystalline regions 301A and crystalline regions 301B. Thus, by forming the crystalline semiconductor film 303 on the inner bottom surface of the slit ST, the amorphous body 301a connected to the crystalline semiconductor film 303 can be crystallized to become a crystalline body 301a1, and its crystallization growth can be allowed, thereby reducing or eliminating the void S, thus improving the embedding properties of the crystalline conductor 301 in the slit ST. This, in turn, can suppress the reduction in bending strength. Therefore, it can suppress the decrease in the reliability of semiconductor memory devices.

[0130] Furthermore, by crystallizing the amorphous body 301a, which replaces silicon and is mainly composed of germanium, into a crystalline body 301a1, and then growing it to form a crystalline conductor 301, a fluorine-free feed gas can be selected, thus preventing damage to the source layer 28 and the interlayer insulating film 21 by fluorine atoms. Therefore, it is possible to suppress the decrease in the reliability of the semiconductor memory device. Further descriptions of the third variation of the structure BS can be appropriately referenced from the description of the above embodiments.

[0131] In addition, the first, second, and third variations can be appropriately combined.

[0132] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0133] [Explanation of reference numerals in the attached figures]

[0134] 1: Memory cell array, 2: Command register, 3: Address register, 4: Sequencer, 5: Driver, 6: Line decoder, 7: Sensing amplifier, 10: Circuit area, 11: Semiconductor substrate, 12: Transistor, 12a: Gate insulating film, 12b: Gate electrode, 13: Interlayer insulating film, 14: Contact plug, 15: Wiring layer, 15a: Wiring layer, 15b: Wiring layer, 16: Via plug, 17: Metal pad, 20: Array area, 21: Interlayer insulating film, 22: Metal pad, 23: Via plug, 24: Wiring layer, 24a: Wiring layer, 25: Contact plug, 26: Stack-up, 28: Source layer, 29: Insulating film, 31: Conductive layer, 32: Insulating layer, 37: Semiconductor layer, 38: Metal layer, 42: Step structure, 43: Contact plug, 44: Word wiring layer, 45: Through-hole plug, 46: Metal pad, 47: Passivation film, 201: Barrier insulating film, 202: Charge storage film, 203: Tunnel insulating film, 204: Semiconductor layer, 205: Core insulating layer, 206: Cap layer, 301: Crystalline conductor, 301A: Crystalline region, 301A1: Crystalline region 301B: Crystalline region, 301B1: Crystalline region, 301C1: Crystalline region, 301a: Amorphous body, 301a1: Crystalline body, 301b: Electrical conductor, 302: Insulating film, 303: Crystalline semiconductor film, 304: Insulating film, BS: Structure, BT: Inner bottom surface, CA: Column address, CLE: Command latch enable signal, CMD: Command signal, DAT: Write data, DAT: Read data, DAT: Write data signal, G: Gap, I / O: Input / output signal, I / O: Signal, LST: Lower slit MC: Memory cell, MP: Memory column, MT: Memory transistor, NS: NAND string, P: Opening, PA: Page address, RBn: Ready / Busy signal, REn: Read enable signal, S: Gap, SGD: Select gate line, SGS: Select gate line, SL: Source line, ST: Slit, ST1: Select transistor, ST2: Select transistor, SU: String cell, SW: Inner wall, T1: First level, T2: Second level, UST: Top slit, W1: Circuit wafer, W2: Array wafer, WEn: Write enable signal, WL: Word line.

Claims

1. A semiconductor memory device comprising: A laminate having a conductive layer and an insulating layer, wherein the conductive layer and the insulating layer are alternately stacked in a first direction; Multiple storage columns extend along the first direction within the stack; as well as A structure that divides the plurality of storage columns and extends within the stack along the first direction. The construct has: A crystalline conductor extending along the first direction within the laminate; A first insulating film is disposed between the laminate and the crystalline conductor; A crystalline semiconductor film disposed between the crystalline conductor and the first insulating film, and containing silicon; as well as A second insulating film, disposed between the crystalline semiconductor film and the side surface of the crystalline conductor, contains silicon and oxygen. The crystalline conductor has: A first crystalline region, which is in contact with the crystalline semiconductor film, and contains germanium; as well as The second crystallization region is disposed above the first crystallization region and is in contact with the second insulating film in a second direction perpendicular to the first direction.

2. The semiconductor memory device according to claim 1, wherein, The structure is divided into multiple levels, including a first level and a second level disposed above the first level. The crystalline semiconductor film is disposed between the crystalline conductor and the first insulating film in the first and second layers. The first crystalline region is in contact with the crystalline semiconductor film in the first layer.

3. The semiconductor memory device according to claim 1, wherein, The second insulating film is not disposed between the crystalline semiconductor film and the crystalline conductor in the first direction.

4. The semiconductor memory device according to claim 1, wherein, The second crystalline region contains germanium.

5. The semiconductor memory device according to claim 1, wherein, The second crystalline region contains at least one metallic element selected from the group consisting of tungsten and molybdenum.

6. The semiconductor memory device according to claim 1, wherein, The second crystalline region contains at least one element composed of silicon, oxygen, carbon, and nitrogen. The concentration of at least one element in the second crystalline region is 1 × 10⁻⁶. 20 / cm 3 Above and 1×10 22 / cm 3 the following.

7. The semiconductor memory device according to claim 1, wherein, The silicon concentration in the crystalline conductor is lower than the germanium concentration in the first crystalline region.

8. A method for manufacturing a semiconductor memory device, wherein, A slit is formed that divides a plurality of storage pillars extending along a first direction within the laminate, the lamination having an inner bottom surface and an inner wall surface, the laminate having a conductive layer and an insulating layer, the conductive layer and the insulating layer being alternately stacked in the first direction. A first insulating film is formed on the inner bottom surface and the inner wall surface. A crystalline semiconductor film containing silicon is formed and disposed on the first insulating film. A second insulating film containing silicon and oxygen is formed on the crystalline semiconductor film in such a manner that at least a portion of the first portion of the crystalline semiconductor film overlapping the inner wall surface in a second direction perpendicular to the first direction is covered, and the second portion of the crystalline semiconductor film overlapping the inner bottom surface in the first direction is exposed. An amorphous body containing germanium is formed on the inner bottom surface in contact with the crystalline semiconductor film. An electrical conductor containing germanium or a metallic element is formed above the amorphous body within the slit, and the amorphous body is crystallized to become a crystalline body. The crystalline body is then allowed to grow crystals, thereby forming a crystalline conductor having a first crystalline region and a second crystalline region. The first crystalline region contains germanium, and the second crystalline region is disposed above the first crystalline region and is connected to the second insulating film in the second direction.

9. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The amorphous body is formed at a temperature above 300°C and below 900°C.

10. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The amorphous body is formed by low-pressure chemical vapor deposition using GeH4 and amino compounds in the raw materials.

11. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The amorphous body is formed in an atmosphere containing hydrogen.

12. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The electrical conductor contains the germanium.

13. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The electrical conductor contains at least one element composed of silicon, oxygen, carbon, and nitrogen. The concentration of at least one element in the electrical conductor is 1×10⁻⁶. 20 / cm 3 Above and 1×10 22 / cm 3 the following.

14. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The electrical conductor contains silicon. The electrical conductor is formed by low-pressure chemical vapor deposition using a raw material containing at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and a second compound selected from the group consisting of Si2H6, SiH4, SiH2Cl2, SiHCl3, Si2Cl6, SiCl4 and amino compounds containing Si.

15. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The electrical conductor contains oxygen. The electrical conductor is formed by low-pressure chemical vapor deposition using a raw material containing at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and at least one third compound selected from the group consisting of O2, O3, N2O, NO and CO.

16. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The electrical conductor contains nitrogen. The electrical conductor is formed by low-pressure chemical vapor deposition using raw materials containing at least one first compound selected from the group consisting of GeH4 and amino compounds containing Ge, and at least one fourth compound selected from the group consisting of NH3, N2O, and NO.

17. The method for manufacturing a semiconductor memory device according to claim 8, wherein, The electrical conductor contains tungsten, tungsten carbide, or molybdenum.

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