Semiconductor memory device and substrate unit

Abstract

A semiconductor storage device according to one embodiment of the present application includes a first substrate and a second substrate. The first substrate includes a first portion, a second portion thinner than the first portion, and a plurality of first conductive portions provided in the second portion. The second substrate includes a plurality of second conductive portions. The plurality of second conductive portions overlap the plurality of first conductive portions when viewed in a first direction that is a thickness direction of the first substrate. The plurality of second conductive portions are respectively connected to the plurality of first conductive portions by solder.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices and substrate units. Background Technology

[0002] A semiconductor storage device is known to have a housing, a substrate housed in the housing, and a semiconductor memory disposed on the substrate. Summary of the Invention

[0003] One embodiment of a semiconductor memory device includes a first substrate and a second substrate. The first substrate has a first portion, a second portion thinner than the first portion, and a plurality of first conductive portions disposed in the second portion. The second substrate has a plurality of second conductive portions. When viewed from the thickness direction of the first substrate, i.e., a first direction, the plurality of second conductive portions overlap with the plurality of first conductive portions. The plurality of second conductive portions are respectively connected to the plurality of first conductive portions by solder. Attached Figure Description

[0004] Figure 1 This is a perspective view of a semiconductor memory device according to the first embodiment.

[0005] Figure 2 This is a perspective view showing a partial exploded view of the semiconductor memory device according to the first embodiment.

[0006] Figure 3 This is a perspective view showing a partial exploded view of the substrate of the first embodiment.

[0007] Figure 4 This is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment.

[0008] Figure 5 This is a perspective view showing the connection structure between the first substrate and the second substrate in the first embodiment.

[0009] Figure 6 This is an enlarged view showing the connection structure between the first substrate and the second substrate in the first embodiment.

[0010] Figure 7 This is an enlarged view showing the connection structure between the first substrate and the second substrate in the first embodiment.

[0011] Figure 8A This is a top view used to illustrate the visual inspection method of the first embodiment.

[0012] Figure 8B This is a top view used to illustrate the visual inspection method of the first embodiment.

[0013] Figure 8CThis is a top view used to illustrate the visual inspection method of the first embodiment.

[0014] Figure 8D This is a top view used to illustrate the visual inspection method of the first embodiment.

[0015] Figure 9 This is a cross-sectional view used to illustrate the electrical inspection method of the first embodiment.

[0016] Figure 10 This is a cross-sectional view showing a portion of a semiconductor memory device according to a first variation of the first embodiment.

[0017] Figure 11 This is a cross-sectional view showing a portion of a semiconductor memory device according to a second variation of the first embodiment.

[0018] Figure 12 This is a cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.

[0019] Figure 13 This is a diagram showing an exploded view of a portion of the semiconductor memory device according to the third embodiment.

[0020] Figure 14 This is a diagram showing a portion of a semiconductor memory device according to a third embodiment.

[0021] Figure 15 This is a diagram showing an exploded view of a portion of the semiconductor memory device according to the fourth embodiment.

[0022] Figure 16 This is a diagram showing a portion of a semiconductor memory device according to a fourth embodiment.

[0023] Explanation of symbols

[0024] 1: Semiconductor memory device; 10: Housing; 17: Fixing part; 18: Fixing part; 20: Substrate unit; 21: Substrate; 21h, 21hS: Fixing hole; 23: Controller; 24: DRAM; 25: NAND (semiconductor memory); 26: Power control component; 27: Capacitor; 30: First substrate; 31: First part; 32: Second part; 32h: Fixing hole (first hole); 40: Second substrate; 41: Third part; 42: Fourth part; 42h: Fixing hole (second hole); 50: Pad (first conductive part); 60: Pad (second conductive part); 60h: Through hole; 61: First part; 62: Second part; S: Solder connection part; M1: First material; M2: Second material; FS: Fastening component. Detailed Implementation

[0025] Hereinafter, the semiconductor memory device and substrate unit according to embodiments will be described with reference to the accompanying drawings. In the following description, structures having the same or similar functions are labeled with the same symbols. Furthermore, repeated descriptions of these structures are sometimes omitted.

[0026] In this application, terms are defined as follows: "Connection" is not limited to mechanical connections but can include electrical connections. That is, "connection" is not limited to the case where two elements are directly connected, but can include cases where two elements are connected by sandwiching other elements between them. "Facing" or "overlapping" refers to the virtual projections of two objects overlapping each other when viewed from a specific direction. That is, "facing" or "overlapping" is not limited to the case where two objects directly face each other, but can include cases where two objects face each other with other components or gaps between them. "Parallel," "orthogonal," or "identical" can respectively include cases of "approximately parallel," "approximately orthogonal," or "approximately identical."

[0027] In this application, the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction, -X direction, +Y direction, and -Y direction are directions parallel to the first surface 21a of the substrate 21 described later (see reference). Figure 2 The +X direction is from the first end 21e1 of the substrate 21 toward the second end 21e2 (refer to...). Figure 2 The -X direction is the direction opposite to the +X direction. Without distinguishing between the +X and -X directions, it is simply referred to as the "X direction". The +Y and -Y directions are directions that intersect (e.g., are orthogonal) the X direction. The +Y direction is the direction from the first sidewall 13 of the housing 10 (described later) toward the second sidewall 14 (see reference). Figure 2 The -Y direction is the direction opposite to the +Y direction. Without distinguishing between the +Y and -Y directions, it is simply referred to as the "Y direction". The +Z and -Z directions are directions that intersect (e.g., are orthogonal) the X and Y directions. The +Z direction is the direction from the first surface 21a of the substrate 21 towards the second surface 21b (see reference). Figure 2 The -Z direction is the opposite direction to the +Z direction. Without distinguishing between the +Z and -Z directions, it is simply referred to as the "Z direction". The Z direction is the thickness direction of the substrate 21. The Z direction is an example of a "first direction". The -Z direction side is an example of a "first side". The +Z direction side is an example of a "second side". The X direction is an example of a "second direction".

[0028] (First Implementation)

[0029] <1. Overall Structure of Semiconductor Memory Devices>

[0030] First, the semiconductor storage device 1 according to the first embodiment will be described. The semiconductor storage device 1 is, for example, a storage device such as an SSD (Solid State Drive). The semiconductor storage device 1 is connected to a host device and serves as the storage device for the host device. The host device is a personal computer, mobile device, video recorder, or vehicle-mounted device, etc., but is not limited to these examples.

[0031] Figure 1 This is a perspective view of a semiconductor memory device 1. The semiconductor memory device 1, for example, has a housing 10 and a substrate unit 20.

[0032] <1.1 Shell>

[0033] The housing 10 is a component that houses the substrate unit 20. The housing 10 is, for example, a metal component formed in a cylindrical shape. The housing 10 has, for example, a first main wall 11, a second main wall 12, a first side wall 13, and a second side wall 14.

[0034] Figure 2 This is a perspective view showing a partial exploded view of the semiconductor memory device 1. The first main wall 11 is a plate-shaped wall along both the X and Y directions. The first main wall 11 faces the substrate unit 20 from the -Z direction. The second main wall 12 is a plate-shaped wall along both the X and Y directions. The second main wall 12 is located on the opposite side of the first main wall 11 relative to the substrate unit 20. The second main wall 12 faces the substrate unit 20 from the +Z direction.

[0035] The first sidewall 13 is a plate-shaped wall along the X and Z directions. The first sidewall 13 faces the substrate unit 20 from the -Y direction. The second sidewall 14 is a plate-shaped wall along the X and Z directions. The second sidewall 14 is located on the opposite side of the first sidewall 13 relative to the substrate unit 20. The second sidewall 14 faces the substrate unit 20 from the +Y direction.

[0036] In this embodiment, a base member 10MA is formed from a first main wall 11. On the other hand, a cover member 10MB is formed from a second main wall 12, a first side wall 13, and a second side wall 14. In this embodiment, a cylindrical housing 10 is formed by combining the base member 10MA and the cover member 10MB. Furthermore, the shape of the housing 10 is not limited to the example described above.

[0037] like Figure 2As shown, the first main wall 11 has a plurality of fixing portions 17. The fixing portions 17 are for fixing the substrate 21 (described later) to the housing 10. The plurality of fixing portions 17 are arranged separately in the X and Y directions along the outline of the substrate 21. Each fixing portion 17 protrudes from the first main wall 11 in the +Z direction. Each fixing portion 17 has a fixing hole 17h for inserting a fastening member FS. The fixing hole 17h is, for example, a through hole without a threaded groove. The fixing hole 17h penetrates the first main wall 11 and the fixing portion 17 in the Z direction.

[0038] The second main wall 12 has a plurality of fixing portions 18. The fixing portions 18 are for fixing the substrate 21 to the housing 10. The plurality of fixing portions 18 are arranged separately along the outline of the substrate 21 in the X and Y directions. The plurality of fixing portions 18 are positioned to overlap with a plurality of fixing portions 17 in a one-to-one relationship when viewed from the Z direction. Each fixing portion 18 protrudes from the second main wall 12 in the -Z direction. Each fixing portion 18 has a fixing hole 18h for inserting a fastening member FS. The fixing hole 18h is, for example, a locking hole with a threaded groove. Furthermore, the shapes of the fixing portions 17 and 18 are not limited to the examples described above. For example, the fixing hole 18h of the fixing portion 18 may also be a through hole without a threaded groove. The fixing hole 17h of the fixing portion 17 may also be a locking hole with a threaded groove.

[0039] <1.2 Substrate Unit>

[0040] Next, the substrate unit 20 will be described. The substrate unit 20 is an assembly in which components including circuitry are mounted. The substrate unit 20 includes, for example, a substrate 21, a connector 22, a controller 23, one or more DRAM (Dynamic Random Access Memory) 24, multiple NAND flash memory 25 (hereinafter referred to as "NAND 25"), a power control component 26, and multiple capacitors 27.

[0041] Substrate 21 is a board component along the X and Y directions. Substrate 21 is a printed wiring board. Substrate 21 includes an insulating substrate and a wiring pattern disposed on the insulating substrate. Substrate 21 has a first surface 21a and a second surface 21b located on the side opposite to the first surface 21a. The first surface 21a and the second surface 21b are surfaces along the X and Y directions, respectively. The first surface 21a is the surface facing the -Z direction. The second surface 21b is the surface facing the +Z direction.

[0042] The substrate 21 has a first end 21e1 and a second end 21e2 as its long side (X direction) end. The first end 21e1 is the end of the substrate 21 on the -X direction side. The second end 21e2 is the end of the substrate 21 on the +X direction side. For example, the substrate 21 has a uniform thickness throughout. Furthermore, details of the substrate 21 will be described later.

[0043] Connector 22 is a connection portion capable of connecting to a connector of a host device. Connector 22 includes a plurality of metal terminals 22a capable of connecting to a connector of a host device. Connector 22 is, for example, disposed at a first end 21e1 of substrate 21. Connector 22 passes through an opening 10a in housing 10 (see reference). Figure 1 It is exposed to the outside of the housing 10.

[0044] The controller 23 is a component that provides unified control over the entire semiconductor memory device 1. The controller 23 is a semiconductor package. The semiconductor package includes, for example, a System on a Chip (SoC) that integrates host interface circuitry for the host device and control circuitry for controlling multiple NAND flash memory 25s onto a single semiconductor chip. The controller 23 is, for example, disposed on the second surface 21b of the substrate 21.

[0045] In this embodiment, for example, high-speed signals are transmitted between connector 22 and controller 23. High-speed signals are, for example, signals conforming to communication interface standards such as PCIe (PCI Express) (registered trademark) or SATA (Serial Advanced Technology Attachment).

[0046] DRAM 24 is a data buffer that temporarily stores write data received from the host device or read data read from NAND 25. There can be one or more DRAM 24s. Alternatively, DRAM 24 can be integrated into the controller 23 as part of the controller 23, rather than being a separate component from the controller 23.

[0047] NAND 25 is a semiconductor package that includes a non-volatile semiconductor memory chip. Multiple NAND 25s may include, for example, multiple NAND 25s disposed on a first surface 21a of substrate 21 and multiple NAND 25s disposed on a second surface 21b of substrate 21. NAND 25 is an example of a "semiconductor memory". Furthermore, the term "semiconductor memory" as used in this application is not limited to NAND 25, and may also refer to other types of semiconductor memory such as NOR memory, MRAM (Magnetoresistive Random Access Memory), or resistive variable memory.

[0048] Power control component 26 controls the power supply to controller 23, DRAM 24, and multiple NAND 25. Power control component 26 may be, for example, a semiconductor package integrating multiple power circuits required to supply power to controller 23, DRAM 24, or NAND 25 into a single semiconductor chip. Power control component 26 may receive power from the outside via connector 22 and distribute the received power within substrate cell 20. Power control component 26 may be, for example, a PMIC (Power Management IC).

[0049] Capacitor 27 serves as a power backup for data protection in the event of an unexpected power outage. In the event of an unexpected power outage from the host device, capacitor 27 supplies power to controller 23, multiple DRAMs 24, and multiple NAND 25 for a certain period of time.

[0050] <2. Substrate Segmentation Structure>

[0051] Next, the segmentation structure of the substrate 21 will be described.

[0052] <2.1 Overview of the First and Second Substrates>

[0053] Figure 3 This is a perspective view showing a partial exploded view of the substrate 21. In this embodiment, the substrate 21 is divided into a first substrate 30 and a second substrate 40, for example, according to various purposes required for the substrate 21. In this embodiment, the materials of the first substrate 30 and the second substrate 40 are different depending on the purpose.

[0054] The first substrate 30 is a printed wiring board. The first substrate 30 includes an insulating substrate and a wiring pattern disposed on the insulating substrate. The first substrate 30 is, for example, a substrate intended to reduce transmission loss of high-speed signals. The first substrate 30, as the insulating substrate, includes a first material M1 (refer to...) which is a low-loss material. Figure 6 The first material M1 is a material whose dielectric constant and dielectric loss tangent are at least smaller than those of the second material M2, which will be described later. The first material M1 is, for example, a fluorinated resin. However, the first material M1 is not limited to the examples described above.

[0055] In this embodiment, connector 22, controller 23, DRAM 24, and multiple NAND 25 are disposed on first substrate 30. First substrate 30, for example, has signal lines 30p for transmitting high-speed signals. In this application, "high-speed signal" refers to, for example, a signal conforming to communication interface standards such as PCIe or SATA, as described above. However, the "high-speed signal" used in this application is not limited to the examples described above. "High-speed signal" can be, for example, a signal related to data writing or data reading. "High-speed signal" can be, for example, any signal faster than the signal sent from the power control component 26 described later. First substrate 30 is, for example, a 16-layer multilayer substrate. First substrate 30 includes 16 conductive layers 30c stacked in the Z direction (see reference). Figure 6 ).

[0056] The second substrate 40 is a printed wiring board. The second substrate 40 includes an insulating substrate and a wiring pattern disposed on the insulating substrate. The second substrate 40 is a substrate designed to reduce the cost of substrate 21. The second substrate 40, as the insulating substrate, includes a second material M2 (refer to...) which is a general material. Figure 6 The second material M2 is a material that is cheaper than the first material M1. The second material M2 is, for example, glass epoxy resin or phenolic resin. However, the second material M2 is not limited to the examples described above.

[0057] In this embodiment, a power control component 26 and a plurality of capacitors 27 are disposed on a second substrate 40. The second substrate 40, for example, has a signal line 40p for transmitting a non-high-speed signal. In this application, a "non-high-speed signal" is a signal related to power supply. For example, a "low-speed signal" is a signal transmitted from the power control component 26. The second substrate 40 is, for example, a double-layer through-substrate. The second substrate 40 includes two conductive layers 40c stacked in the Z direction (see reference). Figure 6 The number of layers of the conductive layer 40c of the second substrate 40 is different from the number of layers of the conductive layer 30c of the first substrate 30. For example, the number of layers of the conductive layer 40c of the second substrate 40 is less than the number of layers of the conductive layer 30c of the first substrate 30.

[0058] <2.2 Cross-sectional shape of the first substrate>

[0059] Figure 4 This is a cross-sectional view showing a portion of the semiconductor memory device 1. The first substrate 30 includes, for example, a first portion 31 and a second portion 32.

[0060] (Part 1)

[0061] The thickness T31 in the Z direction of the first portion 31 is the same as the thickness T21 in the Z direction of the substrate 21. The first portion 31 has a first surface 31a and a second surface 31b. The first surface 31a and the second surface 31b are surfaces along the X direction and the Y direction, respectively. The first surface 31a is the surface facing the -Z direction. The first surface 31a forms a portion of the first surface 21a of the substrate 21. On the other hand, the second surface 31b is the surface facing the +Z direction. The second surface 31b forms a portion of the second surface 21b of the substrate 21.

[0062] (Part Two)

[0063] The second portion 32 is located on the +X direction side relative to the first portion 31. The second portion 32 has a Z-direction step difference 30s with the first portion 31. The second portion 32 is thinner than the first portion 31. That is, the Z-direction thickness T32 of the second portion 32 is less than the Z-direction thickness T31 of the first portion 31. In this embodiment, the second portion 32 is located offset towards the -Z direction side from the center C1 in the Z direction relative to the first portion 31. The second portion 32 is formed, for example, by cutting a portion of the second substrate 40 through machining or laser processing. However, the manufacturing method of the second portion 32 is not limited to the above example.

[0064] The second part 32 has a first surface 32a and a second surface 32b. The first surface 32a and the second surface 32b are surfaces along the X and Y directions, respectively. The first surface 32a is a surface facing the -Z direction. In this embodiment, the first surface 32a is located on the same plane as the first surface 31a of the first part 31. The first surface 32a forms a part of the first surface 21a of the substrate 21. Electronic components can also be mounted on the first surface 32a. On the other hand, the second surface 32b is a surface facing the +Z direction. The second surface 32b is located at a different height than the second surface 31b of the first part 31. The aforementioned step difference 30s exists between the second surface 32b and the second surface 31b of the first part 31.

[0065] <2.3 Cross-sectional shape of the second substrate>

[0066] The second substrate 40 includes, for example, a third portion 41 and a fourth portion 42.

[0067] (Part Three)

[0068] The thickness T41 in the Z direction of the third portion 41 is the same as the thickness T21 in the Z direction of the substrate 21. The third portion 41 has a first surface 41a and a second surface 41b. The first surface 41a and the second surface 41b are surfaces along the X direction and the Y direction, respectively. The first surface 41a is a surface facing the -Z direction. The first surface 41a is located on the same plane as the first surface 31a of the first portion 31 and the first surface 32a of the second portion 32. The first surface 41a forms a portion of the first surface 21a of the substrate 21. In this embodiment, the first surface 21a of the substrate 21 is formed by the first surface 31a of the first portion 31, the first surface 32a of the second portion 32, and the first surface 41a of the third portion 41. On the other hand, the second surface 41b is a surface facing the +Z direction. The second surface 41b is located on the same plane as the second surface 31b of the first portion 31. The second surface 41b forms a portion of the first surface 21a of the substrate 21.

[0069] (Part Four)

[0070] The fourth portion 42 is located on the -X direction side relative to the third portion 41. When viewed from the Z direction, the fourth portion 42 overlaps with the second portion 32 of the first substrate 30. The fourth portion 42 has a Z-direction step 40s with the third portion 41. The fourth portion 42 is thinner than the third portion 41. That is, the Z-direction thickness T42 of the fourth portion 42 is less than the Z-direction thickness T41 of the third portion 41. In this embodiment, the fourth portion 42 is located at a position offset towards the +Z direction side relative to the center C2 of the third portion 41 in the Z direction.

[0071] The fourth portion 42 has a first surface 42a and a second surface 42b. The first surface 42a and the second surface 42b are surfaces along the X and Y directions, respectively. The first surface 42a faces the -Z direction. The first surface 42a is located at a different height than the first surface 41a of the third portion 41. There is the aforementioned step difference 40s between the first surface 42a and the first surface 41a of the third portion 41. The first surface 42a faces the second surface 32b of the second portion 32 of the first substrate 30 from the Z direction. On the other hand, the second surface 42b faces the +Z direction. The second surface 42b is located on the same plane as the second surface 31b of the first portion 31 and the second surface 41b of the third portion 41. The second surface 42b forms a part of the second surface 21b of the substrate 21. Electronic components can also be mounted on the second surface 42b. In this embodiment, the second surface 21b of the substrate 21 is formed by the second surface 31b of the first portion 31, the second surface 41b of the third portion 41, and the second surface 42b of the fourth portion 42.

[0072] <3. Connection structure of the first substrate and the second substrate>

[0073] Next, the connection structure between the first substrate 30 and the second substrate 40 will be described.

[0074] <3.1 First Conductor>

[0075] Figure 5 This is an exploded perspective view showing the connection structure between the first substrate 30 and the second substrate 40. In this embodiment, the first substrate 30 has a plurality of (e.g., eight) pads 50. The plurality of pads 50 are disposed on the second surface 32b of the second portion 32 of the first substrate 30 and exposed to the outside of the first substrate 30. The plurality of (e.g., eight) pads 50 are arranged, for example, at intervals in the Y direction. Each pad 50 is a metal foil (e.g., copper foil) disposed on the second surface 32b. The pad 50 is an example of a "first conductive portion".

[0076] In this embodiment, each pad 50 has a first portion 51 and a second portion 52. The first portion 51 and the second portion 52 are spaced apart in the X direction. The first portion 51 and the second portion 52 are respectively formed, for example, into a rectangular shape along the X direction. The first portion 51 and the second portion 52 are connected via a conductive layer 30c in the first substrate 30 (see reference). Figure 6 They are electrically connected to each other. Alternatively, the first portion 51 and the second portion 52 may not be electrically connected in the first substrate 30. In addition, the pad 50 may be formed as a single conductor portion consisting of the first portion 51 and the second portion 52, instead of the structure that is divided into the first portion 51 and the second portion 52.

[0077] <3.2 Second Conductor>

[0078] In this embodiment, the second substrate 40 has a plurality of (e.g., eight) pads 60. The plurality of pads 60 are disposed on the surface of a fourth portion 42 of the second substrate 40 (e.g., first surface 42a and second surface 42b) and exposed to the outside of the second substrate 40. The plurality of (e.g., eight) pads 60 are arranged, for example, at intervals in the Y direction. At least a portion of each pad 60 is a metal foil (e.g., copper foil) disposed on the surface of the second substrate 40 (e.g., first surface 42a and second surface 42b). When viewed from the Z direction, the plurality of pads 60 overlap with a plurality of pads 50 in a one-to-one relationship. The pads 60 are an example of a "second conductive portion".

[0079] Figure 6 This is an enlarged view showing the connection structure between the first substrate 30 and the second substrate 40. Figure 6This indicates the state before the first substrate 30 and the second substrate 40 are connected. In this embodiment, each pad 60 has a through hole 60h, a first portion 61, and a second portion 62. The through hole 60h is provided at the center of the pad 60. The through hole 60h penetrates the second substrate 40 in the Z direction. The through hole 60h is an elongated hole with its long side in the X direction. The through hole 60h has a first end portion 60ha located on the -X direction side and a second end portion 60hb located on the +X direction side.

[0080] The first portion 61 and the second portion 62 are disposed separately on opposite sides of the through hole 60h in the X direction. For example, the first portion 61 is disposed adjacent to the first end 60ha of the through hole 60h. The second portion 62 is separate from the first portion 61 and disposed adjacent to the second end 60hb of the through hole 60h. The first portion 61 and the second portion 62 are not electrically connected to each other in the second substrate 40. That is, the first portion 61 and the second portion 62 are insulated from each other in the second substrate 40.

[0081] The first part 61, for example, has a first metal part 61a, a second metal part 61b, and a third metal part 61c. The first metal part 61a is a metal foil disposed on the first surface 42a of the fourth part 42. The second metal part 61b is a metal foil disposed on the second surface 42b of the fourth part 42. The third metal part 61c is a metal foil disposed on the inner surface of the first end portion 60ha of the through hole 60h. The first metal part 61a, the second metal part 61b, and the third metal part 61c are disposed, for example, continuously to each other.

[0082] The second part 62, for example, has a first metal part 62a, a second metal part 62b, and a third metal part 62c. The first metal part 62a is a metal foil disposed on the first surface 42a of the fourth part 42. The second metal part 62b is a metal foil disposed on the second surface 42b of the fourth part 42. The third metal part 62c is a metal foil disposed on the inner surface of the second end 60hb of the through hole 60h. The first metal part 62a, the second metal part 62b, and the third metal part 62c are disposed, for example, continuously.

[0083] <3.3 Solder Joint>

[0084] Figure 7 This is an enlarged view showing the connection structure between the first substrate 30 and the second substrate 40. Figure 7 This indicates that the first substrate 30 and the second substrate 40 are connected. In this embodiment, the pads 50 and the pads 60 are connected by solder. For example, a solder connection portion S is provided between the pads 50 and the pads 60. Multiple pads 50 and multiple pads 60 are physically and electrically connected in a one-to-one relationship via multiple solder connection portions S.

[0085] In this embodiment, a portion of the solder joint S is located between the first portion 51 of the pad 50 and the first portion 61 of the pad 60. The portion of the solder joint S connects the first portion 51 of the pad 50 to the first portion 61 of the pad 60. For example, the portion of the solder joint S extends across the first metal portion 61a and the third metal portion 61c of the first portion 61 of the pad 60 and engages with the first portion 61 of the pad 60.

[0086] Another portion of the solder joint S is located between the second portion 52 of the pad 50 and the second portion 62 of the pad 60. This other portion of the solder joint S connects the second portion 52 of the pad 50 to the second portion 62 of the pad 60. For example, this other portion of the solder joint S extends across the first metal portion 62a and the third metal portion 62c of the second portion 62 of the pad 60 and engages with it.

[0087] Furthermore, the solder joint S is located in the X direction between the first portion 61 and the second portion 62 of the pad 60. The solder joint S connects the first portion 61 and the second portion 62 of the pad 60.

[0088] <4. Fixing structure to the shell>

[0089] Next, return Figure 2 The method for fixing the substrate 21 to the housing 10 will be described. The substrate 21 has a plurality of fixing holes 21h. The plurality of fixing holes 21h are arranged separately along the outer shape of the substrate 21. When viewed from the Z direction, the plurality of fixing holes 21h are arranged at positions overlapping with the plurality of fixing portions 17, 18 of the housing 10. Each fixing hole 21h is a through hole that penetrates the substrate 21 in the Z direction. In this embodiment, the fastening member FS passes through the fixing hole 17h of the fixing portion 17 of the base member 10MA, passes through the fixing hole 21h of the substrate 21, and engages with the fixing hole 18h of the fixing portion 18 of the cover member 10MB. Through this engagement, the base member 10MA and the cover member 10MB are fixed in a state where the substrate 21 is clamped from both sides in the Z direction by the fixing portions 17 of the base member 10MA and the fixing portions 18 of the cover member 10MB. Thus, the substrate 21 is fixed to the housing 10.

[0090] In this embodiment, the plurality of fixing holes 21h include fixing holes 21hS disposed at the connection portion between the first substrate 30 and the second substrate 40.

[0091] like Figure 3 As shown, the second portion 32 of the first substrate 30 has two fixing holes 32h. When viewed from the Z direction, the fixing holes 32h are located at positions corresponding to the fixing holes 21hS. The fixing hole 32h is an example of a "first hole".

[0092] Similarly, the fourth portion 42 of the second substrate 40 has two fixing holes 42h. Viewed from the Z direction, the fixing holes 42h are positioned corresponding to the fixing hole 21hS. The fixing holes 42h of the second substrate 40 face the fixing hole 32h of the first substrate 30 in the Z direction. The fixing hole 42h is an example of a "second hole". In this embodiment, the fixing hole 21hS is formed by the fixing hole 32h of the first substrate 30 and the fixing hole 42h of the second substrate 40.

[0093] In this embodiment, the fastening member FS, passing through the fixing hole 17h of the base member 10MA, passes through the fixing holes 32h of the first substrate 30 and 42h of the second substrate 40, and engages with the fixing hole 18h of the cover member 10MB. Through this engagement, with the second portion 32 of the first substrate 30 and the fourth portion 42 of the second substrate 40 clamped from both sides in the Z direction by the fixing portions 17 and 18 of the base member 10MA and the cover member 10MB, the base member 10MA and the cover member 10MB are fixed. Thus, the connection portion between the first substrate 30 and the second substrate 40 is fixed to the housing 10.

[0094] <5. Manufacturing Method of Semiconductor Memory Devices>

[0095] <5.1 Manufacturing Method Flow>

[0096] First, a first substrate 30 and a second substrate 40 are prepared. Then, a second portion 32 of the first substrate 30 and a fourth portion 42 of the second substrate 40 are connected. For example, with the second portion 32 of the first substrate 30 and the fourth portion 42 of the second substrate 40 overlapping in the Z direction, the first substrate 30 and the second substrate 40 are held by a clamp. Then, solder is supplied to the through-holes 60h of each pad 60 of the second substrate 40. As a result, the second portion 32 of the first substrate 30 and the fourth portion 42 of the second substrate 40 are connected by the solder connection portion S. Thus, substrate 21 is formed.

[0097] Next, a controller 23, a DRAM 24, multiple NAND flash units 25, a power control component 26, and multiple capacitors 27 are mounted on the substrate 21. Furthermore, the mounting of these electronic components can be performed before the first substrate 30 and the second substrate 40 are connected. Additionally, as part of the process of mounting these electronic components, the process of connecting the first substrate 30 and the second substrate 40 can also be performed. Then, the housing 10 is assembled by clamping the substrate 21 between the base component 10MA and the cover component 10MB. Next, the semiconductor memory device 1 is inspected. Thus, the semiconductor memory device 1 is completed.

[0098] <5.2 Inspection Method>

[0099] Next, the inspection method for the semiconductor memory device 1 will be described. In this embodiment, the inspection method for the semiconductor memory device 1 includes inspecting the connection state between the second portion 32 of the first substrate 30 and the fourth portion 42 of the second substrate 40. This inspection can be performed by at least one of visual inspection and electrical inspection.

[0100] <5.2.1 Visual Inspection Methods>

[0101] Figures 8A to 8D This is a top view used to illustrate the visual inspection method. In this embodiment, the solder joint S can be visually confirmed from the outside of the substrate 21 through the through-hole 60h of the pad 60 of the second substrate 40. Furthermore, in this application, "visual inspection" is not limited to the case of directly visually confirming the substrate 21; visual confirmation using a magnifying glass, visual confirmation of an image captured by a photographic device, etc., are also acceptable.

[0102] Figure 8A This indicates a good connection between the first substrate 30 and the second substrate 40. For example, when solder joints S are present throughout the first portion 61 and the second portion 62 of the pad 60 inside the through-hole 60h, it is known that a sufficient amount of solder has been supplied. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is good.

[0103] Figure 8B This indicates a poor connection between the first substrate 30 and the second substrate 40. For example, if the solder joint S inside the through-hole 60h is connected to either the first portion 61 or the second portion 62 of the pad 60, but the solder joint S between the first portion 61 and the second portion 62 of the pad 60 is interrupted, it indicates insufficient solder. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is poor.

[0104] Figure 8C This indicates a poor connection between the first substrate 30 and the second substrate 40. For example, if the solder joint S inside the through-hole 60h is not in contact with the first portion 61 or the second portion 62 of the pad 60, or if the solder joint S between the first portion 61 and the second portion 62 of the pad 60 is interrupted, it indicates insufficient solder. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is poor.

[0105] Figure 8DThis refers to the case where the pad 50 is formed by a single conductor portion (i.e., not divided into a first portion 51 and a second portion 52), and the connection between the first substrate 30 and the second substrate 40 is good. For example, when solder joints S are present throughout the first portion 61 and the second portion 62 of the pad 60 inside the through-hole 60h, it is known that a sufficient amount of solder has been supplied appropriately. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is good.

[0106] <5.2.2 Electrical Inspection>

[0107] Figure 9 This is a cross-sectional view used to illustrate the electrical inspection method. In this embodiment, the connection state between the first substrate 30 and the second substrate 40 can be checked by verifying the continuity between the first portion 61 and the second portion 62 of the pad 60. For example, by contacting the first terminal 91 of the inspection device 90 with the second metal portion 61b of the first portion 61 of the pad 60, and by contacting the second terminal 92 of the inspection device 90 with the second metal portion 62b of the second portion 62 of the pad 60, the continuity between the first portion 61 and the second portion 62 of the pad 60 can be verified.

[0108] In this case, when the first portion 61 and the second portion 62 of the pad 60 are in a conductive state, it can be determined that a sufficient amount of solder has been supplied. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is good. On the other hand, when the first portion 61 and the second portion 62 of the pad 60 are not in a conductive state, it can be determined that the solder is insufficient. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is poor.

[0109] <6. Advantages>

[0110] As a first comparative example, consider a substrate that is not divided into a first substrate 30 and a second substrate 40. In such a first comparative example, the material or thickness of the substrate is the same throughout the substrate, which sometimes makes it difficult to increase the degree of freedom in design and component replacement. For example, if the substrate is formed entirely of a high-cost material suitable for high-speed signals, electronic components that do not need to handle high-speed signals may also be mounted on the substrate formed of the aforementioned high-cost material. In this case, the substrate may sometimes exceed the specifications for some components.

[0111] Therefore, as a second comparative example, consider the case where the substrate is divided into a first substrate 30 and a second substrate 40, and the first substrate 30 and the second substrate 40 are connected via connector components (e.g., B to B connectors). However, when connector components are used to connect the first substrate 30 and the second substrate 40, the semiconductor memory device becomes larger and it is difficult to reduce the cost.

[0112] On the other hand, in this embodiment, the semiconductor memory device 1 includes a first substrate 30 and a second substrate 40. The first substrate 30 has a first portion 31, a second portion 32 that is thinner than the first portion 31, and a plurality of pads 50 disposed on the second portion 32. The second substrate 40 has a plurality of pads 60. When viewed from the Z direction, the plurality of pads 60 overlap with the plurality of pads 50. The plurality of pads 60 are respectively connected to the plurality of pads 50 by solder. With such a structure, the substrate 21 can be divided into the first substrate 30 and the second substrate 40 according to the purpose, and the materials or thicknesses of the first substrate 30 and the second substrate 40 can be different. Therefore, compared with a substrate that is not divided into the first substrate 30 and the second substrate 40, an increase in the degree of freedom of design, etc., can be achieved.

[0113] In another example, the second substrate 40 can also be replaced relative to the first substrate 30. In this case, compared to a substrate that is not divided into the first substrate 30 and the second substrate 40, the degree of freedom for component replacement and the like can be increased. In this case, if an electronic component provided on the second substrate 40 malfunctions, the substrate 21 can be repaired by replacing the second substrate 40.

[0114] Furthermore, according to the structure that connects the first substrate 30 and the second substrate 40 via the solder connection portion S, compared to the case where connector parts are used, the connection structure between the first substrate 30 and the second substrate 40 can be made thinner. Additionally, by having a second portion 32 that is thinner than the first portion 31 in the first substrate 30, as in this embodiment, and by providing a plurality of pads 50 in the second portion 32, the connection structure between the first substrate 30 and the second substrate 40 can be further made thinner.

[0115] In this embodiment, the second substrate 40 has a third portion 41 and a fourth portion 42 that is thinner than the third portion 41 and overlaps with the second portion 32 of the first substrate 30 when viewed from the Z direction. A plurality of pads 60 are disposed on the fourth portion 42. With this structure, the thickness of the connection structure between the first substrate 30 and the second substrate 40 can be reduced compared to a case where the second substrate 40 as a whole has the same thickness.

[0116] In this embodiment, the second portion 32 of the first substrate 30 is located at a position offset towards the -Z direction from the center C1 in the Z direction relative to the first portion 31 of the first substrate 30. On the other hand, the fourth portion 42 of the second substrate 40 is located at a position offset towards the +Z direction from the center C2 in the Z direction relative to the third portion 41 of the second substrate 40. With this structure, since the step difference 30s of the first substrate 30 and the step difference 40s of the second substrate 40 are in opposite directions, the overall thickness of the substrate 21 can be reduced compared to the case where the step difference 30s of the first substrate 30 and the step difference 40s of the second substrate 40 are in the same direction.

[0117] In this embodiment, the controller 23, DRAM 24, and NAND 25 are disposed on the first substrate 30, and the power control component 26 is disposed on the second substrate 40. With this structure, the first substrate 30 can be configured for high-speed signal transmission, while the second substrate 40 can be configured to be less expensive than the first substrate 30. Thus, while improving the functionality of the semiconductor memory device 1, cost reduction can be achieved. Here, the less expensive configuration includes, for example, a configuration based on less expensive materials and a configuration with fewer conductive layers.

[0118] In this embodiment, the controller 23, DRAM 24, and NAND 25 are disposed on the first substrate 30, and the capacitor 27 is disposed on the second substrate 40. With this structure, the first substrate 30 can be configured for high-speed signal transmission, while the second substrate 40 can be configured to be less expensive than the first substrate 30. Thus, both improved functionality and reduced cost of the semiconductor memory device 1 can be achieved simultaneously. Here, the less expensive configuration includes, for example, a configuration based on inexpensive materials and a configuration with fewer conductive layers.

[0119] In this embodiment, the first substrate 30 includes a first material M1. The second substrate 40 includes a second material M2. Compared to the second material M2, the first material M1 has a smaller dielectric constant or dielectric loss tangent, at least one of these. With this structure, the first substrate 30 can be configured for high-speed signal transmission, while the second substrate 40 can be made of a lower-cost material than the first substrate 30. Thus, both improved functionality and reduced cost of the semiconductor memory device 1 can be achieved simultaneously.

[0120] In this embodiment, the first substrate 30 has a pad 50. The second substrate 40 has a pad 60. The pad 60 includes a through-hole 60h extending through the second substrate 40 in the Z direction. With this structure, solder can be supplied between the first substrate 30 and the second substrate 40 through the through-hole 60h of the pad 60. As a result, the manufacturability of the semiconductor memory device 1 can be improved.

[0121] In this embodiment, the through-hole 60h is an elongated hole having a long side in the X direction (or Y direction). With this structure, the state of the solder joint S in the long side direction of the elongated hole can be visually or electrically confirmed, thereby facilitating the inspection of the connection state between the first substrate 30 and the second substrate 40. This improves the manufacturability of the semiconductor memory device 1.

[0122] In this embodiment, the through-hole 60h, which is the aforementioned elongated hole, includes a first end portion 60ha located on one side in the X direction (or Y direction) and a second end portion 60hb located on the other side in the X direction (or Y direction). The pad 60 includes a first portion 61 adjacent to the first end portion 60ha of the through-hole 60h and a second portion 62 separated from the first portion 61 and adjacent to the second end portion 60hb of the through-hole 60h. With this structure, the connection state between the first substrate 30 and the second substrate 40 can be easily inspected. Specifically, by visually confirming the connection state of the solder joint S with respect to the first portion 61 and the second portion 62 of the pad 60, the connection state between the first substrate 30 and the second substrate 40 can be easily inspected. Furthermore, by confirming the electrical connection state between the first portion 61 and the second portion 62 of the pad 60, the connection state between the first substrate 30 and the second substrate 40 can be easily inspected. This improves the manufacturability of the semiconductor memory device 1.

[0123] In this embodiment, the housing 10 has fixing portions 17 and 18. The second portion 32 of the first substrate 30 has a fixing hole 32h. The second substrate 40 has a fixing hole 42h facing the fixing hole 32h. The fastening member FS is inserted into the fixing holes 32h and 42h and fixed to the fixing portions 17 and 18. According to this structure, by fixing the substrate 21 to the housing 10, at least a part of the structure connecting the first substrate 30 and the second substrate 40 is formed. Therefore, compared with the case where the fixing structure for fixing the substrate 21 to the housing 10 and the structure for connecting the first substrate 30 and the second substrate 40 are respectively provided, miniaturization and cost reduction of the semiconductor memory device 1 can be achieved.

[0124] In this embodiment, a portion of the second portion 32 of the first substrate 30 is connected to a portion of the fourth portion 42 of the second substrate 40 by solder (e.g., a portion of the solder connection portion S). On the other hand, another portion of the second portion 32 of the first substrate 30 may also contact another portion of the fourth portion 42 of the second substrate 40. This allows for further thinning of the connection structure between the first substrate 30 and the second substrate 40.

[0125] Alternatively, instead of the above examples or based thereon, a portion of the first portion 31 of the first substrate 30 (e.g., a step 30s) may contact the fourth portion 42 of the second substrate 40 in the X direction. This sometimes makes it easier to position the first substrate 30 and the second substrate 40. Alternatively, instead of the above examples or based thereon, a portion of the third portion 41 of the second substrate 40 (e.g., a step 40s) may contact the second portion 32 of the first substrate 30 in the X direction. This sometimes makes it easier to position the first substrate 30 and the second substrate 40.

[0126] <7. Variations>

[0127] Next, variations of the first embodiment will be described. Furthermore, in each variation, the structure except as described below is the same as that of the first embodiment.

[0128] <7.1 First Variation>

[0129] Figure 10 This is a cross-sectional view showing a portion of the semiconductor memory device 1A in a first modified example. In this modified example, for example, the pad 50 is formed of a single conductor portion. That is, the pad 50 is not divided into a first portion 51 and a second portion 52. However, the pad 50 may also have a first portion 51 and a second portion 52 in the same manner as in the first embodiment.

[0130] In this modified example, the first substrate 30 has a test pad 95 electrically connected to the pad 50. The test pad 95 is electrically connected to the pad 50 via one or more of a through hole, via, or conductive layer 30c disposed inside the first substrate 30. The test pad 95 is exposed on the surface of the first substrate 30 (e.g., first surface 31a, second surface 31b, or first surface 32a).

[0131] In this modified example, the connection status between the first substrate 30 and the second substrate 40 can be checked by verifying the continuity between the pad 60 and the test pad 95. For example, the continuity between the pad 60 and the test pad 95 can be verified by contacting the first terminal 91 of the inspection device 90 with the pad 60 and the second terminal 92 of the inspection device 90 with the test pad 95.

[0132] In this case, when there is a conductive connection between the pad 60 and the test pad 95, it indicates that a sufficient amount of solder has been supplied. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is good. On the other hand, when there is no conductive connection between the pad 60 and the test pad 95, it indicates that the solder is insufficient. In this case, it can be determined that the connection between the first substrate 30 and the second substrate 40 is poor.

[0133] <7.2 Second Variation>

[0134] Figure 11 This is a cross-sectional view showing a portion of the semiconductor memory device 1B according to a second modified example. In this modified example, the fourth portion 42 of the second substrate 40 is thinner compared to the first embodiment. For example, the thickness T42 of the fourth portion 42 of the second substrate 40 in the Z direction is less than half the thickness T41 of the third portion 41 of the second substrate 40 in the Z direction. For example, the thickness T42 of the fourth portion 42 of the second substrate 40 in the Z direction is less than the thickness T32 of the second portion 32 of the first substrate 30 in the Z direction. For example, the thickness T42 of the fourth portion 42 of the second substrate 40 in the Z direction is less than half the thickness T31 of the first portion 31 of the first substrate 30 in the Z direction.

[0135] With this structure, since the fourth portion 42 of the second substrate 40 is relatively thin, the state inside the through-hole 60h can be easily confirmed by visual inspection from the surface of the second substrate 40, and the state of the connection portion between the first substrate 30 and the second substrate 40 can be easily confirmed. Therefore, the manufacturability of the semiconductor memory device 1B can be further improved.

[0136] (Second Implementation)

[0137] Next, the semiconductor memory device 1C according to the second embodiment will be described. The difference between the second embodiment and the first embodiment is that the thickness of the second substrate 40 in the Z direction is less than the thickness of the first substrate 30 in the Z direction. Otherwise, the structure is the same as that in the first embodiment, except for the following description.

[0138] Figure 12 This is a cross-sectional view showing a portion of the semiconductor memory device 1C according to the second embodiment. In this embodiment, the thickness T40 in the Z direction of the second substrate 40 is less than the thickness T30 in the Z direction of the first substrate 30. For example, the thickness T41 in the Z direction of the third portion 41 of the second substrate 40 is less than the thickness T31 in the Z direction of the first portion 31 of the first substrate 30.

[0139] For example, the thickness T42 of the fourth portion 42 of the second substrate 40 in the Z direction is less than the thickness T30s of the step 30s of the first substrate 30 in the Z direction. The second surfaces 41b and 42b of the second substrate 40 are located at positions offset in the -Z direction relative to the second surface 31b of the first substrate 30. As a result, in the region overlapping with the second substrate 40 in the Z direction, a space SU is formed that can be used due to the difference in height between the second surfaces 41b and 42b of the second substrate 40 and the second surface 31b of the first substrate 30.

[0140] In this embodiment, a controller 23, a DRAM 24, and a plurality of NAND 25s are mounted on the second surface 31b of the first substrate 30. A power control component 26 and a plurality of capacitors 27 are mounted on the second surface 41b of the second substrate 40. At least a portion of each of the power control component 26 and capacitors 27 is disposed in the aforementioned space SU. In this embodiment, the thickness T27 in the Z direction of the capacitor 27 is greater than the thickness T23 in the Z direction of the controller 23, greater than the thickness T24 in the Z direction of the DRAM 24, and greater than the thickness T25 in the Z direction of the NAND 25. The capacitor 27 is an example of an electronic component that is thicker than the controller 23, DRAM 24, and NAND 25, respectively.

[0141] Based on the structure described above, a space SU is formed that can be utilized due to the difference between the second surfaces 41b and 42b of the second substrate 40 and the second surface 31b of the first substrate 30. Therefore, even when thicker electronic components (such as capacitor 27) are mounted on the second substrate 40, it is easy to achieve overall thinning of the semiconductor memory device 1C.

[0142] (Third Implementation)

[0143] Next, the semiconductor memory device 1D according to the third embodiment will be described. The difference between the third embodiment and the first embodiment is that a second substrate 40 is connected in the middle of the first substrate 30. Otherwise, the structure is the same as the first embodiment except for the following description.

[0144] Figure 13 This is an exploded view of a portion of the semiconductor memory device 1D according to the third embodiment. In this embodiment, the second portion 32 of the first substrate 30 is disposed midway along the X direction of the first portion 31 of the first substrate 30. On the other hand, the fourth portion 42 of the second substrate 40 is disposed on both sides of the third portion 41 of the second substrate 40 in the X direction.

[0145] Figure 14 This is a diagram showing a portion of the semiconductor memory device 1D according to the third embodiment. In this embodiment, when viewed from the Z direction, the third portion 41 of the second substrate 40 overlaps with the second portion 32 of the first substrate 30. On the other hand, when viewed from the Z direction, the fourth portion 42 of the second substrate 40 overlaps with the first portion 31 of the first substrate 30.

[0146] In this embodiment, the first conductive portion (e.g., pad 50) is disposed on the first portion 31 of the first substrate 30, and the second conductive portion (e.g., pad 60) is disposed on the fourth portion 42 of the second substrate 40. Alternatively, the first conductive portion (e.g., pad 50) may be disposed on the second portion 32 of the first substrate 30, and the second conductive portion (e.g., pad 60) may be disposed on the third portion 41 of the second substrate 40.

[0147] With this structure, compared to a substrate that is not divided into a first substrate 30 and a second substrate 40, greater freedom in design and component replacement is achieved. Furthermore, according to this embodiment, a protrusion formed by a third portion 41 and a fourth portion 42 of the second substrate 40 is inserted (e.g., fitted) into a recess formed by a first portion 31 and a second portion 32 of the first substrate 30. This allows for approximate positioning of the second substrate 40 relative to the first substrate 30. Consequently, the manufacturability of the semiconductor memory device 1D is improved.

[0148] (Fourth Implementation)

[0149] Next, the semiconductor memory device 1E according to the fourth embodiment will be described. The difference between the fourth embodiment and the first embodiment is that the first substrate 30 has a two-stage step difference. Otherwise, the structure is the same as that of the first embodiment, except for the following description.

[0150] Figure 15 This is a diagram showing a portion of the semiconductor memory device 1E according to the fourth embodiment. In this embodiment, the first substrate 30 includes, for example, a first portion 31, a second portion 32, and a fifth portion 35. The second portion 32 of the first substrate 30 is disposed midway along the X direction of the first portion 31 of the first substrate 30. The second portion 32 has a Z-direction step 30s1 between itself and the first portion 31, and is thinner than the first portion 31. The Z-direction length of the step 30s1 is, for example, greater than the Z-direction thickness T42 of the fourth portion 42 of the second substrate 40.

[0151] The fifth portion 35 of the first substrate 30 is disposed midway along the X direction of the second portion 32 of the first substrate 30. The fifth portion 35 has a Z-direction step 30s2 between itself and the second portion 32, and is thinner than the second portion 32. The Z-direction length of the step 30s2 is, for example, greater than the Z-direction length of the step 40s of the second substrate 40.

[0152] Figure 16This diagram illustrates a portion of the semiconductor memory device 1E according to the fourth embodiment. In this embodiment, the third portion 41 of the second substrate 40 overlaps with the fifth portion 35 of the first substrate 30 in the Z direction. Conversely, the fourth portion 42 of the second substrate 40 overlaps with the second portion 32 of the first substrate 30 in the Z direction. In this embodiment, the second surface 31b of the first substrate 30 and the second surfaces 41b and 42b of the second substrate 40 are located on the same plane.

[0153] In this embodiment, the first conductive portion (e.g., pad 50) is disposed on the second portion 32 of the first substrate 30, and the second conductive portion (e.g., pad 60) is disposed on the fourth portion 42 of the second substrate 40. Alternatively, the first conductive portion (e.g., pad 50) may be disposed on the fifth portion 35 of the first substrate 30, and the second conductive portion (e.g., pad 60) may be disposed on the third portion 41 of the second substrate 40.

[0154] Based on the structure described above, compared to a substrate that is not divided into a first substrate 30 and a second substrate 40, greater freedom in design and component replacement is achieved. Furthermore, according to this embodiment, by utilizing either the first portion 31 or the second portion 32 of the first substrate 30, approximate positioning of the second substrate 40 relative to the first substrate 30 is possible. This improves the manufacturability of the semiconductor memory device 1E.

[0155] The first to fourth embodiments and their variations have been described above. However, the embodiments and variations are not limited to the examples described above. For example, the embodiments or variations described above can be combined with each other. In addition, the connection structure between the first substrate 30 and the second substrate 40 described in the above embodiments can also be applied to substrate cells used in devices other than semiconductor memory devices.

[0156] In the above embodiments, an example was described in which a second portion 32 is provided on the first substrate 30 and a fourth portion 42 is provided on the second substrate 40. Alternatively, the first substrate 30 may have a first portion 31 and a second portion 32, and the second substrate 40 may be of the same thickness throughout. Alternatively, the second substrate 40 may have a third portion 41 and a fourth portion 42, and the first substrate 30 may be of the same thickness throughout.

[0157] In the above embodiment, an example was described in which the controller 23, DRAM 24, and NAND 25 are disposed on the first substrate 30, and the power control component 26 and capacitor 27 are disposed on the second substrate 40. Alternatively, the controller 23, DRAM 24, and NAND 25 may be disposed on the second substrate 40, and the power control component 26 and capacitor 27 may be disposed on the first substrate 30.

[0158] In the above embodiment, an example in which the first conductive portion is a pad 50 and the second conductive portion is a solder pad 60 has been described. Alternatively, both the first and second conductive portions may be pads 50, or conductive portions of other shapes may be used.

[0159] According to at least one embodiment described above, a semiconductor memory device includes a first substrate and a second substrate. The first substrate has a first portion, a second portion thinner than the first portion, and a plurality of first conductive portions disposed in the second portion. The second substrate has a plurality of second conductive portions. When viewed from the thickness direction of the first substrate, i.e., a first direction, the plurality of second conductive portions overlap with the plurality of first conductive portions. The plurality of second conductive portions are respectively connected to the plurality of first conductive portions by solder. With this structure, an increase in degrees of freedom can be achieved.

[0160] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: A first substrate has a first portion, a second portion thinner than the first portion, and a plurality of first conductive portions disposed in the second portion; and The second substrate has multiple second conductive sections. When viewed from the thickness direction of the first substrate, i.e., the first direction, the plurality of second conductive portions overlap with the plurality of first conductive portions. The plurality of second conductive parts are respectively connected to the plurality of first conductive parts by solder.

2. The semiconductor memory device according to claim 1, wherein, The second substrate has: Part Three; as well as The fourth portion, thinner than the third portion, overlaps with the second portion of the first substrate when viewed from the first direction. The plurality of second conductive sections are disposed in the fourth part.

3. The semiconductor memory device according to claim 2, wherein, The second portion is located at a position offset from the center of the first portion in the first direction towards a first side of the first direction. The fourth part is located at a position offset from the center of the first direction relative to the third part, towards the second side opposite to the first side, i.e., the second side of the first direction.

4. The semiconductor memory device according to claim 3, wherein, The second substrate is thinner than the first substrate.

5. The semiconductor memory device according to any one of claims 1 to 4, further comprising: Semiconductor memory; A controller capable of controlling the semiconductor memory; and The power control component is capable of controlling the power supply to the semiconductor memory and the controller. The semiconductor memory and the controller are disposed on one of the first substrate and the second substrate. The power control component is disposed on the other of the first substrate and the second substrate.

6. The semiconductor memory device according to any one of claims 1 to 4, further comprising: Semiconductor memory; A controller capable of controlling the semiconductor memory; and The capacitor is capable of supplying power to the semiconductor memory and the controller. The semiconductor memory and the controller are disposed on one of the first substrate and the second substrate. The capacitor is disposed on the other of the first substrate and the second substrate.

7. The semiconductor memory device according to any one of claims 1 to 4, wherein, The first substrate includes a first material. The second substrate includes a second material. Compared to the second material, the first material has at least one smaller dielectric constant or dielectric loss tangent.

8. The semiconductor memory device according to any one of claims 1 to 4, wherein, The plurality of first conductive parts are each a pad.

9. The semiconductor memory device according to any one of claims 1 to 4, wherein, The plurality of first conductive parts include a first conductive part. The plurality of second conductive portions include second conductive portions that overlap with the first conductive portion when viewed from the first direction. The second conductive portion includes a through hole that penetrates the second substrate in the first direction.

10. The semiconductor memory device according to claim 9, wherein, The through hole is an elongated hole with its long side facing in a second direction that intersects the first direction.

11. The semiconductor memory device according to claim 10, wherein, The through hole includes a first end located on one side of the second direction and a second end located on the other side of the second direction. The second conductive portion includes a first portion adjacent to the first end of the through hole and a second portion separate from the first portion and adjacent to the second end of the through hole.

12. The semiconductor memory device according to any one of claims 2 to 4, wherein, The second portion of the first substrate is in contact with the fourth portion of the second substrate.

13. The semiconductor memory device according to any one of claims 1 to 4, further comprising: A housing that accommodates the first substrate and the second substrate, and has a fixing portion; and Fastening components are installed on the fixing part. The second portion of the first substrate has a first hole. The second substrate has a second hole facing the first hole. The fastening component is inserted into the first hole and the second hole and fixed to the fixing part.

14. A substrate unit comprising: A first substrate has a first portion, a second portion thinner than the first portion, and a plurality of first conductive portions disposed in the second portion; and The second substrate has multiple second conductive sections. When viewed from the thickness direction of the first substrate, i.e., the first direction, the plurality of second conductive portions overlap with the plurality of first conductive portions. The plurality of second conductive parts are respectively connected to the plurality of first conductive parts by solder.

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