Trench mosfet device with reduced high frequency switching noise and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor device manufacturing, in particular to a trench MOSFET device capable of reducing high-frequency switching noise and a manufacturing method thereof. The trench MOSFET device comprises a substrate, an epitaxial layer, a doped region, a JTE region, a gate, a first implantation buried layer, a second implantation buried layer and a source metal layer. By optimizing the structure of the JTE region and the implantation buried layer, the high-frequency switching noise is effectively reduced, and the reliability and performance of the device are improved. In addition, by specific trench design and process steps, the voltage resistance and electrical characteristics of the device are further enhanced.

Description

Technical Field

[0001] This application relates to the field of trench MOSFET devices, and in particular to a trench MOSFET device and a method for manufacturing the same, which reduces high-frequency switching noise. Background Technology

[0002] Trench MOSFETs achieve high cell density by densely arranging trenches on a chip. These trenches extend into oppositely doped regions of the chip, and each trench contains a gate dielectric and a gate electrode, controlling current conduction in its vicinity via a field effect. This structure makes trench MOSFETs have the lowest on-resistance (RDS(on)) of all MOS devices.

[0003] However, at high drain voltages, a large electric field exists at the bottom of the trench, which can easily break down the gate oxide layer, affecting the device's voltage withstand capability and reliability. Meanwhile, switching noise is a common problem in high-frequency power switching circuits, especially when the high-side MOSFET is on and the low-side MOSFET is off. Voltage overshoot and oscillation can occur; excessive overshoot may cause mis-conduction or avalanche breakdown, while oscillation may lead to component failure. Summary of the Invention

[0004] To enhance the device's voltage resistance and reduce high-frequency switching noise, this application provides a trench MOSFET device and its manufacturing method for reducing high-frequency switching noise.

[0005] The first aspect of this application provides a trench MOSFET device for reducing high-frequency switching noise using the following technical solution: A trench MOSFET device for reducing high-frequency switching noise, comprising: The substrate has an epitaxial layer of the first doping type formed on its upper surface; The doped region includes a base region, a well region, and a source region, which are disposed within the epitaxial layer; JTE regions are located within the epitaxial layer. The JTE regions include peripheral JTE regions and in-plane JTE regions. The peripheral JTE regions surround the periphery of all base regions. The upper surface of the peripheral JTE regions is exposed on the upper surface of the epitaxial layer. The in-plane JTE regions are located between adjacent base regions and the two ends of the in-plane JTE regions are connected to the inner side of the peripheral JTE regions. A gate is disposed between the base regions, and the bottom end of the gate extends through the well region and the source region; A first buried layer and a second buried layer are formed at the bottom of the gate. The first buried layer is formed by the in-plane JTE region. The second buried layer is disposed on the side of the first buried layer away from the gate. The first buried layer and the second buried layer are not connected to the base region. The first buried layer is of the second doping type, and the second buried layer is of the first doping type, which is different from the second doping type. A source metal layer is formed on the upper surface of the epitaxial layer to connect the base region, the source region, and the surrounding JTE region.

[0006] By adopting the above technical solution, P-type and N-type regions are formed at the bottom of the trench, effectively protecting the trench bottom from the influence of high electric fields and improving the device's voltage resistance and reliability. The second implanted buried layer reduces the on-resistance. Simultaneously, the first implanted buried layer is grounded through the JTE region, avoiding charge accumulation caused by repeated switching, solving overshoot and oscillation problems, and thus reducing high-frequency switching noise. Furthermore, the JTE region and the first implanted buried layer share the same implantation step, reducing the number of implantation steps and simplifying the process flow.

[0007] Optionally, the epitaxial layer is etched with trenches, the gate is filled in the trenches, the angle between the trench sidewall and the horizontal plane is 80°-91°, and the connection between the trench sidewall and the bottom of the trench is arc-shaped.

[0008] By adopting the above technical solution, the electric field concentration effect caused by sharp corners is effectively reduced, the local electric field strength is lowered, and the withstand voltage and reliability of the device are improved. At the same time, this design also helps to improve the stress generated during trench etching, prevent crack formation, and further improve the overall performance of the device.

[0009] Optionally, the depth of the base region is shallower than the depth of the source region, and the second implantation layer has a structure that is thin in the middle and thick on both sides, with both sides of the second implantation layer extending directly below the base region.

[0010] By adopting the above technical solution, the distance between trenches can be reduced, the cell unit size can be reduced, and the on-resistance can be reduced; at the same time, the second implanted buried layer can be wider, further reducing the on-resistance.

[0011] Optionally, the depth of the base region is deeper than the depth of the well region, the well region is connected to the base region, and the well region includes a first channel region and a second channel region arranged from bottom to top, the first channel region being a second doping type and the second channel region being a first doping type; The base region has a higher doping concentration than the first channel region, and the second channel region has a lower doping concentration than the source region, so as to form a negative feedback resistor between the first channel region and the source region to achieve gate-source breakdown voltage.

[0012] By employing the above technical solution, the base region is deeper than the well region, allowing for better control of the channel's opening and closing, thus improving the device's reliability and stability. The negative feedback resistor enables voltage division between the gate and source, effectively enhancing the gate oxide's withstand voltage performance, reducing the risk of gate oxide breakdown, and consequently improving the device's overall reliability and lifespan.

[0013] Optionally, a recessed contact region is etched on the upper surface of the epitaxial layer, and a metal interconnect layer is filled in the recessed contact region. The metal interconnect layer is connected to the source metal layer and the base region, source region, and peripheral JTE region, respectively.

[0014] By adopting the above technical solution, the recessed contact area can effectively reduce contact resistance and improve the conductivity of the device. The introduction of the metal interconnect layer not only ensures good electrical connection, but also enhances the overall reliability and stability of the device. In particular, the connection between the metal interconnect layer and the source metal layer, base region, source region, and surrounding JTE region makes the current distribution more uniform, reduces the generation of local hot spots, thereby reducing the temperature rise of the device and extending its service life.

[0015] The second aspect of this application provides a method for manufacturing a trench MOSFET device to reduce high-frequency switching noise, using the following technical solution: A method for fabricating a trench MOSFET device to reduce high-frequency switching noise includes the following steps: S10. Provide a substrate and form an epitaxial layer of a first doped type on the upper surface of the substrate; S20. Ions are sequentially implanted into the epitaxial layer to form a base region, a well region, and a source region within the epitaxial layer. S30. Ions are implanted into the epitaxial layer to form a peripheral JTE region, the peripheral JTE region surrounds the periphery of all base regions, and the upper surface of the peripheral JTE region is exposed on the upper surface of the epitaxial layer; Ions are implanted into the epitaxial layer to form an in-plane JTE region, such that the in-plane JTE region is located between adjacent base regions and the two ends of the in-plane JTE region are connected to the inner side of the peripheral JTE region. S40. Etch the epitaxial layer to form a trench that penetrates the well region and the source region. The trench removes the upper structure of the in-plane JTE region, leaving only the in-plane JTE region at the bottom of the trench. The in-plane JTE region at the bottom of the trench forms a first implanted buried layer of a second doping type. The first doping type is opposite to the second doping type. The two ends of the first implanted buried layer are connected to the surrounding JTE region. S50. Ions are implanted into the bottom of the trench to form a second implanted buried layer of the first doping type. The second implanted buried layer is located on the outer periphery of the first implanted buried layer. The first implanted buried layer and the second implanted buried layer are not in contact with the base region. S60. Deposit polysilicon into the trench to form a gate; S70. A source metal layer is formed on the upper surface of the epitaxial layer to connect the base region, the source region, and the surrounding JTE region.

[0016] By adopting the above technical solutions, noise issues in trench MOSFETs during high-frequency switching applications can be effectively reduced. Specifically, by forming P-type and N-type buried layers at the bottom of the trench, not only is the device's voltage resistance and reliability improved, but the on-resistance is also significantly reduced, thereby reducing switching losses. Furthermore, the JTE region design effectively mitigates charge accumulation, further improving the device's dynamic performance and ensuring stability and durability under high-frequency operating conditions.

[0017] Optionally, the angle between the trench sidewall and the horizontal plane is 80°-91°, and the connection between the trench sidewall and the bottom of the trench is arc-shaped.

[0018] By adopting the above technical solution, the angle between the trench sidewall and the horizontal plane is 80°-91°, giving the trench good mechanical strength and electrical properties. This effectively prevents the trench sidewall from collapsing, ensuring the stability and reliability of the device. The connection between the trench sidewall and the bottom of the trench is arc-shaped, which can effectively disperse local electric field concentration, reduce electric field stress, thereby improving the breakdown voltage and withstand voltage of the device, further enhancing the reliability and service life of the device.

[0019] Optionally, the depth of the base region is shallower than the depth of the source region; step S50 includes: S54. Control the ion implantation angle so that the second implantation layer has a structure that is thin in the middle and thick on both sides, and the two sides of the second implantation layer extend to the direct below the base region.

[0020] By adopting the above technical solution, the distance between trenches can be reduced, the cell unit size can be reduced, and the on-resistance can be reduced; at the same time, the second implanted buried layer can be wider, further reducing the on-resistance.

[0021] Optionally, step S20 includes: S21. Ions are implanted into the epitaxial layer to form a base region of the second doping type; S22. Ions are implanted into the epitaxial layer to form a first channel region of the second doping type; S23. Ions are implanted into the epitaxial layer to form a second channel region of the first doping type, and the first channel region and the second channel region are combined to form a well region; S24. Ions are implanted into the epitaxial layer to form a source region of the first doping type; The base region has a higher doping concentration than the first channel region, and the second channel region has a lower doping concentration than the source region, so as to form a negative feedback resistor between the first channel region and the source region to achieve gate-source breakdown voltage.

[0022] By adopting the above technical solution, the doping concentration of the base region is higher than that of the first channel region, resulting in a higher doping gradient between the base region and the first channel region. This enhances the electric field strength between the base region and the first channel region, improving the device's breakdown voltage capability. The doping concentration of the second channel region is lower than that of the source region, resulting in a lower doping gradient between the first channel region and the source region. This reduces the electric field strength between the first channel region and the source region, reducing the risk of gate oxide layer breakdown. The formation of the negative feedback resistor can effectively reduce the actual voltage between the gate and source when a high voltage is applied between them through the voltage division effect of the negative feedback resistor. This further improves the breakdown voltage performance of the gate and source, ensuring the stability and reliability of the device under high voltage.

[0023] Optionally, step S20 includes: S25. A first channel region of the second doping type, a second channel region of the first doping type, and a source region of the first doping type are sequentially formed in the epitaxial layer by epitaxy, and the first channel region and the second channel region are combined to form a well region; or a first channel region of the second doping type is formed in the epitaxial layer by implantation, and a second channel region of the first doping type and a source region of the first doping type are formed in the epitaxial layer by epitaxy, and the first channel region and the second channel region are combined to form a well region; S26. Ions are implanted into the epitaxial layer to form a base region of the second doping type; The base region has a higher doping concentration than the first channel region, and the second channel region has a lower doping concentration than the source region, so as to form a negative feedback resistor between the first channel region and the source region to achieve gate-source breakdown voltage.

[0024] By adopting the above technical solution, the trap region and source region are formed by epitaxy, which can more accurately control the concentration and thickness of each region of the trap region and source region, and the formation of each region does not interfere with each other.

[0025] In summary, this application includes at least one of the following beneficial technical effects: 1. The formation of P-type and N-type regions at the bottom of the trench effectively protects it from the influence of high electric fields, improving the device's voltage resistance and reliability. The second implanted buried layer reduces on-resistance. Simultaneously, the first implanted buried layer is grounded through the JTE region, avoiding charge accumulation caused by repeated switching and resolving overshoot and oscillation issues, thereby reducing high-frequency switching noise. Furthermore, the JTE region and the first implanted buried layer share the same implantation step, reducing the number of implantation steps and simplifying the process flow.

[0026] 2. The depth of the base region is shallower than the depth of the source region. The distance between the trenches can be reduced, the cell unit size can be reduced, and the on-resistance can be reduced. At the same time, the second implanted buried layer can be wider, further reducing the on-resistance.

[0027] 3. The negative feedback resistor can achieve voltage division between the gate and source, which effectively improves the withstand voltage performance of the gate oxide layer, reduces the risk of gate oxide layer breakdown, and thus improves the overall reliability and service life of the device. Attached Figure Description

[0028] Figure 1 VDS waveform diagrams showing overshoot and oscillation phenomena in related technologies; Figure 2 This is a partial cross-sectional schematic diagram of a trench MOSFET device in a preferred embodiment of this application; Figure 3 This is a top cross-sectional view of a trench MOSFET device in a preferred embodiment of this application; Figure 4 yes Figure 3 A sectional view along line AA. Figure 5 This is a partial cross-sectional schematic diagram of a trench MOSFET device in another preferred embodiment of this application; Figure 6 This is a VDS waveform diagram during the testing process of the solution in this application; Figure 7 This is a schematic diagram illustrating the provision of a substrate and the growth of an epitaxial layer on the substrate during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 8 This is a schematic diagram of the formation of a base region in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 9This is a schematic diagram of the formation of a well region and a source region in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 10 This is a schematic diagram of the formation of a well region and a source region in the epitaxial layer during the fabrication of a trench MOSFET device according to some other preferred embodiments of this application; Figure 11 This is a schematic diagram of the formation of a base region in the epitaxial layer during the fabrication of a trench MOSFET device according to some other preferred embodiments of this application; Figure 12 This is a schematic diagram of the formation of a JTE region in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 13 This is a top view of the formation of the JTE region in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 14 yes Figure 13 Sectional view along line BB; Figure 15 This is a schematic diagram of the etching of trenches in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 16 This is a schematic diagram of the second buried layer injected at the bottom of the trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 17 This is a schematic diagram of the formation of a protective layer on the upper surface of the epitaxial layer and the inner wall of the trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 18 This is a schematic diagram of the formation of a gate oxide layer on the upper surface of the epitaxial layer and the inner wall of the trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 19 This is a schematic diagram of polysilicon deposition in a trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 20 This is a schematic diagram of the formation of an isolation layer and a metal interconnect layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 21 This is a top view of the formation of a metal interconnect layer in the recessed contact area during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 22 This is a schematic diagram illustrating the formation of a source metal layer, a passivation layer, a resin layer, and a drain metal layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application.

[0029] Explanation of reference numerals in the attached figures: 10. Substrate; 20. Epitaxial layer; 30. Base region; 31. First channel region; 32. Second channel region; 33. Source region; 40. Peripheral JTE region; 41. In-plane JTE region; 42. Second buried implantation layer; 50. Gate; 51. Trench; 52. Gate oxide layer; 60. Isolation layer; 61. Metal interconnect layer; 70. Source metal layer; 80. Passivation layer; 81. Resin layer; 90. Drain metal layer. Detailed Implementation

[0030] The following will refer to the appendices in the embodiments of the present invention. Figure 1-22 The technical solutions in the embodiments of the present invention are clearly and completely described herein. Obviously, the described embodiments are only a part of the embodiments for understanding the inventive concept of the present invention, and cannot represent all embodiments, nor are they interpreted as the only embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art under the premise of understanding the inventive concept of the present invention are within the protection scope of the present invention.

[0031] It should be noted that if directional indicators (such as up, down, left, right, front, back, etc.) are involved in the embodiments of the present invention, these directional indicators are only used to explain the relative positional relationships and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. To better understand the technical solution of the present invention, the trench MOSFET device for reducing high-frequency switching noise and its manufacturing method of the present invention will be described and explained in further detail below, but this should not be construed as limiting the scope of protection of the present invention.

[0032] In specific applications of the variations, the source of the example can be used as the drain, and the drain of the example can be used as the source. The source and drain represent the relative flow direction of electrons. When the source described in the specification is used as the source, the drain described in the specification must be used as the drain; when the drain described in the specification is used as the drain, the drain described in the specification must be used as the source. For ease of understanding of the technical solution of this application, the specification and the scope of protection still use "source" and "drain," but in fact, they are not limited to source and drain, but rather use a first electrode and a second electrode that represent two different potential poles. Therefore, those skilled in the art can interchange the "source" and "drain" of the semiconductor device after understanding the technical solution of this invention, and the scope of protection of this invention naturally includes such equivalent interchange.

[0033] The accompanying drawings only show the common parts of multiple embodiments; differences or distinctions are described in words or presented in comparison with the drawings. Based on industry characteristics and the nature of the technology, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination thereof described below can characterize the same embodiment, or whether multiple mutually exclusive technical features can only characterize different variations of the embodiment.

[0034] Furthermore, the first doping type in this application is the opposite of the second doping type. When the first doping type is N-type, the second doping type is P-type; when the first doping type is P-type, the second doping type is N-type. The embodiments in this application are described with the first doping type being N-type and the second doping type being P-type.

[0035] The inventors of this application have discovered that switching noise is a common problem in high-frequency power switching circuits, especially when the high-side MOSFET is on and the low-side MOSFET is off, resulting in voltage overshoot and oscillation. Excessive overshoot can lead to mis-conduction or avalanche breakdown, while oscillation can cause component failure. Figure 1 As shown, Figure 1 This is a VDS waveform diagram showing overshoot and oscillation phenomena in related technologies.

[0036] The trench MOSFET device for reducing high-frequency switching noise provided in the embodiments of this application refers to... Figure 2 The trench MOSFET device includes a substrate 10, an epitaxial layer 20, a doped region, a JTE region, a gate 50, a first buried implantation layer, a second buried implantation layer 42, and a source metal layer 70. The materials of the substrate 10 and the epitaxial layer 20 include, but are not limited to, SiC. The epitaxial layer 20 is formed on the upper surface of the substrate 10 and is of the first doping type, namely, an N-type epitaxial layer 20.

[0037] The doped region includes a base region 30, a well region, and a source region 33. In one embodiment, the base region 30 is formed by implanting ions into the epitaxial layer 20. The base region 30 is a second doping type, namely a P+ pillar. The formation method of the P+ pillar includes, but is not limited to, channeling implantation or high-energy implantation.

[0038] The well region and source region 33 are disposed within the epitaxial layer 20. The depth of the base region 30 is greater than the depth of the well region, and the sides of the well region and source region 33 are connected to the base region 30. Specifically, the well region includes a first channel region 31 and a second channel region 32 from bottom to top. The first channel region 31 is of the second doping type, and the second channel region 32 is of the first doping type. The source region 33 is disposed above the second channel region 32. Simultaneously, the doping concentration of the base region 30 is higher than that of the first channel region 31, and the doping concentration of the second channel region 32 is lower than that of the source region 33. The second channel region 32 constitutes a negative feedback resistor between the first channel region 31 and the source region 33, realizing gate-source breakdown voltage. Specifically, the first channel region 31 is a P- region, the second channel region 32 is an N- region, and the source region 33 is an N+ region.

[0039] Reference Figure 3 and Figure 4 In one embodiment, the JTE region is disposed within the epitaxial layer 20. The JTE region includes a peripheral JTE region 40 and an in-plane JTE region 41. The peripheral JTE region 40 surrounds the periphery of all base regions 30, and the upper surface of the peripheral JTE region 40 is exposed on the upper surface of the epitaxial layer 20. The in-plane JTE region 41 is located between adjacent base regions 30, and the two ends of the in-plane JTE region 41 are connected to the inner side of the peripheral JTE region 40.

[0040] Reference Figure 2 and Figure 3 A gate 50 is disposed between the base regions 30, and the bottom end of the gate 50 penetrates the well region and the source region 33. Specifically, the epitaxial layer 20 is etched to form a trench 51 penetrating the well region and the source region 33. The trench 51 is filled with polysilicon to form the gate 50. In addition, a gate oxide layer 52 is disposed between the polysilicon and the inner wall of the trench 51.

[0041] In a preferred embodiment, the angle between the sidewall of the trench 51 and the horizontal plane is 80°-91°, preferably 86°, and the connection between the sidewall of the trench 51 and the bottom of the trench 51 is arc-shaped. This effectively reduces the electric field concentration effect caused by sharp angles, lowers the local electric field intensity, and improves the device's withstand voltage and reliability. Simultaneously, this design also helps to mitigate the stress generated during the etching process of the trench 51, prevents crack formation, and further enhances the overall performance of the device.

[0042] Reference Figure 2The in-plane JTE region 41 is located at the bottom of the trench 51. The first implanted buried layer is formed by the in-plane JTE region 41. Therefore, the JTE region and the first implanted buried layer share the implantation step, which can reduce the number of implantations and simplify the process flow. Before setting the gate oxide layer 52, ions are implanted into the trench 51 through a mask to form the second implanted buried layer 42. The first implanted buried layer and the second implanted buried layer 42 are not connected to the base region 30. The first implanted buried layer is of the second doping type, and the second implanted buried layer 42 is of the first doping type. Specifically, the first implanted buried layer is a P-type region, and the second implanted buried layer 42 is an N-type region.

[0043] Optionally, the second implanted buried layer 42 can be vertically implanted to form a ring-shaped distribution at the bottom of the first implanted buried layer. Alternatively, by controlling the ion implantation angle, the second implanted buried layer 42 can be made denser on both sides and thinner at the bottom of the first implanted buried layer, thus forming a structure that is thin in the middle and thick at both sides. This structure can form an effective electric field shield at the bottom of the trench 51, reducing the concentration of large electric fields at the bottom of the trench 51, improving the device's voltage resistance and reliability. It can also further enhance the electric field dispersion effect at the bottom of the trench 51, effectively reducing the local electric field intensity and improving the device's breakdown voltage and reliability.

[0044] Reference Figure 5 In another preferred embodiment, the depth of the base region 30 is shallower than the depth of the source region 33, and the second implanted buried layer 42 has a structure that is thin in the middle and thick at both sides. Furthermore, the two sides of the second implanted buried layer 42 extend directly below the base region 30. This design allows the distance between the trenches 51 to be smaller, the cell unit size to be smaller, and the on-resistance to be smaller; at the same time, the second implanted buried layer 42 can be wider, further reducing the on-resistance.

[0045] Reference Figure 2 and Figure 3 After the trench 51 is filled with polysilicon, an isolation layer 60 is formed on the upper surface of the epitaxial layer 20, and the isolation layer 60 and the upper surface of the epitaxial layer 20 are etched to form a recessed contact area on the upper surface of the epitaxial layer 20. The recessed contact area is filled with a metal interconnect layer 61, which is connected to the source metal layer 70, the base region 30, the source region 33, and the peripheral JTE region 40.

[0046] Optionally, the material of the isolation layer 60 includes, but is not limited to, SiO2, SiN, or a combination thereof; the metal interconnect layer 61 is formed by depositing metal in the recessed contact area and then subjecting it to high temperature, and the deposited metal includes, but is not limited to, Ni and Ti; the material of the source metal layer 70 includes, but is not limited to, pure Al / Cu and its alloys (AlSi alloy, AlCu alloy and AlSiCu alloy) or their stacked combinations.

[0047] In addition, a passivation layer 80 is disposed on the upper surface of the source metal layer 70. Optionally, the material of the passivation layer 80 includes, but is not limited to, SiO, SiN, and combinations thereof. The thickness of the passivation layer 80 is 0.1µm-20µm. A resin layer 81 is disposed on the upper surface of the passivation layer 80. The material of the resin layer 81 can be at least one of polyimide, polyamide, and polybenzoxazole. The thickness of the resin layer 81 is 1µm-50µm, and in this embodiment, the preferred thickness range is 150µm-200µm. The thickness of the substrate 10 ranges from 80µm to 250µm, and in this embodiment, the preferred thickness range is 150µm-200µm.

[0048] A drain metal layer 90 is disposed on the lower surface of the substrate 10. Optionally, the material of the drain metal layer 90 includes, but is not limited to, Ti / Ni / Ag / Pd / Au and their alloys or combinations.

[0049] The implementation principle of this embodiment is as follows: By forming P-type and N-type regions at the bottom of trench 51, the bottom of trench 51 is effectively protected, the influence of large electric fields is reduced, and the device's voltage resistance is improved. Simultaneously, the JTE region effectively adjusts the electric field distribution, preventing breakdown. The grounding method of the JTE and P-type regions further addresses voltage overshoot and oscillation issues in high-frequency switching noise. The overall device structure is simple, with fewer process steps, effectively improving the device's reliability and performance. (Refer to...) Figure 6 As can be seen, the improved switch noise oscillation amplitude is small and quickly stops oscillating.

[0050] The method for manufacturing a trench MOSFET device with reduced high-frequency switching noise provided in this application includes the following steps: Reference Figure 7 S10, a substrate 10 is provided, and an epitaxial layer 20 of a first doping type is formed on the upper surface of the substrate 10. Optionally, an N-type epitaxial layer 20 is used, and the substrate 10 and its material can be SiC or other suitable materials. The growth of the epitaxial layer 20 can be achieved by chemical vapor deposition (CVD) or other suitable methods to ensure the uniformity and doping concentration of the epitaxial layer 20.

[0051] S20. Ions are sequentially implanted into the epitaxial layer 20 to form a base region 30, a well region, and a source region 33 within the epitaxial layer 20.

[0052] In one embodiment, reference is made to Figure 8 and Figure 9 Step S20 includes: S21. Ions are implanted into the epitaxial layer 20 to form a base region 30 of the second doped type. Specifically, a mask is formed on the epitaxial layer 20, and then the required openings are formed on the mask through photolithography and etching processes. Finally, multiple parallel P+ base regions 30 are formed by ion implantation.

[0053] S22. Ions are implanted into the epitaxial layer 20 to form a first channel region 31 of the second doping type.

[0054] S23. Ions are implanted into the epitaxial layer 20 to form a second channel region 32 of the first doping type, and the first channel region 31 and the second channel region 32 are combined to form a well region.

[0055] S24. Ions are implanted into the epitaxial layer 20 to form a source region 33 of the first doped type. Specifically, the well region and the source region 33 are disposed within the epitaxial layer 20, the depth of the base region 30 is deeper than the depth of the well region, and the sides of the well region and the source region 33 are adjacent to the base region 30. Optionally, the formation methods of the first channel region 31, the second channel region 32, and the source region 33 include, but are not limited to, implantation or diffusion. The first channel region 31 is a P- region, the second channel region 32 is an N- region, and the source region 33 is an N+ region.

[0056] The base region 30 has a higher doping concentration than the first channel region 31, and the second channel region 32 has a lower doping concentration than the source region 33, so as to form a negative feedback resistor between the first channel region 31 and the source region 33, thereby realizing gate-source breakdown voltage.

[0057] In another preferred embodiment, refer to Figure 10 and Figure 11 Step S20 includes: S25. A first channel region 31 of a second doped type, a second channel region 32 of a first doped type, and a source region 33 of a first doped type are sequentially formed in the epitaxial layer 20 by epitaxy, and the first channel region 31 and the second channel region 32 are combined to form a well region; or a first channel region 31 of a second doped type is formed in the epitaxial layer 20 by implantation, and a second channel region 32 of a first doped type and a source region 33 of a first doped type are formed in the epitaxial layer 20 by epitaxy, and the first channel region 31 and the second channel region 32 are combined to form a well region.

[0058] S26. Ions are implanted into the epitaxial layer 20 to form a base region 30 of the second doping type. The doping concentration of the base region 30 is higher than that of the first channel region 31, and the doping concentration of the second channel region 32 is lower than that of the source region 33, thus forming a negative feedback resistor between the first channel region 31 and the source region 33, achieving gate-source breakdown voltage. This embodiment forms the well region and source region 33 epitaxially, allowing for more precise control of the concentration and thickness of each region in the well region and source region 33, and ensuring that the formation of each region does not interfere with each other.

[0059] Reference Figure 12 and Figure 13S30. Ions are implanted into the epitaxial layer 20 to form a peripheral JTE region 40. The peripheral JTE region 40 surrounds the periphery of all base regions 30, and the upper surface of the peripheral JTE region 40 is exposed on the upper surface of the epitaxial layer 20. Ions are implanted into the epitaxial layer 20 to form an in-plane JTE region 41, such that the in-plane JTE region 41 is located between adjacent base regions 30 and the two ends of the in-plane JTE region 41 are connected to the inner side of the peripheral JTE region 40.

[0060] Optionally, the peripheral JTE region 40 can be formed first, and then the in-plane JTE region 41 can be formed, so that the in-plane JTE region 41 is directly connected to the peripheral JTE region 40; or the peripheral JTE region 40 and the in-plane JTE region 41 can be formed directly through a mask.

[0061] Reference Figure 14 and Figure 15 S40, etch the epitaxial layer 20 to form a trench 51 that penetrates the well region and the source region 33. The trench 51 removes the upper structure of the in-plane JTE region 41, leaving only the in-plane JTE region 41 at the bottom of the trench 51. The in-plane JTE region 41 at the bottom of the trench 51 forms a first implanted buried layer of the second doping type. The two ends of the in-plane JTE region 41 are connected to the surrounding JTE region 40.

[0062] Optionally, the bottom of the groove 51 can be flat or round, the angle between the sidewall of the groove 51 and the horizontal plane is 80°-91°, preferably 86°, and the connection between the sidewall of the groove 51 and the bottom of the groove 51 is arc-shaped to reduce stress concentration.

[0063] Reference Figure 16 S50, ions are implanted into the bottom of trench 51 to form a second implanted buried layer 42 of the first doped type. The second implanted buried layer 42 is located on the outer periphery of the first implanted buried layer, and the first implanted buried layer and the second implanted buried layer 42 are not in contact with the base region 30. In this embodiment, the first implanted buried layer is P-type, and the second implanted buried layer 42 is N-type.

[0064] In one embodiment, step S50 includes: S51. A mask is formed on the upper surface of the epitaxial layer 20, and the mask also covers the sidewalls of the trench 51. Specifically, the mask extends to the arcuate bottom of the trench 51.

[0065] S52. Ions are implanted to form a second implanted layer 42 at the bottom of the trench 51. By controlling the implantation angle, the second implanted layer 42 is made to have a structure that is thin in the middle and thick at both sides; or by vertical implantation, the second implanted layer 42 is made to be distributed in a ring shape at the bottom of the first implanted layer. The mask is then removed.

[0066] After step S50, the following is also included: Reference Figure 17 S53. Using photoresist or sputtered carbon, a protective layer is formed on the upper surface of the epitaxial layer 20 and the inner wall of the trench 51, and then the internal structure of the trench MOSFET device is activated at high temperature. The protective layer includes, but is not limited to, a photoresist protective layer, a carbon protective layer, and an aluminum nitride protective layer. In this embodiment, the activation temperature range is 1400-2100℃, with a preferred range of 1700-1800℃. The protective layer is removed after activation.

[0067] Reference Figure 18 and Figure 19 Before step S60, the following are also included: S58. The surface of the epitaxial layer 20 is oxidized at high temperature, and then the sacrificial oxide layer on the surface is removed.

[0068] S59. A gate oxide layer 52 is formed on the surface by means of thermal oxidation or chemical vapor deposition.

[0069] S60. Polysilicon is deposited in the trench 51 to form the gate 50. Specifically, a layer of polysilicon is deposited in the trench 51 and on the upper surface of the epitaxial layer 20, and then the polysilicon in the trench 51 is retained by an etching process. The polysilicon in the trench 51 forms the required gate 50.

[0070] Reference Figure 20 and Figure 21 After step S60, the following steps are also included: S61. An isolation layer 60 is provided on the upper surface of the epitaxial layer 20.

[0071] S62. A mask is formed on the upper surface of the isolation layer 60. An opening is formed on the mask by photolithography and etching. Holes are drilled in the isolation layer 60 by etching.

[0072] S63. After the isolation layer 60 is removed, the mask is retained. Etching continues downwards on this basis to form a recessed contact area. After the recessed contact area is formed, the mask is removed. Specifically, the recessed contact area includes the annular region on the upper surface of the peripheral JTE region 40 and parts of the upper surface of the base region 30 and source region 33.

[0073] S64. The recessed contact area is filled with metal to form a metal interconnect layer 61. Optionally, the deposited metal includes, but is not limited to, Ni and Ti.

[0074] Reference Figure 21 and Figure 22In step S70, a source metal layer 70 is formed on the upper surface of the epitaxial layer 20. The metal interconnect layer 61 is connected to the source metal layer 70, the base region 30, the source region 33, and the peripheral JTE region 40, respectively. Specifically, the material of the source metal layer 70 includes, but is not limited to, pure Al / Cu and its alloys (AlSi alloy, AlCu alloy, and AlSiCu alloy) or their stacked combinations.

[0075] Reference Figure 22 S80, a passivation layer 80 is provided on the upper surface of the source metal layer 70, and the thickness of the passivation layer 80 is 0.1um-20um. Optionally, the material of the passivation layer 80 includes, but is not limited to, SiO, SiN and combinations thereof.

[0076] S81. A resin layer 81 is formed on the upper surface of the passivation layer 80, and the thickness of the resin layer 81 is 1µm-50µm. Optionally, the material of the passivation layer 80 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the preferred thickness range is 150µm-200µm.

[0077] S90. Thinning of substrate 10, the thickness of substrate 10 after thinning is 80um-250um. In this embodiment, the preferred thickness range is 150um-200um.

[0078] S91. A drain metal layer 90 is formed on the lower surface of the substrate 10. The material of the drain metal layer 90 includes, but is not limited to, Ti / Ni / Ag / Pd / Au and their alloys or combinations.

[0079] Reference Figure 5 In another preferred embodiment, the depth of the base region 30 is shallower than the depth of the source region 33; step S50 includes: S54. Control the ion implantation angle so that the second implanted buried layer 42 has a structure that is thin in the middle and thick on both sides, with the two sides of the second implanted buried layer 42 extending directly below the base region 30. This design allows the distance between the trenches 51 to be reduced, the cell unit size to be reduced, and the on-resistance to be reduced; at the same time, the second implanted buried layer 42 can be wider, further reducing the on-resistance.

[0080] The implementation principle of this embodiment is as follows: The above-described fabrication method enables the fabrication of a trench MOSFET device with reduced high-frequency switching noise. This method effectively protects the bottom of trench 51 by forming P-type and N-type regions at the bottom of trench 51, reducing the influence of large electric fields and improving the device's voltage resistance. Simultaneously, the JTE region effectively regulates the electric field distribution, preventing breakdown. The grounding method of the JTE and P-type regions further addresses voltage overshoot and oscillation issues in high-frequency switching noise. The entire fabrication process is simple, with few steps, effectively improving the device's reliability and performance.

[0081] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A trench MOSFET device for reducing high-frequency switching noise, characterized in that, include: Substrate (10), with an epitaxial layer (20) of the first doping type formed on its upper surface; The doped region includes a base region (30), a well region, and a source region (33), wherein the base region (30), the well region, and the source region (33) are disposed within the epitaxial layer (20); JTE regions are located within the epitaxial layer (20). The JTE regions include peripheral JTE regions (40) and in-plane JTE regions (41). The peripheral JTE regions (40) surround the periphery of all base regions (30). The upper surface of the peripheral JTE regions (40) is exposed on the upper surface of the epitaxial layer (20). The in-plane JTE regions (41) are located between adjacent base regions (30) and the two ends of the in-plane JTE regions (41) are connected to the inner side of the peripheral JTE regions (40). A gate (50) is disposed between base regions (30) and the bottom end of the gate (50) extends through the well region and the source region (33). A first buried layer and a second buried layer (42) are formed at the bottom of the gate (50). The first buried layer is formed by the in-plane JTE region (41). The second buried layer (42) is disposed on the side of the first buried layer away from the gate (50). The first buried layer and the second buried layer (42) are not connected to the base region (30). The first buried layer is of the second doping type, and the second buried layer (42) is of the first doping type, which is different from the second doping type. A source metal layer (70) is formed on the upper surface of the epitaxial layer (20) to connect the base region (30), the source region (33) and the surrounding JTE region (40).

2. The trench MOSFET device for reducing high-frequency switching noise according to claim 1, characterized in that: The epitaxial layer (20) has a trench (51) etched in it, and the gate (50) is filled in the trench (51). The angle between the sidewall of the trench (51) and the horizontal plane is 80°-91°, and the connection between the sidewall of the trench (51) and the bottom of the trench (51) is arc-shaped.

3. The trench MOSFET device for reducing high-frequency switching noise according to claim 1, characterized in that: The depth of the base region (30) is shallower than the depth of the source region (33), and the second injection layer (42) has a structure that is thin in the middle and thick on both sides, with both sides of the second injection layer (42) extending directly below the base region (30).

4. The trench MOSFET device for reducing high-frequency switching noise according to claim 1, characterized in that: The depth of the base region (30) is greater than the depth of the well region. The well region is connected to the base region (30). The well region includes a first channel region (31) and a second channel region (32) arranged from bottom to top. The first channel region (31) is of the second doping type, and the second channel region (32) is of the first doping type. The base region (30) has a higher doping concentration than the first channel region (31), and the second channel region (32) has a lower doping concentration than the source region (33), so as to form a negative feedback resistor between the first channel region (31) and the source region (33) to realize gate-source breakdown voltage.

5. The trench MOSFET device for reducing high-frequency switching noise according to claim 1, characterized in that: The upper surface of the epitaxial layer (20) is etched with a recessed contact area, and the recessed contact area is filled with a metal interconnect layer (61). The metal interconnect layer (61) is connected to the source metal layer (70) and the base region (30), source region (33), and peripheral JTE region (40), respectively.

6. A method for fabricating a trench MOSFET device to reduce high-frequency switching noise, characterized in that, Includes the following steps: S10, Provide a substrate (10) and form an epitaxial layer (20) of a first doping type on the upper surface of the substrate (10); S20. Ions are implanted sequentially into the epitaxial layer (20) to form a base region (30), a well region and a source region (33) in the epitaxial layer (20). S30. Ions are implanted into the epitaxial layer (20) to form a peripheral JTE region (40), the peripheral JTE region (40) surrounds the periphery of all base regions (30), and the upper surface of the peripheral JTE region (40) is exposed on the upper surface of the epitaxial layer (20); Ions are implanted into the epitaxial layer (20) to form an in-plane JTE region (41), such that the in-plane JTE region (41) is located between adjacent base regions (30) and the two ends of the in-plane JTE region (41) are connected to the inner side of the peripheral JTE region (40); S40. Etch the epitaxial layer (20) to form a trench (51) that penetrates the well region and the source region (33). The trench (51) removes the upper structure of the in-plane JTE region (41) and retains only the in-plane JTE region (41) at the bottom of the trench (51). The in-plane JTE region (41) at the bottom of the trench (51) forms a first implanted buried layer of the second doping type. The first doping type is opposite to the second doping type. The two ends of the first implanted buried layer are connected to the surrounding JTE region (40). S50. Ions are implanted into the bottom of the trench (51) to form a second implanted buried layer (42) of the first doping type. The second implanted buried layer (42) is located on the outer periphery of the first implanted buried layer. The first implanted buried layer and the second implanted buried layer (42) are not in contact with the base region (30). S60. Polysilicon is deposited in the trench (51) to form a gate (50). S70. A source metal layer (70) is formed on the upper surface of the epitaxial layer (20) to connect the base region (30), the source region (33), and the surrounding JTE region (40).

7. The method for fabricating a trench MOSFET device for reducing high-frequency switching noise according to claim 6, characterized in that: The angle between the sidewall of the groove (51) and the horizontal plane is 80°-91°, and the connection between the sidewall of the groove (51) and the bottom of the groove (51) is arc-shaped.

8. The method for fabricating a trench MOSFET device for reducing high-frequency switching noise according to claim 6, characterized in that: The depth of the base region (30) is shallower than the depth of the source region (33); step S50 includes: S54. Control the ion implantation angle so that the second implantation buried layer (42) has a structure that is thin in the middle and thick on both sides, and the two sides of the second implantation buried layer (42) extend to the base region (30) directly below.

9. The method for fabricating a trench MOSFET device for reducing high-frequency switching noise according to claim 6, characterized in that, Step S20 includes: S21. Ions are implanted into the epitaxial layer (20) to form a base region (30) of the second doping type. S22. Ions are implanted into the epitaxial layer (20) to form a first channel region (31) of the second doping type. S23. Ions are implanted in the epitaxial layer (20) to form a second channel region (32) of the first doping type, and the first channel region (31) and the second channel region (32) are combined to form a well region; S24. Ions are implanted into the epitaxial layer (20) to form a source region (33) of the first doping type. The base region (30) has a higher doping concentration than the first channel region (31), and the second channel region (32) has a lower doping concentration than the source region (33), so as to form a negative feedback resistor between the first channel region (31) and the source region (33) to realize gate-source breakdown voltage.

10. The method for fabricating a trench MOSFET device for reducing high-frequency switching noise according to claim 6, characterized in that, Step S20 includes: S25. A first channel region (31) of the second doping type, a second channel region (32) of the first doping type, and a source region (33) of the first doping type are sequentially formed in the epitaxial layer (20) by epitaxy, and the first channel region (31) and the second channel region (32) are combined to form a well region; or a first channel region (31) of the second doping type is formed in the epitaxial layer (20) by implantation, and a second channel region (32) of the first doping type and a source region (33) of the first doping type are formed in the epitaxial layer (20) by epitaxy, and the first channel region (31) and the second channel region (32) are combined to form a well region; S26. Ions are implanted into the epitaxial layer (20) to form a base region (30) of the second doping type. The base region (30) has a higher doping concentration than the first channel region (31), and the second channel region (32) has a lower doping concentration than the source region (33), so as to form a negative feedback resistor between the first channel region (31) and the source region (33) to realize gate-source breakdown voltage.

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