LDMOS device and method of manufacturing the same
By introducing a combination of trench contact structure, silicide barrier structure, and silicon local oxidation structure into LDMOS devices to form a field plate structure, the breakdown voltage and parasitic leakage current problems are solved, and device size reduction and performance improvement are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2026-02-10
- Publication Date
- 2026-06-23
AI Technical Summary
Existing LDMOS devices have limitations in optimizing on-resistance and improving breakdown voltage, and the local silicon oxide structure is susceptible to the effects of etching processes, which affect device performance and reliability.
A field plate structure is formed by combining a trench-type contact structure with a silicide barrier structure and a silicon local oxidation structure. The drain electric field is dispersed by the trench-type contact structure, and isolation is achieved by combining the silicide barrier structure and the silicon local oxidation structure, thereby optimizing the electric field distribution.
This improves the breakdown voltage and high-voltage reliability of LDMOS devices, while reducing device size, lowering on-resistance, and enhancing device performance.
Smart Images
Figure CN122269760A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an LDMOS device and its fabrication method. Background Technology
[0002] In semiconductor manufacturing processes, laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used due to their high breakdown voltage and low on-resistance. Most high-voltage LDMOS devices employ field plate (FP) technology to optimize the peak electric field.
[0003] Please see Figure 1 This is a schematic cross-sectional view of an existing LDMOS device employing field plate technology. The essence of field plate technology is to cover the drain region with a metal field plate 12, isolated from the silicon substrate 10 by an oxide layer 11, and utilize electric field coupling to disperse the electric field concentration at the drain edge. The dashed line in the figure indicates the depletion boundary. The basic principle of field plate technology is to introduce additional charge to reduce the original electric field peak. Applying different potentials (Bais) to the field plate causes the space charge region to extend into or out of the drift region.
[0004] Please see Figure 2 The diagram shows a cross-sectional view of an LDMOS device with a LOCOS structure. The drain side of an LDMOS device can isolate adjacent components through a Local Oxidation of Silicon (LOCOS) structure 21. That is, the LOCOS structure can serve as the field oxygen in the drift region of a high-voltage LDMOS device, improving the surface electric field and increasing the device's breakdown voltage. However, the area of the local oxide structure not covered by the gate structure is easily affected by etching processes in semiconductor fabrication, leading to excessive oxide loss and impacting device performance and reliability. Furthermore, simultaneously optimizing the on-resistance (Ron) and increasing the breakdown voltage (BV) is limited by the MOS transistor size and surface electric field strength; therefore, this type of LDMOS can only achieve a high BV by sacrificing device area. Summary of the Invention
[0005] The purpose of this invention is to provide an LDMOS device and its fabrication method, which can improve the breakdown voltage of LDMOS, while reducing the device size, reducing the on-resistance of the device, and reducing the chip area.
[0006] To achieve the above objectives, the present invention provides an LDMOS device, comprising: a substrate, wherein an active region is defined in the substrate by an isolation structure, a drift region and a body region are formed in the active region at intervals, a silicon local oxide structure is formed in the drift region, and the silicon local oxide structure is exposed at the top of the drift region and divided into a first region and a second region; a drain is formed in the drift region; a source is formed in the body region; a gate structure is formed on the substrate, the gate structure covers a portion of the body region and the first region covering the silicon local oxide structure, and the gate structure is isolated from the drain through the silicon local oxide structure; a silicide barrier structure covers the second region of the silicon local oxide structure and extends to cover a portion of the gate structure; and a trench contact structure is in contact with the region of the silicide barrier structure covering the second region of the silicon local oxide structure, wherein the trench contact structure, the silicide barrier structure, and the silicon local oxide structure together serve as the field plate structure of the LDMOS device.
[0007] In some embodiments, the minimum total thickness of the silicide barrier structure and the silicon localized oxide structure below the trench-type contact structure is greater than 500 angstroms.
[0008] In some embodiments, the orthographic projections of the silicon localized oxide structure, the silicide barrier structure, and the trench-type contact structure onto the active region are all elongated strips extending along a first direction, and in the first direction, the silicon localized oxide structure, the silicide barrier structure, and the trench-type contact structure all have portions protruding beyond the active region; wherein, the first direction is parallel to the surface of the active region.
[0009] To achieve the above objectives, the present invention also provides a method for fabricating an LDMOS device, the method comprising the following steps: providing a substrate, the substrate including a substructure, an active region defined therein by an isolation structure, a drift region and a body region formed therein at intervals, a silicon local oxide structure formed therein in the drift region, the silicon local oxide structure being exposed at the top of the drift region and divided into a first region and a second region, a drain electrode also formed therein in the drift region, an active electrode formed therein in the body region, a gate structure formed on the substrate, the gate structure covering a portion of the body region. The first region of the silicon local oxide structure is covered, and the gate structure is isolated from the drain through the silicon local oxide structure; a silicide barrier structure is formed, which covers the second region of the silicon local oxide structure and extends to cover part of the gate structure; and a trench contact structure is formed, which contacts the region of the silicide barrier structure that covers the second region of the silicon local oxide structure, and the trench contact structure, the silicide barrier structure, and the silicon local oxide structure together serve as the field plate structure of the LDMOS device.
[0010] The above technical solution combines a trench-type contact structure with the silicide barrier structure and the silicon localized oxide structure to form a field plate structure. This utilizes the silicide barrier structure and the silicon localized oxide structure for isolation, while the trench-type contact structure disperses the drain electric field, solving the breakdown voltage and parasitic leakage current problems of high-voltage LDMOS devices, improving the breakdown voltage, and effectively enhancing the high-voltage reliability of LDMOS devices. By designing a trench-type contact structure with a larger size, the contact area between the trench-type contact structure and the silicide barrier structure is increased. This allows the trench-type contact structure, silicide barrier structure, and silicon localized oxide structure to better serve as the field plate structure of the LDMOS device. Furthermore, the trench-type contact structure can better disperse the drain electric field, solving the breakdown voltage and parasitic leakage current problems of high-voltage LDMOS devices, improving the breakdown voltage, and effectively enhancing the high-voltage reliability of LDMOS devices. By adjusting the longitudinal electric field of the LDMOS device and optimizing the electric field distribution at the drain terminal, the size of some components can be reduced while maintaining the breakdown voltage, lowering the specific on-resistance, and improving device performance. Attached Figure Description
[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1This is a schematic diagram of a cross-section of an existing LDMOS device using field plate technology; Figure 2 This is a schematic diagram of a cross-section of an LDMOS device with a LOCOS structure. Figure 3 This is a schematic cross-sectional view of an LDMOS device provided in an embodiment of the present invention; Figure 4 This is a top view schematic diagram of an LDMOS device provided in an embodiment of the present invention; Figure 5 This is a comparison diagram of field strength distribution provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the dimensions of some components in an LDMOS device provided in an embodiment of the present invention; Figure 7 A flowchart illustrating a method for fabricating an LDMOS device according to an embodiment of the present invention; Figures 8A to 8G This is a schematic diagram of the device structure formed by the main steps of the fabrication method of the LDMOS device described in this invention.
[0013] Explanation of reference numerals in the attached figures: 10. Silicon substrate; 11. Oxide layer; 12. Metal field plate; 21. LOCOS structure; 300, Substrate; 301, Isolation structure; 302, Active region; 303. Drift region; 304. Body region; 3041. Back base region; 31. Localized oxidation structure of silicon; 311. First region; 312. Second region; 32. Drain; 33. Source; 34. Gate structure; 341. Polysilicon gate; 342. Gate oxide layer; 343. Sidewall; 35. Silicide barrier structure; 36. Groove-type contact structure; 361. Adhesive layer; 362. Filler layer; 37. Conventional contact structure; 38. Patterned metal silicide layer; 39. Interlayer dielectric layer; 800. Mask layer; 801. Groove type contact groove; 802. Conventional type contact hole. Detailed Implementation
[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0015] Please refer to the following: Figures 3-6 ,in, Figure 3 This is a schematic cross-sectional view of an LDMOS device provided in an embodiment of the present invention; Figure 4 This is a top view schematic diagram of an LDMOS device provided in an embodiment of the present invention; Figure 5 This is a comparison diagram of field strength distribution provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the dimensions of some components in an LDMOS device provided in an embodiment of the present invention.
[0016] like Figures 3-4 As shown, the LDMOS device includes: a substrate 300, a silicon local oxidation structure 31, a drain 32, a source 33, a gate structure 34, a silicide barrier structure 35, and a trench contact structure 36.
[0017] In this embodiment, an active region 302 is defined in the substrate 300 by an isolation structure 301; the active region 302 has a drift region 303 and a body region 304 formed at intervals. In some embodiments, the substrate 300 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; it may also be a stacked structure, such as a silicon / silicon-germanium stack. In some embodiments, an active region 302 is defined between two adjacent isolation structures 301, and the isolation structure 301 is used to isolate the active region 302 from other components in the substrate 300. The isolation structure 301 may be a shallow trench isolation (STI) structure, which includes, but is not limited to, an oxide isolation structure or a composite isolation structure of oxide and nitride.
[0018] In this embodiment, the silicon local oxide structure 31 is formed in the drift region 303, and the silicon local oxide structure 31 is exposed at the top of the drift region 303, dividing it into a first region 311 and a second region 312. The drain electrode 32 is formed in the drift region 303; the source electrode 33 is formed in the body region 304. In this embodiment, both the drift region 303 and the body region 304 are formed within the active region 302 defined by two adjacent isolation structures 301, and the drift region 303 is close to one of the two adjacent isolation structures 301, while the body region 304 is close to the other isolation structure of the two adjacent isolation structures 301.
[0019] In this embodiment, the drift region 303 has a first type of conductivity, the body region 304 has a second type of conductivity, and the source 33 and drain 32 have a first type of conductivity. In some embodiments, the first type of conductivity is N-type conductivity, and the second type of conductivity is P-type conductivity; that is, the drift region 303 is an N-type drift region, and the body region 304 is a P-well region, thereby forming an NMOS transistor. In some embodiments, the source 33 and drain 32 may also have a second type of conductivity, for example, P-type conductivity, thereby forming a PMOS transistor.
[0020] In this embodiment, the gate structure 34 is formed on the substrate 300. The gate structure 34 covers a portion of the body region 304 and the first region 311 of the silicon local oxide structure 31, and the gate structure 34 is isolated from the drain 32 through the silicon local oxide structure 31. Specifically, the source 33 and the drain 32 are formed on both sides of the gate structure 34. In this embodiment, the gate structure 34 may include a polysilicon gate 341, a gate oxide (GOX) layer 342 formed between the polysilicon gate 341 and the substrate 300, and a sidewall 343 formed on the sidewalls of the polysilicon gate 341 and the gate oxide layer 342; the sidewall 343 on one side of the gate structure 34 is formed on the first region 311 of the silicon local oxide structure 31.
[0021] In this embodiment, the LDMOS device further includes a back base region 3041 with second-type conductivity. The back base region 3041 is formed in the body region 304 and adjacent to the side of the source 33 away from the gate structure 34. When the formed MOS transistor is an NMOS transistor, that is, the source 33 has N-type conductivity, the back base region 3041 has P-type conductivity, serving as the P-well terminal of the NMOS transistor. Specifically, the back base region 3041 is formed between the isolation structure 301 in the substrate 300 and the source 33.
[0022] In this embodiment, the silicon local oxide structure 31 is formed in the drift region 303, and the silicon local oxide structure 31 is exposed at the top of the drift region 303, divided into a first region 311 and a second region 312; the first region 311 of the silicon local oxide structure 31 is covered by the gate structure 34, and the second region 312 of the silicon local oxide structure 31 is adjacent to the drain 32 on the side near the gate structure 34. That is, the gate structure 34 and the drain 32 are isolated by the silicon local oxide structure 31.
[0023] In some embodiments, the local oxidation of silicon (LOCOS) structure 31 is formed on the surface of the substrate 300 using a local oxidation of silicon (LOCOS) process to isolate transistor elements during chip manufacturing and reduce electrical interference between elements. The LOCOS process involves selectively oxidizing silicon using silicon nitride as a masking layer, embedding a thick oxide layer in the active region to form isolation between elements. The LOCOS structure 31, as a field oxide structure in the drift region of a high-voltage transistor, can also improve the surface electric field and increase the device's breakdown voltage.
[0024] In this embodiment, the silicide barrier structure 35 covers the second region 312 of the silicon local oxide structure 31 and extends to cover a portion of the gate structure 34. Specifically, the silicide barrier structure 35 covers the second region 312 of the silicon local oxide structure 31 and extends to cover the sidewall 343 of the gate structure 34 formed on the first region 311 of the silicon local oxide structure 31 and a portion of the polysilicon gate 341. By adding the silicide barrier structure 35 to the drift region 303 to cover the exposed portion of the silicon local oxide structure 31 not covered by the gate structure 34, the silicide barrier structure 35 and the silicon local oxide structure 31 together serve as the oxide layer of the field plate structure for isolation from the substrate 300. Meanwhile, during the subsequent etching and filling to form the trench contact structure 36, the silicide barrier structure 35 can reduce the loss of oxide in the silicon local oxidation structure 31, ensuring that the etching process will not penetrate the oxide layer of the field plate structure, and ensuring that the formed trench contact structure 36 is isolated from the substrate 300, the gate structure 34 and the drain 32, thereby improving device performance and reliability.
[0025] In some embodiments, the silicide barrier structure 35 is formed on the surface of the localized silicon oxide structure 31 using a silicide block (SAB) process. The SAB process can be implemented using conventional wafer fabrication processes, without increasing the manufacturing complexity of LDMOS devices. It can be achieved through conventional wafer fabrication processes, making it easy to implement and promote.
[0026] In some embodiments, the silicide barrier structure 35 can be achieved by silicon rich oxide (SRO) deposition, SRO+SiN deposition, or tetraethyl orthosilicate (TEOS) deposition. SRO is a dielectric thin film material, and TEOS is a colorless and transparent organosilicon compound.
[0027] In this embodiment, the silicide barrier structure 35 and the silicon localized oxide structure 31 are combined as the oxide layer of the field plate structure, providing dielectric support for the trench contact structure 36. The thick oxide layer formed by the combination of the silicide barrier structure 35 and the silicon localized oxide structure 31 ensures that the etching process will not etch through it. Simultaneously, the thick oxide layer can withstand high voltage and is not easily broken down, thus avoiding oxide layer breakdown caused by excessively strong local electric fields and improving device reliability. The silicide barrier structure 35 and the silicon localized oxide structure 31, combined as the field oxygen in the drift region of the high-voltage LDMOS device, can effectively isolate adjacent devices, improve device withstand voltage, and prevent parasitic leakage current from adjacent devices from causing the LDMOS device to be unable to maintain high-voltage bias. By introducing the trench contact structure 36, the longitudinal electric field of the LDMOS device can be adjusted, optimizing the electric field distribution at the drain 32, thereby reducing electric field concentration on the drain surface and preventing premature device breakdown due to excessive electric field concentration, thus improving the LDMOS withstand voltage.
[0028] In this embodiment, the trench contact structure (Trench CT) 36 is in contact with the region of the silicide barrier structure 35 that covers the second region 312 of the silicon local oxide structure 31. The trench contact structure 36, the silicide barrier structure 35, and the silicon local oxide structure 31 together serve as the field plate structure of the LDMOS device.
[0029] In this embodiment, as Figure 4 As shown, the orthographic projections of the silicon localized oxide structure 31, the silicide barrier structure 35, and the trench-type contact structure 36 onto the active region 302 are all elongated strips extending along the first direction D1; wherein, the areas of each strip are of the same order of magnitude, and the area of the strip is much larger than the area of the orthographic projection of a conventional contact structure onto the active region. The silicon localized oxide structure 31, the silicide barrier structure 35, and the trench-type contact structure 36 all have portions protruding beyond the active region 302 along the first direction D1; wherein, the first direction D1 is parallel to the surface of the active region 302. By designing the trench-type contact structure 36 with a larger size, the contact area between the trench-type contact structure 36 and the silicide barrier structure 35 is increased. As a result, the trench-type contact structure 36, the silicide barrier structure 35, and the silicon local oxidation structure 31 can better serve as the field plate structure of the LDMOS device. Furthermore, the trench-type contact structure 36 can better disperse the drain electric field, solve the breakdown voltage and parasitic leakage current problems of high-voltage LDMOS devices, improve the breakdown voltage, and effectively improve the high-voltage reliability of LDMOS devices.
[0030] In this embodiment, the orthogonal projection of the gate structure 34 (especially the polysilicon gate 341) onto the active region 302 is also an elongated strip extending along the first direction D1.
[0031] In this embodiment, the minimum total thickness of the silicide barrier structure 35 and the silicon local oxide structure 31 below the trench contact structure 36 is greater than 500 angstroms. Because the silicon local oxide structure 31 has a curved shape, the total thickness of the silicide barrier structure 35 and the silicon local oxide structure 31 ranges from approximately 600 to 1000 angstroms, ensuring that the etching process will not etch through it, thereby improving device performance and reliability.
[0032] This embodiment combines the trench contact structure 36 with the silicide barrier structure 35 and the silicon local oxidation structure 31 to form a field plate structure. This utilizes the silicide barrier structure 35 and the silicon local oxidation structure 31 for isolation, while the trench contact structure 36 disperses the drain electric field, solving the breakdown voltage and parasitic leakage current problems of high-voltage LDMOS devices, improving the breakdown voltage (BV), and effectively enhancing the high-voltage reliability of LDMOS devices. By adjusting the longitudinal electric field of the LDMOS device and optimizing the electric field distribution at the drain 32, the device can reduce the size (pitch) of some components while maintaining the breakdown voltage (BV), lowering the specific on-resistance and improving device performance.
[0033] In this embodiment, the trench-type contact structure 36 uses a Ti / TiN adhesive layer (Glue layer) 361 as sidewalls and a tungsten metal filling layer 362 to fill the sidewalls. The adhesive layer is a key structure in semiconductor processes used to enhance the bonding force between materials. It is typically composed of Ti and / or TiN and is mainly used between tungsten metal (W) and an interlayer dielectric layer (such as silicon oxide). Its function is to promote the diffusion of metal atoms through the Ti / TiN layer, forming a low-resistance contact, while simultaneously blocking the diffusion of oxidizing gases. A layered deposition method can be used, where the Ti layer is deposited using physical vapor deposition (PVD) and the TiN layer is deposited using chemical vapor deposition (CVD). This layered deposition reduces interfacial stress and achieves functional separation.
[0034] In this embodiment, the LDMOS device further includes: a plurality of conventional contact structures 37; the plurality of conventional contact structures 37 are respectively in contact with the drain 32, the source 33 and the gate structure 34 through a patterned metal silicide layer 38.
[0035] In this embodiment, the material of the conventional contact structure 37 is the same as that of the trench contact structure 36. For example, both use Ti / TiN to form an adhesive layer as sidewalls and tungsten metal to form a filling layer within the sidewalls. Specifically, the adhesive layer of the conventional contact structure 37 is applied between the tungsten metal and the interlayer dielectric layer, and between the metal silicide layer and the tungsten metal layer. Metal silicide is a semiconductor process used to reduce gate resistance and source / drain contact resistance. Its core process involves forming metal silicides in the polysilicon gate and source / drain regions. Specifically, this can be achieved by depositing a metal (such as Ti, Co, or Ni), followed by rapid thermal annealing (RTA) to induce a reaction between the metal and silicon to form silicides; selective wet etching is then used to remove unreacted metal layers, leaving only the silicides in the polysilicon gate and source / drain regions. This process achieves metallization of the gate edge and source / drain regions through self-alignment, while optimizing transistor performance, reducing contact resistance, and accommodating smaller device sizes.
[0036] In this embodiment, as Figure 4 As shown, the orthographic projection of the conventional contact structure 37 onto the active region 302 is a square, while the orthographic projection of the trench contact structure 36 onto the active region 302 is an elongated strip extending along a first direction; and the area of the elongated strip is on the order of magnitude larger than the area of the square. The first direction D1 is parallel to the surface of the active region 302. The conventional contact structure 37 is a small square, while the trench contact structure 36 is a relatively long strip; their shapes and areas differ significantly. That is, the trench contact structure 36 shown in this embodiment is an unconventional contact structure creatively proposed to optimize the performance and reliability of LDMOS devices, reduce contact resistance, and adapt to smaller device sizes.
[0037] like Figure 5As shown, (a) is the electric field distribution diagram of an LDMOS device using the trench contact structure 36, the silicide barrier structure 35, and the silicon local oxide structure 31 provided in this embodiment; (b) is the electric field distribution diagram of an LDMOS device using only the LOCOS structure. The redder the color in the diagram, the higher the electric field intensity, and circles mark high field intensity points. (c) quantifies the electric field magnitude at different locations, where the green curve (BSL) indicates the electric field distribution diagram of an LDMOS device using the trench contact structure 36, the silicide barrier structure 35, and the silicon local oxide structure 31 provided in this embodiment, and the red curve (Split) indicates the electric field distribution diagram of an LDMOS device using only the LOCOS structure. The high field intensity points in (a) are located at the junction of LOCOS and the gate oxide layer (left circle) and the right boundary of the Trench CT (right circle). The high field intensity points in (b) are located at the junction of LOCOS and the gate oxide layer (left circle) and the edge of the polysilicon (right circle). A comparison shows that the LDMOS device combining the trench contact structure 36, the silicide barrier structure 35, and the silicon local oxidation structure 31 provided in this embodiment effectively adjusts the longitudinal electric field of the device and optimizes the electric field distribution at the drain terminal due to the introduction of the trench contact structure. This reduces the electric field concentration on the drain surface and prevents premature breakdown caused by excessive electric field concentration. A comparison also shows that the LDMOS device combining the trench contact structure 36, the silicide barrier structure 35, and the silicon local oxidation structure 31 provided in this embodiment has a more uniform electric field distribution.
[0038] like Figure 6 As shown, the component dimensions (pitch) of the LDMOS device include: the distance 'a' from the conventional contact structure above the drain (Drain CT) to the polysilicon gate (Poly Gate), the dimension 'b' of the trench contact structure (Trench CT), and the dimension 'c' of the polysilicon gate. Based on the electric field optimization of the LDMOS device using the trench contact structure 36 combined with the silicide barrier structure 35 and the silicon local oxidation structure 31 provided in this embodiment, the dimensions of 'a', 'b', and 'c' can be reduced. Since the specific on-resistance Rsp is positively correlated with the dimensions of 'a', 'b', and 'c', reducing the dimensions of 'a', 'b', and 'c' significantly reduces the specific on-resistance, thereby further improving device performance.
[0039] Based on the same inventive concept, this invention also provides a method for fabricating an LDMOS device, which can produce the aforementioned LDMOS device.
[0040] Please refer to the following: Figures 7-8G , Figure 3 ,in, Figure 7This is a flowchart of a method for fabricating an LDMOS device according to an embodiment of the present invention. Figures 8A to 8G , Figure 3 This is a schematic diagram of the device structure formed by the main steps of the fabrication method of the LDMOS device described in this invention.
[0041] like Figure 7 As shown, the fabrication method of the LDMOS device in this embodiment includes the following steps: S1, providing a substrate, the substrate including a base, an active region defined in the substrate by an isolation structure, a drift region and a body region formed in the active region, a silicon local oxide structure formed in the drift region, and the silicon local oxide structure exposed at the top of the drift region dividing it into a first region and a second region, a drain electrode also formed in the drift region, an active electrode formed in the body region, a gate structure formed on the substrate, the gate structure covering part of the drift region and covering the silicon local oxide structure. S1, a first region of the oxide structure, wherein the gate structure is isolated from the drain through the silicon local oxide structure; S2, a silicide barrier structure is formed, the silicide barrier structure covers the second region of the silicon local oxide structure and extends to cover part of the gate structure; and S3, a trench contact structure is formed, the trench contact structure is in contact with the region of the silicide barrier structure covered by the second region of the silicon local oxide structure, the trench contact structure, the silicide barrier structure, and the silicon local oxide structure together serve as the field plate structure of the LDMOS device.
[0042] Please refer to steps S1 and... Figure 8D A substrate is provided, the substrate including a substrate 300, an active region 302 defined in the substrate 300 by an isolation structure 301, a drift region 303 and a body region 304 formed in the active region 302, the drift region 303 having a silicon local oxide structure 31 formed therein, and the silicon local oxide structure 31 being exposed at the top of the drift region 303 and divided into a first region 311 and a second region 312; a drain electrode 32 is also formed in the drift region 303; an active electrode 33 is formed in the body region 304; a gate structure 34 is formed on the substrate 300, the gate structure 34 covering a portion of the body region 304 and the first region 311 covering the silicon local oxide structure 31, and the gate structure 34 being isolated from the drain electrode 32 by the silicon local oxide structure 31.
[0043] In some embodiments, the provision of a substrate in step S1 can be implemented by the following steps S11 to S14.
[0044] Please refer to steps S11 and... Figure 8AA substrate 300 is provided, wherein an active region 302 is defined in the substrate 300 by an isolation structure 301; a silicon local oxidation structure 31 is formed in the active region 302. The process flow of the isolation structure 301 and the silicon local oxidation structure 31 can refer to the existing process flow, and will not be described in detail here.
[0045] Please refer to steps S12 and... Figure 8B A drift region 303 is formed in the substrate 100 surrounding the silicon local oxide structure 31. The drift region 303 is adjacent to one of the isolation structures 301. The process flow for forming the drift region can refer to the existing well implant process, and will not be described in detail here. The drift region 303 may have type I conductivity, such as N-type conductivity.
[0046] Please refer to steps S13 and... Figure 8C A gate structure 34 is formed on the substrate 300, and a body region 304 is formed in the active region 302. The gate structure 34 covers a portion of the body region 304 and a first region 311 covering the silicon local oxide structure 31. In this embodiment, the gate structure 34 may include a polysilicon gate 341, a gate oxide (GOX) layer 342 formed between the polysilicon gate 341 and the substrate 300, and a sidewall 343 formed on the sidewalls of the polysilicon gate 341 and the gate oxide layer 342; the sidewall 343 on one side of the gate structure 34 is formed on the first region 311 of the silicon local oxide structure 31.
[0047] In some embodiments, the steps of forming a gate structure 34 on the substrate 300 and forming a body region 304 in the active region 302 may specifically include: first forming a gate oxide layer 342 and a polysilicon gate 341 for the gate structure 34 on the substrate 300; lightly doping the polysilicon gate 341 under self-alignment to form a body region 304 in the active region 302; forming sidewalls 343 on the sidewalls of the gate oxide layer 342 and the polysilicon gate 341, wherein the sidewall 343 on one side of the gate structure 34 is formed on the first region 311 of the silicon local oxide structure 31. The process flow for forming the gate structure and the body region 304 can refer to existing process flows and will not be described in detail here. The body region 304 may have a second type of conductivity, such as P-type conductivity. In some embodiments, the first type of conductivity is N-type conductivity, and the second type of conductivity is P-type conductivity, that is, the drift region 303 is an N-type drift region, and the body region 304 is a P-well region.
[0048] Please refer to step S14 and... Figure 8DA drain 32 is formed in the drift region 303, a source 33 is formed in the body region 304, and a back base region 3041 is formed in the body region 304. Specifically, the source 33 and drain 32 are formed on both sides of the gate structure 34, and the gate structure 34 is isolated from the drain 32 by the silicon local oxide structure 31; the back base region 3041 is formed in the body region 304 and adjacent to the side of the source 33 away from the gate structure 34. The back base region 3041 may have type II conductivity. When the formed MOS transistor is an NMOS transistor, that is, the source 33 has N-type conductivity, then the back base region 3041 has P-type conductivity, so as to serve as the P-well region lead-out terminal of the NMOS transistor. The formation of the drain 32, source 33, and back base region 3041 can be achieved by ion implantation process, which can be referred to the existing process flow, and will not be described in detail here.
[0049] Please refer to step S2 and... Figure 8E A silicide barrier structure 35 is formed, which covers the second region 312 of the silicon local oxide structure 31 and extends to cover a portion of the gate structure 34. In some embodiments, the silicide barrier structure 35 is formed on the surface of the silicon local oxide structure 31 using an SAB process. In some embodiments, the silicide barrier structure 35 can be implemented by silicon-rich oxide (SRO) deposition, SRO+SiN deposition, or tetraethyl orthosilicate (TEOS) deposition.
[0050] In some embodiments, step S2, forming the silicide barrier structure 35, further includes: (21) forming a silicide barrier material layer, the silicide barrier material layer at least covering the second region 312 of the silicon local oxide structure 31 and a portion of the gate structure 34; (22) forming a patterned photoresist layer on the silicide barrier material layer, and etching the silicide barrier material layer with the patterned photoresist layer as a mask, retaining the silicide barrier material layer on the second region 312 of the silicon local oxide structure 31 and a portion of the gate structure 34 to form the silicide barrier structure 31. Specifically, the required mask pattern can be pre-determined by optimizing the layout and adding a silicide barrier structure pattern in the drift region, and the photoresist layer can be patterned with the mask pattern to form a patterned photoresist layer; (23) removing the patterned photoresist layer. In some embodiments, the silicide barrier material layer can be etched using a combination of dry and wet etching; for example, the silicide barrier material layer can be dry-etched first, followed by wet etching of the remaining silicide barrier material layer to etch the desired silicide barrier structure. In some embodiments, the patterned photoresist layer can be removed using a wet stripping method.
[0051] In this embodiment, the silicide barrier structure 35 and the silicon localized oxide structure 31 are combined as the oxide layer of the field plate structure, providing dielectric support for the subsequently formed trench contact structure 36. The thick oxide layer formed by the combination of the silicide barrier structure 35 and the silicon localized oxide structure 31 ensures that the etching process will not etch through it. Simultaneously, the thick oxide layer can withstand high voltage and is not easily broken down, thus avoiding oxide layer breakdown caused by excessively strong local electric fields and improving device reliability. The silicide barrier structure 35 and the silicon localized oxide structure 31, combined as the field oxygen in the drift region of the high-voltage LDMOS device, can effectively isolate adjacent devices, improve device withstand voltage, and prevent parasitic leakage current from adjacent devices from causing the LDMOS device to be unable to maintain high-voltage bias. By introducing the trench contact structure 36, the longitudinal electric field of the LDMOS device can be adjusted, optimizing the electric field distribution at the drain 32, thereby reducing electric field concentration on the drain surface and preventing premature device breakdown due to excessive electric field concentration, thus improving the LDMOS withstand voltage.
[0052] Please refer to step S2 and... Figure 3 A trench-type contact structure 36 is formed, which contacts the region of the silicide barrier structure 35 that covers the second region 312 of the silicon local oxide structure 31. The trench-type contact structure 36, the silicide barrier structure 35, and the silicon local oxide structure 31 together serve as the field plate structure of the LDMOS device.
[0053] In some embodiments, the formation of the groove-type contact structure 36 in step S3 can be specifically achieved by the following steps S31 to S33.
[0054] Please refer to steps S31 and... Figure 8F An inter-layer dielectric layer 39 is formed, which covers the substrate and the silicide barrier structure 35. Specifically, the inter-layer dielectric (ILD) is a crucial insulating material in semiconductor manufacturing, used to achieve electrical isolation, ensure the integrity of signal transmission and reduce parasitic capacitance, and provide planarization support, providing a smooth surface for subsequent processes through chemical mechanical polishing (CMP).
[0055] Please refer to steps S32 and... Figure 8GA mask layer 800 is formed on the interlayer dielectric layer 39, and the interlayer dielectric layer 39 is etched using the mask layer 800 as a shield to form a trench-type contact trench 801. The bottom of the trench-type contact trench 801 is located in the region of the silicide barrier structure 35 covering the second region 312 of the silicon local oxide structure 31. The mask layer 800 can be formed by SiN deposition (Dep), photolithography (Photo), and etching (ET). Since SiN exists, the selectivity ratio of oxide layer and SiN can be adjusted during trench etching, thereby achieving a non-target etching effect; for example, the minimum remaining oxide layer at the bottom of the trench-type contact trench 801 is about 500-600 angstroms, and the width of the trench-type contact trench 801 is greater than 0.2 μm (different voltages have different widths).
[0056] In this embodiment, the minimum total thickness of the silicide barrier structure 35 and the silicon local oxide structure 31 at the bottom of the trench-type contact groove 801 is greater than 500 angstroms. This means that the trench etching will at least not penetrate the silicon local oxide structure 31, thereby improving device performance and reliability. Because the silicon local oxide structure 31 has a curved shape, the total thickness of the silicide barrier structure 35 and the silicon local oxide structure 31 ranges from approximately 600 to 1000 angstroms.
[0057] Please refer to steps S33 and... Figure 3 The grooved contact structure 36 is formed in the grooved contact groove 801 and the mask layer 800 is removed. The grooved contact structure 36 includes an adhesive layer 361 formed on the sidewall of the grooved contact groove 801 and a filler layer 362 filled in the adhesive layer 361.
[0058] In this embodiment, the trench-type contact structure 36 uses a Ti / TiN adhesive layer 361 as the sidewall and a tungsten metal filling layer 362 to fill the sidewall. In some embodiments, the adhesive layer can be deposited using a layered deposition method, where a Ti layer is deposited using physical vapor deposition (PVD) and a TiN layer is deposited using chemical vapor deposition (CVD). This layered deposition method can reduce interfacial stress and achieve functional separation.
[0059] In this embodiment, the minimum total thickness of the silicide barrier structure 35 and the silicon local oxide structure 31 below the trench contact structure 36 is greater than 500 angstroms. Because the silicon local oxide structure 31 has a curved shape, the total thickness of the silicide barrier structure 35 and the silicon local oxide structure 31 ranges from approximately 600 to 1000 angstroms, ensuring that the etching process will not etch through it, thereby improving device performance and reliability.
[0060] This embodiment combines the trench contact structure 36 with the silicide barrier structure 35 and the silicon local oxidation structure 31 to form a field plate structure. This utilizes the silicide barrier structure 35 and the silicon local oxidation structure 31 for isolation, while the trench contact structure 36 disperses the drain electric field, solving the breakdown voltage and parasitic leakage current problems of high-voltage LDMOS devices, improving the breakdown voltage (BV), and effectively enhancing the high-voltage reliability of LDMOS devices. By adjusting the longitudinal electric field of the LDMOS device and optimizing the electric field distribution at the drain 32, the device can reduce the size (pitch) of some components while maintaining the breakdown voltage (BV), lowering the specific on-resistance and improving device performance.
[0061] In this embodiment, as Figure 4 As shown, the orthographic projections of the silicon localized oxide structure 31, the silicide barrier structure 35, and the trench-type contact structure 36 onto the active region 302 are all elongated strips extending along the first direction D1; wherein, the areas of each strip are of the same order of magnitude, and the area of the strip is much larger than the area of the orthographic projection of a conventional contact structure onto the active region. The silicon localized oxide structure 31, the silicide barrier structure 35, and the trench-type contact structure 36 all have portions protruding beyond the active region 302 along the first direction D1; wherein, the first direction D1 is parallel to the surface of the active region 302. By designing the trench-type contact structure 36 with a larger size, the contact area between the trench-type contact structure 36 and the silicide barrier structure 35 is increased. As a result, the trench-type contact structure 36, the silicide barrier structure 35, and the silicon local oxidation structure 31 can better serve as the field plate structure of the LDMOS device. Furthermore, the trench-type contact structure 36 can better disperse the drain electric field, solve the breakdown voltage and parasitic leakage current problems of high-voltage LDMOS devices, improve the breakdown voltage, and effectively improve the high-voltage reliability of LDMOS devices.
[0062] In this embodiment, prior to the step of forming the interlayer dielectric layer 39, the method further includes: forming a patterned metal silicide layer 38, wherein the patterned metal silicide layer 38 is in contact with the drain 32, the source 33, and the gate structure 34, respectively, as shown below. Figure 8FAs shown. Metal silicide is a technique used in semiconductor manufacturing to reduce gate resistance and source / drain contact resistance. Its core process involves forming metal silicides in the polysilicon gate and source / drain regions. Specifically, this can be achieved by depositing a metal (such as Ti, Co, or Ni), followed by rapid thermal annealing (RTA) to induce a reaction between the metal and silicon to form silicides; selective wet etching is then used to remove the unreacted metal layer, leaving only the silicides in the polysilicon gate and source / drain regions. This process achieves metallization of the gate edge and source / drain regions through self-alignment, while optimizing transistor performance, reducing contact resistance, and accommodating smaller device sizes.
[0063] The step of etching the interlayer dielectric layer 39 to form a trench-type contact trench 801 using the mask layer 800 as a shield further includes: forming a plurality of conventional contact holes 802, the bottoms of which are respectively located on the patterned metal silicide layer 38 in contact with the drain 32, the source 33, and the gate structure 34. The step of forming the trench-type contact structure 36 in the trench-type contact trench 801 further includes: forming a conventional contact structure 37 in each conventional contact hole 802, the material of which is the same as that of the trench-type contact structure 36. That is, in this embodiment, the trench-type contact structure 36 and the conventional contact structure 37 can share the same mask and be fabricated using the same process, without requiring additional process steps.
[0064] In this embodiment, as Figure 4 As shown, the orthographic projection of the conventional contact structure 37 onto the active region 302 is a square, while the orthographic projection of the trench contact structure 36 onto the active region 302 is an elongated strip extending along a first direction; and the area of the elongated strip is on the order of magnitude larger than the area of the square. The first direction D1 is parallel to the surface of the active region 302. The conventional contact structure 37 is a small square, while the trench contact structure 36 is a relatively long strip; their shapes and areas differ significantly. That is, the trench contact structure 36 shown in this embodiment is an unconventional contact structure creatively proposed to optimize the performance and reliability of LDMOS devices, reduce contact resistance, and adapt to smaller device sizes.
[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. Additionally, embodiments and features thereof in this invention can be combined with each other without conflict. Moreover, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concept of the invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.
[0066] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. An LDMOS device, characterized in that, include: A substrate in which an active region is defined by an isolation structure, wherein a drift region and a body region are formed at intervals in the active region, and a silicon local oxide structure is formed in the drift region, and the silicon local oxide structure is exposed on the top of the drift region to divide it into a first region and a second region; The drain electrode is formed in the drift region; The source electrode is formed in the aforementioned body region; A gate structure is formed on the substrate, the gate structure covering a portion of the body region and a first region covering the silicon local oxide structure, and the gate structure is isolated from the drain through the silicon local oxide structure; A silicide barrier structure covers the second region of the silicon local oxide structure and extends to cover a portion of the gate structure; as well as A trench-type contact structure contacts the region of the silicide barrier structure that covers the second region of the silicon local oxide structure. The trench-type contact structure, the silicide barrier structure, and the silicon local oxide structure together serve as the field plate structure of the LDMOS device.
2. The LDMOS device according to claim 1, characterized in that, The minimum total thickness of the silicide barrier structure and the silicon localized oxide structure below the trench-type contact structure is greater than 500 angstroms.
3. The LDMOS device according to claim 1, characterized in that, The silicon localized oxide structure, the silicide barrier structure, and the trench contact structure are all elongated strips extending along a first direction on the active region, and each of the silicon localized oxide structure, the silicide barrier structure, and the trench contact structure has a portion protruding from the active region in the first direction; wherein, the first direction is parallel to the surface of the active region.
4. The LDMOS device according to claim 1, characterized in that, The grooved contact structure uses a Ti / TiN adhesive layer as the sidewall and a tungsten metal filling layer to fill the sidewall.
5. The LDMOS device according to claim 1, characterized in that, Also includes: Multiple conventional contact structures are respectively connected to the drain, source, and gate structures via patterned metal silicide layers; wherein the material of the conventional contact structures is the same as that of the trench contact structures, the orthographic projection of the conventional contact structures onto the active region is square, and the orthographic projection of the trench contact structures onto the active region is an elongated strip extending along a first direction, wherein the area of the elongated strip is on the order of magnitude larger than the area of the square; wherein the first direction is parallel to the surface of the active region.
6. The LDMOS device according to claim 1, characterized in that, The gate structure includes a polysilicon gate, a gate oxide layer formed between the polysilicon gate and the substrate, and a sidewall formed on the sidewall of the polysilicon gate and the gate oxide layer. The sidewall on one side of the gate structure is formed on a first region of the silicon local oxide structure, and the silicide barrier structure extends to cover the sidewall and part of the polysilicon gate.
7. A method for fabricating an LDMOS device, characterized in that, The method includes the following steps: A substrate is provided, the substrate including a substrate, an active region defined therein by an isolation structure, a drift region and a body region formed therein by spaced-apart drift region, a silicon local oxide structure formed therein by the drift region, the silicon local oxide structure being exposed at the top of the drift region and divided into a first region and a second region, a drain electrode also being formed therein by the drift region, an active electrode being formed therein by the body region, a gate structure formed on the substrate, the gate structure covering a portion of the body region and the first region covering the silicon local oxide structure, and the gate structure being isolated from the drain electrode by the silicon local oxide structure; A silicide barrier structure is formed, which covers the second region of the silicon local oxide structure and extends to cover a portion of the gate structure; as well as A trench-type contact structure is formed, which contacts the region of the silicide barrier structure that covers the second region of the silicon local oxide structure. The trench-type contact structure, the silicide barrier structure, and the silicon local oxide structure together serve as the field plate structure of the LDMOS device.
8. The method according to claim 7, characterized in that, The steps for forming the silicide barrier structure specifically include: A silicide barrier material layer is formed, the silicide barrier material layer at least covering the second region of the silicon localized oxide structure and a portion of the gate structure; A patterned photoresist layer is formed on the silicide barrier material layer, and the silicide barrier material layer is etched using the patterned photoresist layer as a shield, retaining the second region of the silicon local oxidation structure and part of the silicide barrier material layer on the gate structure to form the silicide barrier structure. Remove the patterned photoresist layer.
9. The method according to claim 8, characterized in that, The silicide barrier material layer is etched using a combination of dry and wet etching methods, and the patterned photoresist layer is removed using a wet stripping method.
10. The method according to claim 7, characterized in that, The steps for forming the grooved contact structure specifically include: An interlayer dielectric layer is formed, which covers the substrate and the silicide barrier structure; a mask layer is formed on the interlayer dielectric layer, and the interlayer dielectric layer is etched with the mask layer as a shield to form a trench-type contact trench, the bottom of the trench-type contact trench being located in the region of the silicide barrier structure covering the second region of the silicon local oxidation structure; The grooved contact structure is formed in the grooved contact groove and the mask layer is removed. The grooved contact structure includes an adhesive layer formed on the sidewall of the grooved contact groove and a filler layer filled in the adhesive layer.
11. The method according to claim 10, characterized in that, The mask layer is made of SiN, the adhesive layer is made of Ti and / or TiN, and the filler layer is made of tungsten.
12. The method according to claim 10, characterized in that, Its features are, Before the step of forming the interlayer dielectric layer, the method further includes: forming a patterned metal silicide layer, wherein the patterned metal silicide layer is in contact with the drain, the source, and the gate structure, respectively; The step of etching the interlayer dielectric layer to form a trench-type contact groove using the mask layer as a shield further includes: forming a plurality of conventional contact holes, the bottoms of the plurality of conventional contact holes being located on the patterned metal silicide layer that is in contact with the drain, the source, and the gate structure, respectively; The step of forming the grooved contact structure in the grooved contact groove further includes: forming a conventional contact structure in each conventional contact hole, wherein the material of the conventional contact structure is the same as that of the grooved contact structure, the orthographic projection of the conventional contact structure onto the active region is a square, and the orthographic projection of the grooved contact structure onto the active region is an elongated strip extending along a first direction, and the area of the elongated strip is on the order of magnitude larger than the area of the square; wherein the first direction is parallel to the surface of the active region.
13. The method according to claim 7, characterized in that, The minimum total thickness of the silicide barrier structure and the silicon localized oxide structure below the trench-type contact structure is greater than 500 angstroms.
14. The method according to claim 7, characterized in that, The silicon localized oxide structure, the silicide barrier structure, and the trench contact structure are all elongated strips extending along a first direction on the active region, and each of the silicon localized oxide structure, the silicide barrier structure, and the trench contact structure has a portion protruding from the active region in the first direction; wherein, the first direction is parallel to the surface of the active region.