Semiconductor device

Abstract

Embodiments of this disclosure relate to semiconductor devices. A semiconductor device includes one or more LDMOS transistors and a semiconductor substrate having a top surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed on the top surface of the semiconductor substrate; a plurality of drain layers formed on the top surface of the semiconductor substrate; and a plurality of insulating films formed on the top surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction in a plan view. The plurality of impurity diffusion layers are arranged in a plan view along a second direction perpendicular to the first direction, with gaps inserted between two adjacent impurity diffusion layers.

Description

Cross-reference to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-226358, filed on December 23, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor equipment. Background Technology

[0003] The following technologies have been disclosed.

[0004] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-45884 The semiconductor device disclosed in Patent Document 1 includes a semiconductor substrate and a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

[0005] The semiconductor substrate has an upper surface. The semiconductor substrate includes a first impurity diffusion layer, a second impurity diffusion layer, a drain layer, a first body layer, a second body layer, and a drift layer. The first and second impurity diffusion layers are formed in the semiconductor substrate at the upper surface. The first and second impurity diffusion layers extend along a first direction in a plan view. The first and second impurity diffusion layers are arranged along a second direction perpendicular to the first direction in the plan view, with a gap inserted between the first and second impurity diffusion layers. The drift layer is formed in the semiconductor substrate at the upper surface. The drift layer extends along the first direction and is located between the first and second impurity diffusion layers.

[0006] A first body layer is formed in the semiconductor substrate and on its upper surface to surround a first impurity diffusion layer in a cross-sectional view. A second body layer is formed in the semiconductor substrate and on its upper surface to surround a second impurity diffusion layer in a cross-sectional view. A drift layer is formed in the semiconductor substrate and on its upper surface to surround a drain layer in a cross-sectional view. Each of the first and second impurity diffusion layers includes a source layer and a back gate layer.

[0007] An LDMOS transistor includes a first impurity diffusion layer, a second impurity diffusion layer, a first body layer, a second body layer, a drain layer, and a drift layer. An LDMOS transistor also includes a first insulating film, a second insulating film, a first gate insulating film, a second gate insulating film, a first gate electrode, and a second gate electrode.

[0008] A first insulating film is formed on the upper surface of the semiconductor substrate to contact the drift layer and separate from the first impurity diffusion layer. A second insulating film is formed on the upper surface of the semiconductor substrate to contact the drift layer and separate from the second impurity diffusion layer. A first gate insulating film is formed on the upper surface of the semiconductor substrate between the first insulating film and the first impurity diffusion layer. A second gate insulating film is formed on the upper surface of the semiconductor substrate between the second insulating film and the second impurity diffusion layer. A first gate electrode is formed on the first gate insulating film and the first insulating film, and a second gate electrode is formed on the second gate insulating film and the second insulating film. Summary of the Invention

[0009] In the LDMOS transistor of the semiconductor device disclosed in Patent Document 1, the electrical characteristics of the LDMOS transistor are difficult to change linearly with respect to the number of fingers when the number of fingers increases or when the number of drain layers increases. Other objects and novel features will become apparent from the description and drawings in this specification.

[0010] The semiconductor device according to this disclosure includes one or more LDMOS transistors and a semiconductor substrate having a top surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed in the semiconductor substrate at the top surface; a plurality of drain layers formed in the semiconductor substrate at the top surface; and a plurality of insulating films formed on the top surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction in a plan view. The plurality of impurity diffusion layers are arranged in a plan view along a second direction perpendicular to the first direction, with gaps inserted between two adjacent impurity diffusion layers. The plurality of impurity diffusion layers includes a first impurity diffusion layer and a second impurity diffusion layer located at both ends of the second direction, and a third impurity diffusion layer located between the first and second impurity diffusion layers. Each of the plurality of drain layers is located between two adjacent impurity diffusion layers. Each of the plurality of insulating films is located between one of the plurality of adjacent drain layers and one of the plurality of impurity diffusion layers, such that it is in contact with and separate from one of the plurality of drain layers. In a first LDMOS transistor of one or more LDMOS transistors, each of the first and second impurity diffusion layers includes a first back gate layer but does not include a source layer. A third impurity diffusion layer in the first LDMOS transistor includes a second back gate layer and a first source layer alternately arranged along a first direction.

[0011] According to the semiconductor device disclosed herein, the electrical characteristics of an LDMOS transistor can be changed linearly with respect to the number of fingers. Attached Figure Description

[0012] Figure 1 This is a plan view showing the semiconductor device DEV1 on the LDMOS transistor Tr1.

[0013] Figure 2 It shows along Figure 1 The cross-sectional view of semiconductor device DEV1 taken from line II-II.

[0014] Figure 3 It shows along Figure 1 The cross-sectional view of semiconductor device DEV1 taken from line III-III.

[0015] Figure 4 This is a plan view showing the semiconductor device DEV1 on the LDMOS transistor Tr2.

[0016] Figure 5 It shows along Figure 4 A cross-sectional view of semiconductor device DEV1 taken from line VV.

[0017] Figure 6 It shows along Figure 4 The cross-sectional view of semiconductor device DEV1 taken by line VI-VI.

[0018] Figure 7 This is a plan view showing the semiconductor device DEV1 on the LDMOS transistor Tr3.

[0019] Figure 8 It shows along Figure 7 A cross-sectional view of semiconductor device DEV1 taken from line VIII-VIII.

[0020] Figure 9 It shows along Figure 7 The cross-sectional view of semiconductor device DEV1 taken by line IX-IX.

[0021] Figure 10 This is a circuit diagram showing a current mirror circuit.

[0022] Figure 11 This is a diagram of the manufacturing process of semiconductor device DEV1.

[0023] Figure 12 This is a cross-sectional view used to explain the ion implantation step S1.

[0024] Figure 13 This is a cross-sectional view used to explain step S2 of the insulating film formation process.

[0025] Figure 14 This is a cross-sectional view used to explain step S3 of forming the gate insulating film.

[0026] Figure 15 This is a cross-sectional view used to explain the gate electrode deposition step S4.

[0027] Figure 16 This is a cross-sectional view used to explain the gate electrode etching step S5.

[0028] Figure 17 This is a cross-sectional view used to explain the ion implantation step S6.

[0029] Figure 18 This is a cross-sectional view used to explain step S7 of the sidewall-spacer formation process.

[0030] Figure 19 This is a cross-sectional view used to explain the ion implantation step S8.

[0031] Figure 20 This is a cross-sectional view used to explain the ion implantation step S9.

[0032] Figure 21 This is a cross-sectional view used to explain step S10 of forming the interlayer insulating film.

[0033] Figure 22 This is a cross-sectional view used to explain the contact plug formation step S11.

[0034] Figure 23 This is a plan view showing the semiconductor device DEV4 on the LDMOS transistor Tr4.

[0035] Figure 24 It shows along Figure 23 The cross-sectional view of semiconductor device DEV4 taken from line XXIV-XXIV.

[0036] Figure 25 It shows along Figure 23 A cross-sectional view of semiconductor device DEV4 taken from line XXV-XXV.

[0037] Figure 26 This is a cross-sectional view showing the semiconductor device DEV2.

[0038] Figure 27 This is a diagram of the manufacturing process of the semiconductor device DEV2.

[0039] Figure 28 This is a cross-sectional view of the ion implantation step S1 in the method for manufacturing semiconductor device DEV2.

[0040] Figure 29This is a cross-sectional view of the gate electrode etching step S5 in the method for explaining the manufacturing of semiconductor device DEV2.

[0041] Figure 30 This is a cross-sectional view of the ion implantation step S13 in the method for manufacturing semiconductor device DEV2.

[0042] Figure 31 This is a cross-sectional view showing the semiconductor device DEV3.

[0043] Figure 32 This is a cross-sectional view of the ion implantation step S1 in the method for manufacturing semiconductor device DEV3.

[0044] Figure 33 This is a cross-sectional view of the gate electrode etching step S5 in the method for explaining the manufacturing of semiconductor device DEV3.

[0045] Figure 34 This is a cross-sectional view of the ion implantation step S13 in the method for manufacturing semiconductor device DEV3. Detailed Implementation

[0046] Details of embodiments of the present disclosure will be described with reference to the accompanying drawings. In all the drawings, the same or similar parts are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0047] First Embodiment The semiconductor device DEV1 according to the first embodiment will be described.

[0048] Configuration of semiconductor device DEV1 Semiconductor device DEV1 includes multiple LDMOS transistors Tr, such as Figures 1 to 9 As shown. The number of LDMOS transistors included in the semiconductor device DEV1 can be one. The semiconductor device DEV1 includes a semiconductor substrate SUB. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 opposite to the upper surface F1. The semiconductor substrate SUB includes multiple impurity diffusion layers IDL, multiple drain layers DRA, multiple body layers BDL, and multiple drift layers DRI.

[0049] Multiple impurity diffusion layers (IDLs) and multiple drain layers (DRAs) are formed on the upper surface F1 of the semiconductor substrate SUB. The IDLs and DRAs extend along a first direction DR1 in the plan view. The multiple IDLs are arranged along a second direction DR2 perpendicular to the first direction DR1 in the plan view to insert gaps between two adjacent impurity diffusion layers. The DRAs are located between two adjacent impurity diffusion layers in the multiple IDLs.

[0050] The impurity diffusion layer (IDL) consists of a first portion (IDLa) and a second portion (IDLb). The first portion (IDLa) is located between the second portion (IDLb) and the drain layer (DRA). That is, the impurity diffusion layer (IDL) has a lightly doped diffusion (LDD) structure.

[0051] A body layer BDL is formed on the upper surface F1 to surround the impurity diffusion layer IDL in a cross-sectional view. A drift layer DRI is formed on the upper surface F1 to surround the drain layer DRA in a cross-sectional view. The semiconductor substrate SUB may also include multiple well layers WEL. The well layers WEL are formed to surround the drain layer DRA and are surrounded by the drift layer DRI in a cross-sectional view.

[0052] The semiconductor substrate SUB is made of, for example, single-crystal silicon. The semiconductor substrate SUB has a first conductivity type. The body layer BDL has a first conductivity type. Each of the drain layer DRA, well layer WEL, and drift layer DRI has a second conductivity type relative to the first conductivity type. The first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type. The first conductivity type can be n-type, and the second conductivity type can be p-type.

[0053] Semiconductor device DEV1 also includes multiple insulating films IF1. The insulating films IF1 are formed on an upper surface F1. The insulating films IF1 extend along a first direction DR1. Multiple trenches TR1 are formed on the upper surface F1. The trenches TR1 extend toward a lower surface F2. The trenches TR1 are located between adjacent impurity diffusion layers IDL and drain layers DRA. The trenches TR1 are in contact with the drain layer DRA and separated from the impurity diffusion layers IDL. The insulating films IF1 are formed in the trenches TR1. Therefore, the insulating films IF1 are formed on the upper surface F1 to be in contact with the drain layer DRA and separated from the impurity diffusion layers IDL. The insulating films IF1 are made of, for example, silicon oxide.

[0054] The semiconductor device DEV1 also includes multiple gate insulating films G1 and multiple gate electrodes GE. Gate insulating films G1 are formed on an upper surface F1 located between adjacent insulating films IF1 and impurity diffusion layers IDL. Gate insulating films G1 are made of, for example, silicon oxide. Gate electrodes GE are formed on adjacent gate insulating films G1 and IF1. Gate electrodes GE are made of, for example, polysilicon.

[0055] The LDMOS transistor Tr includes multiple impurity diffusion layers (IDL), multiple drain layers (DRA), multiple body layers (BDL), multiple drift layers (DRI), multiple insulating films (IF1), multiple gate insulating films (GI), and multiple gate electrodes (GE). The semiconductor device DEV1 also includes an insulating film (IF2). The insulating film (IF2) is formed on the upper surface (F1) to surround the LDMOS transistor Tr in a plan view. A trench (TR2) extending toward the lower surface (F2) is formed in the upper surface (F1), and the insulating film (IF2) is formed in the trench (TR2). The LDMOS transistor Tr is electrically isolated from other components by the insulating film (IF2). The insulating film (IF2) is made of, for example, silicon oxide.

[0056] The semiconductor device DEV1 also includes a sidewall spacer SWS. The sidewall spacer SWS is formed on the upper surface F1 (on the first portion IDLa) and the insulating film IF1 to contact both sides of the gate electrode GE. The sidewall spacer SWS is made of, for example, silicon nitride.

[0057] Semiconductor device DEV1 also includes an interlayer insulating film (ILD). The ILD is formed on the upper surface F1 to cover the insulating film IF1, the insulating film IF2, the gate electrode GE, and the sidewall spacers SWS. The ILD is made of, for example, silicon oxide.

[0058] Semiconductor device DEV1 also includes wiring WL1, wiring WL2, contact plug CP1, and contact plug CP2. Wiring WL1 and wiring WL2 are formed on an interlayer insulating film (ILD). Each of wiring WL1 and wiring WL2 is made of, for example, aluminum or an aluminum alloy. Contact plug CP1 and contact plug CP2 are formed in the interlayer insulating film (ILD). Contact plug CP1 electrically connects wiring WL1 and the drain layer DRA. Contact plug CP2 electrically connects wiring WL2 and the impurity diffusion layer (IDL). Each of contact plug CP1 and contact plug CP2 is made of, for example, tungsten.

[0059] like Figures 1 to 3 As shown, in LDMOS transistor Tr1 of the plurality of LDMOS transistors Tr, each of the impurity diffusion layers IDL1 and IDL2 located at both ends of the second direction DR2 includes only a back gate layer BGL. That is, each of the impurity diffusion layers IDL1 and IDL2 includes a back gate layer BGL, but does not include any source layer. The conductivity type of the back gate layer BGL is a first conductivity type. In LDMOS transistor Tr1, the impurity diffusion layer IDL3 located between impurity diffusion layers IDL1 and IDL2 includes a back gate layer BGL and a source layer SL arranged alternately along the first direction DR1. The conductivity type of the source layer SL is a second conductivity type.

[0060] like Figures 4 to 6 As shown, in LDMOS transistor Tr2 of the plurality of LDMOS transistors Tr, each of the impurity diffusion layers IDL1 and IDL2 includes only a back gate layer BGL. That is, each of the impurity diffusion layers IDL1 and IDL2 includes a back gate layer BGL, but does not include any source layer. In LDMOS transistor Tr2, the impurity diffusion layer IDL3 includes a back gate layer BGL and a source layer SL arranged alternately along the first direction DR1. Note that the number of multiple drain layers DRA in LDMOS transistor Tr2 may differ from the number of multiple drain layers DRA in LDMOS transistor Tr1.

[0061] like Figure 10 As shown, semiconductor device DEV1 includes a current mirror circuit. The current mirror circuit includes LDMOS transistors Tr1 and Tr2, a resistor R, and a load L. The drain layer DRA of LDMOS transistors Tr1 and Tr2 is electrically connected to the drain voltage V. DD The source layer SL of LDMOS transistor Tr1 and the source layer SL of LDMOS transistor Tr2 are grounded. That is, LDMOS transistor Tr1 and LDMOS transistor Tr2 are connected in parallel.

[0062] The gate electrode GE of LDMOS transistor Tr1 is electrically connected to the gate electrode GE of LDMOS transistor Tr2. The gate electrodes GE of LDMOS transistor Tr1 and LDMOS transistor Tr2 are both electrically connected to the drain layer DRA of LDMOS transistor Tr1. Resistor R is electrically connected to the drain layer DRA of LDMOS transistor Tr1 and the drain voltage V. DD Between. The load L is electrically connected to the drain layer DRA of the LDMOS transistor Tr2 and the drain voltage V. DD between.

[0063] In a current mirror circuit, the ratio between the current I1 flowing in LDMOS transistor Tr1 and the current I2 flowing in LDMOS transistor Tr2 is determined by the mirror ratio, that is, the ratio between the dimensions of LDMOS transistor Tr1 and LDMOS transistor Tr2. For example, when the gate length of LDMOS transistor Tr1 is equal to the gate length of LDMOS transistor Tr2, and the gate width of LDMOS transistor Tr1 is equal to the gate width of LDMOS transistor Tr2, the mirror ratio is 1:1, and the current I2 is equal to the current I1. When the gate length of LDMOS transistor Tr1 is equal to the gate length of LDMOS transistor Tr2, and the gate width of LDMOS transistor Tr2 is twice the gate width of LDMOS transistor Tr1, the mirror ratio is 1:2, and the current I2 is twice the current I1. Note that the gate widths in LDMOS transistors Tr1 and Tr2 are proportional to the number of fingers.

[0064] In LDMOS transistors Tr1 and Tr2, the number of multiple drain layers (DRAs) is, for example, equal to or less than six. In the assumption that the number of multiple drain layers (DRAs) is “n” (where “n” is a natural number), each of the number of fingers in LDMOS transistor Tr1 and the number of fingers in LDMOS transistor Tr2 is represented as “2n-2”.

[0065] like Figures 7 to 9 As shown, the plurality of LDMOS transistors Tr may include LDMOS transistor Tr3. In LDMOS transistor Tr3, each of the impurity diffusion layers IDL1, IDL2 and IDL3 includes a back gate layer BGL and a source layer SL alternately arranged along the first direction DR1.

[0066] Method for manufacturing semiconductor device 1 like Figure 11 As shown, the method for manufacturing semiconductor device DEV1 includes an ion implantation step S1, an insulating film formation step S2, a gate insulating film formation step S3, a gate electrode deposition step S4, a gate electrode etching step S5, an ion implantation step S6, a sidewall spacer formation step S7, an ion implantation step S8, and an ion implantation step S9. The method for manufacturing semiconductor device DEV1 also includes an interlayer insulating film formation step S10, a contact plug formation step S11, and a wiring formation step S12.

[0067] like Figure 12 As shown, in the ion implantation step S1, ion implantation is performed by using a photoresist pattern formed on the upper surface F1 as a mask, thereby forming the body layer BDL, the trap layer WEL, and the drift layer DRI.

[0068] like Figure 13 As shown, in the insulating film formation step S2, insulating films IF1 and IF2 are formed. In the insulating film formation step S2, firstly, a hard mask is formed on the upper surface F1. Secondly, the semiconductor substrate SUB is dry-etched through the openings of the hard mask, thereby forming trenches TR1 and TR2 in the upper surface F1. Thirdly, the constituent materials of the insulating film IF1, etc., are deposited in the trenches TR1 and TR2 and on the hard mask by, for example, chemical vapor deposition (CVD). Fourthly, the constituent materials of the insulating film IF1, etc., formed outside the trenches TR1 and TR2 are removed by, for example, CMP or etch-back.

[0069] like Figure 14 As shown, in the gate insulating film formation step S3, for example, the upper surface F1 is thermally oxidized, thereby forming the gate insulating film G1 on the upper surface F1. Figure 15 As shown, in the gate electrode deposition step S4, the gate electrode GE is formed on the gate insulating film GI by, for example, a CVD method. Figure 16 As shown, in the gate electrode etching step S5, the gate electrode GE is dry-etched through the openings of the photoresist pattern formed on the gate electrode GE, thereby patterning the gate electrode GE. At this time, the gate insulating film GI in the regions other than the region below the patterned gate electrode GE is also removed.

[0070] like Figure 17 As shown, in the ion implantation step S6, ion implantation is performed by using the gate electrode GE, the insulating film IF1, and the insulating film IF2 as masks, thereby forming the first part IDLa.

[0071] like Figure 18 As shown, in the sidewall spacer formation step S7, the sidewall spacer SWS is formed on the upper surface F1 (first portion IDLa) and the insulating film IF1 to contact the two side surfaces of the gate electrode GE. In the sidewall spacer formation step S7, firstly, the constituent material of the sidewall spacer SWS is deposited on the upper surface F1 by, for example, a CVD method to cover the insulating film IF1, the insulating film IF2, the gate electrode GE, and the gate insulating film GI. Secondly, the constituent material of the sidewall spacer SWS is etched back.

[0072] like Figure 19 As shown, in the ion implantation step S8, ion implantation is performed using a photoresist pattern formed on the gate electrode GE, sidewall spacer SWS, insulating film IF1, and upper surface F1 as a mask, thereby forming the second portion IDLb (source layer SL) of the impurity diffusion layer IDL3 and forming the drain layer DRA. Figure 20As shown, in the ion implantation step S9, ion implantation is performed using a photoresist pattern formed on the gate electrode GE, sidewall spacer SWS, insulating film IF1, insulating film IF2, and upper surface F1 as a mask, thereby forming the second portion IDLb (back gate layer BGL) of the impurity diffusion layer IDL1 and the impurity diffusion layer IDL2. At this time, the second portion IDLb (back gate layer BGL) of the impurity diffusion layer IDL3 is also formed.

[0073] like Figure 21 As shown, in the interlayer insulating film formation step S10, an interlayer insulating film ILD is formed on the upper surface F1 to cover the insulating film IF1, the insulating film IF2, the sidewall spacer SWS, and the gate electrode GE. In the interlayer insulating film formation step S10, firstly, the constituent material of the interlayer insulating film ILD is deposited on the upper surface F1 to cover the insulating film IF1, the insulating film IF2, the sidewall spacer SWS, and the gate electrode GE. Secondly, the upper surface of the constituent material of the interlayer insulating film ILD is planarized using, for example, a CMP method.

[0074] like Figure 22 As shown, in the contact plug formation step S11, contact plugs CP1 and CP2 are formed in the interlayer insulating film (ILD). In the contact plug formation step S11, firstly, the ILD is dry-etched through openings in the photoresist pattern formed on the ILD, thereby forming contact holes in the ILD. Secondly, constituent materials such as contact plug CP1 are deposited in the contact holes and on the ILD using, for example, a CVD method. Thirdly, the constituent materials of contact plug CP1 formed outside the contact holes are removed using, for example, a CMP method.

[0075] In the wiring formation step S12, wirings WL1 and WL2 are formed on an interlayer insulating film (ILD). In wiring formation step S12, firstly, a constituent material such as wiring WL1 is deposited on the ILD by, for example, sputtering. Secondly, the constituent material such as wiring WL1 is dry-etched through openings in the photoresist pattern formed on the constituent material. The wiring is formed as described above. Figures 1 to 9 The structure of the semiconductor device DEV1 is shown.

[0076] The effect of semiconductor device DEV1 In the LDMOS transistor Tr3, each of the impurity diffusion layers IDL1 and IDL2 includes not only the back gate layer BGL but also the source layer SL. Therefore, the gate width of the LDMOS transistor Tr3 is greater than the gate width of each of the LDMOS transistors Tr1 and Tr2. Consequently, the current capability of the LDMOS transistor Tr3 is higher than that of each of the LDMOS transistors Tr1 and Tr2.

[0077] However, during the formation of the insulating film IF1, the insulating film IF1 located at both ends of the second direction DR2 is affected by the insulating film IF2. Because it differs from the insulating film IF1 located in other regions outside the ends of the second direction DR2, the shape of the insulating film IF1 located at both ends of the second direction DR2 is different from the shape of the insulating film IF1 located in other regions outside the ends of the second direction DR2. This also applies to the body layer BDL, the drift layer DR1, and the gate electrode GE located at both ends of the second direction DR2.

[0078] Therefore, in the LDMOS transistor Tr3, the electrical characteristics such as threshold voltage, on-resistance, and saturation drain current in the channel between the source layer SL and drain layer DRA of the impurity diffusion layers IDL1 (and IDL2) differ from the electrical characteristics in the channel between the source layer SL and drain layer DRA of the impurity diffusion layers IDL3. In other words, the electrical characteristics of the LDMOS transistor Tr3 are difficult to change linearly with respect to the number of fingers. Therefore, when the LDMOS transistor Tr3 is used in a current mirror circuit, even if the number of fingers in the transistor is adjusted to achieve the desired current ratio, the actual current ratio deviates from the desired current ratio, and the accuracy in the current mirror circuit is reduced.

[0079] Conversely, in LDMOS transistors Tr1 and Tr2, the impurity diffusion layer IDL1 (and IDL2) does not include the source layer SL. Therefore, the region between the impurity diffusion layer IDL1 (and IDL2) and the drain layer DRA is not used as a channel. Consequently, the linear variation of the electrical characteristics of LDMOS transistors Tr1 and Tr2 with respect to the number of fingers is greater than that of LDMOS transistor Tr3. Therefore, according to semiconductor device DEV1, the accuracy of analog circuits such as current mirror circuits can be improved.

[0080] like Figures 23 to 25As shown, the semiconductor device DEV4 according to the comparative example includes an LDMOS transistor Tr4 as an LDMOS transistor Tr. In the LDMOS transistor Tr4, each of the impurity diffusion layers IDL1 and IDL2 includes only a back gate layer BGL. In the LDMOS transistor Tr4, the insulating film IF1 located at both ends of the second direction DR2 is in contact with both the impurity diffusion layers IDL1 (and IDL2) and the drain layer DRA. In the LDMOS transistor Tr4, the gate electrode GE is not formed on the insulating film IF1 located at both ends of the second direction DR2.

[0081] In LDMOS transistor Tr4, the impurity diffusion layer IDL1 (and IDL2) does not include a source layer SL similar to those in LDMOS transistors Tr1 and Tr2. Therefore, the region between the impurity diffusion layer IDL1 (and IDL2) and the drain layer DRA is not used as a channel. Consequently, the linear change in the electrical characteristics of LDMOS transistor Tr4 with respect to the number of fingers is greater than that of LDMOS transistor Tr3.

[0082] However, in LDMOS transistor Tr4, the gate electrode GE is not formed on the insulating film IF1 located at both ends of DR2 in the second direction. Therefore, the dielectric breakdown voltage is lower than that of LDMOS transistors Tr1 and Tr2 due to the difference in field plate effect. On the other hand, in order to achieve the same dielectric breakdown voltage as LDMOS transistors Tr1 and Tr2, the distance between the impurity diffusion layer IDL1 (and IDL2) and the drain layer DRA must be greater than the distance between LDMOS transistors Tr1 and Tr2. As described above, according to semiconductor device DEV1, the planar dimensions of LDMOS transistors Tr1 and Tr2 can be reduced.

[0083] As mentioned above, the LDMOS transistor Tr3 is difficult to apply to analog circuits that require high precision. However, when an analog circuit that requires high current capability but not high precision is installed on the semiconductor device DEV1, the LDMOS transistor Tr3 can be used for such an analog circuit.

[0084] In LDMOS transistor Tr3, the smaller the number of fingers, in other words, the smaller the number of multiple drain layers (DRA), the greater the influence of electrical characteristics on the channel between the source layer (SL) and drain layer (DRA) of the impurity diffusion layers (IDL1) (and (IDL2)). Therefore, LDMOS transistors Tr1 and Tr2 are particularly effective when the number of fingers is equal to or less than 10, or in other words, when the number of multiple drain layers (DRA) is equal to or less than 6.

[0085] Second Embodiment The semiconductor device DEV2 according to the second embodiment will be described here. The differences from the semiconductor device DEV1 will be mainly described here, and overlapping descriptions will not be repeated.

[0086] Configuration of semiconductor device DEV2 like Figure 26 As shown, semiconductor device DEV2 includes an LDMOS transistor Tr1 as one of a plurality of LDMOS transistors Tr. In the LDMOS transistor Tr1 of semiconductor device DEV2, among the plurality of body layers BDL, the depth of body layer BDL1 surrounding impurity diffusion layer IDL1 in the cross-sectional view and the depth of body layer BDL2 surrounding impurity diffusion layer IDL2 in the cross-sectional view are greater than the depth of body layer BDL3 surrounding impurity diffusion layer IDL3 in the cross-sectional view. The depth of body layer BDL3 is less than the depth of drift layer DR1. The depth of body layer BDL (drift layer DRI) corresponds to the distance between the lower surface and the upper surface F1 of body layer BDL (drift layer DRI).

[0087] In the plan view of LDMOS transistor Tr1 of semiconductor device DEV2, the overlap width of gate electrode GE and body layer BDL3 in the second direction DR2 is smaller than the overlap width of gate electrode GE and body layer BDL1 in the second direction DR2 and the overlap width of gate electrode GE and body layer BDL2 in the second direction DR2.

[0088] Method for manufacturing semiconductor device DEV2 like Figure 27 As shown, the method for manufacturing the semiconductor device DEV2 also includes an ion implantation step S13.

[0089] like Figure 28 As shown, in the method for manufacturing semiconductor device DEV2, the body layer BDL3 is not formed via ion implantation step S1. Figure 29 As shown, in the method for manufacturing semiconductor device DEV2, the gate electrode GE located above the formation portion of the body layer BDL3 is not removed by the gate electrode etching step S5.

[0090] like Figure 30 As shown, the body layer BDL3 is formed in a self-aligned manner through ion implantation in step S13. In step S13, firstly, a photoresist pattern RP is formed on the upper surface F1 to cover the gate electrode GE, insulating film IF1, and insulating film IF2. The photoresist pattern RP has an opening above the formed portion of the body layer BDL3. Secondly, the gate electrode GE and the gate insulating film GI are dry-etched through the opening of the photoresist pattern RP to remove the gate electrode GE and the gate insulating film GI exposed from the opening of the photoresist pattern RP. Thirdly, ion implantation is performed through the opening of the photoresist pattern RP. At this time, the ion implantation direction is inclined from the normal direction of the upper surface F1.

[0091] Therefore, in the planar view, the overlap width between the gate electrode GE and the body layer BDL3 in the second direction DR2 is smaller than the overlap width between the gate electrode GE and the body layer BDL1 in the second direction DR2, and the overlap width between the gate electrode GE and the body layer BDL2 in the second direction DR2. The depth of the body layer BDL3 is also smaller than the depth of the body layer BDL1 and the depth of the body layer BDL2. After the ion implantation step S13, steps from the ion implantation step S6 to the wiring formation step S12 are sequentially performed to form... Figure 26 The structure of the semiconductor device DEV2 is shown.

[0092] The effect of semiconductor device DEV2 In the LDMOS transistor Tr1 of semiconductor device DEV2, the overlap width between the gate electrode GE and the body layer BDL3 is smaller than the overlap width between the gate electrode GE and the body layer BDL1 in the second direction DR2, and the overlap width between the gate electrode GE and the body layer BDL2 in the second direction DR2. Therefore, the channel length is smaller than the channel length in the LDMOS transistor Tr1 of semiconductor device DEV1. Consequently, the electrical characteristics (on-resistance) of the LDMOS transistor Tr1 in semiconductor device DEV2 are relatively small.

[0093] Third Embodiment The semiconductor device DEV3 according to the third embodiment will be described. The differences from the semiconductor device DEV2 will be described here, and the overlapping descriptions will not be repeated.

[0094] Semiconductor equipment DEV3 like Figure 31As shown, semiconductor device DEV3 includes an LDMOS transistor Tr1 as one of a plurality of LDMOS transistors Tr. In the LDMOS transistor Tr1 of semiconductor device DEV3, the depth of each of the body layers BDL1 and BDL2 is approximately equal to the depth of the body layer BDL3 and less than the depth of the drift layer DR1. In the LDMOS transistor Tr1 of semiconductor device DEV3, the overlap width between the body layer BDL1 and the gate electrode GE in the second direction DR2, and the overlap width between the body layer BDL2 and the gate electrode GE in the second direction DR2, are approximately equal to the overlap width between the body layer BDL3 and the gate electrode GE in the second direction DR2.

[0095] In the semiconductor device DEV3, the semiconductor substrate SUB may further include an impurity diffusion layer IDL4 and an impurity diffusion layer IDL5. The impurity diffusion layer IDL4 is formed beneath and in contact with the body layer BDL1 in the semiconductor substrate SUB. The impurity diffusion layer IDL5 is formed beneath and in contact with the body layer BDL2 in the semiconductor substrate SUB. The conductivity type of each of the impurity diffusion layers IDL4 and IDL5 is a first conductivity type.

[0096] Method for manufacturing semiconductor device DEV3 like Figure 32 As shown, in the method for manufacturing semiconductor device DEV3, impurity diffusion layers IDL4 and IDL5 are formed together with well layer WEL and drift layer DRI by ion implantation in ion implantation step S1.

[0097] like Figure 33 and Figure 34 As shown, in the method for manufacturing semiconductor device DEV3, body layers BDL1 and BDL2 are formed in a self-aligned manner similar to that of body layer BDL3. More specifically, as... Figure 33 As shown, the gate electrode GE, located above the formation regions of body layers BDL1, BDL2, and BDL3, is not etched and remains in gate electrode etching step S5. Figure 34 As shown, in the ion implantation step S13, the gate electrode GE and the gate insulating film GI are dry etched through the opening of the photoresist pattern RP located above the formation regions of the body layers BDL1, BDL2 and BDL3, and then ion implantation is performed through the opening in an inclined direction relative to the normal direction of the upper surface F1.

[0098] The effect of semiconductor device DEV3 In semiconductor device DEV3, the same gate etching step S5 and ion implantation step S13 are applied to both ends of LDMOS transistor Tr1 in the second direction DR2 and to other regions of LDMOS transistor Tr1 other than those ends in the second direction DR2. Therefore, in LDMOS transistor Tr1 of semiconductor device DEV3, even with a smaller number of fingers, the gate electrode GE and body layer BDL3 in regions other than those ends in the second direction DR2 can be formed more appropriately than in LDMOS transistor Tr1 of semiconductor device DEV2, and the electrical characteristics of LDMOS transistor Tr1 change more linearly with respect to the number of fingers.

[0099] The invention made by the inventors of this application has been specifically described above based on embodiments. However, it should be noted that the invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention.

Claims

1. A semiconductor device, comprising: One or more laterally diffused metal-oxide-semiconductor LDMOS transistors; as well as Semiconductor substrate, the semiconductor substrate having an upper surface, Each of the one or more LDMOS transistors includes: Multiple impurity diffusion layers are formed on the upper surface in the semiconductor substrate; Multiple drain layers are formed on the upper surface in the semiconductor substrate; and Multiple insulating films are formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction in the plan view. The plurality of impurity diffusion layers are arranged along a second direction in a plan view, with gaps inserted between two adjacent impurity diffusion layers, the second direction being perpendicular to the first direction. The plurality of impurity diffusion layers include a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer. The first and second impurity diffusion layers are located at opposite ends of the second direction, and the third impurity diffusion layer is located between the first and second impurity diffusion layers. Each of the plurality of drain layers is located between two adjacent impurity diffusion layers in the plurality of impurity diffusion layers. Each of the plurality of insulating films is located between one of the plurality of drain layers and one of the plurality of impurity diffusion layers, such that it is in contact with and separate from one of the plurality of drain layers, and the drain layer and the impurity diffusion layer are adjacent to each other. Each of the first impurity diffusion layer and the second impurity diffusion layer in the first LDMOS transistor of the one or more LDMOS transistors includes a first back gate layer, but does not include a source layer, and The third impurity diffusion layer in the first LDMOS transistor includes a second back gate layer and a first source layer, wherein the second back gate layer and the first source layer are alternately arranged along the first direction.

2. The semiconductor device according to claim 1, Each of the one or more LDMOS transistors further includes multiple gate insulating films and multiple gate electrodes. In the first LDMOS transistor, each of the plurality of gate insulating films is formed on the upper surface located between one of the plurality of impurity diffusion layers and one of the plurality of insulating films, wherein the impurity diffusion layer and the insulating film are adjacent to each other, and In the first LDMOS transistor, each of the plurality of gate electrodes is formed on one of the plurality of gate insulating films and one of the plurality of insulating films, wherein the gate insulating film and the insulating film are adjacent to each other.

3. The semiconductor device according to claim 1, Each of the one or more LDMOS transistors further includes multiple drift layers and multiple body layers, the multiple drift layers being formed in the semiconductor substrate, and the multiple body layers being formed in the semiconductor substrate. Each of the plurality of drift layers is formed on the upper surface to surround each of the plurality of drain layers in a cross-sectional view, and Each of the plurality of body layers is formed on the upper surface to surround each of the plurality of impurity diffusion layers in a cross-sectional view.

4. The semiconductor device according to claim 3, In the first LDMOS transistor, the depth of the first body layer surrounding the first impurity diffusion layer and the depth of the second body layer surrounding the second impurity diffusion layer are less than the depth of the third body layer surrounding the third impurity diffusion layer.

5. The semiconductor device according to claim 3, In the first LDMOS transistor, the depth of each of the plurality of drift layers is greater than the depth of the first body layer surrounding the first impurity diffusion layer, the depth of the second body layer surrounding the second impurity diffusion layer, and the depth of the third body layer surrounding the third impurity diffusion layer.

6. The semiconductor device according to claim 1, In the first LDMOS transistor, the number of the plurality of drain layers is equal to or less than six.

7. The semiconductor device according to claim 1, The one or more LDMOS transistors mentioned above include multiple LDMOS transistors. In the second LDMOS transistor among the plurality of LDMOS transistors, each of the first and second impurity diffusion layers includes a third back gate layer, but does not include a source layer. In the second LDMOS transistor, the third impurity diffusion layer includes a fourth back gate layer and a second source layer, and the fourth back gate layer and the second source layer are alternately arranged along the first direction. The number of drain layers in the first LDMOS transistor is different from the number of drain layers in the second LDMOS transistor, and The first LDMOS transistor and the second LDMOS transistor are configured as a current mirror circuit.

8. The semiconductor device according to claim 1, The one or more LDMOS transistors mentioned above include a plurality of LDMOS transistors, and In the third LDMOS transistor among the plurality of LDMOS transistors, each of the first impurity diffusion layer, the second impurity diffusion layer and the third impurity diffusion layer includes a fifth back gate layer and a third source layer, wherein the fifth back gate layer and the third source layer are alternately arranged along the first direction.

9. The semiconductor device according to claim 1, The length of the first back gate layer in the first direction is greater than the length of the second back gate layer in the first direction.

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