An LDMOS device structure and manufacturing method

Abstract

This invention discloses an LDMOS device and its manufacturing method. The manufacturing method includes: providing a substrate, forming a drift layer and a body region located in the drift layer on the substrate; depositing an HVOX layer on the substrate using thermal oxidation; fabricating a first field plate based on a defined first field plate region pattern; depositing a gate oxide layer on the substrate using thermal oxidation, and depositing a gate structure on the gate oxide layer; the first field plate is located on one side of the first gate structure and the second gate structure, respectively; depositing a sidewall material on the substrate; coating the deposited sidewall material with photoresist; providing a photomask for photolithography; and performing anisotropic etching after development to obtain the gate sidewall structure and the second field plate; and depositing an SAB layer on the second field plate structure to fabricate a third field plate, wherein the first field plate, the second field plate, and the third field plate constitute a stepped field plate structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS device structure and manufacturing method. Background Technology

[0002] In high-voltage power integrated circuits (such as BCD process platforms), improving the breakdown voltage (BV) of devices is one of the core design goals. Field plate technology is a widely adopted end-user technology that uses metal or conductive field plates fabricated on the dielectric layer on the surface of the device's drift region to control the planar electric field distribution on the drift region surface, thereby suppressing electric field spikes and effectively improving the device's breakdown voltage.

[0003] While traditional single-field-plate or inclined-field-plate structures can alleviate some of the electric field concentration problem, new peak electric fields still form at their edges, becoming a bottleneck limiting further improvements in breakdown voltage. Stepped-field-plate structures are considered a superior solution. By introducing multiple potential steps, they can more evenly distribute the electric field on the surface of the drift region, significantly reducing the peak electric field at the field-plate edges, thus theoretically achieving higher breakdown voltage and more reliable performance.

[0004] However, integrating the ideal stepped field plate structure into advanced and complex standard processes (such as 55nm BCD process) faces significant challenges. A common approach is to add a photomask and continue oxidation during the gate oxide growth stage to form the thick oxide layer steps required for the stepped field plate. However, this method has an inherent drawback: charge tends to accumulate at the edges of this thick oxide layer. These accumulated charges distort the electric field distribution, potentially inducing premature breakdown at the edges of the thick oxide layer, thus failing to fully realize the advantages of the stepped field plate and possibly even degrading device reliability.

[0005] Furthermore, while pursuing high-performance power devices, it is essential to ensure complete compatibility with low-voltage CMOS devices in the core area of ​​the process platform. Any complex process steps added to power devices, if not skillfully integrated into the existing flow, may negatively impact the performance and stability of the core devices, as well as the overall complexity and cost of the process flow.

[0006] Therefore, there is an urgent need in the current technology field for a method to manufacture LDMOS device structures. The stepped field plate prepared by this method can effectively optimize the electric field distribution to improve the breakdown voltage, while being highly compatible with the existing manufacturing process. Summary of the Invention

[0007] This invention provides an LDMOS device structure and manufacturing method that, while being compatible with existing manufacturing processes, effectively optimizes the electric field distribution and improves the breakdown voltage.

[0008] One technical solution adopted in this invention is: a method for manufacturing an LDMOS device, comprising providing a substrate, forming a drift layer and a body region located in the drift layer on the substrate, depositing an HVOX layer on the substrate using thermal oxidation, retaining the HVOX layer in the first field plate region as a first field plate based on a defined first field plate region pattern; depositing a gate oxide layer on the substrate using thermal oxidation, and depositing a gate structure on the gate oxide layer; the gate structure deposited on the substrate includes a first gate structure and a second gate structure spaced apart; the first field plate is located on one side of the first gate structure and the second gate structure respectively; depositing a sidewall material on the substrate, coating photoresist on the deposited sidewall material, providing a photomask for photolithography, the photomask having a second field plate pattern, developing, and performing anisotropic etching to obtain the gate sidewall structure and the second field plate; depositing an SAB layer on the second field plate structure, retaining the SAB layer in the third field plate region as a third field plate based on a defined third field plate region pattern, the first field plate, the second field plate, and the third field plate constituting a stepped field plate structure.

[0009] After the stepped field plate structure is fabricated, an interlayer structure is fabricated on the substrate, and through holes are fabricated on the interlayer structure. The through holes are filled with conductive pillars to connect the stepped field plate structure.

[0010] The first gate structure is located on the drift layer on one side of the body region and extends into the body region, and the second gate structure is located on the drift layer on the other side of the body region and extends into the body region.

[0011] After the gate sidewall structure is fabricated, the substrate is doped to form a drain region and a source region. After the drain region and the source region are fabricated, an SAB layer is deposited on the field plate structure. The length of the deposited third field plate is 30%-40% of the length of the first field plate.

[0012] The sidewall material is an ONO structure composed of silicon oxide, silicon nitride, and silicon oxide deposited sequentially, and the total thickness of the ONO structure deposited in the first field plate and the gate sidewall region is 550 Å-700 Å.

[0013] The length of the second field plate deposited is 60%-70% of the length of the first field plate.

[0014] The first, second, and third field plates are aligned on one side near the edge of the drain region; the thickness of the deposited third field plate and the first field plate is 150 Å-250 Å.

[0015] Another technical solution of the present invention provides an LDMOS device structure, including a substrate, on which a drift layer and a body region located in the drift layer are formed; a first gate structure and a second gate structure are deposited on the substrate at intervals, and a gate oxide layer is formed below the first gate structure and the second gate structure; a first field plate formed by an HVOX layer is disposed on the side of the first gate structure and the second gate structure facing the drain region; a second field plate and a third field plate are sequentially disposed on the first field plate; the second field plate is an ONO structure formed by sequentially deposited silicon oxide, silicon nitride, and silicon oxide, and the third field plate is an SAB layer; a sidewall structure formed by an ONO structure is disposed on the first gate structure and the second gate structure; the first field plate, the second field plate, and the third field plate are aligned on the side near the edge of the drain region, and the first field plate, the second field plate, and the third field plate form a stepped field plate, and a conductive pillar is connected above the stepped field plate.

[0016] The ONO structure is composed of silicon oxide, silicon nitride, and silicon oxide deposited sequentially.

[0017] The length of the second field plate is 60%-70% of the length of the first field plate, and the length of the third field plate is 30%-40% of the length of the first field plate; the thickness of the third field plate and the first field plate is 150A-250A, and the thickness of the second field plate is 550A-700A.

[0018] The beneficial effects of this invention are as follows: 1. By constructing a stepped field plate consisting of a first field plate (HVOX layer), a second field plate (ONO structure), and a third field plate (SAB layer), this invention can gradually modulate the potential of the drift region surface, making the surface electric field distribution flatter. In particular, the second field plate adopts an ONO (silicon oxide / silicon nitride / silicon oxide) composite dielectric structure, whose dielectric constant and thickness are precisely designed (total thickness 550A-700A), which can effectively suppress electric field spikes that may be caused by a single dielectric at the edge of the field plate. The length of each field plate follows a specific ratio (the second field plate is 60%-70% of the first field plate, and the third field plate is 30%-40% of the first field plate), ensuring a smooth transition of the electric field, thereby significantly improving the lateral breakdown voltage of the device. 2. In the CMOS sidewall etching and SAB (silicide barrier layer) fabrication process, this invention defines and retains the key dielectric layer (ONO structure as the second field plate) by adding a photomask, rather than introducing a completely new thick oxide layer growth step that may bring the risk of charge accumulation. This method completely avoids the problem of interface charge accumulation caused by the additional thermal oxidation growth of thick oxygen in traditional methods, eliminating the risk of premature breakdown caused by this at its source. 3. The three-layer field plate is strictly aligned on the side near the drain edge and reliably connected to the source through conductive pillars, ensuring the stability and consistency of the potential. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the device structure after depositing the first gate structure and the second gate structure in Example 1.

[0020] Figure 2 for Figure 1 A schematic diagram of the device structure after the deposition of the second field plate structure and the gate sidewall structure.

[0021] Figure 3 for Figure 2 A schematic diagram of the device structure after the deposition of the third field plate structure.

[0022] Figure 4 for Figure 3 A schematic diagram of the device structure after the device is connected to the conductive pillar.

[0023] In the figure: 1. Drift layer; 2. P-type inversion layer; 3. N-type layer; 4. Body region; 5. First gate structure; 6. Second gate structure; 7. First field plate; 8. Gate oxide layer; 9. Second field plate; 10. Source; 11. Gate sidewall; 12. Drain; 13. Third field plate; 14. Conductive pillar. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the drawings. The embodiments of the present invention shown in and described with reference to the drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0025] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0026] Example 1 Example 1 provides a method for manufacturing an LDMOS device. The method includes providing a substrate, forming a drift layer and a body region within the drift layer on the substrate, depositing an HVOX layer (a silicon dioxide layer in a specific process step, used for via etching stop) on the substrate using thermal oxidation, retaining the HVOX layer within a defined first field plate region as a first field plate based on a defined first field plate region pattern, depositing a gate oxide layer on the substrate using thermal oxidation, and depositing a gate structure on the gate oxide layer; the gate structure deposited on the substrate includes spaced-apart first... A gate structure and a second gate structure are provided; a first field plate is located on one side of the first gate structure and the second gate structure, respectively; a sidewall material is deposited on the substrate, photoresist is coated on the deposited sidewall material, a photomask is provided for photolithography, the photomask has a second field plate pattern, after development, anisotropic etching is performed to obtain the gate sidewall structure and the second field plate; an SAB layer is deposited on the second field plate structure, and based on the defined third field plate region pattern, the SAB layer in the third field plate region is retained as the third field plate, and the first field plate, the second field plate and the third field plate constitute a stepped field plate structure.

[0027] The following will be combined with the appendix Figure 1-4 The manufacturing method of an LDMOS device provided in Embodiment 1 will be explained and described. The manufacturing method of an LDMOS device provided in Embodiment 1 includes the following steps: Step 1: Deposit HVOX layer.

[0028] An HVOX layer is deposited on a substrate having a drift layer 1 and a body region 4 formed in the drift layer 1. During deposition, a thermal oxidation process is used to form an HVOX layer with a thickness of 150 Å-250 Å on the substrate.

[0029] A photomask is provided. Based on the pattern on the photomask, photoresist coated on a substrate is patterned. After photolithography and development, excess HVOX layer is removed to obtain the desired result. Figure 1 The first field plate 7 structure is shown.

[0030] The length of the first field plate 7 varies for LDMOS devices with different threshold voltages, ranging from 0.2 μm to 0.9 μm.

[0031] Step 2: Deposit the gate structure.

[0032] After completing the fabrication of the first field board in step 1, the gate structure is fabricated, including depositing the gate oxide layer 8 on the substrate by thermal oxidation, and then depositing the gate structure on top of the gate oxide layer.

[0033] The gate structure deposited on the substrate includes a first gate 5 and a second gate 6, wherein the first gate 5 and the second gate 6 are located at both ends of the body region 4, and both the first gate 5 and the second gate 6 are disposed in the region where the body region 4 transitions to the drift layer 1.

[0034] The first field plate 7 is attached to one side of the first gate 5 or the second gate 6, and the other side of the first field plate 7 is adjacent to the edge of the drain 12.

[0035] Step 3: Fabricate the gate sidewall structure and the second field plate.

[0036] After fabricating the first gate structure 5 and the second gate structure 6, sidewall material is deposited on the substrate. Photoresist is coated on the deposited sidewall material, a photomask is provided for photolithography, and after development, anisotropic etching is performed to obtain the gate sidewall structure 11 and the second field plate 9.

[0037] The sidewall structure 11 and the second field plate 9 can be fabricated using a single photomask. Specifically, this includes depositing sidewall material on the substrate. The sidewall material deposited in step 3 is an ONO structure, specifically SiO2 / Si3N4 / SiO2 deposited sequentially from bottom to top. The total thickness of the deposited ONO structure is 550 Å-700 Å.

[0038] Step 3 completes the second field plate structure and the sidewall structure in one etching operation. Specifically, a photomask with the pattern of the second field plate structure is provided. Photoresist is applied to the deposited sidewall material. The pattern of the second field plate is transferred to the photoresist by photolithography and development. Then, anisotropic etching (controlling the etching rate of each region; this technology is prior art and will not be described in detail in this application) is performed to etch away the sidewall material except for the second field plate region. At the same time, the etching rate is controlled to form the gate sidewall structure 11 in the gate sidewall region.

[0039] In this process, etching the gate sidewall structure alone does not require a photomask and can be completed using anisotropic etching. However, this application uses a single photomask to simultaneously complete the etching of the second field plate 9 and the gate sidewall structure 11 in conjunction with anisotropic etching. This process has strong compatibility and does not increase the complexity of the process steps.

[0040] The second field plate 9 and the gate sidewall structure 11 formed as follows Figure 2 As shown.

[0041] After completing the fabrication of the gate sidewall structure 11 and the second field plate 9, the residual photoresist is removed.

[0042] The length of the second board 9 produced is 60%-70% of the length of the first board 7.

[0043] Step 4: Form the source and drain.

[0044] The source 10 and drain 12 are formed by ion implantation or other suitable methods, wherein the drain 12 is located at the edge of the first field plate on one side of the first gate structure 5 and the edge of the first field plate on one side of the second gate structure 6, respectively. The drain 12 is located on the upper surface of the drift layer 1, and the source 10 is located on the upper surface of the body region 4.

[0045] Step 5: Deposit the third field plate.

[0046] After completing step 4, an SAB layer (silicide barrier layer) is deposited on the substrate. After the SAB layer is deposited, photoresist is applied over the deposited SAB layer. After photolithography and development processes, a patterned photoresist is obtained. The SAB layer is etched using the photoresist as a mask to obtain the third field plate 13. The obtained third field plate 13 is as follows: Figure 3 As shown.

[0047] The thickness of the deposited third field plate 13 is 150 Å-250 Å, and the length of the deposited third field plate 13 is 30%-40% of the length of the first field plate 7.

[0048] The first field plate 7, the second field plate 9, and the third field plate 13 are aligned on one side near the edge of the drain region, forming a stepped field plate structure.

[0049] The three field plates are strictly aligned on the side near the drain edge and reliably connected to the source via conductive pillars, ensuring the stability and consistency of the potential. At the same time, the lengths of each field plate follow a specific ratio (the second field plate is 60%-70% of the first field plate, and the third field plate is 30%-40% of the first field plate), ensuring a smooth transition of the electric field, thereby significantly improving the device's lateral breakdown voltage.

[0050] Step 6: Make conductive pillars.

[0051] After the stepped field plate is fabricated, the conductive post 14 can connect the stepped field plate to external devices.

[0052] As an example, an interlayer structure can be fabricated on a substrate first, through-holes can be etched in the interlayer dielectric layer, and conductive material can be filled into the through-holes to obtain conductive pillars 14, wherein the etched through-holes can be W-shaped through-holes.

[0053] As an example, the conductive post 14 can be made of tungsten (W) pillars or other suitable conductive materials. Wiring is used to ensure that both conductive posts 14 on the stepped field plate structure are electrically connected to the source 10.

[0054] Example 2 Example 2 provides an LDMOS device structure, such as Figure 4As shown, the LDMOS device structure includes a substrate, on which a drift layer 1 and a body region 4 are formed; a first gate structure 5 and a second gate structure 6 are deposited at intervals on the substrate, with a gate oxide layer 8 below the first gate structure 5 and the second gate structure 6; a first field plate 7 formed of an HVOX layer is disposed on the side of the first gate structure 5 and the second gate structure 6 facing the drain region 12. The length of the first field plate 7 varies for LDMOS devices with different threshold voltages, and the length of the deposited first field plate 7 is 0.2μm-0.9μm. A second field plate 9 and a third field plate 13 are sequentially disposed on the first field plate 7. The second field plate 9 is an ONO structure formed by sequentially depositing silicon oxide, silicon nitride, and silicon oxide, and the third field plate 13 is an SAB layer. A sidewall structure 11 formed by the ONO structure is disposed on the first gate structure 5 and the second gate structure 6. The first field plate 7, the second field plate 9, and the third field plate 13 are aligned on one side near the edge of the drain 12 region. The first field plate 7, the second field plate 9, and the third field plate 13 form a stepped field plate. A conductive post 14 is connected above the stepped field plate, and the stepped field plates on both sides are electrically connected to the source 10 (connected through a metal layer) through the conductive post 14.

[0055] The ONO structure is composed of silicon oxide, silicon nitride, and silicon oxide deposited sequentially.

[0056] The first gate structure 5 is located on the drift layer 1 on one side of the body region 4 and extends to the body region 4, while the second gate structure 6 is located on the drift layer 1 on the other side of the body region 4 and extends to the body region 4.

[0057] The length of the second plate 9 is 60%-70% of the length of the first plate 7, and the length of the third plate 13 is 30%-40% of the length of the first plate 7; the thickness of the third plate 13 and the first plate 7 is 150A-250A, and the thickness of the second plate 9 is 550A-700A.

[0058] In the description of this invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0059] Furthermore, it should be noted that in this specification, "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0060] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for manufacturing an LDMOS device, characterized in that, A substrate is provided, on which a drift layer and a volume region located in the drift layer are formed. An HVOX layer is deposited on the substrate using a thermal oxidation method. Based on the defined first field plate region pattern, the HVOX layer within the first field plate region is retained as the first field plate. A gate oxide layer is deposited on the substrate using a thermal oxidation method, and a gate structure is deposited on the gate oxide layer; The gate structure deposited on the substrate includes a first gate structure and a second gate structure spaced apart. The first field plate is located on one side of the first gate structure and the second gate structure, respectively; Sidewall material is deposited on the substrate, photoresist is coated on the deposited sidewall material, a photomask is provided for photolithography, the photomask has a second field plate pattern, after development, anisotropic etching is performed to obtain the gate sidewall structure and the second field plate. An SAB layer is deposited on the second field plate structure. Based on the defined third field plate region pattern, the SAB layer in the third field plate region is retained as the third field plate. The first field plate, the second field plate, and the third field plate constitute a stepped field plate structure.

2. The method for manufacturing an LDMOS device according to claim 1, characterized in that, After the stepped field plate structure is fabricated, an interlayer structure is fabricated on the substrate, and through holes are fabricated on the interlayer structure. The through holes are filled with conductive pillars to connect the stepped field plate structure.

3. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The first gate structure is located on the drift layer on one side of the body region and extends into the body region, and the second gate structure is located on the drift layer on the other side of the body region and extends into the body region.

4. The method for manufacturing an LDMOS device according to claim 1, characterized in that, After the gate sidewall structure is fabricated, the substrate is doped to create the drain region and the source region. After the fabrication of the drain region and the source region is completed, an SAB layer is deposited on the field plate structure; The length of the deposited third field plate is 30%-40% of the length of the first field plate.

5. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The sidewall material is an ONO structure composed of silicon oxide, silicon nitride, and silicon oxide deposited sequentially, and the total thickness of the ONO structure deposited in the first field plate and the gate sidewall region is 550 Å-700 Å.

6. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The length of the second field plate deposited is 60%-70% of the length of the first field plate.

7. A method for manufacturing an LDMOS device according to claim 4, characterized in that, The first field plate, the second field plate, and the third field plate are aligned on the side closest to the edge of the drain region; The thickness of the deposited third field plate and the first field plate is 150 Å-250 Å.

8. An LDMOS device structure, characterized in that, Includes a substrate, on which a drift layer and a volume region located in the drift layer are formed; A first gate structure and a second gate structure are deposited on the substrate at intervals, and a gate oxide layer is located below the first gate structure and the second gate structure. A first field plate formed of an HVOX layer is disposed on the side of the first gate structure and the second gate structure facing the drain region; The first field plate is sequentially provided with a second field plate and a third field plate; The second field plate is an ONO structure formed by sequentially depositing silicon oxide, silicon nitride, and silicon oxide, and the third field plate is an SAB layer; The first gate structure and the second gate structure are provided with sidewall structures formed by ONO structures; The first field plate, the second field plate, and the third field plate are aligned on one side near the edge of the drain region, forming a stepped field plate, with a conductive post connected above the stepped field plate.

9. The LDMOS device structure according to claim 8, characterized in that, The ONO structure is composed of silicon oxide, silicon nitride, and silicon oxide deposited sequentially.

10. An LDMOS device structure according to claim 8, characterized in that, The length of the second plate is 60%-70% of the length of the first plate, and the length of the third plate is 30%-40% of the length of the first plate. The thickness of the third field plate and the first field plate is 150A-250A, and the thickness of the second field plate is 550A-700A.

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