A method, device and equipment for constructing a multi-finger structure LDMOS model
By constructing a nonlinear drift region resistance model and thermal network, and combining thermoelectric coupling, the problem of low accuracy in existing LDMOS models is solved, and accurate description and thermal management of multi-finger LDMOS structures are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTH CHINA UNIV OF TECH
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-09
AI Technical Summary
Existing methods for constructing multi-finger LDMOS models assume that thermal resistance and drift region resistance are linearly inversely proportional to the number of finger cells, leading to inaccurate models that cannot accurately describe the self-heating effect, thus affecting the output accuracy and reliability of the circuit.
A model reflecting the nonlinear effect of the number of finger cells on the drift region resistance is constructed. By combining the drift region resistance model and the intrinsic metal-oxide-semiconductor model with thermal resistance, thermal capacity and power consumption input sources, a non-distributed thermal network is constructed and thermoelectric coupling is performed to achieve nonlinear correction of multi-finger structure LDMOS.
This improves the accuracy of the LDMOS model, enabling it to accurately reflect the nonlinear effect of the number of finger cells on thermal resistance and electrical resistance, thus improving the thermal management and performance prediction of the circuit.
Smart Images
Figure CN122174785A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit simulation technology, and more specifically, to a method, apparatus and device for constructing a multi-finger LDMOS model. Background Technology
[0002] In the fields of power electronics and radio frequency communications, lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors are widely used in DC-DC converters, RF power amplifiers, and other circuits due to their high voltage tolerance and high power density. To meet the high current output requirements of LDMOS devices, the industry commonly employs a multi-finger structure in LDMOS device design, which involves connecting multiple single-finger LDMOS cells in parallel. This increases the number of current channels, reduces on-resistance, and improves the device's current drive capability. However, multi-finger LDMOS devices exhibit significant self-heating effects during operation due to current concentration and uneven heat dissipation. For example, the heat converted from device power consumption leads to increased chip temperature, resulting in decreased mobility, threshold voltage drift, and other electrical characteristic degradations, severely impacting the circuit's output accuracy, efficiency, and reliability. Therefore, constructing a SPICE model that accurately describes the LDMOS self-heating effect is crucial for predicting device performance and optimizing thermal management schemes during the circuit design phase.
[0003] Currently, the SPICE simulation model used to describe the self-heating effect of LDMOS typically assumes that the thermal resistance and drift region resistance are linearly inversely proportional to the number of finger cells.
[0004] However, the above-mentioned method of constructing the LDMOS model uses a linear inverse relationship to characterize the relationship between thermal resistance and the number of finger cells, and the relationship between drift region resistance and the number of finger cells, which is inaccurate and leads to the inaccuracy of the SPICE model of multi-finger LDMOS. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide a method, apparatus and device for constructing a multi-finger LDMOS model, so as to overcome at least one of the above-mentioned defects.
[0006] In a first aspect, embodiments of this application provide a method for constructing a multi-finger LDMOS model, including: A drift region resistance model is constructed to reflect the nonlinear effect of the number of finger units on the drift region resistance in a multi-finger structure. Based on the drift region resistance model and intrinsic metal-oxide semiconductor, an electrical model of LDMOS reflecting the characteristics of multi-finger structure is constructed. Based on thermal resistance, thermal capacity, and power consumption input sources, a non-distributed thermal network is constructed to simulate the self-heating effect, and the thermal resistance of the multi-finger LDMOS is nonlinearly corrected. By thermoelectrically coupling the LDMOS electrical model with a non-distributed thermal network, an LDMOS model with a multi-finger structure including a self-heating effect is obtained.
[0007] In an optional implementation, the step of constructing a drift region resistance model that reflects the nonlinear effect of the number of finger units in a multi-finger structure on the drift region resistance includes: determining a first relationship expression between the drift region resistance and the gate-source voltage and a second relationship expression between the drift region resistance and the drift region voltage drop; and based on the first and second relationship expressions, determining a drift region resistance model including a nonlinear correction term to reflect the nonlinear effect of the number of finger units on the drift region resistance through the nonlinear correction term.
[0008] In an optional implementation, the first relational expression is determined as follows: with a fixed drain-source voltage and given different gate-source voltages, the characteristic curve of the drain-source current changing with the gate-source voltage is determined; the drain voltage of the intrinsic metal-oxide-semiconductor is determined according to the drain-source current and drain current formulas; the channel resistance is determined according to the drain voltage and drain-source current of the intrinsic metal-oxide-semiconductor; the drift region resistance is determined according to the difference between the drain-source resistance and the channel region resistance; and the relationship between the drift region resistance and the gate-source voltage is fitted to obtain the first relational expression.
[0009] In an optional implementation, the second relational expression is determined by: transforming the drift region conduction current formula using the surface resistivity formula of the drift region to obtain the first drift region current formula; performing spatial integration on the differential equation of the first drift region current formula to obtain the drift region equivalent resistance formula; and converting the drift region equivalent resistance formula into a function of voltage to obtain the second relational expression.
[0010] In an optional implementation, the nonlinear correction term is determined based on the number of finger units in the multifinite structure and the critical exponent for thermal resistance saturation.
[0011] In an optional implementation, the step of constructing an LDMOS electrical model reflecting the multi-finger structure characteristics based on the drift region resistance model and the intrinsic metal-oxide-semiconductor includes: obtaining parasitic resistance using a post-parametric simulation extraction method, the parasitic resistance including source metal resistance and drain metal resistance; connecting the drift region resistance model and drain metal resistance in series with the drain of the intrinsic metal-oxide-semiconductor as the drain of the LDMOS, and associating the drift region resistance model with the drift region resistance; connecting the source metal resistance in series with the source of the intrinsic metal-oxide-semiconductor model as the source of the LDMOS, thereby generating the LDMOS electrical model.
[0012] In an optional implementation, the step of thermoelectrically coupling the LDMOS electrical model with a non-distributed thermal network to obtain an LDMOS model with a multi-finger structure including a self-heating effect includes: connecting the drain and source of the electrical model using a current source, and converting the electrical power consumption in the non-distributed thermal network into the thermal current output by the power consumption input source; using the node voltage corresponding to the thermal current to characterize the temperature change, and adding the node voltage to the current source to feed the temperature change back to the electrical model.
[0013] In an optional implementation, the steps of constructing a non-distributed thermal network to simulate the self-heating effect based on thermal resistance, thermal capacity, and power consumption input sources, and performing nonlinear correction on the thermal resistance of the multi-finger LDMOS, include: connecting the thermal resistance, thermal capacity, and power consumption input sources in parallel to construct a non-distributed thermal network to simulate the self-heating effect; and performing nonlinear correction on the thermal resistance using a thermal resistance model with the same form but different parameters as the drift region resistance model.
[0014] Secondly, embodiments of this application also provide a multi-finger LDMOS model construction apparatus, the apparatus comprising: The resistance model construction module is used to construct a drift region resistance model that reflects the nonlinear effect of the number of finger units on the drift region resistance in a multi-finger structure. The electrical model building module is used to construct an LDMOS electrical model that reflects the characteristics of the multi-finger structure based on the drift region resistance model and intrinsic metal-oxide-semiconductor. The thermal network construction module is used to construct a non-distributed thermal network to simulate the self-heating effect based on thermal resistance, thermal capacity, and power consumption input sources, and to perform nonlinear correction on the thermal resistance of the multi-finger LDMOS. The final model building module is used to thermo-electrically couple the LDMOS electrical model with the non-distributed thermal network to obtain an LDMOS model with a multi-finger structure that includes self-heating effects.
[0015] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the LDMOS model construction method for the multi-finger structure described above are performed.
[0016] The embodiments of this application bring the following beneficial effects: This application provides a method, apparatus, and device for constructing a multi-finger LDMOS model. The drift region resistance model accurately reflects the nonlinear influence of the number of finger cells on the drift region resistance. Furthermore, the drift region resistance model and the intrinsic metal-oxide-semiconductor model are used to construct the LDMOS model, improving the accuracy of the LDMOS model construction. Simultaneously, the thermal resistance of the multi-finger LDMOS is nonlinearly corrected, accurately reflecting the nonlinear influence of the number of finger cells on the thermal resistance. Compared with existing multi-finger LDMOS model construction methods, this application solves the problem of low accuracy in constructing multi-finger LDMOS models.
[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart illustrating the method for constructing a multi-finger LDMOS model according to an embodiment of this application is shown. Figure 2 An equivalent circuit diagram of the LDMOS provided in an embodiment of this application is shown; Figure 3 A flowchart illustrating the steps for determining the drift region resistance model provided in an embodiment of this application is shown; Figure 4 A structural diagram of the non-distributed heat network provided in an embodiment of this application is shown; Figure 5 A structural diagram of the LDMOS model provided in an embodiment of this application is shown; Figure 6 A schematic diagram showing the SPICE simulation results of the LDMOS model with 10 finger units provided in the embodiments of this application is illustrated. Figure 7 A schematic diagram showing the SPICE simulation results of the LDMOS model with 50 finger cells provided in the embodiments of this application is illustrated. Figure 8 This paper shows a schematic diagram of the structure of the LDMOS model building device with a multi-finger structure provided in an embodiment of this application; Figure 9A schematic diagram of the structure of the electronic device provided in the embodiments of this application is shown. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.
[0021] To facilitate understanding of this embodiment, the following describes each of the exemplary steps provided in this embodiment using the multi-finger structure LDMOS model construction method provided in this application as an example applied to a terminal device.
[0022] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for constructing a multi-finger LDMOS model, as provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the method for constructing a multi-finger LDMOS model includes: Step S101: Construct a drift region resistance model that reflects the nonlinear effect of the number of finger units in the multi-finger structure on the drift region resistance.
[0023] A multi-finger structure can refer to a layout in which a single power device with a large aspect ratio is broken down into multiple parallel finger-like units with the same structure, and the multiple finger-like units are connected in parallel to form an overall layout.
[0024] The drift region resistance refers to the resistance of the lightly doped drift region in an LDMOS.
[0025] To construct an LDMOS model for SPICE simulation, an LDMOS electrical model needs to be built. To do this, the equivalent circuit diagram of LDMOS can be determined first.
[0026] The following reference Figure 2 Let's introduce the equivalent circuit diagram of LDMOS.
[0027] Figure 2 The equivalent circuit diagram of the LDMOS provided in the embodiments of this application is shown, such as... Figure 2 As shown, in the equivalent circuit of LDMOS, G represents the gate; S represents the source; and D represents the drain. Indicates the resistance in the drift region; and Indicates external parasitic resistance; The MOS structure between node di1 and node di2 is the channel region; node di1 is the connection node between the channel region and the drift region, and node di1 serves as the intrinsic drain; node di is the external drain node and is the drift region resistance. The electrical output terminal.
[0028] In one embodiment, when constructing the LDMOS electrical model, the LDMOS electrical model includes source-drain resistance, which can refer to the equivalent resistance between the source (S) and drain (D) of the LDMOS, and includes the drift region resistance and the channel region resistance.
[0029] The drift region resistance and channel region resistance are determined by the external voltage bias, which includes the drain-source voltage Vds (the voltage between the drain and source) and the gate-source voltage. The voltage between the gate and the source together determines the operating state of the LDMOS device (such as the degree of conduction and the magnitude of current) and the resistance distribution in the channel region and the drift region.
[0030] When the external voltage bias applied to the LDMOS device is small, the channel region resistance accounts for the majority of the resistance, while the drift region resistance is less affected by the external voltage bias and can be considered a constant resistance. When the external voltage bias applied to the LDMOS device is large, the drift region current path narrows, the drift region resistance increases rapidly and becomes much larger than the channel region resistance, and at this time, most of the voltage drop falls on the drift region.
[0031] This shows that the voltage at node di1 remains low throughout the entire operating region, and the internal MOS with di1 as its intrinsic drain is minimally affected by external high-voltage bias. Therefore, a regional modeling method can be adopted, modeling the channel region and the drift region separately. The channel region model still uses the original BSIM4 model, and only the drift region needs to be modeled. Together, they constitute the LDMOS electrical model.
[0032] The following reference Figure 3 This section will introduce the process of determining the resistance model in the drift region.
[0033] Figure 3 A flowchart illustrating the steps for determining the drift region resistance model provided in this application embodiment is shown, as follows: Figure 3 As shown, the steps for determining the resistance model in the drift region include: Step S1011: Determine the first relationship expression between the drift region resistance and the gate-source voltage, and the second relationship expression between the drift region resistance and the drift region voltage drop.
[0034] In one embodiment, when determining the first relational expression, under a fixed drain-source voltage and given different gate-source voltages, the characteristic curve of the drain-source current changing with the gate-source voltage is determined; the drain voltage of the intrinsic metal-oxide-semiconductor is determined according to the drain-source current and drain current formulas; the channel resistance is determined according to the drain voltage and drain-source current of the intrinsic metal-oxide-semiconductor; the drift region resistance is determined according to the difference between the drain-source resistance and the channel region resistance; and the relationship between the drift region resistance and the gate-source voltage is fitted to obtain the first relational expression.
[0035] Specifically, the first step is the drain-source voltage of the LDMOS. (The voltage between the drain and source) is taken as a small fixed value, in Obtained by measurement under fixed conditions - Curve, in which, - The curves are obtained through actual measurements using a semiconductor parameter analyzer or extraction using device simulation tools. The core steps are to fix a small bias voltage between the drain and source, scan the gate-source voltage, and simultaneously acquire the drain-source current. .
[0036] The second step is that since the entire LDMOS is in the linear region when Vds is small, the intrinsic metal-oxide semiconductor (intrinsic MOS) must also be in the linear region. Therefore, the drain current calculation formula for the linear region can be used, based on the measured values. Calculate the drain voltage of the intrinsic MOS. The linear region refers to the state in which the entire LDMOS device (including the core region and drift region of the intrinsic metal-oxide-semiconductor) operates without pinch-off, without saturation, and where the current and voltage exhibit a strictly ohmic linear relationship.
[0037] The third step is to calculate the channel resistance. , The source-drain resistance is Then the drift region resistance is .
[0038] The fourth step, after determining the drift region resistance, is to adjust the drift region resistance... The relationship between the gate-source voltage Vgs and the gate voltage Vgs is fitted to obtain the first relationship expression. The first relationship expression is: ; In the above formula, This represents the resistance in the zero-bias drift region; Indicates the resistance of the drift region The modulation coefficient.
[0039] In one embodiment, when determining the second relational expression, the drift region conduction current formula is transformed using the surface resistivity formula of the drift region to obtain the first drift region current formula; the differential equation of the first drift region current formula is spatially integrated to obtain the drift region equivalent resistance formula; and the drift region equivalent resistance formula is converted into a voltage function to obtain the second relational expression.
[0040] Specifically, the first step is to determine the conduction current in the drift region. The calculation formula.
[0041] ; In the above formula, the drift region is regarded as an ideal semiconductor rod, and W represents the width of the semiconductor rod through which the current flows. Indicates the thickness of the semiconductor rod; Indicates doping concentration; q represents electron charge; Indicates the carrier drift velocity. ; Indicates low-field mobility; E represents electric field strength; This represents the critical electric field.
[0042] The second step is to Substitute the drift region current The calculation formula yields: .
[0043] The third step is to define the reciprocal of the two-dimensional surface resistance (i.e., the conductivity term): Then the formula for the conduction current in the drift region can be converted into the formula for the current in the first drift region: ; By rearranging the formula for the current in the first drift region, we obtain the differential form of the formula for the current in the first drift region: ,in, , , It is actually the maximum possible current (saturation current). Because... Then, the differential equation for the current formula in the first drift region can be obtained: ,in, This represents the saturation current in the drift region.
[0044] Fourth step, assuming the current is constant (steady-state conservation), perform spatial integration on the differential equation of the current formula in the first drift region (from... arrive ), we can obtain: ; In the above formula, The length of the semiconductor rod is represented; the right side of the equation is a constant integral: .
[0045] Therefore, the equivalent resistance of the drift region can be obtained as: ; in, Indicates low field resistance. ,and We can obtain: ; In the above formula, This represents the correction factor.
[0046] Fifth, in a circuit simulator (such as SPICE), on the one hand, since most circuit components can only use voltage as the independent variable and cannot directly use current as the input variable; on the other hand, when hour, At this time, the function is The resistance is not differentiable at certain points, causing numerical instability. Therefore, the resistance expression needs to be converted into a function of voltage, and a smoothing mechanism needs to be introduced to avoid singularities.
[0047] For example: If a new node di1 is added, and node di1 represents the potential point before entering the drift region, then we have: , This represents the actual voltage drop across the drift region. Using the previously obtained current expression... Let the critical voltage be... The critical voltage is the voltage required for the entire drift region to reach the critical electric field, then we can obtain: According to Ohm's law, the resistance of the drift region is... .
[0048] because and Substituting this into the drift region resistance calculation formula, we can obtain the preliminary voltage dependence model of the drift region resistance: The initial voltage-dependent model is linear and cannot reflect the true nonlinear trend. To more accurately fit the experimental data and simulate complex behaviors, two empirical parameters can be introduced to control the curvature (power-law exponent). and symmetry factor The second relation expression can be obtained as follows: ; In the above formula, This represents the built-in potential difference, which is automatically calculated from the global state of the circuit using Kirchhoff's laws. Not an independent variable, but a variable subject to The result of combined influences.
[0049] Step S1012: Based on the first relational expression and the second relational expression, determine the drift region resistance model including the nonlinear correction term, so as to reflect the nonlinear effect of the number of finger units on the drift region resistance through the nonlinear correction term.
[0050] The first and second relational expressions are combined, and a nonlinear correction term is added to obtain the drift region resistance model. The nonlinear correction term is determined based on the number of finger units in the multi-finger structure and the critical exponent for thermal resistance saturation. For example, the drift region resistance model is: ; In the above formula, This represents the resistance in the zero-bias drift region; β represents the number of finger units in the multi-finger structure; β represents the exponential fitting parameter, used to adjust the curvature of the resistance in the drift region as a function of current / voltage. In the basic physical model, β is assumed to be 1 (ideal velocity saturation), but the actual device characteristics may deviate from this assumption. The larger the value of β, the smoother the change of resistance with current / voltage, and the smaller the value of β, the steeper the change (close to ideal saturation). Indicates the drift region resistance for The modulation coefficient; The critical saturation index represents the resistance in the drift region of a multi-finger structure. Indicate the symmetry factor to ensure that the drift region resistance model is within... The smooth symmetry of the vicinity (to avoid numerical discontinuities) is crucial for SPICE convergence.
[0051] Indicates that the resistance in the drift region is affected The nonlinear correction term has an impact. In LDMOS, each finger cell represents a current channel. Increasing the number of finger cells is equivalent to connecting multiple channels in parallel, which can shunt the current and thus reduce the resistance.
[0052] When the finger units increase to At this stage, parasitic resistances between the multi-finger structures (such as contact resistance and interconnect resistance) begin to limit the overall performance of the LDMOS. The drift region resistance is nearing its limit, the current in each finger cell tends to be evenly distributed, and the reduction in drift region resistance tends to saturate. The drain is typically located on one side of the device (drain-on-side). Therefore, as the number of finger cells increases, the current distribution becomes more uniform, the reduction in parasitic resistance is more significant, and the correction term is positive, meaning... The reduction is faster, meaning the value of the nonlinear correction term is greater than 1.
[0053] Step S102: Based on the drift region resistance model and intrinsic metal-oxide semiconductor, construct an LDMOS electrical model that reflects the characteristics of the multi-finger structure.
[0054] When constructing the LDMOS electrical model, parasitic resistance is obtained using the post-parametric simulation extraction (PEX) method. Parasitic resistance includes the source metal resistance. and drain metal resistor The drift region resistor and the drain metal resistor The drain of the intrinsic metal-oxide-semiconductor is connected in series with the drain of the LDMOS, and the drift region resistance model is correlated with the drift region resistance. Simultaneously, the source metal resistance is... The source of the intrinsic metal-oxide-semiconductor is connected in series with the source of the LDMOS to generate the LDMOS electrical model.
[0055] For example: drift region resistance One end is connected in series with the drain of the intrinsic metal-oxide-semiconductor (intrinsic MOS), and the drift region resistance... The other end is connected to the drain metal resistor One end is connected in series, drain metal resistor The other end serves as the drain of the LDMOS, while the source of the intrinsic metal-oxide-semiconductor is connected to the source metal resistor. One end is connected to the source metal resistor. The other end serves as the source of the LDMOS.
[0056] Step S103: Based on thermal resistance, thermal capacity, and power consumption input sources, a non-distributed thermal network is constructed to simulate the self-heating effect, and the thermal resistance of the multi-finger LDMOS is nonlinearly corrected.
[0057] By connecting thermal resistance, thermal capacity, and power consumption input sources in parallel, a non-distributed thermal network is constructed.
[0058] The following reference Figure 4 Let's introduce non-distributed thermal networks.
[0059] Figure 4 A structural diagram of the non-distributed heat network provided in an embodiment of this application is shown, as follows: Figure 4 As shown, the non-distributed thermal network includes thermal resistance. Heat capacity and power input source And thermal resistance Heat capacity The power input source is connected in parallel to simulate the self-heating effect.
[0060] In one embodiment, when the number of finger units increases, ideally, each finger unit can be assumed to be completely independent, with heat moving vertically downwards to the substrate and no lateral heat diffusion between different finger units, which is linear behavior. However, in reality, multiple finger units generate heat simultaneously, resulting in thermal coupling. The temperature changes caused by this coupling are superimposed, so the thermal resistance no longer decreases inversely proportionally with the number of finger units, but gradually approaches saturation, which is nonlinear behavior. Therefore, nonlinear corrections can be made to the thermal resistance.
[0061] Specifically, since the drift region resistance model is a nonlinear model, it can be used to achieve nonlinear correction of thermal resistance.
[0062] For example, the thermal resistance model (i.e. the formula for calculating thermal resistance) can be set to the same form as the drift region resistance model, but with different parameters, including the modulation coefficient and the critical saturation index. In the thermal resistance model, the modulation coefficient represents the modulation coefficient of thermal resistance to the number of finger units, and the critical saturation index represents the critical saturation index of the thermal resistance of the multi-finger structure.
[0063] Step S104: The LDMOS electrical model is thermoelectrically coupled with a non-distributed thermal network to obtain an LDMOS model with a multi-finger structure including a self-heating effect.
[0064] Using a current source The drain and source of the electrical model are connected, and the electrical power consumption in the non-distributed thermal network is converted into the thermal current output by the power consumption input source. The node voltage corresponding to the thermal current is used to characterize the temperature change, and the node voltage is added to the current source to feed the temperature change back to the electrical model.
[0065] The following reference Figure 5 Let's introduce the structure of the LDMOS model.
[0066] Figure 5 A structural diagram of the LDMOS model provided in the embodiments of this application is shown, as follows: Figure 5 As shown, the drift region resistance One end is connected in series with the drain of the intrinsic metal-oxide-semiconductor (intrinsic MOS), and the drift region resistance... The other end is connected to the drain metal resistor One end is connected in series, drain metal resistor The other end serves as the drain of the LDMOS, with a drain metal resistor. One end is also connected to the current source One end is connected to the current source. The other end is connected to the source of the intrinsic metal-oxide-semiconductor (MOS) semiconductor, and the source of the MOS semiconductor is also connected to the source metal resistor. One end is connected to the source metal resistor. The other end serves as the source of the LDMOS. The dashed box represents the LDMOS electrical model.
[0067] In non-distributed thermal networks, electrical power consumption ( ) converted into thermoelectric current The voltage at node Tnote is driven by thermal current. At the same time, due to If the voltage is directly proportional to the temperature change, then... It can be detected by temperature changes ( ) is used to characterize it.
[0068] Get the temperature change at node Tnote Using an electric current source This temperature change This feedback is used in the electrical model to correct the drift region resistance and intrinsic MOS parameters, thereby obtaining an LDMOS model that reflects the self-heating effect. The intrinsic MOS parameters include, but are not limited to, mobility and threshold voltage.
[0069] For example: Obtain the voltage at node Tnote. ,Will Add to current source In order to change the temperature This feedback is then incorporated into the electrical model.
[0070] In this way, thermal resistance and thermal capacitance can be isolated from the electrical model. By introducing independent nodes (Tnodes), thermal capacitance is separated from its parallel connection with device capacitance, eliminating unnecessary capacitive coupling and enhancing the stability and convergence of the simulation.
[0071] The following reference Figure 6 and Figure 7 This paper presents the results of SPICE simulation using the LDMOS model with a multi-finger structure including a self-heating effect provided in this embodiment.
[0072] Figure 6 A schematic diagram showing the simulation results of the LDMOS model with 10 finger cells provided in the embodiments of this application is illustrated. Figure 6 As shown, simulations reveal that the number of finger cells in the LDMOS model is 10. The values at 0.5V, 1.4V, 2.3V, 3.2V, 4.1V, and 5V respectively. - The curve shows a maximum error of only 2.55%, determined by dividing the maximum difference between the measured data and the model-fitted value (simulation value) by the absolute value of the measured data; the root mean square error (RMSError) is only 0.73%. The LDMOS model operates at a power supply voltage of 16V, and W represents the gate width. The gate width of the multi-finger LDMOS structure is determined by the product of W and the number of finger cells.
[0073] Figure 7 A schematic diagram showing the simulation results of the LDMOS model with 50 finger cells provided in the embodiments of this application is illustrated. Figure 7 As shown, simulations reveal that the number of finger cells in the LDMOS model is 50. The values at 0.5V, 1.4V, 2.3V, 3.2V, 4.1V, and 5V respectively. - The curve shows a maximum error of only 1.99%, determined by dividing the maximum difference between the measured data and the model-fitted value (simulation value) by the absolute value of the measured data; the root mean square error (RMSError) is only 0.86%. The LDMOS model operates at a power supply voltage of 16V, and W represents the gate width. The gate width of the multi-finger LDMOS structure is determined by the product of W and the number of finger cells.
[0074] The multi-finger LDMOS model construction method provided in this application can accurately reflect the nonlinear influence of the number of finger cells on the drift region resistance through the drift region resistance model. Then, the LDMOS model is constructed by using the drift region resistance model and the intrinsic metal-oxide-semiconductor model, which improves the accuracy of LDMOS model construction. At the same time, it can also perform nonlinear correction on the thermal resistance of multi-finger LDMOS, accurately reflect the nonlinear influence of the number of finger cells on the thermal resistance, and solve the problem of low accuracy in constructing multi-finger LDMOS models.
[0075] Based on the same inventive concept, this application also provides an LDMOS model construction device for a multi-finger structure corresponding to the LDMOS model construction method for a multi-finger structure. Since the principle of the device in this application is similar to the LDMOS model construction method for a multi-finger structure described above, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.
[0076] Please see Figure 8 , Figure 8 This is a schematic diagram of a multi-finger LDMOS model building device provided in an embodiment of this application. Figure 8 As shown, the LDMOS modeling apparatus 200 with a multi-finger structure includes: The resistance model construction module 201 is used to construct a drift region resistance model that reflects the nonlinear effect of the number of finger units in a multi-finger structure on the drift region resistance. The electrical model building module 202 is used to build an LDMOS electrical model that reflects the characteristics of the multi-finger structure based on the drift region resistance model and intrinsic metal-oxide semiconductor. The thermal network construction module 203 is used to construct a non-distributed thermal network to simulate the self-heating effect based on thermal resistance, thermal capacity and power consumption input sources, and to perform nonlinear correction on the thermal resistance of the multi-finger LDMOS. The final model building module 204 is used to thermo-electrically couple the LDMOS electrical model with the non-distributed thermal network to obtain an LDMOS model with a multi-finger structure including a self-heating effect.
[0077] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 9 As shown, the electronic device 300 includes a processor 310, a memory 320, and a bus 330.
[0078] The memory 320 stores machine-readable instructions executable by the processor 310. When the electronic device 300 is running, the processor 310 and the memory 320 communicate via the bus 330. When the machine-readable instructions are executed by the processor 310, they can perform the operations described above. Figure 1 The steps of the LDMOS model construction method for the multi-finger structure shown in the method embodiment can be found in the method embodiment for specific implementation, and will not be repeated here.
[0079] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 The steps of the LDMOS model construction method for the multi-finger structure shown in the method embodiment can be found in the method embodiment for specific implementation, and will not be repeated here.
[0080] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0081] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.
[0082] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0083] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0084] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0085] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for constructing a multi-finger LDMOS model, characterized in that, include: A drift region resistance model is constructed to reflect the nonlinear effect of the number of finger units on the drift region resistance in a multi-finger structure. Based on the drift region resistance model and intrinsic metal-oxide semiconductor, an LDMOS electrical model reflecting the characteristics of the multi-finger structure is constructed. Based on thermal resistance, thermal capacity, and power consumption input sources, a non-distributed thermal network is constructed to simulate the self-heating effect, and the thermal resistance of the multi-finger LDMOS is nonlinearly corrected. The LDMOS electrical model is thermoelectrically coupled with the non-distributed thermal network to obtain an LDMOS model with a multi-finger structure that includes a self-heating effect.
2. The method according to claim 1, characterized in that, The step of constructing a drift region resistance model that reflects the nonlinear influence of the number of finger units in a multi-finger structure on the drift region resistance includes: Determine the first relationship between the drift region resistance and the gate-source voltage, and the second relationship between the drift region resistance and the drift region voltage drop; Based on the first relational expression and the second relational expression, a drift region resistance model including a nonlinear correction term is determined so as to reflect the nonlinear effect of the number of finger units on the drift region resistance through the nonlinear correction term.
3. The method according to claim 2, characterized in that, The first relational expression is determined in the following way: Under a fixed drain-source voltage and given different gate-source voltages, determine the characteristic curves of drain-source current as a function of gate-source voltage; The drain voltage of the intrinsic metal-oxide-semiconductor is determined based on the drain-source current and drain current formulas, and the channel resistance is determined based on the drain voltage and drain-source current of the intrinsic metal-oxide-semiconductor. The drift region resistance is determined based on the difference between the drain-source resistance and the channel region resistance. The relationship between the drift region resistance and the gate-source voltage is then fitted to obtain a first relationship expression.
4. The method according to claim 2, characterized in that, The second relational expression is determined in the following manner: The formula for the conduction current in the drift region is transformed using the formula for the surface resistivity of the drift region to obtain the formula for the current in the first drift region. By spatially integrating the differential equation of the first drift region current formula, the formula of the drift region equivalent resistance is obtained. The formula for the equivalent resistance of the drift region is converted into a function of voltage to obtain the second relational expression.
5. The method according to claim 2, characterized in that, The nonlinear correction term is determined based on the number of finger units in the multi-finger structure and the critical exponent for thermal resistance saturation.
6. The method according to claim 1, characterized in that, The step of constructing an LDMOS electrical model reflecting the multi-finger structure characteristics based on the drift region resistance model and intrinsic metal-oxide semiconductor includes: Parasitic resistance is obtained using a post-parametric simulation extraction method, and the parasitic resistance includes source metal resistance and drain metal resistance; The drift region resistance and the drain metal resistance are connected in series with the drain of the intrinsic metal oxide semiconductor as the drain of the LDMOS, and the drift region resistance model is associated with the drift region resistance. The source metal resistor is connected in series with the source of the intrinsic metal-oxide semiconductor to form the source of the LDMOS, thus generating the LDMOS electrical model.
7. The method according to claim 1, characterized in that, The step of thermoelectrically coupling the LDMOS electrical model with the non-distributed thermal network to obtain an LDMOS model with a multi-finger structure including a self-heating effect includes: The drain and source of the electrical model are connected by a current source, and the electrical power consumption in the non-distributed thermal network is converted into the thermocurrent output by the power consumption input source. The temperature change is characterized by the node voltage corresponding to the thermocurrent, and the node voltage is added to the current source to feed the temperature change back to the electrical model.
8. The method according to claim 1, characterized in that, The steps of constructing a non-distributed thermal network to simulate the self-heating effect based on thermal resistance, thermal capacity, and power consumption input sources, and performing nonlinear correction on the thermal resistance of the multi-finger LDMOS, include: By connecting the thermal resistance, the thermal capacity, and the power consumption input source in parallel, a non-distributed thermal network is constructed to simulate the self-heating effect. The thermal resistance is nonlinearly corrected using a thermal resistance model that has the same form but different parameters as the drift region resistance model.
9. A multi-finger structure LDMOS model construction device, characterized in that, include: The resistance model construction module is used to construct a drift region resistance model that reflects the nonlinear effect of the number of finger units on the drift region resistance in a multi-finger structure. The electrical model construction module is used to construct an LDMOS electrical model that reflects the characteristics of the multi-finger structure based on the drift region resistance model and the intrinsic metal-oxide semiconductor. The thermal network construction module is used to construct a non-distributed thermal network to simulate the self-heating effect based on thermal resistance, thermal capacity, and power consumption input sources, and to perform nonlinear correction on the thermal resistance of the multi-finger LDMOS. The final model building module is used to thermo-electrically couple the LDMOS electrical model with the non-distributed thermal network to obtain an LDMOS model with a multi-finger structure including a self-heating effect.
10. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the steps of the LDMOS model construction method for a multi-finger structure as described in any one of claims 1 to 8.