A high-voltage LDMOS device and its fabrication method
By introducing a dielectric layer and a metal field plate into the LDMOS device to form a MIS capacitor and optimize the electric field distribution, the problem of low breakdown voltage of existing LDMOS devices is solved, and the withstand voltage capability of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SIRIUS CORE SEMICON (CHENGDU) CO LTD
- Filing Date
- 2022-08-26
- Publication Date
- 2026-05-26
AI Technical Summary
In the blocking state, the PN junction at the drain terminal of the existing LDMOS transistor experiences a large voltage drop, which leads to excessive concentration of electric field lines at the drain terminal, resulting in a low breakdown voltage of the device.
By introducing a dielectric layer and a metal field plate into the LDMOS device, MIS capacitors are formed and the electric field distribution is optimized. The dielectric layer connects the drain electrode and the semiconductor substrate, and the metal field plate guides the electric field into the device, reducing the electric field pressure near the drain region.
The breakdown voltage of the device was improved, the electric field distribution in the drain region was optimized, and the withstand voltage capability of the device was enhanced.
Smart Images
Figure CN115332352B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and in particular relates to a high-voltage LDMOS device and its fabrication method. Background Technology
[0002] Laterally diffused metal-oxide-semiconductor field-effect transistors, commonly known as LDMOS transistors, are a type of MOSFET that primarily supports drain-to-source voltage in the lateral direction within the transistor's semiconductor material. LDMOS transistors are typically integrated with other circuit systems in integrated circuits, particularly in power supply or radio frequency applications.
[0003] However, in the blocking state, the existing LDMOS transistor will have a high voltage at its drain terminal, and the PN junction at its drain terminal will experience a large voltage drop. Because the electric field lines at the drain terminal are too concentrated, it will lead to premature breakdown and reduce the breakdown voltage of the device. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides a high-voltage LDMOS device and its fabrication method, which can solve the problem of low breakdown voltage in existing high-voltage LDMOS devices.
[0005] This application provides a high-voltage LDMOS device, the high-voltage LDMOS device comprising:
[0006] Semiconductor substrate;
[0007] A buried oxide region is disposed on the semiconductor substrate;
[0008] A P-type trap region is provided on the buried oxygen region, wherein the P-type trap region is L-shaped;
[0009] The source region is located on the horizontal portion of the P-type well region;
[0010] A P-type base region is disposed on the buried oxide region and is in contact with the P-type well region and the source region, respectively.
[0011] A drift region is provided on the buried oxygen region and in contact with the P-type trap region; wherein the drift region is L-shaped.
[0012] The drain region is located on the horizontal portion of the drift region;
[0013] A dielectric layer is disposed on the semiconductor substrate and is in contact with the buried oxide region, the drift region and the drain region, respectively;
[0014] A passivation layer is disposed on the source region and the P-type well region; wherein the passivation layer is L-shaped.
[0015] A source electrode is disposed on the P-type base region and the source region;
[0016] A gate electrode is disposed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is disposed between the gate electrode and the source electrode;
[0017] A drain electrode is disposed on the drain region and the dielectric layer;
[0018] A metal field plate is disposed on the side of the dielectric layer and is in contact with the drain electrode.
[0019] In one embodiment, the buried oxide region is a trapezoidal structure; wherein the bottom of the trapezoidal structure is in contact with the dielectric layer, and the top of the trapezoidal structure is disposed between the semiconductor substrate and the P-type well region and the P-type base region.
[0020] In one embodiment, the angle between the upper surface and the lower surface of the semiconductor substrate is an acute angle.
[0021] In one embodiment, the angle between the upper surface and the lower surface of the semiconductor substrate is 0-30°.
[0022] In one embodiment, the sum of the widths of the P-type well region and the P-type base region is less than the width of the drift region.
[0023] In one embodiment, the distance between the metal field plate and the semiconductor substrate is less than half the thickness of the buried oxide region and greater than 0.
[0024] In one embodiment, the sum of the widths of the buried oxide region and the dielectric layer is equal to the width of the semiconductor substrate.
[0025] In one embodiment, the dielectric layer is a dielectric material with a high dielectric constant.
[0026] In one embodiment, the width of the drain electrode is equal to the sum of the widths of the drain region and the dielectric layer.
[0027] A second aspect of this application provides a method for fabricating a high-voltage LDMOS device, comprising:
[0028] A buried oxide region is formed on a semiconductor substrate;
[0029] A drift region, a P-type well region, and a P-type base region are sequentially formed on the buried oxygen region; wherein, the P-type well region is located between the P-type base region and the drift region;
[0030] N-type doped ions are implanted into a portion of the drift region and the P-type well region to form a drain region on the drift region and a source region on the P-type well region; wherein the drift region is L-shaped and the P-type well region is L-shaped.
[0031] The buried oxide region is etched down to the semiconductor substrate to form a dielectric trench; wherein the dielectric trench is in contact with the drain region, the drift region and the buried oxide region;
[0032] A dielectric layer is formed by filling the deep trench with a dielectric material.
[0033] A passivation layer is formed on the source region and the P-type well region, and the passivation layer is etched to make the passivation layer "L" shaped; then the buried oxide region on the side of the dielectric layer is removed to reserve the position of the metal field plate.
[0034] A gate electrode is formed on the horizontal portion of the passivation layer, a source electrode is formed on the source region and the P-type base region, and a drain electrode is formed on the drain region.
[0035] A metal field plate is formed on the side of the dielectric layer; wherein the distance between the metal field plate and the semiconductor substrate is greater than 0.
[0036] The buried oxide region and semiconductor substrate at the bottom of the metal field plate are etched away to form the LDMOS device.
[0037] The beneficial effects of this embodiment compared to the prior art are as follows: In this embodiment, the dielectric layer is used to connect the drain electrode and the semiconductor substrate. By adding the dielectric layer, a MIS capacitor can be formed, making the electric field distribution near the drain region more uniform, thereby optimizing the electric field in the drain region, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage in existing devices. By setting a metal field plate, the breakdown voltage space of the drain region can be fully utilized, and the electric field near the drain region can be introduced into the device, reducing the electric field pressure near the drain region, improving the breakdown voltage of the device, and thus improving the breakdown voltage capability of the device. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the structure of a high-voltage LDMOS device provided in one embodiment of this application. Figure 1 ;
[0039] Figure 2 This is a schematic diagram of the structure of a high-voltage LDMOS device provided in one embodiment of this application. Figure 2 ;
[0040] Figure 3 This is a schematic diagram of the fabrication steps of a high-voltage LDMOS device according to an embodiment of this application;
[0041] Figure 4 This is a schematic diagram of the formation of the buried oxygen zone provided in one embodiment of this application;
[0042] Figure 5 This is a schematic diagram of the formation of a P-type well region, a P-type base region, and a drift region according to an embodiment of this application;
[0043] Figure 6 This is a schematic diagram of the formation of the source and drain regions provided in one embodiment of this application;
[0044] Figure 7 This is a schematic diagram of the formation of a medium trench according to an embodiment of this application;
[0045] Figure 8 This is a schematic diagram of the dielectric layer after formation according to an embodiment of this application;
[0046] Figure 9 This is a schematic diagram of the formation of a passivation layer and the reservation of the position of the metal field plate according to one embodiment of this application;
[0047] Figure 10 This is a schematic diagram of the formation of the gate electrode, drain electrode, and source electrode according to an embodiment of this application;
[0048] Figure 11 This is a schematic diagram of the metal field plate after it has been formed, according to one embodiment of this application;
[0049] Figure 12 This is a schematic diagram of the etched oxide region and semiconductor substrate at the bottom of the metal field plate according to one embodiment of this application. Detailed Implementation
[0050] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0051] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0052] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.
[0054] Laterally diffused metal-oxide-semiconductor field-effect transistors, commonly known as LDMOS transistors, are a type of MOSFET that primarily supports drain-to-source voltage in the lateral direction within the transistor's semiconductor material. LDMOS transistors are typically integrated with other circuit systems in integrated circuits, particularly in power supply or radio frequency applications.
[0055] However, in the blocking state, the existing LDMOS transistor will have a high voltage at its drain terminal, and the PN junction at its drain terminal will experience a large voltage drop. Because the electric field lines at the drain terminal are too concentrated, it will lead to premature breakdown and reduce the breakdown voltage of the device.
[0056] To address the aforementioned technical problems, this application provides a high-voltage LDMOS device, as shown in the reference. Figure 1 As shown, the high-voltage LDMOS device includes: a semiconductor substrate 10, a buried oxide region 20, a P-type well region 30, a source region 50, a P-type base region 40, a drain region 60, a drift region 70, a passivation layer 80, a dielectric layer 90, a source electrode S, a drain electrode D, a gate electrode G, and a metal field plate 100.
[0057] Specifically, the buried oxide region 20 is disposed on the semiconductor substrate 10; the P-type well region 30 is disposed on the buried oxide region 20, and the P-type well region 30 is L-shaped; the source region 50 is disposed on the horizontal portion of the P-type well region 30; the P-type base region 40 is disposed on the buried oxide region 20, and the P-type base region 40 contacts both the P-type well region 30 and the source region 50; the drift region 70 is disposed on the buried oxide region 20, and the drift region 70 contacts the P-type well region 30; the drift region 70 is L-shaped; the drain region 60 is disposed on the horizontal portion of the drift region 70; and the dielectric layer 90 is disposed on the semiconductor substrate 10. The dielectric layer 90 is in contact with the buried oxide region 20, the drift region 70, and the drain region 60, respectively; the passivation layer 80 is disposed on the source region 50 and the P-type well region 30; wherein, the passivation layer 80 is L-shaped; the source electrode S is disposed on the P-type base region 40 and the source region 50; the gate electrode G is disposed on the horizontal portion of the passivation layer 80; the vertical portion of the passivation layer 80 is disposed between the gate electrode G and the source electrode S; the drain electrode D is disposed on the drain region 60 and the dielectric layer 90; the metal field plate 100 is disposed on the side of the dielectric layer 90, and the metal field plate 100 is in contact with the drain electrode D.
[0058] In this embodiment, the P-type well region 30 is L-shaped, with a horizontal portion and a vertical portion. The source region 50 is disposed on the horizontal portion of the P-type well region 30. In a specific application embodiment, the upper surface of the source region 50 is flush with the upper surface of the vertical portion of the P-type well region 30, and the width of the source region 50 is equal to the width of the horizontal portion of the P-type well region 30. In this case, the source region 50 and the P-type well region 30 form a cuboid. The drift region 70 is L-shaped, with a horizontal portion and a vertical portion. The drain region 60 is disposed on the horizontal portion of the drift region 70. In a specific application, the upper surface of the drain region 60 is flush with the upper surface of the vertical portion of the drift region 70, and the width of the drain region 60 is equal to the width of the horizontal portion of the drift region 70. In this case, the drain region 60 and the drift region 70 form a cuboid.
[0059] In this embodiment, the thickness of the drift region 70 is the same as the thickness of the P-type well region 30. The passivation layer 80 is L-shaped, with a horizontal portion and a vertical portion. The gate electrode G is disposed on the horizontal portion of the passivation layer 80, and the gate electrode G is in contact with the vertical portion of the passivation layer 80. In a specific application embodiment, the upper surface of the gate electrode G is flush with the upper surface of the vertical portion of the passivation layer 80, and the width of the gate electrode G is equal to the width of the horizontal portion of the passivation layer 80. In this case, the gate electrode G and the passivation layer 80 together form a cuboid.
[0060] In this embodiment, the dielectric layer 90 is used to connect the drain electrode D and the semiconductor substrate 10. The dielectric layer 90 is made of a high dielectric constant material with a dielectric constant of about 50-200, such as TiO2, La2O3, etc. The drain electrode D is made of a metal material. By adding the dielectric layer 90, a MIS capacitor (metal-insulator-semiconductor) can be formed. Because the electric field strength is large and the electric field distribution is dense near the drain region 60 when the device is working, forming a MIS capacitor can make the electric field distribution near the drain region 60 more uniform, thereby optimizing the electric field of the drain region 60, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage of existing devices.
[0061] In this embodiment, the metal field plate 100 is disposed on the side of the dielectric layer 90 and is in contact with the drain electrode D. For example, the metal field plate 100 is vertically disposed, with its first end in contact with the drain electrode D, its upper surface flush with the upper surface of the drain electrode D, and its second end separated from the buried oxide region 20 by the dielectric layer 90. The second end of the metal field plate 100 passes through the midpoint of the buried oxide region 20. It can be understood that the thickness of the metal field plate 100 is greater than the sum of the thicknesses of the drain electrode D, the drift region 70, and half of the buried oxide region 20. The metal field plate 100 is made of a metallic material, such as gold, silver, copper, or aluminum. By setting the metal field plate 100, the voltage withstand space of the drain region 60 can be fully utilized, and the electric field near the drain region 60 can be introduced into the device, reducing the electric field pressure near the drain region 60, improving the breakdown voltage of the device, and thus improving the voltage withstand capability of the device.
[0062] In one embodiment, reference Figure 1 As shown, the buried oxide region 20 has a trapezoidal structure; the bottom of the trapezoidal structure is in contact with the dielectric layer 90, and the top of the trapezoidal structure is located between the semiconductor substrate 10 and the P-type well region 30 and the P-type base region 40.
[0063] In this embodiment, the buried oxygen zone 20 has a trapezoidal structure, and the bottom of the trapezoidal structure is in contact with the dielectric layer 90, that is, the lower surface of the trapezoidal structure is in contact with the dielectric layer 90. The thickness of the top of the trapezoidal structure is less than the thickness of the bottom of the trapezoidal structure. Specifically, refer to... Figure 2 As shown, the thickness H1 of the buried oxide region 20 located directly below the drain region 60 is greater than the thickness H2 of the buried oxide region 20 located directly below the source region 50. That is, H2 is the thickness of the upper surface of the buried oxide region 20. Because the electric field strength of the drain region 60 of the device is relatively large and the electric field lines are relatively densely distributed, it will cause the device to break down prematurely. By setting a thicker buried oxide region 20 directly below the drain region 60, sufficient voltage withstand space can be reserved for the drain region 60, thereby improving the voltage withstand capability of the device.
[0064] In one embodiment, the angle between the upper surface of the semiconductor substrate 10 and the lower surface of the semiconductor substrate 10 is an acute angle.
[0065] In this embodiment, reference Figure 2 As shown, the thickness of the semiconductor substrate 10 gradually decreases from the source region 50 to the drain region 60. Specifically, the thickness H2 of the semiconductor substrate 10 located directly below the source region 50 is smaller than the thickness H1 of the semiconductor substrate 10 located directly below the drain region 60. That is, the angle between the upper surface and the lower surface of the semiconductor substrate 10 is an acute angle. By providing a thinner semiconductor substrate 10 directly below the drain region 60, sufficient voltage withstand space can be reserved for the drain region 60, thereby improving the voltage withstand capability of the device.
[0066] In one embodiment, the angle between the upper surface of the semiconductor substrate 10 and the lower surface of the semiconductor substrate 10 is 0-30°.
[0067] In this embodiment, the angle between the upper surface and the lower surface of the semiconductor substrate 10 is 0-30°, and the acute angle is located directly below the drain region 60. The upper surface of the semiconductor substrate 10 is in contact with the buried oxide region 20, and the lower surface of the semiconductor substrate 10 serves as the bottom surface of the device, the ground terminal, or the low level. The semiconductor substrate 10 has a right angle and is located directly below the source region 50. By setting the angle between the upper surface and the lower surface of the semiconductor substrate 10 to 0-30°, the semiconductor substrate 10 can be thinner and the buried oxide region 20 can be thicker directly below the drain region 60. This allows sufficient voltage withstand space to be reserved for the drain region 60, thereby improving the voltage withstand capability of the device.
[0068] In one specific application, the angle between the upper surface of the semiconductor substrate 10 and the lower surface of the semiconductor substrate 10 is 20°.
[0069] In one embodiment, reference Figure 2 The sum of the widths of the P-type well region 30 and the P-type base region 40 (w1+w2) is less than the width w3 of the drift region 70.
[0070] In this embodiment, w1 is the width of the P-type base region 40, w2 refers to the maximum width of the P-type well region 30, which is the sum of the width of the horizontal portion and the width of the vertical portion of the P-type well region 30, and w3 is the width of the drift region 70. The drift region 70 is made of silicon layer material. According to the dielectric layer 90 field strength enhancement theorem (ENDIF), when the device starts working, the critical breakdown electric field of the drift region 70 will be increased. By setting the width of the drift region 70 to be greater than the sum of the widths of the P-type well region 30 and the P-type base region 40, it is helpful to improve the breakdown voltage of the LDMOS device.
[0071] In one embodiment, reference Figure 2 As shown, the distance L1 between the metal field plate 100 and the semiconductor substrate 10 is less than half the thickness H1 of the buried oxide region 20 and is greater than 0.
[0072] In this embodiment, the metal field plate 100 is in contact with the drain region 60 and the dielectric layer 90, but the metal field plate 100 is not in contact with the semiconductor substrate 10. Therefore, it is only necessary to set the distance L1 between the metal field plate 100 and the semiconductor substrate 10 to be less than half the thickness H1 of the buried oxide region 20. This can reduce costs while optimizing the electric field of the drain region 60. When the device is working, the electric field strength near its drain region 60 is relatively large and the electric field lines are relatively dense. The purpose of using the metal field plate 100 is to introduce the electric field near the drain region 60 into the device, reduce the electric field pressure near the drain region 60, improve the breakdown voltage of the device, and thus improve the withstand voltage capability of the device. Using the metal field plate 100 can help improve the surface electric field distribution and achieve vertical electric field optimization.
[0073] In one embodiment, the sum of the widths of the buried oxide region 20 and the dielectric layer 90 is equal to the width of the semiconductor substrate 10.
[0074] In this embodiment, the buried oxide region 20 and the dielectric layer 90 are both disposed on the semiconductor substrate 10, and the buried oxide region 20 and the dielectric layer 90 are disposed adjacent to each other from left to right on the semiconductor substrate 10. In this embodiment, the semiconductor substrate 10, the buried oxide region 20, the dielectric layer 90, the P-type base region 40, the P-type well region 30, the source region 50, and the drain region 60 form a cuboid. By disposing the semiconductor substrate 10 thinner below the drain region 60, sufficient voltage withstand space can be reserved in the drain region 60. By disposing the dielectric layer 90 to connect the drain electrode D and the semiconductor substrate 10, an additional MIS capacitor is formed near the drain region 60, making the electric field near the drain region 60 more uniform, thereby optimizing the electric field distribution and improving the breakdown voltage of the device.
[0075] In one embodiment, by setting the buried oxide region 20 as a trapezoidal structure, the equipotential lines in the buried oxide region 20 can be released, avoiding the formation of electric field spikes that could cause breakdown within the device. This can improve the breakdown voltage of the LDMOS device and prevent it from being broken down.
[0076] In one embodiment, the dielectric layer 90 is a high dielectric material with a dielectric constant of approximately 50-200, such as TiO2 or La2O3. By adding the dielectric layer 90, a MIS capacitor (metal-insulator-semiconductor) can be formed. Because the electric field strength and electric field distribution are relatively high near the drain region 60, forming an MIS capacitor can make the electric field distribution near the drain region 60 more uniform, thereby optimizing the electric field of the drain region 60, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage in existing devices.
[0077] In a specific application, the dielectric layer 90 is made of piezoelectric material. By using piezoelectric material in the dielectric layer 90, a MIS capacitor can be formed, thereby optimizing the electric field of the drain region 60, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage of existing devices.
[0078] In one embodiment, the thickness of the P-type base region 40 is the sum of the thicknesses of the source region 50 and the horizontal portion of the P-type well region 30.
[0079] Specifically, the thickness of the P-type base region 40 is greater than the thickness of the source region 50 because the P-type base region 40 is the voltage access point of the device. By setting the thickness of the P-type base region 40 to be the sum of the thicknesses of the source region 50 and the horizontal portion of the P-type well region 30, the voltage can be better accessed, maintaining the stability of the LDMOS device and improving the performance of the LDMOS device.
[0080] In one embodiment, the width of the drain electrode D is equal to the sum of the widths of the drain region 60 and the dielectric layer 90. Specifically, both the drain region 60 and the dielectric layer 90 are disposed on the bottom surface of the drain electrode D, and the metal field plate 100 is disposed on the side surface of the drain electrode D, and the metal field plate 100 is in contact with the dielectric layer 90. In this way, the metal field plate 100 can improve the surface electric field distribution and achieve vertical electric field optimization.
[0081] In one embodiment, the dielectric layer 90 and the metal field plate 100 are of equal length and are arranged in a stepped manner. Specifically, the dielectric layer 90 is in contact with the semiconductor substrate 10, and the metal field plate 100 is arranged in a stepped manner with the dielectric layer 90, that is, the metal field plate 100 is not in contact with the semiconductor substrate 10. In a specific application, the distance between the metal field plate 100 and the semiconductor substrate 10 is the thickness of the drain electrode D, which can reduce costs while optimizing the electric field of the drain region 60.
[0082] In one embodiment, the passivation layer 80 is made of a high-k dielectric material.
[0083] In one embodiment, the semiconductor substrate 10 may be a silicon-based substrate or a silicon carbide substrate.
[0084] In one embodiment, the buried oxide region 20 is silicon oxide.
[0085] In one embodiment, the drift region 70 is Si.
[0086] In one embodiment, the gate electrode G can be at least one of copper, gold, and silver.
[0087] In one embodiment, the drain electrode D can be at least one of copper, gold, and silver.
[0088] In one embodiment, the source electrode S can be at least one of copper, gold, and silver.
[0089] In one embodiment, the source region 50 and the drain region 60 can serve as pads for the corresponding electrodes. Specifically, the source region 50 and the drain region 60 can be made of semiconductor materials, such as gallium nitride, or they can be made of metal materials.
[0090] This application also provides a method for fabricating an LDMOS device, referencing... Figure 3 As shown, it includes steps S100 to S900.
[0091] In step S100, refer to Figure 4 As shown, a buried oxide region 20 is formed on the semiconductor substrate 10.
[0092] Specifically, the method for forming the buried oxide region 20 on the semiconductor substrate 10 is as follows: oxygen is injected into the semiconductor substrate 10 to oxidize the semiconductor substrate 10, wherein the shape of the formed buried oxide region 20 can be determined by controlling the amount of oxygen injected.
[0093] For example, in one specific application, the amount of oxygen injected into the semiconductor substrate 10 increases sequentially from left to right, so that the shape of the buried oxide region 20 formed is trapezoidal.
[0094] In step S200, refer to Figure 5 As shown, a drift region 70, a P-type trap region 30, and a P-type base region 40 are sequentially formed on the buried oxygen region 20; wherein, the P-type trap region 30 is located between the P-type base region 40 and the drift region 70.
[0095] In this embodiment, the positions of the drift region 70, the P-type well region 30 and the P-type base region 40 are etched out by etching, and corresponding metal materials are deposited on the mask to form the corresponding drift region 70, P-type well region 30 and P-type base region 40. For example, the P-type base region 40 and the P-type well region 30 are formed by depositing P-type material.
[0096] In step S300, refer to Figure 6As shown, N-type doped ions are implanted into a portion of the drift region 70 and the P-type well region 30 to form a drain region 60 on the drift region 70 and a source region 50 on the P-type well region 30; wherein the drift region 70 is L-shaped and the P-type well region 30 is L-shaped.
[0097] In a specific application, a mask is used to determine the positions of the drain region 60 and the source region 50, and metal ions are implanted on the mask to form the drain region 60 and the source region 50. The doping concentration of the drain region 60 and the source region 50 can be controlled by controlling the amount of implanted ions.
[0098] In step S400, refer to Figure 7 As shown, the buried oxide region 20 is etched down to the semiconductor substrate 10 to form a dielectric trench; wherein the dielectric trench is in contact with the drain region 60, the drift region 70 and the buried oxide region 20.
[0099] In this embodiment, selective etching is performed on the buried oxide region 20 up to the semiconductor substrate 10 to form a dielectric trench. Specifically, the area to be etched can be determined on the buried oxide region 20 using a mask, and a chemical etching solution is diffused to the surface of the buried oxide region 20 to be etched. The etching solution reacts chemically with the area to be etched, and the reaction products diffuse from the surface of the etched area into the solution and are discharged with the solution, thereby completing the etching of the buried oxide region 20 and the semiconductor substrate 10.
[0100] In step S500, refer to Figure 8 As shown, a dielectric layer 90 is formed by filling a dielectric deep trench with dielectric material.
[0101] In step S600, refer to Figure 9 As shown, a passivation layer 80 is formed on the source region 50 and the P-type well region 30, and the passivation layer 80 is etched to make the passivation layer 80 "L" shaped; then the buried oxide region 20 on the side of the dielectric layer 90 is removed to reserve the position of the metal field plate 100.
[0102] In this embodiment, a passivation layer 80 is formed on the source region 50 and the P-type well region 30, and the passivation layer 80 is selectively etched. At the same time, the buried oxide region 20 on the side of the dielectric layer 90 is selectively etched to reserve the position of the metal field plate 100.
[0103] In step S700, refer to Figure 10 As shown, a gate electrode G is formed on the horizontal portion of the passivation layer 80, a source electrode S is formed on the source region 50 and the P-type base region 40, and a drain electrode D is formed on the drain region 60.
[0104] In one embodiment, a mask is used to determine the shape of the source electrode S, the gate electrode G, and the drain electrode D, and metal is deposited on the mask to form the source electrode S, the gate electrode G, and the drain electrode D.
[0105] In this embodiment, a mask is used to define the shapes of the source electrode S, the gate electrode G, and the drain electrode D, thereby depositing metal material on the mask to form the source electrode S, the gate electrode G, and the drain electrode D, and then removing the mask.
[0106] In step S800, refer to Figure 11 As shown, a metal field plate 100 is formed on the side of the dielectric layer 90; wherein the distance between the metal field plate 100 and the semiconductor substrate 10 is greater than 0.
[0107] In this embodiment, a metal field plate 100 is formed by depositing a corresponding metal material. The material of the metal field plate 100 can be gold, silver, copper, aluminum, etc. By setting the distance between the metal field plate 100 and the semiconductor substrate 10 to be greater than 0, the voltage withstand space of the drain region 60 can be fully utilized, and the electric field near the drain region 60 can be introduced into the device, reducing the electric field pressure near the drain region 60, improving the breakdown voltage of the device, thereby improving the voltage withstand capability of the device, and reducing costs while optimizing the electric field of the drain region 60.
[0108] In step S900, refer to Figure 12 As shown, the buried oxide region 20 and the semiconductor substrate 10 at the bottom of the metal field plate 100 are etched away to form an LDMOS device.
[0109] In this embodiment, the buried oxide region 20 and the semiconductor substrate 10 at the bottom of the metal field plate 100 are removed by etching to form an LDMOS device.
[0110] This application provides a high-voltage LDMOS device and its fabrication method. The high-voltage LDMOS device includes: a semiconductor substrate 10, a buried oxide region 20, a P-type well region 30, a source region 50, a P-type base region 40, a drain region 60, a drift region 70, a passivation layer 80, a dielectric layer 90, a source electrode S, a drain electrode D, a gate electrode G, and a metal field plate 100. The dielectric layer 90 connects the drain electrode D and the semiconductor substrate 10. By adding the dielectric layer 90, a MIS capacitor can be formed, making the electric field distribution near the drain region 60 more uniform, thereby optimizing the electric field of the drain region 60, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage in existing devices. By setting the metal field plate 100, the voltage withstand space of the drain region 60 can be fully utilized, and the electric field near the drain region 60 can be introduced into the device, reducing the electric field pressure near the drain region 60, improving the breakdown voltage of the device, and thus improving the device's withstand voltage capability.
[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0112] The units described as separate components may or may not be physically separate. The components that display data may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.
[0113] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A high-voltage LDMOS device, characterized by, The high-voltage LDMOS device includes: Semiconductor substrate; A buried oxide region is disposed on the semiconductor substrate; A P-type trap region is provided on the buried oxygen region, wherein the P-type trap region is L-shaped; The source region is located on the horizontal portion of the P-type well region; A P-type base region is disposed on the buried oxide region and is in contact with the P-type well region and the source region, respectively. A drift region is provided on the buried oxygen region and in contact with the P-type trap region; wherein the drift region is L-shaped. The drain region is located on the horizontal portion of the drift region; A dielectric layer is disposed on the semiconductor substrate and is in contact with the buried oxide region, the drift region and the drain region, respectively; A passivation layer is disposed on the source region and the P-type well region; wherein the passivation layer is "L" shaped; A source electrode is disposed on the P-type base region and the source region; A gate electrode is disposed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is disposed between the gate electrode and the source electrode; A drain electrode is disposed on the drain region and the dielectric layer; A metal field plate is disposed on the side of the dielectric layer and is in contact with the drain electrode.
2. The high voltage LDMOS device of claim 1, wherein, The buried oxide region has a trapezoidal structure; wherein the bottom of the trapezoidal structure is in contact with the dielectric layer, the top of the trapezoidal structure is in contact with the semiconductor substrate, and is located below the P-type base region.
3. The high voltage LDMOS device of claim 1, wherein, The angle between the upper surface and the lower surface of the semiconductor substrate is an acute angle.
4. The high voltage LDMOS device of claim 3, wherein, The angle between the upper surface and the lower surface of the semiconductor substrate is 0-30°.
5. The high voltage LDMOS device of claim 1, wherein, The sum of the widths of the P-type well region and the P-type base region is less than the width of the drift region.
6. The high voltage LDMOS device of claim 1, wherein, The distance between the metal field plate and the semiconductor substrate is less than half the thickness of the buried oxide region and greater than 0.
7. The high voltage LDMOS device of claim 1, wherein, The sum of the widths of the buried oxide region and the dielectric layer is equal to the width of the semiconductor substrate.
8. The high voltage LDMOS device of claim 1, wherein, The dielectric layer is a dielectric material with a high dielectric constant.
9. The high-voltage LDMOS device as described in claim 1, characterized in that, The width of the drain electrode is equal to the sum of the width of the drain region and the width of the dielectric layer.
10. A method for fabricating a high-voltage LDMOS device, characterized in that, include: A buried oxide region is formed on a semiconductor substrate; A drift region, a P-type well region, and a P-type base region are sequentially formed on the buried oxygen region; wherein, the P-type well region is located between the P-type base region and the drift region; N-type dopant ions are implanted into a portion of the drift region and the P-type well region to form a drain region on the drift region and a source region on the P-type well region; wherein, after implantation of N-type dopant ions, the drift region is L-shaped and the P-type well region is L-shaped. The buried oxide region is etched down to the semiconductor substrate to form a dielectric trench; wherein the dielectric trench is in contact with the drain region, the drift region and the buried oxide region; A dielectric layer is formed by filling the deep trench with a dielectric material. A passivation layer is formed on the source region and the P-type well region, and the passivation layer is etched to make the passivation layer "L" shaped; then a portion of the buried oxide region on the side of the dielectric layer is removed to reserve the position of the metal field plate. A gate electrode is formed on the horizontal portion of the passivation layer, a source electrode is formed on the source region and the P-type base region, and a drain electrode is formed on the drain region; A metal field plate is formed on the side of the dielectric layer; wherein the distance between the metal field plate and the semiconductor substrate is greater than 0. The buried oxide region and semiconductor substrate at the bottom of the metal field plate are etched away to form the LDMOS device.