Tbc battery and method of making

Abstract

The application discloses a TBC battery and a preparation method thereof. The TBC battery comprises a substrate and a P-zone assembly arranged on the back of the substrate. The P-zone assembly comprises a first electrode, a first tunneling silicon oxide layer, a boron-doped polysilicon layer and a first passivation layer which are sequentially stacked on the back of the substrate. The first electrode penetrates through the first passivation layer and the boron-doped polysilicon layer. The P-zone assembly further comprises a tunneling silicon nitride layer arranged between the first tunneling silicon oxide layer and the boron-doped polysilicon layer. The tunneling silicon nitride layer is used to block the boron element in the boron-doped polysilicon layer from being precipitated to the first tunneling silicon oxide layer. The application inhibits the precipitation of the boron element in the boron-doped polysilicon layer through the silicon nitride layer, enhances the passivation effect, and further improves the final conversion efficiency and reliability of the battery.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to TBC cells and their preparation methods. Background Technology

[0002] With the rapid iteration of photovoltaic technology, TOPCon cells, thanks to their excellent passivation contact performance, have become the mainstream direction for current industrialization, and their mass production efficiency is gradually approaching the theoretical limit. Against this backdrop, back contact (BC) cell technology, which combines high conversion efficiency with an aesthetically pleasing appearance, has attracted widespread attention. As a platform technology, BC cells completely eliminate the obstruction of incident light by arranging the emitter, surface field, and metal electrodes in an interdigitated pattern on the back of the cell, thus theoretically achieving higher conversion efficiency and better aesthetic consistency. The TBC cell, which combines the structural advantages of BC cells with the superior passivation technology of TOPCon cells, is widely regarded by the industry as an important development trend for next-generation battery technology.

[0003] Currently, the fabrication of TBC cells commonly employs plasma-enhanced chemical vapor deposition (PECVD) technology, which sequentially grows a tunneling silicon oxide layer on a silicon substrate and then performs in-situ doping of a polycrystalline silicon layer. This process introduces a boron source during the deposition of the polycrystalline silicon layer. However, this technical approach exposes inherent material interface problems in the subsequent high-temperature annealing process.

[0004] During high-temperature annealing, boron readily undergoes abnormal diffusion, migrating to the tunneling silicon oxide layer, which has a higher diffusion coefficient. This introduces defect states into the ultrathin oxide layer, degrading its insulation properties and leading to increased leakage current or even dielectric breakdown, severely impairing passivation. Furthermore, boron loss at the interface causes depletion in the near-interface region of the polysilicon layer, generating additional parasitic capacitance. This parasitic capacitance weakens the gate's control over the device channel's electric field, thus affecting the device's drive current and final conversion efficiency. Therefore, suppressing abnormal dopant diffusion at high temperatures and ensuring the stability and electrical integrity of the tunneling silicon oxide / polysilicon interface are key challenges for improving the performance and reliability of TBC cells. Summary of the Invention

[0005] To address the defect of abnormal boron diffusion in existing technologies, this invention proposes a TBC battery and its fabrication method. By adding a silicon nitride layer between the tunneling silicon oxide layer and the boron-doped polycrystalline silicon layer, the precipitation of boron in the boron-doped polycrystalline silicon layer is suppressed, the passivation effect is enhanced, and the final conversion efficiency and reliability of the battery are improved.

[0006] The technical solution adopted in this invention is to design a TBC battery, including a substrate and a P-region component disposed on the back side of the substrate. The P-region component includes a first electrode, a first tunneling silicon oxide layer, a boron-doped polycrystalline silicon layer, and a first passivation layer sequentially stacked on the back side of the substrate. The first electrode passes through the first passivation layer and the boron-doped polycrystalline silicon layer. The P-region component also includes a tunneling silicon nitride layer, which is disposed between the first tunneling silicon oxide layer and the boron-doped polycrystalline silicon layer. The tunneling silicon nitride layer is used to prevent boron elements in the boron-doped polycrystalline silicon layer from precipitating into the first tunneling silicon oxide layer.

[0007] Furthermore, the end face of the first electrode abuts against the surface of the tunneling silicon nitride layer away from the substrate, and the tunneling silicon nitride layer isolates the first electrode from the first tunneling silicon oxide layer.

[0008] Furthermore, the end of the first electrode is embedded inside the tunneling silicon nitride layer, which isolates the first electrode from the first tunneling silicon oxide layer.

[0009] Furthermore, the first electrode penetrates the tunneling silicon nitride layer and abuts against the first tunneling silicon oxide layer.

[0010] Furthermore, the TBC cell also includes an N-region module disposed on the back side of the substrate, and a P-region module disposed at intervals with the N-region module. The N-region module includes a second electrode, a second tunneling silicon oxide layer, a phosphorus-doped polycrystalline silicon layer and a second passivation layer sequentially stacked on the back side of the substrate. The second electrode passes through the second passivation layer and the phosphorus-doped polycrystalline silicon layer and abuts against the second tunneling silicon oxide layer.

[0011] Furthermore, in the first embodiment, an intrinsic polysilicon layer is provided between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer.

[0012] Furthermore, in the second embodiment, a spacer groove is provided between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer.

[0013] The present invention also proposes a method for preparing the TBC battery in the first embodiment described above, comprising: Step A1: Deposit a tunneling silicon oxide layer on the back side of the substrate; Step A2: Deposit a tunneling silicon nitride layer on the surface of the tunneling silicon oxide layer and remove the tunneling silicon nitride layer outside the P-emitter region; Step A3: Deposit an intrinsic amorphous silicon layer on the surface of the tunneling silicon oxide layer and on the surface of the tunneling silicon nitride layer located in the P-emitter region. The intrinsic amorphous silicon layer covers the tunneling silicon oxide layer and the tunneling silicon nitride layer in the P-emitter region. Step A4: Phosphorus source and boron source are distributed at intervals on the surface of intrinsic amorphous silicon layer. The boron source (114) serves as the doping source for forming the P emitter and the phosphorus source serves as the doping source for the N emitter. Step A5: Deposit a mask layer on the surface of an intrinsic amorphous silicon layer in which phosphorus and boron sources are distributed; Step A6: Anneal the substrate of the deposited mask layer to transform the intrinsic amorphous silicon layer into an intrinsic polycrystalline silicon layer. Simultaneously, the boron element in the boron source diffuses into the intrinsic polycrystalline silicon layer of the P-emitter region to form a boron-doped polycrystalline silicon layer, which serves as the P-emitter. Simultaneously, phosphorus from the phosphorus source diffuses into the intrinsic polysilicon layer of the N-emitter region to form a phosphorus-doped polysilicon layer, which serves as the N-emitter. Step A7: Remove the mask layer from the substrate; Step A8: Prepare passivation layers on both sides of the substrate; Step A9: Prepare the first electrode and the second electrode on the back side of the substrate.

[0014] The present invention also proposes a method for preparing the TBC battery in the second embodiment described above, comprising: Step B1: Deposit a first tunneling silicon oxide layer on the back side of the substrate; Step B2: Deposit a tunneling silicon nitride layer on the surface of the tunneling silicon oxide layer and remove the tunneling silicon nitride layer outside the P-emitter region; Step B3: In-situ doping is performed on the surface of the first tunneling silicon oxide layer to obtain a boron-doped amorphous silicon layer. The boron-doped amorphous silicon layer covers the first tunneling silicon oxide layer and the tunneling silicon nitride layer. A mask layer is deposited on the surface of the boron-doped amorphous silicon layer. The substrate on which the mask layer is deposited is annealed to transform the boron-doped amorphous silicon layer into a boron-doped polycrystalline silicon layer. Step B4: Remove the mask layer of the N-emitter region, and use alkaline solution to remove the boron-doped polysilicon layer, tunneling silicon nitride layer and first tunneling silicon oxide layer of the N-emitter region. Step B5: Deposit a second tunneling silicon oxide layer on the back side of the substrate. The second tunneling silicon oxide layer covers the mask layer and the N-emitting region. Step B6: Deposit a phosphorus-doped amorphous silicon layer on the surface of the second tunneling silicon oxide layer, deposit an N-region mask layer on the surface of the phosphorus-doped amorphous silicon layer, and anneal the substrate to transform the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer. Step B7: Remove the N-region mask layer outside the N-emitter region, and then remove the phosphorus-doped polysilicon layer and the second tunneling silicon oxide layer outside the N-emitter region. Step B8: Remove the mask layer of the substrate and the N-region mask layer of the N-emitting region; Step B9: Prepare passivation layers on both sides of the substrate; Step B10: Prepare the first electrode and the second electrode on the back side of the substrate.

[0015] Furthermore, both of the above preparation methods include introducing nitrogen atoms during the deposition of the tunneling silicon oxide layer.

[0016] Compared with existing technologies, this invention adds a tunneling silicon nitride layer between the tunneling silicon oxide layer and the boron-doped polysilicon layer. Since boron diffusion in silicon nitride is much weaker than in silicon oxide, silicon nitride can suppress abnormal diffusion of boron from the boron-doped polysilicon layer into the tunneling silicon oxide layer, achieving three key technical effects: First, it significantly reduces the defect state density within the tunneling silicon oxide layer, effectively improving its insulation performance, reducing leakage current and breakdown risk, thereby enhancing interface passivation stability. Second, it avoids the formation of interface depletion regions due to boron loss, reducing parasitic capacitance effects, optimizing the gate's control over channel carriers, and improving device drive current. Third, by maintaining the electrical integrity of the polysilicon / silicon oxide interface, it ultimately achieves a synergistic improvement in the open-circuit voltage, fill factor, and conversion efficiency of the TBC cell, while ensuring the long-term reliability of the device. Attached Figure Description

[0017] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein: Figure 1 This is a schematic diagram of the TBC battery structure according to the first embodiment of the present invention; Figure 2 This is a schematic diagram of a TBC battery structure according to the second embodiment of the present invention; Figure 3 This is a schematic diagram of another TBC battery structure according to the second embodiment of the present invention; Figures 4A to 4M This is a schematic diagram of the preparation method of the first embodiment of the present invention; Figures 5A to 5T This is a schematic diagram of the preparation method according to the second embodiment of the present invention; Explanation of reference numerals in the attached figures: 100, substrate; 101, tunneling silicon oxide layer; 1011, first tunneling silicon oxide layer; 1012, second tunneling silicon oxide layer; 102a, intrinsic polycrystalline silicon layer; 102b, intrinsic amorphous silicon layer; 103a, boron-doped polycrystalline silicon layer; 103b, boron-doped amorphous silicon layer; 104a, phosphorus-doped polycrystalline silicon layer; 104b, phosphorus-doped amorphous silicon layer; 105, aluminum oxide layer; 106, silicon nitride passivation layer; 107, first electrode; 108, second electrode; 109, front aluminum oxide layer; 110, front silicon nitride passivation layer; 111, tunneling silicon nitride layer; 112, spacer trench; 113, phosphorus source; 114, boron source; 115, mask layer; 116, N-region mask layer. Detailed Implementation

[0018] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] like Figures 1 to 3 As shown, the present invention provides a TBC battery, including a substrate 100, a P-region component and an N-region component disposed on the back side of the substrate 100, wherein the P-region component and the N-region component are integrated on the back side of the substrate 100 in an interdigitated arrangement to form a back contact structure.

[0020] Specifically, the P-region component includes a first electrode 107, a first tunneling silicon oxide layer 1011, a boron-doped polysilicon layer 103a, and a first passivation layer. The first tunneling silicon oxide layer 1011, the boron-doped polysilicon layer 103a, and the first passivation layer are sequentially stacked on the back side of the substrate 100. The first electrode 107 passes through the first passivation layer and the boron-doped polysilicon layer 103a. In particular, the P-region component also includes a tunneling silicon nitride layer 111, which is disposed between the first tunneling silicon oxide layer 1011 and the boron-doped polysilicon layer 103a. The tunneling silicon nitride layer 111 is used to prevent boron from the boron-doped polysilicon layer 103a from precipitating into the first tunneling silicon oxide layer 1011.

[0021] This design effectively suppresses the abnormal diffusion of boron into the tunneling silicon oxide layer 111 during the annealing process by introducing a tunneling silicon nitride layer 111, thereby significantly improving the interface passivation quality and enhancing the gate control capability, ultimately achieving synergistic optimization of TBC cell conversion efficiency and reliability.

[0022] The thickness of the first tunneling silicon oxide layer 1011 is between 0.5 and 2.5 nm, and the thickness of the tunneling silicon nitride layer 111 is between 0.5 and 2.5 nm. Within this thickness range, both silicon oxide and silicon nitride have tunneling effects, but silicon nitride has a higher tunneling barrier and a lower carrier tunneling probability. Therefore, it is a more preferred embodiment that the first electrode 107 penetrates the tunneling silicon nitride layer 111 and the end face of the first electrode 107 directly contacts the first tunneling silicon oxide layer 1011.

[0023] Based on the above P-region component structure, the first electrode 107 has at least the following three configuration methods.

[0024] like Figure 3 As shown, the first method involves placing the end face of the first electrode 107 against the surface of the tunneling silicon nitride layer 111 facing away from the substrate. The tunneling silicon nitride layer 111 acts as a complete isolation barrier, blocking the space between the first electrode 107 and the first tunneling silicon oxide layer 1011, preventing metal atoms (such as boron atoms) from diffusing into the oxide layer, reducing the interface defect state density, and lowering leakage current. This configuration only requires the surface of the first electrode 107 to contact the tunneling silicon nitride layer 111, resulting in a relatively simple structure and high reliability. However, because the current needs to be transmitted through the tunneling silicon nitride layer 111, and the contact area between the first electrode 107 and the tunneling silicon nitride layer 111 is small, the contact resistance is the highest.

[0025] The second method involves embedding the end of the first electrode 107 inside the tunneling silicon nitride layer 111. The tunneling silicon nitride layer 111 encloses the end of the first electrode 107, isolating the first electrode 107 from the first tunneling silicon oxide layer 1011. This suppresses abnormal diffusion of boron or other dopants from the polysilicon layer to the oxide layer, protecting the integrity of the tunneling silicon oxide layer 111. This method requires embedding the end of the first electrode 107 inside the tunneling silicon nitride layer 111, making the process relatively complex. However, this method results in a larger contact area between the first electrode 107 and the tunneling silicon nitride layer 111, and the first electrode 107 is closer to the first tunneling silicon oxide layer 1011, thus leading to lower contact resistance.

[0026] like Figure 1 and Figure 2 As shown, the third method involves inserting the first electrode 107 through the tunneling silicon nitride layer 111, with the end face of the first electrode 107 directly contacting the first tunneling silicon oxide layer 1011. This method requires the first electrode 107 to penetrate the tunneling silicon nitride layer 111, making it the most technically challenging. However, because the first electrode 107 directly contacts the first tunneling silicon oxide layer 1011, the contact resistance is the lowest.

[0027] like Figures 1 to 3 As shown, in some embodiments of the present invention, the N-region component includes a second electrode 108, a second tunneling silicon oxide layer 1012, a phosphorus-doped polysilicon layer 104a, and a second passivation layer. The second tunneling silicon oxide layer 1012, the phosphorus-doped polysilicon layer 104a, and the second passivation layer are sequentially stacked on the back side of the substrate 100. The second electrode 108 passes through the second passivation layer and the phosphorus-doped polysilicon layer 104a and abuts against the second tunneling silicon oxide layer 1012.

[0028] It should be understood that the first tunneling silicon oxide layer 1011 and the second tunneling silicon oxide layer 1012 mentioned herein are only for distinguishing between P-region and N-region modules. In practical applications, the first tunneling silicon oxide layer 1011 and the second tunneling silicon oxide layer 1012 can be generated simultaneously or stepwise on the back side of the substrate 100. Similarly, the first passivation layer and the second passivation layer are also for distinguishing between P-region and N-region modules, and can also be generated simultaneously or stepwise. The passivation layer can be any passivation material known in the art suitable for crystalline silicon solar cells, such as a single silicon nitride passivation layer 106 or an aluminum oxide layer 105 plus a silicon nitride passivation layer 106. The present invention does not impose any special limitations on this.

[0029] Based on the above construction of P-area and N-area modules, TBC batteries have at least the following two structures.

[0030] like Figure 1As shown, in the first embodiment of the present invention, an intrinsic polycrystalline silicon layer 102a is provided between the boron-doped polycrystalline silicon layer 103a and the phosphorus-doped polycrystalline silicon layer 104a. This structure passivates the sidewall interface between the P-region module and the N-region module through the intrinsic polycrystalline silicon layer 102a, reduces interface recombination, which is beneficial to improving battery efficiency, and the process is relatively simple.

[0031] like Figure 2 and Figure 3 As shown, in the second embodiment of the present invention, a spacer groove 112 is provided between the boron-doped polysilicon layer 103a and the phosphorus-doped polysilicon layer 104a. This structure uses physical isolation to eliminate crosstalk between P-region and N-region components, resulting in higher reliability, but the process is complex and costly.

[0032] The present invention also proposes a method for preparing the TBC battery in the first embodiment described above, comprising: Step A1, deposit a tunneling silicon oxide layer 101 on the back side of the polished substrate 100 (see...) Figure 4A and Figure 4B The tunneling silicon oxide layer 101 here is composed of the first tunneling silicon oxide layer 1011 and the second tunneling silicon oxide layer 1012 mentioned above. That is, the first tunneling silicon oxide layer 1011 and the second tunneling silicon oxide layer 1012 are generated simultaneously. The thickness of the tunneling silicon oxide layer 101 is usually between 0.5 nm and 2.5 nm. Step A2, deposit a tunneling silicon nitride layer 111 on the surface of the tunneling silicon oxide layer 101 (see Figure 4C The region where the second end of the first electrode 107 is located is the P-emission region. The tunneling silicon nitride layer 111 outside the P-emission region is removed (see...). Figure 4D ); Step A3: An intrinsic amorphous silicon layer 102b is deposited on the surface of the tunneling silicon oxide layer 101, the intrinsic amorphous silicon layer 102b covering the tunneling silicon oxide layer 101 and the tunneling silicon nitride layer 111 (see...). Figure 4E ); Step A4: Phosphorus source 113 and boron source 114 are distributed at intervals on the surface of the intrinsic amorphous silicon layer 102b as doping sources to form P and N emitters (see...). Figure 4F After a period of time, phosphorus from phosphorus source 113 diffused into the N emission region, and boron from boron source 114 diffused into the P emission region (see...). Figure 4G ); Step A5, deposit a mask layer 115 on the surface of the intrinsic amorphous silicon layer 102b, on which phosphorus source 113 and boron source 114 are distributed (see Figure 4H ); Step A6: The substrate 100 of the deposited mask layer 115 is subjected to high-temperature annealing, and the intrinsic amorphous silicon layer 102b is transformed into an intrinsic polycrystalline silicon layer 102a (see...). Figure 4IPhosphorus diffuses into the intrinsic polycrystalline silicon layer 102a, forming a phosphorus-doped polycrystalline silicon layer 104a (see...). Figure 4I ), as the N emitter; Since boron requires higher excitation energy than phosphorus, laser scanning of the boron source region is needed for heating to assist in the excitation of boron doping, allowing boron to diffuse into the intrinsic polycrystalline silicon layer 102a to form the boron-doped polycrystalline silicon layer 103a (see...). Figure 4I As the P emitter; in particular, the tunneling silicon nitride layer 111 also plays a physical isolation and protection role for the first tunneling silicon oxide layer 1011. The use of laser scanning of the boron source region utilizes the photothermal effect failure to activate and directionally diffuse boron atoms. However, the strong photothermal effect can also affect the performance of the first tunneling silicon oxide layer 1011, such as structural damage and passivation failure. The isolation and protection role of the tunneling silicon nitride layer 111 can avoid or weaken such situations. Step A7: Acid etching is performed on the front side of the substrate 100 to coat the mask layer 115 on the front side, followed by texturing using an alkaline solution, and then the mask layer 115 of the substrate is removed (see...). Figure 4J ); Step A8: Passivation layers are prepared on both sides of the substrate 100 (see...) Figure 4K and Figure 4L ); Step A9: Form corresponding metal electrodes on the P and N emitters of the substrate 100 (see...) Figure 4M ).

[0033] For ease of understanding, a detailed description is provided using a practical application example of the present invention. The coating equipment is a tubular PECVD system, the radio frequency power supply is 40-400kHz, and the coating direction is with the substrate vertically placed at 100°. The specific steps are as follows: Step A1: The substrate 100 is an N-type silicon wafer with a resistivity of 1.0 Ω·cm. The damaged layer of the substrate 100 is removed and the substrate is cleaned and polished. A tunneling silicon oxide layer 101 and an intrinsic amorphous silicon layer 102b are deposited on the back side of the polished substrate 100. Specifically, the substrate 100 is inserted into a graphite boat and sent into a furnace tube for discharge oxidation at 420°C for 100 seconds. The nitrous oxide flow rate is 10000 sccm, the pressure is 1800 mtorr, the discharge power is 7500 W, and the pulse switching ratio is 20:1000. A 1.4 nm thick SiOx tunneling silicon oxide layer 101 is oxidized and grown on the front side of the substrate 100. Step A2: SiH4 and NH3 are introduced into the furnace tube. The tunneling silicon nitride layer 111 is deposited on the surface of the tunneling silicon oxide layer 101 by plasma ionization of SiH4 and NH3. The region where the second end of the first electrode 107 is located is the P emission region. The tunneling silicon nitride layer 111 outside the P emission region is removed. Step A3: Continue to introduce 2500 sccm of SiH4 and 5000 sccm of H2 into the furnace tube to deposit a 200 nm intrinsic amorphous silicon layer 102b. The deposition time is 2000 s, the power is 7600 W, the pulse switching ratio is 30:450, and the pressure is 2800 mtorr. The intrinsic amorphous silicon layer 102b is deposited on the surface of the tunneling silicon oxide layer 101. The intrinsic amorphous silicon layer 102b covers the tunneling silicon oxide layer 101 and the tunneling silicon nitride layer 111. Step A4: Using a dual-head printer, simultaneously print P-emitter and N-emitter on the surface of the intrinsic amorphous silicon layer 102b. The P-type dopant source is boric acid or an organoboron body, and the N-type dopant source is phosphoric acid or phosphorus oxide solution. The printhead size is 1 pL to 4 pL, the print height is 0.3 μm to 4 μm, the dopant source print thickness is 0.3 μm to 4 μm, the print interval is 20 μm to 100 μm, and the print width is 40 μm to 100 μm. Then dry at a temperature of 100°C to 200°C for 5 min to 10 min. Step A5: Deposit a mask layer 115 of 10 nm to 50 nm on the surface of the intrinsic amorphous silicon layer 102b, on which phosphorus source 113 and boron source 114 are distributed. The mask layer 115 can be SiO2. Step A6: The substrate of the deposited mask layer 115 is subjected to high-temperature annealing treatment. It is annealed at 920°C for 25 minutes, and the intrinsic amorphous silicon layer 102b is transformed into an intrinsic polycrystalline silicon layer 102a. Phosphorus diffuses into the intrinsic polycrystalline silicon layer 102a to form a phosphorus-doped polycrystalline silicon layer 104a, which serves as an N emitter. Because boron requires a higher excitation energy than phosphorus, laser scanning is performed using a green laser or a red light collector, with the laser energy controlled at 0.5 J / cm². 2 Up to 3J / cm 2 Local heating of boron source 114 is used to assist in the excitation of boron doping, allowing boron to diffuse into intrinsic polycrystalline silicon layer 102a to form boron-doped polycrystalline silicon layer 103a, which serves as a P emitter. Step A7: Acid etching is performed on the front side of the substrate 100 to coat the mask layer 115 on the front side. Then, alkaline solution is used to texturize the front side of the substrate 100. Finally, HF acid is used to remove the mask layer 115 on the back side of the substrate 100. Step A8: The substrate 100 is prepared with an aluminum oxide layer 105 on the back side and an aluminum oxide layer 109 on the front side at 280°C. Then, the silicon nitride passivation layer 110 on the front side of the substrate 100 and the silicon nitride passivation layer 106 on the back side of the substrate 100 are prepared. Step A9: screen printing and sintering to prepare the first electrode 107 and the second electrode 108.

[0034] The present invention also proposes a method for preparing the TBC battery in the second embodiment described above, comprising: Step B1, deposit a first tunneling silicon oxide layer 1011 on the back side of the polished substrate 100 (see...) Figure 5A and Figure 5B ); Step B2, deposit a tunneling silicon nitride layer 111 on the surface of the first tunneling silicon oxide layer 1011 (see...) Figure 5C The region where the second end of the first electrode 107 is located is the P-emission region. The tunneling silicon nitride layer 111 outside the P-emission region is removed (see...). Figure 5D ); Step B3: In-situ doping is performed on the surface of the first tunneling silicon oxide layer 1011 to obtain a boron-doped amorphous silicon layer 103b. The boron-doped amorphous silicon layer 103b covers the first tunneling silicon oxide layer 1011 and the tunneling silicon nitride layer 111 (see...). Figure 5E A mask layer 115 is deposited on the surface of the boron-doped amorphous silicon layer 103b (see [reference]). Figure 5F Annealing is performed on the substrate 100 of the deposited mask layer 115, transforming the boron-doped amorphous silicon layer 103b into a boron-doped polycrystalline silicon layer 103a (see...). Figure 5G ); Step B4: The region located at the second end of the second electrode 108 is the N-emission region. The mask layer 115 of the N-emission region is removed (see...). Figure 5H The boron-doped polysilicon layer 103a, the tunneling silicon nitride layer 111, and the first tunneling silicon oxide layer 1011 in the N-emitter region were removed using alkaline solution (see [link to alkaline solution]). Figure 5I ); Step B5: A second tunneling silicon oxide layer 1012 is deposited on the back side of the substrate 100. The second tunneling silicon oxide layer 1012 covers the mask layer 115 and the N-emitter region (see [link to documentation]). Figure 5J ); Step B6, deposit a phosphorus-doped amorphous silicon layer 104b on the surface of the second tunneling silicon oxide layer 1012 (see...) Figure 5K An N-region mask layer 116 is deposited on the surface of the phosphorus-doped amorphous silicon layer 104b (see [link]). Figure 5L The substrate 100 is annealed, and the phosphorus-doped amorphous silicon layer 104b is transformed into a phosphorus-doped polycrystalline silicon layer 104a (see...). Figure 5M ); Step B7, remove the N-region mask layer 116 outside the N-emission region (see...) Figure 5N Then, acid was used to remove the phosphorus-doped polysilicon layer 104a and the second tunneling silicon oxide layer 1012 outside the N-emitter region (see [link]). Figure 5O ); Step B8 involves acid etching the front side of the substrate 100 to form the mask layer 115, followed by texturing using an alkaline solution. Then, acid is used to remove the mask layer 115 and the N-region mask layer 116 of the N-emitter region from the substrate 100 (see [link to step B8]). Figure 5P ); Step B9: Passivation layers are prepared on both sides of the substrate 100 (see Figures Q to Q). Figure 5R ); Step B10: Form corresponding metal electrodes on the P and N emitters of the substrate 100 (see...) Figure 5S or Figure 5T ).

[0035] Based on the above preparation method, a preferred embodiment further includes introducing nitrogen atoms during the deposition of the tunneling silicon oxide layer 101 to counteract the mechanical stress generated after subsequent in-situ doping of polycrystalline silicon. Specifically, the introduced N2O and NH3 are ionized into plasma by radio frequency glow discharge to form a nitrogen-doped tunneling silicon oxide layer 101 on the back side of the substrate 100. This nitrogen-doped structure can effectively suppress stress accumulation in the boron-doped polycrystalline silicon layer 103a during subsequent in-situ doping and annealing of polycrystalline silicon, thereby improving passivation quality and reliability.

[0036] It should be noted that the terminology used above is for describing specific embodiments only and is not intended to limit the exemplary embodiments of the present invention. When the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. The order of execution of actions, steps, etc., in the apparatus and methods shown in the specification and drawings can be implemented in any order unless a specific order is expressly specified, and as long as the output of a previous process is not used in a subsequent process. Similar sequential terms used for ease of description do not imply that such an order must be followed.

[0037] Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0038] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A TBC battery, comprising a substrate (100) and a P-region assembly disposed on the back side of the substrate (100), the P-region assembly comprising a first electrode (107), a first tunneling silicon oxide layer (1011), a boron-doped polycrystalline silicon layer (103a) sequentially stacked on the back side of the substrate (100), and a first passivation layer, wherein the first electrode (107) passes through the first passivation layer and the boron-doped polycrystalline silicon layer (103a), characterized in that, The P-region component further includes a tunneling silicon nitride layer (111), which is disposed between the first tunneling silicon oxide layer (1011) and the boron-doped polysilicon layer (103a). The tunneling silicon nitride layer (111) is used to prevent boron from the boron-doped polysilicon layer (103a) from precipitating into the first tunneling silicon oxide layer (1011).

2. The TBC battery according to claim 1, characterized in that, The end face of the first electrode (107) abuts against the surface of the tunneling silicon nitride layer (111) away from the substrate (100), and the tunneling silicon nitride layer (111) isolates the first electrode (107) from the first tunneling silicon oxide layer (1011).

3. The TBC battery according to claim 1, characterized in that, The end of the first electrode (107) is embedded inside the tunneling silicon nitride layer (111), which isolates the first electrode (107) from the first tunneling silicon oxide layer (1011).

4. The TBC battery according to claim 1, characterized in that, The first electrode (107) penetrates the tunneling silicon nitride layer (111) and abuts against the first tunneling silicon oxide layer (1011).

5. The TBC battery according to any one of claims 1 to 4, characterized in that, The TBC battery also includes an N-region component disposed on the back side of the substrate (100), the P-region component being disposed at a distance from the N-region component, the N-region component including a second electrode (108), a second tunneling silicon oxide layer (1012), a phosphorus-doped polycrystalline silicon layer (104a) and a second passivation layer sequentially stacked on the back side of the substrate (100), the second electrode (108) passing through the second passivation layer and the phosphorus-doped polycrystalline silicon layer (104a) and abutting against the second tunneling silicon oxide layer (1012).

6. The TBC battery according to claim 5, characterized in that, An intrinsic polysilicon layer (102a) is provided between the boron-doped polysilicon layer (103a) and the phosphorus-doped polysilicon layer (104a).

7. The TBC battery according to claim 5, characterized in that, A spacer groove (112) is provided between the boron-doped polycrystalline silicon layer (103a) and the phosphorus-doped polycrystalline silicon layer (104a).

8. A preparation method, wherein the preparation method is used to prepare the TBC battery according to claim 6, characterized in that, include: Step A1: Deposit a tunneling silicon oxide layer (101) on the back side of the substrate (100). Step A2: Deposit a tunneling silicon nitride layer (111) on the surface of the tunneling silicon oxide layer (101) and remove the tunneling silicon nitride layer (111) outside the P-emitting region. Step A3, deposit an intrinsic amorphous silicon layer (102b) on the surface of the tunneling silicon oxide layer (101) and the surface of the tunneling silicon nitride layer (111) located in the P-emitter region, the intrinsic amorphous silicon layer (102b) covering the tunneling silicon oxide layer (101) and the tunneling silicon nitride layer (111) in the P-emitter region. Step A4: Phosphorus source (113) and boron source (114) are distributed at intervals on the surface of the intrinsic amorphous silicon layer (102b), wherein the boron source (114) serves as a doping source for forming the P emitter and the phosphorus source (113) serves as a doping source for the N emitter. Step A5: Deposit a mask layer (115) on the surface of an intrinsic amorphous silicon layer (102b) in which phosphorus source (113) and boron source (114) are distributed. Step A6: Anneal the substrate (100) on which the mask layer (115) is deposited, and the intrinsic amorphous silicon layer (102b) is transformed into an intrinsic polycrystalline silicon layer (102a). Simultaneously, the boron element in the boron source (114) diffuses into the intrinsic polycrystalline silicon layer (102a) of the P-emitter region to form a boron-doped polycrystalline silicon layer (103a), which serves as the P-emitter; Simultaneously, the phosphorus element in the phosphorus source (113) diffuses into the intrinsic polycrystalline silicon layer (102a) of the N-emitter region to form a phosphorus-doped polycrystalline silicon layer (104a), which serves as the N-emitter; Step A7: Remove the mask layer (115) from the substrate (100). Step A8: A passivation layer is prepared on both sides of the substrate (100); Step A9: Prepare a first electrode (107) and a second electrode (108) on the back side of the substrate (100).

9. A preparation method, wherein the preparation method is used to prepare the TBC battery according to claim 7, characterized in that, include: Step B1, deposit a first tunneling silicon oxide layer (1011) on the back side of the substrate (100). Step B2: Deposit a tunneling silicon nitride layer (111) on the surface of the first tunneling silicon oxide layer (1011) and remove the tunneling silicon nitride layer (111) outside the P emission region. Step B3: In-situ doping is performed on the surface of the first tunneling silicon oxide layer (1011) to obtain a boron-doped amorphous silicon layer (103b). The boron-doped amorphous silicon layer (103b) covers the first tunneling silicon oxide layer (1011) and the tunneling silicon nitride layer (111). A mask layer (115) is deposited on the surface of the boron-doped amorphous silicon layer (103b). The substrate (100) on which the mask layer (115) is deposited is annealed, and the boron-doped amorphous silicon layer (103b) becomes a boron-doped polycrystalline silicon layer (103a). Step B4: Remove the mask layer (115) of the N-emitter region, and use alkaline solution to remove the boron-doped polysilicon layer (103a), the tunneling silicon nitride layer (111), and the first tunneling silicon oxide layer (1011) of the N-emitter region. Step B5, depositing a second tunneling silicon oxide layer (1012) on the back side of the substrate (100), the second tunneling silicon oxide layer (1012) covering the mask layer (115) and the N emission region; Step B6: A phosphorus-doped amorphous silicon layer (104b) is deposited on the surface of the second tunneling silicon oxide layer (1012), an N-region mask layer (116) is deposited on the surface of the phosphorus-doped amorphous silicon layer (104b), and the substrate (100) is annealed to transform the phosphorus-doped amorphous silicon layer (104b) into a phosphorus-doped polycrystalline silicon layer (104a). Step B7: Remove the N-region mask layer (116) outside the N-emitting region, and then remove the phosphorus-doped polysilicon layer (104a) and the second tunneling silicon oxide layer (1012) outside the N-emitting region. Step B8: Remove the mask layer (115) of the substrate (100) and the N-region mask layer (116) of the N-emission region. Step B9: A passivation layer is prepared on both sides of the substrate (100); Step B10: Prepare a first electrode (107) and a second electrode (108) on the back side of the substrate (100).

10. The preparation method according to claim 8 or 9, characterized in that, The preparation method further includes introducing nitrogen atoms during the deposition of the tunneling silicon oxide layer (101).

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