Display chip and preparation method thereof

Abstract

The application discloses a display chip and a preparation method thereof. The display chip comprises an epitaxial layer, the epitaxial layer is formed with at least one light emitting unit, the light emitting unit comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked; a first passivation layer covers the light emitting unit; the first passivation layer has a first surface away from the epitaxial layer, the distance between the first surface and the second semiconductor layer is smaller than the distance between the first surface and the first semiconductor layer; the first surface is provided with at least one first through hole and at least one second through hole; the first through hole exposes the first semiconductor layer, and the second through hole exposes the surface of the light emitting unit away from the first semiconductor layer; a first conductive filling column is filled in the first through hole and forms an electrical connection with the first semiconductor layer; and a second conductive filling column is filled in the second through hole and forms an electrical connection with the second semiconductor layer of the light emitting unit. The application can improve the light extraction efficiency and further improve the pixel density.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display chip and its fabrication method. Background Technology

[0002] Display chips can emit light of corresponding brightness according to the received voltage signal, and have important applications in the field of display technology.

[0003] Display chips such as Micro-LED (Micro Light Emitting Diode) are attracting increasing attention due to their small size. However, Micro-LED technology suffers from low light extraction efficiency and limitations in increasing pixel density. Summary of the Invention

[0004] This invention provides a display chip and its fabrication method to improve light extraction efficiency and further increase pixel density.

[0005] According to one aspect of the present invention, a display chip is provided, the display chip comprising: An epitaxial layer having at least one light-emitting unit, the light-emitting unit comprising a stacked first semiconductor layer, a light-emitting layer, and a second semiconductor layer; A first passivation layer covers the light-emitting unit; the first passivation layer has a first surface away from the epitaxial layer, the distance between the first surface and the second semiconductor layer is less than the distance between the first surface and the second semiconductor layer; the first surface has at least one first via and at least one second via; the first via exposes the first semiconductor layer, and the second via exposes the surface of the light-emitting unit away from the first semiconductor layer; A first conductive filler pillar is filled in the first through hole and forms an electrical connection with the first semiconductor layer; The second conductive filler pillar fills the second through hole and forms an electrical connection with the second semiconductor layer of the light-emitting unit.

[0006] Optionally, the first conductive fill pillar includes a first seed layer in contact with the sidewall of the first via and the first semiconductor layer, and a first conductive layer in contact with the first seed layer; the first seed layer is in ohmic contact with the first semiconductor layer.

[0007] Optionally, the material of the first seed layer includes TiCu.

[0008] Optionally, the first surface is a flat surface, and both the first conductive filling pillar and the second conductive filling pillar are flush with the first surface.

[0009] Optionally, the display chip further includes: A second passivation layer is located between the first passivation layer and the light-emitting unit, and covers the light-emitting unit; A metal reflective layer is located between the second passivation layer and the first passivation layer; the metal reflective layer extends to the first through-hole and is isolated from the second through-hole.

[0010] Optionally, the diameter of the second through hole is larger than the diameter of the first through hole.

[0011] Optionally, the diameter of the first through hole is less than or equal to 2 micrometers.

[0012] According to another aspect of the present invention, a method for fabricating a display chip is provided, for fabricating the display chip as described above, the method comprising: An epitaxial layer is provided, wherein at least one light-emitting unit is formed on the epitaxial layer, and the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked together. A first passivation layer is formed covering the light-emitting unit, and a first conductive filler pillar and a second conductive filler pillar are formed; wherein, the first passivation layer has a first surface away from the epitaxial layer, and the distance between the first surface and the second semiconductor layer is less than the distance between the first surface and the first semiconductor layer; the first surface has at least one first via and at least one second via; the first via exposes the first semiconductor layer, and the second via exposes the surface of the light-emitting unit away from the first semiconductor layer; the first conductive filler pillar fills the first via and forms an electrical connection with the first semiconductor layer; the second conductive filler pillar fills the second via and forms an electrical connection with the second semiconductor layer away from the light-emitting unit.

[0013] Optionally, forming a first passivation layer covering the light-emitting unit, and forming a first conductive filling pillar and a second conductive filling pillar include: A first passivation thinning layer is formed covering the light-emitting unit, the thickness of the first passivation thinning layer is greater than the thickness of the first passivation layer; and the first passivation thinning layer includes a second surface away from the first semiconductor layer; At least one first through hole and at least one second through hole are formed on the second surface; A conductive filler layer is formed to fill the first through-hole; Simultaneously, the first passivation layer to be thinned and the conductive filling layer are thinned; wherein, the thinned first passivation layer is the first passivation layer, and the thinned conductive filling layer forms the first conductive filling pillar.

[0014] Optionally, the formation of the conductive filling layer filling the first via includes: Within a first preset time, the first semiconductor layer exposed by the first via is etched using halogen gas. A seed filling layer is formed on the sidewall of the first through hole and on the surface of the first semiconductor layer; A conductive layer is formed in contact with the seed filling layer.

[0015] The technical solution of this invention employs a display chip comprising: an epitaxial layer having at least one light-emitting unit formed thereon, the light-emitting unit comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked thereon; a first passivation layer covering the light-emitting unit; the first passivation layer having a first surface away from the epitaxial layer, the distance between the first surface and the second semiconductor layer being less than the distance between the first surface and the first semiconductor layer; at least one first via and at least one second via formed on the first surface; the first via exposing the first semiconductor layer, and the second via exposing the surface of the light-emitting unit away from the first semiconductor layer; a first conductive filler pillar filling the first via and forming an electrical connection with the first semiconductor layer; and a second conductive filler pillar filling the second via and forming an electrical connection with the second semiconductor layer of the light-emitting unit. Both the first and second conductive filler pillars are located on non-light-emitting surfaces, thereby enabling the display chip to have a high light extraction efficiency. Furthermore, the first and second vias are formed by etching the first passivation layer, allowing the size of the first via to be extremely small, meaning the size of the first conductive filler pillar can be extremely small, thereby reducing the spacing between the light-emitting units and increasing the pixel density.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a display chip provided in an embodiment of the present invention; Figure 2 A flowchart illustrating a method for fabricating a display chip according to an embodiment of the present invention; Figures 3-7 This is a schematic diagram of the product structure corresponding to the main process of a method for fabricating a display chip according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 9 This is a top view of a driver chip provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a schematic diagram of a display chip structure provided in an embodiment of the present invention, with reference to... Figure 1 The display chip includes: an epitaxial layer 11, on which at least one light-emitting unit PX is formed, the light-emitting unit PX including a first semiconductor layer 111, a light-emitting layer 112, and a second semiconductor layer 113 stacked together; the display chip also includes a first passivation layer 15, which covers the light-emitting unit PX; the first passivation layer 15 has a first surface 151 away from the epitaxial layer 11, the distance between the first surface 151 and the second semiconductor layer 113 is less than the distance between the first surface 151 and the first semiconductor layer 111; at least one first via G1 and at least one second via G2 are formed on the first surface 151; the first via G1 exposes the first semiconductor layer 111, and the second via G2 exposes the surface of the light-emitting unit PX away from the first semiconductor layer 111; the display chip also includes a first conductive fill pillar 16, which fills the first via G1 and forms an electrical connection with the first semiconductor layer 111; the display chip also includes a second conductive fill pillar 17, which fills the second via G2 and forms an electrical connection with the second semiconductor layer 113 of the light-emitting unit PX.

[0022] Specifically, the display chip is, for example, a Micro-LED, and more specifically, a Micro-LED with a pixel pitch of less than 10 micrometers, such as a pixel pitch of 2 micrometers, 2.5 micrometers, 3 micrometers, 5 micrometers, 7 micrometers, 8 micrometers, 10 micrometers, or any pitch between 1 micrometer and 10 micrometers. The epitaxial layer 11 is formed by an epitaxial process. In some embodiments, the display chip may also include a substrate on which the epitaxial layer 11 is formed. The light-emitting surface of the display chip is the side of the first semiconductor layer 111 away from the second semiconductor layer 113; therefore, when the display chip includes a substrate, the substrate is a transparent substrate. In some embodiments, the display chip may not include a substrate, for example, by removing the substrate.

[0023] The epitaxial layer 11 has a stacked structure, including at least a first semiconductor layer 111, a light-emitting layer 112, and a second semiconductor layer 113. The first semiconductor layer 111 and the second semiconductor layer 113 have different semiconductor types; for example, the first semiconductor layer 111 may be an N-type semiconductor layer, and the second semiconductor layer 113 may be a P-type semiconductor layer; alternatively, the first semiconductor layer 111 may be a P-type semiconductor layer, and the second semiconductor layer 113 may be an N-type semiconductor layer. In this embodiment, the first semiconductor layer 111 is an N-type semiconductor layer, and the second semiconductor layer 113 is a P-type semiconductor layer. The material of the first semiconductor layer 111 can be GaN, InGaN, AlGaN, or AlGaInP, etc., and the material of the second semiconductor layer 113 can also be GaN, InGaN, AlGaN, or AlGaInP. The light-emitting layer 112 can be a quantum well layer, for example, a stacked structure of InGaN and GaN.

[0024] When a positive voltage is applied to the first semiconductor layer 111 and the second semiconductor layer 113, electrons in the first semiconductor layer 111 diffuse toward the second semiconductor layer 113, while holes in the second semiconductor layer 113 diffuse toward the first semiconductor layer 111. Electrons and holes recombine within the light-emitting layer 112. During this process, electrons release energy, which is converted into photons, thus emitting light.

[0025] The light-emitting unit PX has a stepped structure, which includes at least a light-emitting layer 112 and a second semiconductor layer 113. That is, the light-emitting layers 113 of different light-emitting units PX are isolated, and the second semiconductor layers 113 of different light-emitting units PX are also isolated, so that the brightness of different light-emitting units PX can be independently controlled. In some embodiments, the stepped structure may also include a portion of the first semiconductor layer 111. That is, when etching to form the light-emitting unit PX, in addition to removing the second semiconductor layer 113 and the light-emitting layer 112 outside the light-emitting unit PX, a portion of the first semiconductor layer 111 is also removed. Of course, a portion of the first semiconductor layer 111 needs to be retained so that the first semiconductor layer 111 of all light-emitting units PX remains as a single unit.

[0026] Each light-emitting unit (PX) requires a corresponding electrode to provide voltage to the epitaxial layer 11. In related technologies, the electrodes corresponding to the first semiconductor layer 111 and the second semiconductor layer 113 are located on opposite sides of the light-emitting unit PX. For example, if the electrode corresponding to the first semiconductor layer 111 (hereinafter referred to as the first electrode) is located on the light-emitting surface, and the first electrode is made of metal, which has light-shielding properties, then the first electrode will block light, resulting in a low light extraction efficiency of the display chip. In other related technologies, the first electrode is formed between two adjacent light-emitting units PX using techniques such as electron beam evaporation, and is formed on a non-light-emitting surface. Although this structure can improve the light extraction efficiency, the size of the first electrode is extremely large, making it impossible to further increase the pixel density.

[0027] In this embodiment, at least one first via G1 and at least one second via G2 are formed on the first passivation layer 15, wherein each light-emitting unit PX corresponds to one second via G2. The first conductive filler pillar 16 filled in the first via G1 can be understood as the cathode of the light-emitting unit PX, and the second conductive filler pillar 17 filled in the second via G2 can be understood as the anode of the light-emitting unit PX. The first via G1 and the second via G2 are formed by etching the first passivation layer 15, which allows the size of the first via G1 to be made extremely small, that is, the size of the first conductive filler pillar 16 can be extremely small, thereby reducing the spacing between the light-emitting units PX and thus increasing the pixel density.

[0028] Furthermore, in this embodiment, the first via G1 and the second via G2 are formed on the first passivation layer 15, while the first conductive filler pillar 16 and the second conductive filler pillar 17 are formed by filling the corresponding vias. That is, in this embodiment, the first passivation layer 15 is formed first, then the first via G1 and the second via G2 are formed, and finally the first conductive filler pillar 16 and the second conductive filler pillar 17 are formed. When forming vias by etching, the position of the vias can be precisely controlled, thereby improving the yield of the display chip. Moreover, when filling the vias with conductive filler pillars, the conductive filler pillars can fully contact the inner wall of the vias, without any gaps between them, thus greatly improving the yield of the display chip. In contrast, in related technologies, the passivation layer is formed after the first electrode is formed. Besides the larger size of the first electrode, gaps are easily generated between the passivation layer and the first electrode during the passivation layer formation process, thus affecting the yield of the display chip.

[0029] The technical solution of this embodiment uses a display chip comprising: an epitaxial layer, on which at least one light-emitting unit is formed, the light-emitting unit comprising a stacked first semiconductor layer, a light-emitting layer, and a second semiconductor layer; a first passivation layer covering the light-emitting unit; the first passivation layer having a first surface away from the epitaxial layer, the distance between the first surface and the second semiconductor layer being less than the distance between the first surface and the first semiconductor layer; at least one first via and at least one second via formed on the first surface; the first via exposing the first semiconductor layer, and the second via exposing the surface of the light-emitting unit away from the first semiconductor layer; a first conductive filler pillar filling the first via and forming an electrical connection with the first semiconductor layer; and a second conductive filler pillar filling the second via and forming an electrical connection with the second semiconductor layer of the light-emitting unit. Both the first and second conductive filler pillars are located on non-light-emitting surfaces, thereby enabling the display chip to have a high light extraction efficiency. Furthermore, the first and second vias are formed by etching the first passivation layer, allowing the size of the first via to be extremely small, meaning the size of the first conductive filler pillar can be extremely small, thereby reducing the spacing between light-emitting units and increasing pixel density.

[0030] Optionally, continue to refer to Figure 1 In some embodiments, the light-emitting unit PX further includes a current spreading layer 12, which is located on the side of the second semiconductor layer 113 away from the first semiconductor layer 111. The current spreading layer 12 and the second semiconductor layer 113 are in contact, used to uniformly diffuse the current on the second conductive filling pillar 17 into the second semiconductor layer 113. Along the thickness direction of the display chip, the orthographic projection of the current spreading layer 12 on the first semiconductor layer 111 can be completely overlapped with the orthographic projection of the second semiconductor layer 113 on the first semiconductor layer 111. The material of the current spreading layer 12 can be ITO, etc.

[0031] Optionally, in some embodiments, the first conductive filler post 16 can directly contact the first semiconductor layer to form an electrical connection. When the light-emitting unit PX includes a current spreading layer 12, the second conductive filler post 17 contacts the current spreading layer 12, and the second conductive filler post 17 forms an electrical connection with the second semiconductor layer 113 through the current spreading layer 12. When the light-emitting unit PX does not include a current spreading layer 12, the second conductive filler post 17 can directly contact the second semiconductor layer 113.

[0032] Optionally, continue to refer to Figure 1 The first conductive filling pillar 16 includes a first seed layer 161 in contact with the sidewall of the first through hole G1 and the first semiconductor layer 111, and a first conductive layer 162 in contact with the first seed layer 161; the first seed layer 161 is in ohmic contact with the first semiconductor layer 111.

[0033] Specifically, the first seed layer 161 is a metal lead layer attached to the sidewall of the first via G1 and the surface of the first semiconductor layer 111. The first seed layer 161 can be tightly attached to the first via G1 and can also form an ohmic contact with the first semiconductor layer 111, thereby greatly reducing contact resistance and reducing the power consumption of the display chip. The first seed layer 161 is formed before the first conductive layer 162. After the first seed layer 161 is formed, it also forms a groove, and the groove is filled with metal material to form the first conductive layer 162. By setting the first seed layer 161, it is also easier to form the first conductive layer 162 by subsequent electroplating, that is, to form a first conductive layer 162 with better morphology and higher quality. In addition, in this embodiment, the first seed layer 161 and the first semiconductor layer 111 are made into an ohmic contact by electroplating, which can effectively solve the problem of the difficulty of photolithography, that is, to solve the problem of the small size of the first via and the insufficient photolithography space.

[0034] Optionally, in some embodiments, the material of the first seed layer 161 includes TiCu.

[0035] Specifically, TiCu can form a good ohmic contact with the first semiconductor layer 111, thereby greatly reducing the contact resistance and the power consumption of the display chip. Before forming the first seed layer 161, the first via G1 can be etched with halogen gas for a first preset time, thereby eliminating the damage of fluorine-based gas to the surface of the first semiconductor layer 111, eliminating surface energy, and enabling the first seed layer 161 to form a good ohmic contact with the first semiconductor layer 111.

[0036] Optionally, continue to refer to Figure 1The second conductive filling pillar 17 includes a second seed layer 171 that contacts the sidewall of the second through hole G2 and the second semiconductor layer 113 or the current spreading layer 12, and a second conductive layer 172 that contacts the second seed layer 171.

[0037] Specifically, the second seed layer 171 is a metal lead layer attached to the sidewall of the second via G2 and the surface of the second semiconductor layer 113 or the current spreading layer 12 of the light-emitting unit PX. The second seed layer 171 can be tightly attached to the second via G2 and can also form an ohmic contact with the second semiconductor layer 113 or the current spreading layer 12 of the light-emitting unit PX, thereby greatly reducing the contact resistance and reducing the power consumption of the display chip. The second seed layer 171 is formed before the second conductive layer 172. After the second seed layer 171 is formed, it will also form a groove, and the groove is filled with metal material to form the second conductive layer 172. By setting the second seed layer 171, it is also easier to form the second conductive layer 172 by subsequent electroplating, that is, it is possible to form a second conductive layer 172 with better morphology and higher quality.

[0038] Optionally, in some embodiments, the material of the second seed layer 171 includes TiCu.

[0039] Specifically, TiCu can form a good ohmic contact with the surface of the light-emitting unit PX away from the first semiconductor layer 111, thereby greatly reducing the contact resistance and the power consumption of the display chip. Before forming the second seed layer 171, the second via G2 can be etched with halogen gas for a first preset time, thereby eliminating the damage to the surface by the fluorine-based gas, eliminating surface energy, and enabling the second seed layer 171 to form a good ohmic contact with the second semiconductor layer 113.

[0040] Optionally, continue to refer to Figure 1 The first surface 151 is a flat surface, and the first conductive filling pillar 16 and the second conductive filling pillar 17 are both flat with the first surface 151.

[0041] Specifically, in this embodiment, since both the first conductive filler pillar 16 and the second conductive filler pillar 17 are formed by filling the vias of the first passivation layer 15, the surfaces of the first conductive filler pillar 16 and the second conductive filler pillar 17 away from the epitaxial layer 11 can be made absolutely flush, thereby greatly improving the yield of electrical connections between the conductive filler pillars and subsequent corresponding components such as driver chips. In detail, after the first passivation layer 15 is fabricated, it can be subjected to CMP (Chemical Mechanical Polishing) or similar methods to form a flush surface. Then, vias are opened in the first passivation layer 15, and corresponding conductive filler pillars are formed within the vias. Subsequently, the first passivation layer 15 is subjected to CMP or similar methods again to form a flush first surface 151. Furthermore, since the conductive filler pillars are protected by the first passivation layer 15 during the CMP process, they can be made absolutely flush without damaging the conductive filler pillars. In contrast, in related technologies, electrode blocks are formed first, followed by a passivation layer. It is difficult to make the two electrode blocks perfectly flush, which affects the yield when connecting them to driver chips and other components.

[0042] Optionally, continue to refer to Figure 1 The display chip also includes a second passivation layer 13 and a metal reflective layer 14; the second passivation layer 13 is located between the first passivation layer 15 and the light-emitting unit PX, and covers the light-emitting unit PX. The metal reflective layer 14 is located between the second passivation layer 13 and the first passivation layer 15, and the metal reflective layer 14 extends to the first through hole G1 and is isolated from the second through hole G2.

[0043] Specifically, the second passivation layer 13 isolates the metal reflective layer 14 from the light-emitting unit PX, preventing the metal reflective layer 14 from short-circuiting different light-emitting units PX, and from short-circuiting different layers within the light-emitting unit PX. The metal reflective layer 14 has a reflective function and also prevents optical crosstalk between different light-emitting units PX. The material of the metal reflective layer 14 is not limited. In this embodiment, the metal reflective layer 14 extends to the first via G1 and is electrically connected to the first conductive filler post 16, allowing the metal reflective layer 14 to serve as part of the cathode electrode of the light-emitting unit PX. As mentioned earlier, the first conductive filler post 16 in this embodiment is relatively small, and its resistance is correspondingly larger. By electrically connecting the metal reflective layer 14 and the first conductive filler post 16, the resistance of the first conductive filler post 16 can be effectively reduced, thereby greatly reducing the power consumption of the display chip. Furthermore, the metal reflective layer 14 is isolated from the second conductive filler post 17 by the first passivation layer 15, preventing short-circuiting of the first conductive filler post 16 and the second conductive filler post 17.

[0044] Optionally, the diameter of the second through hole G2 is larger than the diameter of the first through hole G1.

[0045] Specifically, the diameter of the first via G1 can be less than or equal to 2 micrometers. For example, the diameter of the first via G1 can be any size between 0.1 micrometers, 0.2 micrometers, 0.5 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, or 0.1 micrometers to 2 micrometers. The diameter of the second via G2 is larger, which can greatly reduce the resistance of the second conductive filling pillar 17, that is, reduce the resistance of the anode electrode of the light-emitting unit PX, thereby reducing the power consumption of the display chip.

[0046] Optionally, in some embodiments, the first passivation layer 15 and the second passivation layer 13 can be made of the same material, such as silicon oxide. Of course, in other embodiments, the first passivation layer 15 and the second passivation layer 13 can be made of different materials.

[0047] Based on the same inventive concept, this invention also provides a method for fabricating a display chip, used to fabricate the display chip provided in any embodiment of this invention. For example... Figure 2 As shown, Figure 2 This is a flowchart illustrating a method for fabricating a display chip according to an embodiment of the present invention. The method for fabricating a display chip includes: Step S110: Provide an epitaxial layer, the epitaxial layer having at least one light-emitting unit, the light-emitting unit including a stacked first semiconductor layer, a light-emitting layer and a second semiconductor layer; Specifically, Figures 3-7 This is a schematic diagram of the product structure corresponding to the main process of a display chip fabrication method provided in an embodiment of the present invention, with reference to... Figure 3 After the epitaxial layer is formed, it can be etched to form multiple stepped structures. Alternatively, after forming the epitaxial layer, a current spreading layer can be formed on the second semiconductor layer first, and then both the current spreading layer and the epitaxial layer can be etched simultaneously to form multiple light-emitting units.

[0048] Step S120: A first passivation layer covering the light-emitting unit is formed, and a first conductive filling pillar and a second conductive filling pillar are formed; wherein, the first passivation layer has a first surface away from the epitaxial layer, and the distance between the first surface and the second semiconductor layer is less than the distance between the first surface and the first semiconductor layer; at least one first through-hole and at least one second through-hole are formed on the first surface; the first through-hole exposes the first semiconductor layer, and the second through-hole exposes the surface of the light-emitting unit away from the first semiconductor layer; the first conductive filling pillar fills the first through-hole and forms an electrical connection with the first semiconductor layer; the second conductive filling pillar fills the second through-hole and forms an electrical connection with the second semiconductor layer of the light-emitting unit.

[0049] Specifically, the detailed working principle of the display chip can be found in the description of the display chip structure section of this invention, and will not be repeated here. In the display chip, both the first conductive filling pillar and the second conductive filling pillar are located on the non-light-emitting surface, thereby giving the display chip a high light extraction efficiency. Furthermore, the first and second vias are formed by etching the first passivation layer, which allows the size of the first via to be made extremely small, meaning the size of the first conductive filling pillar can be extremely small. This reduces the spacing between the light-emitting units, thereby increasing the pixel density.

[0050] Optionally, such as Figure 3 As shown, before forming the first passivation layer covering the light-emitting unit, and before forming the first conductive filling pillar and the second conductive filling pillar, the following is also included: A second passivation layer 13 is formed to cover the entire surface of the light-emitting unit. Then, a metal reflective layer 14 is formed covering the second passivation layer 13. Next, an opening is formed on the metal reflective layer 14, the position of which corresponds to the position of the subsequently formed second via, and the size of the opening is larger than the size of the second via, so that the first passivation layer can isolate the second conductive filling pillar from the metal reflective layer 14. In this embodiment, "corresponding" means that, along the thickness direction of the display chip, the orthographic projection of the second via on the epitaxial layer lies within the orthographic projection of the opening on the epitaxial layer.

[0051] Optionally, forming a first passivation layer covering the light-emitting unit, and forming a first conductive filling pillar and a second conductive filling pillar include: A first passivation thinning layer is formed to cover the light-emitting unit. The thickness of the first passivation thinning layer is greater than the thickness of the first passivation layer, and the first passivation thinning layer includes a second surface that is away from the first semiconductor layer. Specifically, a relatively thick first passivation layer is first applied to the entire surface, for example, defined as the second passivation thinning layer. Because the surface of the epitaxial layer is uneven, i.e., has a stepped structure, the surface of the second passivation thinning layer is not flat. A first CMP process is then used to thin the second passivation thinning layer to the thickness of the first passivation thinning layer 152, thus forming... Figure 4 The structure is shown. The thickness of the first passivation layer 152 is still relatively thick compared to the first passivation layer, and it can become the first passivation layer after being thinned. The first passivation layer 152 has a flush second surface 152, which facilitates the subsequent opening of the first through hole and the second through hole.

[0052] Then, as Figure 5 As shown, at least one first through hole and at least one second through hole are formed on the second surface.

[0053] Specifically, the first through hole G1 and the second through hole G2 can be formed by etching or other methods.

[0054] Then, a conductive filler layer is formed to fill the first through-hole G1. In some embodiments, the first conductive filler pillar and the second conductive filler pillar are fabricated simultaneously, in which case the conductive filler layer fills not only the first through-hole G1 but also the second through-hole G2. The conductive filler layer is used for the subsequent formation of the first and second conductive filler pillars.

[0055] Optionally, forming a conductive filling layer to fill the first via G1 includes: etching the first semiconductor layer 111 exposed by the first via G1 using a halogen gas within a first preset time.

[0056] Specifically, after the first via G1 is etched, a halogen gas such as chlorine can be used to perform a short etching on the surface of the first via G1, i.e., the first preset time can be 15 seconds. Etching the first via G1 with halogen gas within the first preset time eliminates the damage to the surface of the first semiconductor layer 111 caused by the fluorine-based gas, eliminates surface energy, and allows the first seed layer 161 to form a good ohmic contact with the first semiconductor layer 111. Then, as... Figure 6 As shown, a seed filling layer 163 is formed on the sidewall of the first via G1 and on the surface of the first semiconductor layer 111. The seed filling layer 163 can be TiCu or any other structure that can form an ohmic contact with the first semiconductor layer 111. Simultaneously, the seed filling layer 163 can also cover the inner wall of the second via G2 and the surface of the light-emitting unit away from the first semiconductor layer 111. Then, as... Figure 7 As shown, a conductive layer 164 is formed in contact with the seed filling layer 163. The conductive layer 164 and the seed filling layer 163 together constitute a conductive filling layer, which, in addition to filling the through-hole, also covers the second surface.

[0057] Then, the first passivation layer to be thinned and the conductive filler layer are simultaneously thinned; wherein, the thinned first passivation layer is the first passivation layer, the portion of the thinned conductive filler layer located within the first via forms a first conductive filler pillar, and the portion of the thinned conductive filler layer located within the second via forms a second conductive filler pillar. The thinning method can be, for example, CMP, or other methods. This step forms... Figure 1 The structure shown.

[0058] Based on the same inventive concept, the present invention also provides a display panel. Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 8 The display panel includes the display chip provided in any embodiment of the present invention.

[0059] The display panel also includes a driver chip 4. One side of the driver chip 4 has a bonding layer 21 with corresponding through-holes for mounting electrode posts 22. The driver chip 4 also has a first connection contact 33 for connecting to a first conductive filler post and a second connection contact 31 for connecting to a second conductive filler post. The connection contacts are connected to the conductive filler posts via corresponding electrode posts 22. The size of the electrode post 22 can be larger than the size of the corresponding conductive filler post.

[0060] The driver chip 4 can be a Thin Film Transistor (TFT) board or an Integrated Circuit (IC) board.

[0061] Since the display panel provided in the embodiments of the present invention includes the display chip provided in any embodiment of the present invention, it also has the same beneficial effects, which will not be described again here.

[0062] Based on the same inventive concept, the present invention also provides a driver chip. Figure 9 This is a top view of a driver chip provided in an embodiment of the present invention, with reference to... Figure 9 The driver chip is used to drive the display panel provided in any embodiment of the present invention. The driver chip includes a first contact point 33 connected to a first conductive filler post and a second contact point 31 connected to a second conductive filler post.

[0063] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0064] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display chip, characterized in that, The display chip includes: An epitaxial layer having at least one light-emitting unit, the light-emitting unit comprising a stacked first semiconductor layer, a light-emitting layer, and a second semiconductor layer; A first passivation layer covers the light-emitting unit; the first passivation layer has a first surface away from the epitaxial layer, the distance between the first surface and the second semiconductor layer is less than the distance between the first surface and the second semiconductor layer; the first surface has at least one first via and at least one second via; the first via exposes the first semiconductor layer, and the second via exposes the surface of the light-emitting unit away from the first semiconductor layer; A first conductive filler pillar is filled in the first through hole and forms an electrical connection with the first semiconductor layer; The second conductive filler pillar fills the second through hole and forms an electrical connection with the second semiconductor layer of the light-emitting unit.

2. The display chip according to claim 1, characterized in that, The first conductive fill pillar includes a first seed layer in contact with the sidewall of the first via and the first semiconductor layer, and a first conductive layer in contact with the first seed layer; the first seed layer is in ohmic contact with the first semiconductor layer.

3. The display chip according to claim 2, characterized in that, The material of the first seed layer includes TiCu.

4. The display chip according to claim 1, characterized in that, The first surface is a flat surface, and both the first conductive filling pillar and the second conductive filling pillar are flush with the first surface.

5. The display chip according to claim 1, characterized in that, The display chip also includes: A second passivation layer is located between the first passivation layer and the light-emitting unit, and covers the light-emitting unit; A metal reflective layer is located between the second passivation layer and the first passivation layer; the metal reflective layer extends to the first through-hole and is isolated from the second through-hole.

6. The display chip according to claim 1, characterized in that, The diameter of the second through hole is larger than the diameter of the first through hole.

7. The display chip according to claim 1 or 6, characterized in that, The diameter of the first through hole is less than or equal to 2 micrometers.

8. A method for fabricating a display chip, used to fabricate the display chip according to any one of claims 1-7, characterized in that, The method for manufacturing the display chip includes: An epitaxial layer is provided, wherein at least one light-emitting unit is formed on the epitaxial layer, and the light-emitting unit includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked together. A first passivation layer is formed covering the light-emitting unit, and a first conductive filler pillar and a second conductive filler pillar are formed; wherein, the first passivation layer has a first surface away from the epitaxial layer, and the distance between the first surface and the second semiconductor layer is less than the distance between the first surface and the first semiconductor layer; the first surface has at least one first via and at least one second via; the first via exposes the first semiconductor layer, and the second via exposes the surface of the light-emitting unit away from the first semiconductor layer; the first conductive filler pillar fills the first via and forms an electrical connection with the first semiconductor layer; the second conductive filler pillar fills the second via and forms an electrical connection with the second semiconductor layer of the light-emitting unit.

9. The method for fabricating a display chip according to claim 8, characterized in that, The formation of the first passivation layer covering the light-emitting unit, and the formation of the first conductive filling pillar and the second conductive filling pillar include: A first passivation thinning layer is formed covering the light-emitting unit, the thickness of the first passivation thinning layer is greater than the thickness of the first passivation layer; and the first passivation thinning layer includes a second surface away from the first semiconductor layer; At least one first through hole and at least one second through hole are formed on the second surface; A conductive filler layer is formed to fill the first through-hole; Simultaneously, the first passivation layer to be thinned and the conductive filling layer are thinned; wherein, the thinned first passivation layer is the first passivation layer, and the thinned conductive filling layer forms the first conductive filling pillar.

10. The method for fabricating a display chip according to claim 9, characterized in that, The conductive filling layer forming the first through-hole includes: Within a first preset time, the first semiconductor layer exposed by the first via is etched using halogen gas. A seed filling layer is formed on the sidewall of the first through hole and on the surface of the first semiconductor layer; A conductive layer is formed in contact with the seed filling layer.

Images