A specific preparation process, film layer structure and application of a lead zirconate titanate (PZT) film layer

Abstract

The application discloses a preparation process of a lead zirconate titanate (PZT) film layer, a film layer structure and application thereof, and relates to the technical field of piezoelectric material film layer preparation. The preparation process comprises the following steps: S1, forming a low tensile stress silicon nitride layer on the surface of a substrate, which is used for homogenizing the in-plane stress gradient of a wafer; and S2, forming a piezoelectric functional layer on the surface of the silicon nitride layer in a sputtering mode, wherein the piezoelectric thin film material of the piezoelectric functional layer is lead zirconate titanate (PZT). The film layer structure and the preparation process thereof adopt the silicon nitride layer to relieve the thermal mismatch stress of the piezoelectric functional layer system, can improve the piezoelectric constant e31 of the central region of the wafer, and improve the uniformity of the whole wafer.

Description

Technical Field

[0001] This invention relates to the field of piezoelectric material film preparation technology, and in particular to a preparation process, film structure and application of lead zirconate titanate (PZT) thin film. Background Technology

[0002] Lead zirconate titanate (PZT) films, as typical piezoelectric materials, are widely used in the manufacture of sensors, actuators, and other devices in piezoelectric micromechanical systems (MEMS) due to their excellent piezoelectric properties and electromechanical coupling efficiency. 8-inch silicon substrate-based PZT films have become one of the core substrates for the mass production of microelectronic devices. Currently, the mainstream process for fabricating PZT films on 8-inch silicon substrates involves first growing a silicon oxide layer on the surface of a silicon wafer, and then directly depositing a Pt bottom electrode, a buffer layer, a PZT piezoelectric layer, and a top electrode sequentially using magnetron sputtering. However, this traditional fabrication method has many technical defects, resulting in poor wafer-level performance of the PZT film, making it difficult to meet the application requirements of high-precision devices.

[0003] 1. Uneven nucleation and grain growth: The silicon oxide layer has low surface energy and is prone to containing hydroxyl groups and absorbing water, which makes the nucleation density in the central region of the wafer significantly lower during Pt electrode sputtering. The grains grow coarsely and the crystal orientation is chaotic, directly causing uneven distribution of crystal nuclei on the wafer surface.

[0004] 2. Interfacial diffusion forms a low-performance transition layer: During high-temperature preparation and subsequent processes, Si and O atoms in the silicon oxide layer tend to diffuse to the Pt / PZT interface, forming an amorphous or low-resistivity transition layer, which further exacerbates the non-uniformity of crystal nucleus growth and reduces the electromechanical coupling efficiency of the interface.

[0005] 3. In-plane stress gradient imbalance: The thermal expansion coefficients of silicon oxide, PZT, and silicon substrate are significantly different, resulting in a significant thermal mismatch effect. This leads to a clear in-plane stress gradient in the wafer, and the central region is prone to high compressive stress, which causes the piezoelectric constant e31 in the central region of the wafer to decrease significantly.

[0006] 4. High surface roughness and poor wafer uniformity: The superposition of the above-mentioned nucleation, interface diffusion and stress imbalance problems results in high surface roughness of PZT film, and significant differences in piezoelectric properties between the center and edge regions of the wafer. The uniformity of the entire wafer is poor, and it is difficult to guarantee device yield and performance consistency.

[0007] For example, invention application No. 202411626595.1 discloses a piezoelectric thin film based on a MEMS electric field sensor and its fabrication method. The piezoelectric thin film includes a substrate layer, an electrode layer, and a PZT layer. The fabrication method includes preparing a PZT sol and forming an amorphous recrystallized PZT piezoelectric thin film. This application uses a sol-gel method to prepare the PZT piezoelectric thin film, which helps to form a crystalline PZT piezoelectric thin film, thereby significantly improving the piezoelectric performance and stability of the piezoelectric thin film. However, this method also has problems: the PZT thin film still faces issues during fabrication such as uneven nucleation and grain growth, low-performance transition layers formed by interfacial diffusion, unbalanced in-plane stress gradients, high surface roughness, and poor wafer uniformity. These problems directly affect the piezoelectric performance, stability, and device yield of the PZT thin film.

[0008] Therefore, the traditional PZT thin film preparation process has caused a series of chain problems such as nucleation, interface, stress and uniformity due to the inherent defects of the silicon oxide layer. This limits the large-scale and high-performance application of PZT thin films in high-precision piezoelectric micromechanical systems. There is an urgent need to develop a PZT thin film preparation process and film structure that can effectively homogenize the stress gradient in the wafer surface, improve the uniformity of nucleation and crystallization, and enhance the piezoelectric performance of the whole wafer. Summary of the Invention

[0009] The present invention aims to solve the problems mentioned in the background art. The purpose of one or more embodiments of this specification is to provide a preparation process, film structure and application based on lead zirconate titanate (PZT) thin film. Before depositing the piezoelectric functional layer, a low tensile stress silicon nitride layer is deposited first to homogenize the in-plane stress gradient of the wafer, which is beneficial to the growth of crystal nuclei of the piezoelectric functional layer, resulting in uniform crystal nuclei density, reducing the surface roughness of the wafer, improving the piezoelectric constant e31 in the central region of the wafer, and improving the uniformity of the entire wafer.

[0010] To achieve the above objectives, one or more embodiments of this specification provide a process for preparing a lead zirconate titanate (PZT) thin film, the process comprising the following steps:

[0011] S1 forms a low-tensile-stress silicon nitride layer on the substrate surface to homogenize the in-plane stress gradient of the wafer; and

[0012] S2 forms a piezoelectric functional layer on the surface of the silicon nitride layer by sputtering, wherein the piezoelectric thin film material of the piezoelectric functional layer is lead zirconate titanate (PZT).

[0013] In one embodiment of the present invention, the process for forming the piezoelectric functional layer in S2 includes the following step S21:

[0014] S21 forms a lower electrode layer, a piezoelectric thin film layer, and an upper electrode layer sequentially on the surface of a silicon nitride layer by sputtering.

[0015] In one embodiment of the present invention, the materials of the lower electrode layer and the upper electrode layer are Pt / Ti system materials.

[0016] In one embodiment of the present invention, the preparation process includes the following steps:

[0017] S0 forms a silicon oxide layer on the substrate through a thermal oxidation process. The silicon oxide layer is located between the substrate and the silicon nitride layer to achieve adhesion between the substrate and the silicon nitride layer.

[0018] The present invention also provides a film structure based on lead zirconate titanate (PZT) thin film, which is processed by the above-described preparation process.

[0019] In one embodiment of the present invention, the film structure includes:

[0020] Base;

[0021] A low-tensile-stress silicon nitride layer formed on the substrate is used to homogenize the in-plane stress gradient of the wafer; and

[0022] A piezoelectric functional layer is formed on the silicon nitride layer, and the piezoelectric thin film material of the piezoelectric functional layer is lead zirconate titanate (PZT).

[0023] In one embodiment of the present invention, the piezoelectric functional layer is c-axis oriented and the lattice orientation is (001) crystal plane preferred orientation.

[0024] In one embodiment of the present invention, the film structure further includes a silicon oxide layer formed on the substrate, the silicon oxide layer being located between the substrate and the silicon nitride layer, for achieving adhesion between the substrate and the silicon nitride layer.

[0025] The present invention also provides an application of the above-mentioned film structure, which is used in the manufacture of sensors and actuators for piezoelectric micromechanical systems after being patterned.

[0026] The beneficial effects of this invention are:

[0027] 1. The silicon nitride layer used in this invention has a high Young's modulus and a thermal expansion coefficient between Si and PZT, which effectively alleviates the thermal mismatch stress of the silicon oxide / piezoelectric functional layer system, especially reducing the in-plane compressive stress in the wafer center region, thereby increasing the piezoelectric constant e31 in the wafer center region.

[0028] 2. The silicon nitride layer used in this invention has a higher surface energy than silicon oxide, which results in a higher nucleation density and more uniform grains in the lower electrode layer, reduces the roughness of the wafer surface, thereby improving the uniformity of PZT crystallization, reducing the center-edge performance difference of the whole wafer, and improving the uniformity of the whole wafer.

[0029] 3. This invention employs a dense silicon nitride layer to block the diffusion of Si and O to the piezoelectric functional layer interface, avoiding the formation of a low-performance interface layer and improving electromechanical coupling efficiency. At the same time, the silicon nitride layer has a high Young's modulus and low stress, making it suitable as a vibration structure layer. This not only ensures the stability and mechanical reliability of the device structure but also synergistically improves the electrical performance, high temperature resistance, and process compatibility of the device, providing important support for achieving high performance, long life, and high cost-effectiveness of the device.

[0030] 4. The film structure of this invention utilizes low-tensile-stress silicon nitride for stress regulation, which can effectively achieve stress matching with the structure of various devices in the piezoelectric microelectromechanical system. This significantly reduces the stress accumulation of the film itself, avoids defects such as warping and cracking during patterning and subsequent use, improves the structural stability and mechanical reliability of the film, optimizes the piezoelectric response performance, vibration characteristics, and signal transmission efficiency of the device, reduces device performance degradation caused by stress mismatch, extends device lifespan, and further enhances the adaptability and practicality of this film structure in various application scenarios of piezoelectric microelectromechanical systems. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the overall structure of the membrane layer in Embodiment 2 of the present invention;

[0033] Figure 2 This is a schematic diagram of the overall structure of the membrane layer in Embodiment 4 of the present invention;

[0034] Figures 3 to 4 This is a process flow diagram of the membrane structure in Embodiment 2 of the present invention;

[0035] Figures 5 to 7 This is a process flow diagram of the membrane structure in Embodiment 4 of the present invention;

[0036] Figure 8 This is a diagram of the film structure of Comparative Example 1 of the present invention;

[0037] Figure 9 This is a test point diagram of the whole wafer piezoelectric constant e31 of the present invention;

[0038] Figure 10 This is a normalized curve of the 9-point piezoelectric constant e31 value of Embodiment 4 and Comparative Example 1 of the present invention;

[0039] Figure 11 This is an image showing the atomic force microscopy (AFM) test results of the silicon nitride layer + piezoelectric functional layer of this invention.

[0040] Figure 12 This is an image showing the atomic force microscopy (AFM) test results of the silicon oxide layer + piezoelectric functional layer of this invention.

[0041] Figure 13 This is an XRD test result diagram of the silicon nitride layer + piezoelectric functional layer of the present invention;

[0042] Figure 14 This is an XRD test result diagram of the silicon oxide layer + piezoelectric functional layer of the present invention;

[0043] Figure 15 This is a process flow diagram of S3 in Embodiment 5 of the present invention;

[0044] Figure 16 This is a process flow diagram of S4 in Embodiment 5 of the present invention;

[0045] Figure 17 This is a schematic diagram of the structure of the present invention applied to a cantilever beam;

[0046] Figure 18 For the present invention Figure 17 Exploded view;

[0047] Figure 19 This is a schematic diagram of the structure of the present invention applied to PMUT;

[0048] Figure 20 For the present invention Figure 19 Exploded view;

[0049] Figure 21 This is a schematic diagram of the structure of the present invention applied to a microphone;

[0050] Figure 22 For the present invention Figure 21 Exploded view.

[0051] In the attached diagram:

[0052] 10. Base; 101. Dorsal cavity;

[0053] 20. Silicon oxide layer;

[0054] 30. Silicon nitride layer;

[0055] 40. Piezoelectric functional layer;

[0056] 401. Lower electrode layer; 402. Piezoelectric thin film layer; 403. Upper electrode layer. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments. Figures 1-22 This is used to intuitively describe the specific preparation process, film structure, and application of a lead zirconate titanate (PZT) thin film layer in an embodiment of the present invention.

[0058] Example 1:

[0059] This invention proposes a process for preparing a lead zirconate titanate (PZT) thin film, such as... Figures 3 to 4 As shown, the preparation process includes the following steps S1~S2:

[0060] S1 forms a low-tensile-stress silicon nitride layer 30 on the surface of the substrate 10 to homogenize the in-plane stress gradient of the wafer.

[0061] Specifically, this embodiment does not limit the formation process of the silicon nitride layer 30. It can be deposited using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or vapor deposition. The substrate 10 can be a silicon substrate or an SOI substrate, but is not limited to these.

[0062] Preferably, the stress of the silicon nitride layer 30 is a tensile stress of 0-50 MPa, for example, a tensile stress of 10 MPa. Moderate tensile stress can induce PZT to form domain structures that are more conducive to piezoelectric response (such as 90° domains that are easier to flip), thereby improving the average value of the overall piezoelectric constant e31.

[0063] S2 forms a piezoelectric functional layer 40 on the surface of silicon nitride layer 30 by sputtering. The piezoelectric thin film material of piezoelectric functional layer 40 is lead zirconate titanate (PZT).

[0064] Specifically, the process for forming the piezoelectric functional layer 40 includes the following step S21:

[0065] S21 forms a lower electrode layer 401, a piezoelectric thin film layer 402, and an upper electrode layer 403 sequentially on the surface of the silicon nitride layer 30 by sputtering.

[0066] Preferably, the materials of the lower electrode layer 401 and the upper electrode layer 403 are Pt / Ti system materials.

[0067] The lower electrode layer 401 is made of a metallic material with good conductivity and adhesion, such as a platinum (Pt) system material, a titanium (Ti) system material, or a composite layer of titanium (Ti) and platinum (Pt). Titanium (Ti) can enhance the bonding force between platinum (Pt) and silicon nitride layer 30. The piezoelectric thin film layer 402 is made of lead zirconate titanate (PZT) material, and its composition can be adjusted according to the required piezoelectric properties. The upper electrode layer 403 can also be made of a Pt / Ti system material to ensure good conductive contact and structural stability.

[0068] During the sputtering process, process parameters such as sputtering power, working gas pressure, target-substrate spacing, and deposition temperature are precisely controlled to ensure that the thickness uniformity, crystal quality, and electrical properties of each film layer meet the design requirements.

[0069] The interface bonding between the silicon nitride layer 30 and Pt / Ti can reduce interface defects and stress concentration, and lower the performance degradation starting point in the central region. At the same time, the silicon nitride layer 30 can provide more uniform nucleation sites, suppress abnormal grain growth in the central region, and promote the preferential orientation growth of the piezoelectric functional layer 40 toward the (001) crystal plane, making the wafer grain size, grain boundary density, and domain size more uniform, and directly reducing the piezoelectric constant e31 difference between the center and the edge.

[0070] The effect of lead zirconate titanate (PZT) on the thermal expansion difference of the underlying layer during cooling is shown in the table below:

[0071]

[0072] As shown in the table above, the thermal expansion of silicon nitride layer 30 is closer to that of silicon, which can act as a stress buffer layer and an intermediate matching layer to achieve the purpose of homogenizing the stress gradient in the wafer surface, thereby increasing e31 in the central region of the wafer and improving the uniformity of the wafer.

[0073] Example 2:

[0074] like Figures 5 to 7 As shown, this embodiment, based on Embodiment 1, proposes a preparation process for a lead zirconate titanate (PZT) thin film layer, which further includes the following steps:

[0075] S0 forms a silicon oxide layer 20 on the substrate 10 through a thermal oxidation process to achieve adhesion between the substrate 10 and the upper structure.

[0076] Specifically, before depositing the low tensile stress silicon nitride layer 30, a silicon oxide layer 20 is first formed on the surface of the substrate 10 through a thermal oxidation process, so that the silicon oxide layer 20 is located between the substrate 10 and the silicon nitride layer 30.

[0077] The silicon oxide layer 20 prepared by this process has a smooth surface, high density, and good insulation. It can serve as an adhesion layer between the substrate 10 and the upper film layer, as well as a basic buffer layer, an insulating layer, and a diffusion barrier layer.

[0078] The silicon oxide layer 20 and the silicon nitride layer 30 work together to suppress interface diffusion, optimize the nucleation of the lower electrode layer 401 and the growth of the piezoelectric thin film layer 402, thereby significantly improving the overall piezoelectric performance, structural uniformity and device stability of the piezoelectric functional layer 40.

[0079] Example 3:

[0080] like Figure 1 As shown, this embodiment proposes a film structure based on lead zirconate titanate (PZT) film, which can be processed using the preparation process of Example 1 or 2. The film structure includes a substrate 10, which can be a silicon substrate or an SOI substrate, but is not limited thereto.

[0081] The film structure also includes a low-tensile-stress silicon nitride layer 30 formed on the substrate 10 to homogenize the in-plane stress gradient of the wafer.

[0082] The silicon nitride layer 30 has high hardness and better modulus matching than the silicon oxide layer 20. As a stress buffer layer, it weakens the thermal mismatch transmission between silicon / silicon oxide layer / lower electrode layer / PZT, significantly reducing the stress difference between the center and the edge. At the same time, the low-stress design avoids the risk of warping and cracking caused by the high tensile stress of the silicon nitride layer 30 (hundreds of MPa), while providing stable stress regulation.

[0083] Moreover, the silicon nitride layer 30 has a high Young's modulus and low stress, which can be used as a vibration structure layer for devices, helping to improve the mechanical stability and vibration response characteristics of devices.

[0084] Preferably, the stress of the silicon nitride layer 30 is 0-50 MPa tensile stress, for example, it can be 10 MPa tensile stress.

[0085] The film structure also includes a piezoelectric functional layer 40 formed on the silicon nitride layer 30, and the piezoelectric thin film material of the piezoelectric functional layer 40 is lead zirconate titanate (PZT).

[0086] Among them, the piezoelectric functional layer 40 is c-axis oriented, and the c-axis oriented lead zirconate titanate (PZT) film can significantly improve the piezoelectric performance of the device. This orientation allows the electric domains of the PZT film to rotate and stretch more effectively along the c-axis direction under the action of an external electric field, thereby generating greater mechanical displacement and output force.

[0087] The film structure features a (001) plane preferred orientation. During film growth, grains preferentially grow and align along the (001) plane, forming a highly ordered microstructure. This preferred orientation not only enhances the piezoelectric coefficient of the lead zirconate titanate (PZT) film, ensuring higher energy conversion efficiency during electromechanical conversion, but also helps reduce uneven internal stress distribution and defects caused by lattice mismatch or differences in thermal expansion coefficients, thereby further enhancing the structural integrity and long-term operational reliability of the film.

[0088] The piezoelectric functional layer 40 includes a lower electrode layer 401, a piezoelectric thin film layer 402, and an upper electrode layer 403 sequentially formed on the silicon nitride layer 30.

[0089] Preferably, the materials of the lower electrode layer 401 and the upper electrode layer 403 are Pt / Ti system materials.

[0090] like Figure 11 and Figure 12 As shown, the roughness Ra of the film structure formed by the piezoelectric functional layer 40 deposited on the silicon nitride layer 30 at the center and the edge are 2.367 nm and 2.352 nm, respectively. The arithmetic mean roughness Ra and the root mean square roughness Rq are both lower than the roughness of the film structure formed by the piezoelectric functional layer 40 deposited on the silicon oxide layer 20. Since the surface energy of the low tensile stress silicon nitride layer 30 is higher than that of the silicon oxide layer 20, when the lower electrode layer 401 is deposited on it, the atomic migration barrier is higher and the surface migration distance is shorter, making it easier to form high-density and uniformly distributed nucleation sites. This results in finer grains, more uniform grain size distribution, and lower surface roughness in the lower electrode layer 401. The uniform lower electrode layer 401 can provide consistent interface energy and nucleation conditions for the PZT film, effectively improving the crystallization uniformity and orientation consistency of PZT on the 8-inch wafer, significantly reducing the performance difference between the central region and the edge region, and improving the uniformity of the piezoelectric constant e31 of the whole wafer.

[0091] Example 4:

[0092] like Figure 2 As shown, this embodiment, based on Embodiment 3, proposes a film structure based on lead zirconate titanate (PZT) thin film. This film structure further includes a silicon oxide layer 20 formed on a substrate 10. The silicon oxide layer 20 is located between the substrate 10 and the silicon nitride layer 30, and is used to achieve adhesion between the substrate 10 and the silicon nitride layer 30. In addition to serving as an adhesion layer between the substrate 10 and the silicon nitride layer 30, the silicon oxide layer 20 can also act as a basic buffer layer, an insulating layer, and a diffusion barrier layer.

[0093] Comparative Example 1:

[0094] like Figure 8As shown in the comparative example, a film structure based on lead zirconate titanate (PZT) film is provided. Compared with Example 3, the film structure does not have a silicon nitride layer 30 between the silicon oxide layer 20 and the piezoelectric functional layer 40. The piezoelectric functional layer 40 is formed directly on the silicon oxide layer 20.

[0095] The film structures of Example 3 or Example 4 and Comparative Example 1 were subjected to XRD tests, and the test results are as follows: Figure 13 and 14 As shown, when the piezoelectric functional layer 40 is grown on the silicon nitride layer 30 and when the piezoelectric functional layer 40 is grown on the silicon oxide layer 20, the XRD test results are the same. That is, compared with Comparative Example 1, the growth orientation and quality of the lead zirconate titanate (PZT) film structure in Example 3 or Example 4 have not been degraded. The scheme of directly growing the piezoelectric functional layer 40 on the silicon nitride layer 30 is feasible.

[0096] Stress tests were performed on the film structures obtained in Example 4 and Comparative Example 1. The results showed that the average stress across the entire wafer obtained in Example 4 was 63.90 MPa, and the average stress across the entire wafer obtained in Comparative Example 1 was 72.95 MPa. This indicates that using a low-tensile-stress silicon nitride layer 30 can effectively homogenize the stress distribution within the wafer surface and reduce the stress gradient.

[0097] Furthermore, the film structures of Example 4 and Comparative Example 1 were arranged as follows: Figure 9 As shown, the piezoelectric constant e31 was measured at 9 points, and the obtained piezoelectric constant e31 values ​​were normalized according to the formula " After normalization, the following table is obtained: Figure 10 The data shown:

[0098]

[0099] According to the uniformity calculation formula:

[0100]

[0101] Wherein, U represents uniformity, Max represents the maximum value of piezoelectric constant e31, Min represents the minimum value of piezoelectric constant e31, and Mean represents the average value of e31. It can be seen that the uniformity of piezoelectric constant e31 of the film structure in Example 4 is 20.71%, while the uniformity of piezoelectric constant e31 of the film structure in Comparative Example 1 is 33.80%. The piezoelectric constant e31 value at point 1 in Example 4 is 23.99% higher than that in Comparative Example 1. That is, the piezoelectric constant e31 of the whole wafer center region and the uniformity of the whole wafer of the film structure in Example 4 are significantly improved compared with Comparative Example 1. That is, the piezoelectric functional layer 40 is grown on the silicon nitride layer 30, which can improve the piezoelectric constant e31 value of the whole wafer center region and also improve the uniformity of the whole wafer.

[0102] Example 5:

[0103] This embodiment, based on Embodiments 3 and 4, proposes an application of a lead zirconate titanate (PZT) thin film structure. This film structure can be used in the manufacture of sensors and actuators for piezoelectric micromechanical systems after patterning. Figures 17 to 22 As shown, it can be used in cantilever beams, PMUTs, microphones, and other fields, but is not limited to these.

[0104] Specifically, such as Figures 15 to 16 As shown, the graphical process includes the following steps S3-S4:

[0105] Based on the film structure of Example 3 or Example 4, S3 sequentially patterns the upper electrode layer 403, piezoelectric layer 402, lower electrode layer 401 and silicon nitride layer 30 as needed.

[0106] S4 releases the back cavity 101, ultimately forming devices such as the cantilever beam, PMUT, and microphone. Specifically, the back cavity 101 is formed by etching the substrate 10 using DRIE (deep silicon etching technology). If there is a silicon oxide layer 20 on the substrate 10, the silicon oxide layer 20 needs to be further etched using ICP (inductively coupled plasma) to form the final back cavity 101.

[0107] In the aforementioned fields, silicon nitride layer 30, due to its high Young's modulus and low stress, can be used as a structural layer. It can not only ensure the stability and mechanical reliability of the device structure, but also synergistically improve the electrical performance, high temperature resistance and process compatibility of the device, providing important support for the realization of high performance, long life and high cost performance of the device.

[0108] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.

[0109] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A process for preparing a lead zirconate titanate (PZT) thin film, characterized in that, The preparation process includes the following steps: S1 forms a low-tensile-stress silicon nitride layer on the substrate surface to homogenize the in-plane stress gradient of the wafer; and S2 forms a piezoelectric functional layer on the surface of the silicon nitride layer by sputtering, wherein the piezoelectric thin film material of the piezoelectric functional layer is lead zirconate titanate (PZT).

2. The preparation process according to claim 1, characterized in that, The process for forming the piezoelectric functional layer in S2 includes the following step S21: S21 forms a lower electrode layer, a piezoelectric thin film layer, and an upper electrode layer sequentially on the surface of a silicon nitride layer by sputtering.

3. The preparation process according to claim 2, characterized in that, The materials of the lower electrode layer and the upper electrode layer are Pt / Ti system materials.

4. The preparation process according to claim 1, characterized in that, The preparation process also includes the following steps: S0 forms a silicon oxide layer on the substrate through a thermal oxidation process. The silicon oxide layer is located between the substrate and the silicon nitride layer to achieve adhesion between the substrate and the silicon nitride layer.

5. A film structure based on lead zirconate titanate (PZT) thin film, characterized in that, It is processed using the preparation process described in any one of claims 1-4.

6. The membrane structure according to claim 5, characterized in that, The membrane structure includes: Base; and A low-tensile-stress silicon nitride layer formed on the substrate is used to homogenize the in-plane stress gradient of the wafer; and A piezoelectric functional layer is formed on the silicon nitride layer, and the piezoelectric thin film material of the piezoelectric functional layer is lead zirconate titanate (PZT).

7. The membrane structure according to claim 6, characterized in that, The piezoelectric functional layer is c-axis oriented and the lattice orientation is (001) crystal plane preferred orientation.

8. The membrane structure according to claim 7, characterized in that, The film structure further includes a silicon oxide layer formed on the substrate, the silicon oxide layer being located between the substrate and the silicon nitride layer, for achieving adhesion between the substrate and the silicon nitride layer.

9. An application of the membrane structure according to any one of claims 5-8, characterized in that, The membrane structure, after being patterned, is used in the manufacture of sensors and actuators for piezoelectric micromechanical systems.

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