A protection device and method for a test probe

Abstract

This invention relates to the field of semiconductor technology and discloses a protection device and method for a test probe. The protection device includes a first switching circuit, a second switching circuit, a third switching circuit, a sampling circuit, a discharge circuit, and a controller. The sampling circuit monitors the voltage and current signals of the MOSFET under test in real time. The controller can quickly identify the failure state of the device and then link the first, second, and third switching circuits to cut off the high-voltage power supply circuit and the inductor-probe path in stages. The discharge circuit is connected to accelerate the release of inductor energy and completely block the impact of freewheeling current on the probe. This solves the core problem of probe damage due to prolonged exposure to high current in existing tests and significantly extends the service life of the probe.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a protection device and method for a test probe. Background Technology

[0002] In power semiconductor wafer-level testing, double-pulse testing and avalanche testing are important electrical performance tests, both conducted under inductive load conditions. Due to the small size / diameter of the test probes and their short current withstand time, if the device under test fails and short-circuits during these two types of tests, even if the high-voltage power supply circuit is disconnected, the inductor freewheeling current will still flow through the test probes. Since this circuit has low resistance and a slow current drop rate, prolonged exposure to high current can easily damage the probes and shorten their lifespan. Summary of the Invention

[0003] This invention provides a protection device and method for test probes to solve the problem of how to protect test probes.

[0004] In a first aspect, the present invention provides a protection device for a test probe, the protection device comprising: a first switching circuit, a second switching circuit, a third switching circuit, a sampling circuit, a discharge circuit, and a controller, wherein the controller is connected to the control terminals of the first switching circuit, the second switching circuit, the third switching circuit, and the output terminal of the sampling circuit; the first terminal of the first switching circuit is connected to the first terminal of an inductor and the first terminal of the discharge circuit, and in different tests, the second terminal of the first switching circuit is connected to the drain of the MOSFET under test via a test probe, or to the source of the upper MOSFET under test or the drain of the lower MOSFET under test via a test probe; the first terminal of the second switching circuit is connected to the second terminal of the discharge circuit, and in different tests, the second terminal of the second switching circuit is grounded or connected to the second terminal of the inductor; the first terminal of the third switching circuit is connected to a high-voltage power supply, and the second terminal of the third switching circuit outputs a power supply voltage, which is used to power the MOSFET under test.

[0005] In one optional implementation, during an avalanche test, only the MOSFET under test is tested. The source of the MOSFET under test is connected to the first terminal of a first current sensor via a test probe, and the second terminal of the first current sensor is grounded. The first terminal of a first switching circuit is connected to the first terminal of an inductor and the first terminal of a discharge circuit, and the second terminal of the first switching circuit is connected to the drain of the MOSFET under test via a test probe. The first terminal of a second switching circuit is connected to the second terminal of the discharge circuit and the second terminal of the second switching circuit is connected to the second terminal of the first current sensor. The first terminal of a third switching circuit is connected to a high-voltage power supply, and the second terminal of the third switching circuit is connected to the cathode of a diode and the second terminal of an inductor. The second terminal of the third switching circuit is connected to the drain of the MOSFET under test via a test probe. The anode of the diode is connected to the second terminal of the first current sensor. The sampling circuit acquires the drain-source voltage of the MOSFET under test via a test probe and acquires the current of the first current sensor.

[0006] In one optional implementation, in the double-pulse test mode one, the source of the MOSFET under test is connected to the first terminal of the second current sensor, the second terminal of the second current sensor is connected to the drain of the MOSFET under test, the source of the MOSFET under test is connected to the first terminal of the third current sensor, and the second terminal of the third current sensor is grounded; the first terminal of the first switching circuit is connected to the first terminal of the inductor and the first terminal of the discharge circuit, the second terminal of the first switching circuit is connected to the second terminal of the second current sensor, and the second terminal of the first switching circuit is also connected to the drain of the MOSFET under test through a test probe; the first terminal of the second switching circuit is connected to the second terminal of the discharge circuit, and the second terminal of the third current sensor is connected to the drain of the MOSFET under test. The second terminal of the second switching circuit is connected to the second terminal of the inductor and the second terminal of the third switching circuit. The second terminal of the second switching circuit is also connected to the drain of the MOSFET under test via a test probe. The first terminal of the third switching circuit is connected to the high-voltage power supply. The second terminal of the third switching circuit is connected to the drain of the MOSFET under test via the test probe. The sampling circuit collects the drain-source voltage of the MOSFET under test and the MOSFET under test via the test probe. The sampling circuit collects the current of the second current sensor and the current of the third current sensor. The dual-pulse test mode one is used to test the switching characteristic parameters of the MOSFET under test and the reverse recovery characteristic parameters of the MOSFET under test.

[0007] In an optional implementation, in the second double-pulse test mode, the source of the MOSFET under test is connected to the first terminal of the fourth current sensor via the test probe, the second terminal of the fourth current sensor is connected to the drain of the MOSFET under test via the test probe, and the source of the MOSFET under test is connected to the first terminal of the fifth current sensor via the test probe. The second terminal of the fifth current sensor is grounded. The first terminal of the first switching circuit is connected to the first terminal of the inductor and the first terminal of the discharge circuit. The second terminal of the first switching circuit is connected to the second terminal of the fourth current sensor. The second terminal of the first switching circuit is also connected to the drain of the MOSFET under test via the test probe. The circuit consists of two terminals: a first terminal of the second switching circuit and a second terminal of the discharge circuit; a second terminal of the second switching circuit and a second terminal of the inductor and a second terminal of the fifth current sensor; a first terminal of the third switching circuit and a second terminal of the third switching circuit and a second terminal of the MOSFET under test connected via the test probe; a sampling circuit that acquires the drain-source voltage of the MOSFET under test and the MOSFET under test via the test probe; and a sampling circuit that acquires the current of the fourth current sensor and the current of the fifth current sensor. The second dual-pulse test mode is used to test the switching characteristic parameters of the MOSFET under test and the reverse recovery characteristic parameters of the MOSFET under test.

[0008] In one optional embodiment, the first switch circuit, the second switch circuit, and the third switch circuit each include: a mother switch board and at least one sub-switch board, wherein the control terminal of each sub-switch board is connected to a controller; the first terminal of at least one sub-switch board connected in series and / or parallel is connected to the first terminal of the mother switch board, and the second terminal of at least one sub-switch board connected in series and / or parallel is connected to the second terminal of the mother switch board; the first terminal of the mother switch board is the first terminal of the first switch circuit, the first terminal of the second switch circuit, and the first terminal of the third switch circuit, and the second terminal of the mother switch board is the second terminal of the first switch circuit, the second terminal of the second switch circuit, and the second terminal of the third switch circuit.

[0009] In one optional embodiment, the sub-switch board includes: a first MOSFET, a second MOSFET, a low-voltage power supply, a first driving circuit, and a second driving circuit. The first terminal of the first driving circuit is connected to the controller, and the power supply terminal of the first driving circuit is connected to the low-voltage power supply. The first terminal of the second driving circuit is connected to the controller, and the power supply terminal of the second driving circuit is connected to the low-voltage power supply. The first terminal of the first MOSFET is the first terminal of the sub-switch board, the second terminal of the first MOSFET is connected to the second terminal of the second MOSFET, and the control terminal of the first MOSFET is connected to the second terminal of the first driving circuit. The first terminal of the second MOSFET is the second terminal of the sub-switch board, and the control terminal of the second MOSFET is connected to the second terminal of the second driving circuit.

[0010] In one optional implementation, the sampling circuit includes a first sampling unit and a second sampling unit, wherein both the first sampling unit and the second sampling unit are used to acquire the drain-source voltage and source current of a MOSFET under test.

[0011] In one alternative implementation, the discharge circuit includes at least one resistor.

[0012] In one optional embodiment, the protection device for the test probe further includes multiple interfaces, wherein the first switching circuit, the second switching circuit, the third switching circuit, the sampling circuit, and the discharge circuit are all connected to circuits outside the protection device for the test probe through the interfaces.

[0013] Secondly, the present invention provides a method for protecting a test probe, comprising: a controller controlling a first switching circuit to be turned on and a second switching circuit to be turned off, and simultaneously controlling a third switching circuit to be turned on, so as to perform avalanche testing and double-pulse testing on a MOSFET; during the testing process, the controller determines whether the MOSFET is abnormal based on the voltage and current collected by the sampling circuit; when the MOSFET is abnormal, the controller controls the first switching circuit to be turned off and the second switching circuit to be turned on, and simultaneously controls the third switching circuit to be turned off.

[0014] Beneficial effects:

[0015] By monitoring the voltage and current signals of the MOSFET under test in real time through the sampling circuit, the controller can quickly identify the failure state of the device, and then link the first, second and third switching circuits to cut off the high voltage power supply circuit and the inductor-probe path in stages, and connect the discharge circuit to accelerate the release of inductor energy, completely blocking the impact of freewheeling current on the probe. This solves the core problem of probe damage due to long-term exposure to high current in existing tests, and significantly extends the service life of the probe.

[0016] Through differentiated interface design and flexible circuit connection logic, the device can seamlessly adapt to various power semiconductor electrical performance testing scenarios such as avalanche testing, wafer half-bridge double-pulse testing (mode 1 / mode 2), and KGD testing. It can meet the testing and protection requirements of different devices under test (DUT / HDUT / LDUT) without additional modifications, greatly improving the applicability and practicality of the device.

[0017] The first, second, and third switching circuits are all built on sub-switching boards. By adjusting the number of sub-switching boards and their series-parallel connection methods (series connection to increase withstand voltage and parallel connection to enhance current carrying capacity), they can flexibly adapt to the voltage and current requirements of different test scenarios without redesigning the overall circuit. This effectively shortens the product development cycle and reduces the cost of customized materials and equipment maintenance. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a diagram illustrating the composition of a protection device for a test probe according to an embodiment of the present invention; Figure 2 This is a diagram showing the composition of the first switching circuit, the second switching circuit, and the third switching circuit according to an embodiment of the present invention. Figure 3 This is a detailed circuit structure diagram of the sub-switch board according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the application of a protective device for a test probe according to an embodiment of the present invention in an avalanche test; Figure 5 This is a schematic diagram illustrating the application of the protection device for the test probe according to an embodiment of the present invention in dual-pulse test mode one; Figure 6 This is a schematic diagram illustrating the application of the protection device for the test probe according to an embodiment of the present invention in dual-pulse test mode two. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] This embodiment provides a protection device for a test probe. This device is mainly used in inductive load power semiconductor electrical performance tests such as avalanche testing and wafer half-bridge double-pulse testing to prevent damage to the probe from the inductor freewheeling current after the device under test (DUT) fails. The test probe is used to establish an electrical connection between the protection device and the DUT, such as... Figure 1 As shown, the protection device includes: a first switching circuit 1, a second switching circuit 2, a third switching circuit 3, a sampling circuit 4, a discharge circuit 5, and a controller 6.

[0024] The controller 6 is connected to the control terminals of the first switching circuit 1, the second switching circuit 2, the third switching circuit 3, and the output terminal of the sampling circuit 4. The first terminal of the first switching circuit 1 is connected to the first terminal of the inductor and the first terminal of the discharge circuit 5. In different tests, the second terminal of the first switching circuit 1 is connected to the drain of the MOSFET under test through a test probe or to the source of the upper MOSFET under test or the drain of the lower MOSFET under test through a test probe. The first terminal of the second switching circuit 2 is connected to the second terminal of the discharge circuit 5. In different tests, the second terminal of the second switching circuit 2 is grounded or connected to the second terminal of the inductor. The first terminal of the third switching circuit 3 is connected to the high-voltage power supply HV, and the second terminal of the third switching circuit 3 outputs a power supply voltage, which is used to power the MOSFET under test.

[0025] Specifically, the controller 6, as the core control unit of the entire protection device, has its signal input terminal connected to the output terminal of the sampling circuit 4, and can receive the voltage and current detection data fed back by the sampling circuit 4 in real time; at the same time, its signal output terminal is connected to the control terminal of the first switch circuit 1, the control terminal of the second switch circuit 2, and the control terminal of the third switch circuit 3 respectively, and can accurately output the control command for switching on and off according to the abnormal state of the sampling data, so as to realize the time-sequential control of each circuit.

[0026] Specifically, the first terminal of the first switching circuit 1 is connected to the first terminal of the inductor and the first terminal of the discharge circuit 5. The connection method of its second terminal will change with the test mode: in the avalanche test, this terminal is connected to the drain of the MOSFET under test (DUT) through the test probe; in the dual-pulse test mode one and mode two, this terminal is connected to the source of the upper MOSFET under test (HDUT) or the drain of the lower MOSFET under test (LDUT) through the test probe. The core function is to open or close the current path between the inductor, the probe, and the device under test, so as to avoid damage caused by the freewheeling current flowing through the test probe for a long time.

[0027] Specifically, the first end of the second switching circuit 2 is connected to the second end of the discharge circuit 5. The connection path of the second end will change depending on the test scenario: in the avalanche test and the second double pulse test, the end is directly grounded; in the first double pulse test, the end is connected to the second end of the inductor, mainly responsible for controlling the current switching of the discharge circuit 5, providing a path for the release of the inductor's freewheeling energy.

[0028] Specifically, the first terminal of the third switching circuit 3 is connected to the high-voltage power supply HV, and the second terminal of the third switching circuit 3 outputs a stable power supply voltage. This power supply voltage can provide working power to the MOSFET DUT in the avalanche test, the upper MOSFET HDUT and the lower MOSFET LDUT in the double pulse test through the corresponding interface and test probe. Its on / off state is controlled in real time by the controller 6 according to the test progress and device status.

[0029] The sampling circuit 4 can accurately detect the drain-source voltage (VDS) and drain current (IDS) of the device under test. In the avalanche test, the sampling circuit 4 collects the drain-source voltage of the MOSFET DUT through a probe. In the dual-pulse test mode 1 and mode 2, it collects the drain-source voltage of the upper MOSFET HDUT and the lower MOSFET LDUT and the current data of the corresponding current sensor, and feeds these detection data back to the controller 6 in real time, providing the controller 6 with the core basis for judging whether the device has failed.

[0030] The discharge circuit 5 is a dedicated discharge resistor. Its core function is to accelerate the release of inductor energy. When the device under test fails, the discharge circuit 5 can be connected to the freewheeling circuit through the second switching circuit 2 to quickly dissipate the electrical energy stored in the inductor on the resistor, thus preventing the freewheeling current from flowing through the test probe for a long time and causing damage.

[0031] In one alternative implementation, such as Figure 2 As shown, the first switch circuit 1, the second switch circuit 2, and the third switch circuit 3 each include: a mother switch board 7 and at least one sub-switch board 8, wherein the control terminal of each sub-switch board 8 is connected to the controller 6; the first terminal of at least one sub-switch board 8 connected in series and / or parallel is connected to the first terminal of the mother switch board 7, and the second terminal of at least one sub-switch board 8 connected in series and / or parallel is connected to the second terminal of the mother switch board 7; the first terminal of the mother switch board 7 is the first terminal of the first switch circuit 1, the first terminal of the second switch circuit 2, and the first terminal of the third switch circuit 3, and the second terminal of the mother switch board 7 is the second terminal of the first switch circuit 1, the second terminal of the second switch circuit 2, and the second terminal of the third switch circuit 3.

[0032] Specifically, each switching circuit includes at least one sub-switching board 8. These sub-switching boards 8 are standardized functional units, and can be connected in series, parallel, or a combination of series and parallel connections according to the withstand voltage and current carrying requirements of the actual test conditions. When using a series connection, the second end of the first sub-switch board 8 needs to be connected to the first end of the second sub-switch board 8 in sequence. This connection method can effectively improve the overall withstand voltage of the entire switching circuit and is suitable for high voltage test scenarios. When using parallel connection, the first end of all sub-switching boards 8 must be short-circuited to each other, and the second end must also be short-circuited to each other. This connection method can enhance the current carrying capacity of the switching circuit and meet the working conditions requirements of high current test. If the test scenario has high requirements for both withstand voltage and current carrying capacity, a hybrid series-parallel connection can be used to ensure the circuit's withstand voltage stability while increasing the upper limit of current carrying capacity.

[0033] After all the sub-switches 8 have completed their predetermined connections, their first end is precisely connected to the first end of the mother switch board 7, and their second end is connected to the second end of the mother switch board 7, forming a complete current path from the sub-switches 8 cluster to the mother switch board 7.

[0034] In one alternative implementation, such as Figure 3 As shown, the sub-switch board 8 includes: a first MOSFET Q1, a second MOSFET Q2, a low-voltage power supply 81, a first driving circuit 82, and a second driving circuit 83. The first terminal of the first driving circuit 82 is connected to the controller 6, and the power supply terminal of the first driving circuit 82 is connected to the low-voltage power supply 81. The first terminal of the second driving circuit 83 is connected to the controller 6, and the power supply terminal of the second driving circuit 83 is connected to the low-voltage power supply 81. The first terminal of the first MOSFET Q1 is the first terminal of the sub-switch board 8, and the second terminal of the first MOSFET Q1 is connected to the second terminal of the second MOSFET Q2. The control terminal of the first MOSFET Q1 is connected to the second terminal of the first driving circuit 82. The first terminal of the second MOSFET Q2 is the second terminal of the sub-switch board 8, and the control terminal of the second MOSFET Q2 is connected to the second terminal of the second driving circuit 83.

[0035] When the controller 6 determines that the test circuit needs to turn on the corresponding switch, it simultaneously sends a turn-on command to the first drive circuit 82 and the second drive circuit 83 of the same sub-switch board 8. Supported by a dedicated low-voltage power supply 81, the two drive circuits synchronously output stable drive signals, which act on the control terminals of the first MOSFET Q1 and the second MOSFET Q2, respectively, causing them to turn on simultaneously. At this time, current can flow smoothly from the first terminal of the sub-switch board 8 through the series path of the two MOSFETs to the second terminal, ensuring the current supply of the test circuit. When the device under test fails and the controller 6 issues a turn-off command, the two drive circuits synchronously stop outputting drive signals, and the first MOSFET Q1 and the second MOSFET Q2 quickly turn off, completely cutting off the current path of the sub-switch board 8 and preventing freewheeling current from flowing. This dual-drive-dual-MOSFET architecture not only improves the turn-on reliability of the sub-switch board 8, but also supports the series and parallel combination of multiple sub-switch boards 8 through modular design, which can flexibly improve the withstand voltage and current carrying capacity of the switching circuit, adapting to the needs of different scenarios such as avalanche testing and double-pulse testing.

[0036] In one alternative implementation, refer to Figure 1 In an avalanche test, only the MOSFET under test (i.e., only one MOSFET) is tested. The source of the MOSFET under test (DUT) is connected to the first terminal of the first current sensor through the test probe, and the second terminal of the first current sensor is grounded. The first terminal (A terminal) of the first switching circuit 1 is connected to the first terminal of the inductor and the first terminal of the discharge circuit 5. The second terminal (F terminal) of the first switching circuit 1 is connected to the drain of the MOSFET under test (DUT) through the test probe. The first terminal of the second switching circuit 2 is connected to the second terminal of the discharge circuit 5. The second terminal (I terminal) of the second switching circuit 2 is connected to the second terminal of the first current sensor. The first terminal (B terminal) of the third switching circuit 3 is connected to the high-voltage power supply HV. The second terminal (C terminal) of the third switching circuit 3 is connected to the cathode of the diode and the second terminal of the inductor. The second terminal of the third switching circuit is connected to the drain of the MOSFET under test through the test probe. The anode of the diode is connected to the second terminal of the first current sensor. The sampling circuit 4 collects the drain-source voltage of the MOSFET under test (DUT) through the test probe and collects the current of the first current sensor.

[0037] Specifically, the block diagram of the application of the protective device in avalanche testing is as follows: Figure 4 As shown, the specific steps of the protection method are as follows: (1) The controller 6 controls the first switch circuit 1 to open, the third switch circuit 3 to open, and the second switch circuit 2 to close. The circuit is in normal test state, and the avalanche test current loop is shown as dashed line I.

[0038] (2) The avalanche test begins, and the DUT fails during the avalanche test. The controller 6 identifies that the voltage or current of the DUT is in an abnormal state through VDS and IDS sampling.

[0039] (3) The controller 6 controls the third switch circuit 3 to close, and the high voltage power supply is cut off.

[0040] (4) The controller 6 controls the second switch circuit 2 to turn on, and the discharge resistor is connected to GND.

[0041] (5) The controller 6 controls the first switch circuit 1 to close, the current between the inductor and the DUT is turned off, and the probe current returns to zero.

[0042] (6) The inductor continues to flow through the discharge circuit 5. At this time, the current loop is as shown by the dashed line II. The energy of the inductor is consumed in the resistor until the energy of the inductor is zero.

[0043] In one alternative implementation, refer to Figure 1 In the double-pulse test mode one, the source of the upper MOSFET HDUT is connected to the first terminal of the second current sensor through the test probe. The second terminal of the second current sensor is connected to the drain of the lower MOSFET LDUT through the test probe. The source of the lower MOSFET LDUT is connected to the first terminal of the third current sensor through the test probe. The second terminal of the third current sensor is grounded. The first terminal (A terminal) of the first switching circuit 1 is connected to the first terminal of the inductor and the first terminal of the discharge circuit 5. The second terminal (F terminal) of the first switching circuit 1 is connected to the second terminal of the second current sensor. The second terminal of the first switching circuit 1 is also connected to the drain of the lower MOSFET LDUT through the test probe. The first terminal of the second switching circuit 2 is connected to the second terminal of the discharge circuit 5. The second terminal (I terminal) of the switching circuit 2 is connected to the second terminal of the inductor and the second terminal (C terminal) of the third switching circuit 3. The second terminal of the second switching circuit 2 is also connected to the drain of the MOSFET HDUT under test through a test probe. The first terminal (B terminal) of the third switching circuit 3 is connected to the high-voltage power supply HV. The second terminal of the third switching circuit 3 is connected to the drain of the MOSFET HDUT under test through the test probe. The sampling circuit 4 collects the drain-source voltage of the MOSFET HDUT and the MOSFET LDUT under test through the test probe. The sampling circuit 4 also collects the current of the second current sensor and the current of the third current sensor. The dual-pulse test mode 1 is used to test the switching characteristic parameters of the MOSFET LDUT under test and the reverse recovery characteristic parameters of the MOSFET HDUT under test.

[0044] Specifically, the block diagram of the protection device applied in dual-pulse test mode one is as follows: Figure 5 As shown, the specific steps of the protection method are as follows: (1) Controller 6 controls the first switch circuit 1 to turn on, the third switch circuit 3 to turn on, and the second switch circuit 2 to turn off, starting the double pulse test. The circuit is in normal test state. When the upper MOSFET is off and the lower MOSFET is on, the current loop is shown as dashed line I. When the upper MOSFET under test (HDUT) is off and the lower MOSFET under test (LDUT) is off, the current loop is shown as dashed line II.

[0045] (2) The HDUT or LDUT fails during testing. The controller 6 detects that the voltage or current of the DUT is abnormal.

[0046] (3) The controller 6 controls the third switch circuit 3 to close, and the high voltage power supply is cut off.

[0047] (4) The controller 6 controls the second switch circuit 2 to turn on, and the discharge resistor is connected to the inductor terminal 2.

[0048] (5) The controller 6 controls the first switch circuit 1 to close, the current between the inductor and the DUT is turned off, and the probe current returns to zero.

[0049] (6) The inductor continues to flow through the discharge resistor. At this time, the current loop is as shown by the dashed line III. The energy of the inductor is consumed in the resistor until the energy of the inductor is zero.

[0050] In an optional implementation, in the second double-pulse test mode, the source of the upper MOSFET (HDUT) under test is connected to the first terminal of the fourth current sensor via the test probe, the second terminal of the fourth current sensor is connected to the drain of the lower MOSFET (LDUT) under test via the test probe, the source of the lower MOSFET (LDUT) under test is connected to the first terminal of the fifth current sensor via the test probe, and the second terminal of the fifth current sensor is grounded; the first terminal (A terminal) of the first switching circuit 1 is connected to the first terminal of the inductor and the first terminal of the discharge circuit 5, the second terminal (F terminal) of the first switching circuit 1 is connected to the second terminal of the fourth current sensor, and the second terminal of the first switching circuit 1 is also connected to the drain of the lower MOSFET (LDUT) under test via the test probe; the second switching circuit 1... The first terminal of the switching circuit 2 is connected to the second terminal of the discharge circuit 5. The second terminal (I terminal) of the second switching circuit 2 is connected to the second terminal of the inductor and the second terminal of the fifth current sensor. The first terminal (B terminal) of the third switching circuit 3 is connected to the high-voltage power supply HV. The second terminal (C terminal) of the third switching circuit 3 is connected to the drain of the upper MOSFET HDUT through the test probe. The sampling circuit 4 collects the drain-source voltage of the upper MOSFET HDUT and the lower MOSFET LDUT through the test probe. The sampling circuit 4 collects the current of the fourth current sensor and the current of the fifth current sensor. The double-pulse test mode 2 is used to test the switching characteristic parameters of the upper MOSFET LDUT and the reverse recovery characteristic parameters of the lower MOSFET HDUT.

[0051] Specifically, the block diagram of the protection device applied in the double-pulse test mode two is as follows: Figure 6 As shown, the specific steps of the protection method are as follows: (1) Controller 6 controls the first switch circuit 1 to turn on, the third switch circuit 3 to turn on, and the second switch circuit 2 to turn off, so that the circuit is in normal test state. When the upper MOSFET HDUT under test is turned on and the lower MOSFET LDUT under test is turned off, the current loop is shown as dashed line I. When the upper MOSFET HDUT under test is turned off and the lower MOSFET LDUT under test is turned off, the current loop is shown as dashed line II.

[0052] (2) Start the double pulse test and detect that the upper or lower transistor has failed during the test. Controller 6 recognizes that the voltage or current of the DUT is in an abnormal state.

[0053] (3) The controller 6 controls the third switch circuit 3 to close, and the high voltage power supply is cut off.

[0054] (4) The controller 6 controls the second switch circuit 2 to turn on, and the discharge resistor is connected to GND.

[0055] (5) The controller 6 controls the first switch circuit 1 to close, the current between the inductor and the DUT is turned off, and the probe current returns to zero.

[0056] (6) The inductor continues to flow through the discharge resistor. At this time, the current loop is as shown by the dashed line III. The energy of the inductor is consumed in the resistor until the energy of the inductor is zero.

[0057] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A protective device for a test probe, characterized in that, The protection device includes: a first switching circuit, a second switching circuit, a third switching circuit, a sampling circuit, a discharge circuit, and a controller, wherein, The controller is connected to the control terminal of the first switching circuit, the control terminal of the second switching circuit, the control terminal of the third switching circuit, and the output terminal of the sampling circuit. The first terminal of the first switching circuit is connected to the first terminal of the inductor and the first terminal of the discharge circuit. In different tests, the second terminal of the first switching circuit is connected to the drain of the MOSFET under test through the test probe or to the source of the upper MOSFET under test or the drain of the lower MOSFET under test through the test probe. The first terminal of the second switching circuit is connected to the second terminal of the discharge circuit. In different tests, the second terminal of the second switching circuit is grounded or connected to the second terminal of the inductor. The first terminal of the third switching circuit is connected to a high-voltage power supply, and the second terminal of the third switching circuit outputs a power supply voltage, which is used to power the MOS transistor under test.

2. The protective device for the test probe according to claim 1, characterized in that, In an avalanche test, only the MOSFET under test is tested. The source of the MOSFET under test is connected to the first terminal of the first current sensor through the test probe, and the second terminal of the first current sensor is grounded. The first terminal of the first switching circuit is connected to the first terminal of the inductor and the first terminal of the discharge circuit, and the second terminal of the first switching circuit is connected to the drain of the MOS transistor under test through the test probe. The first terminal of the second switching circuit is connected to the second terminal of the discharge circuit, and the second terminal of the second switching circuit is connected to the second terminal of the first current sensor. The first terminal of the third switching circuit is connected to the high-voltage power supply, the second terminal of the third switching circuit is connected to the cathode of the diode and the second terminal of the inductor, and the second terminal of the third switching circuit is connected to the drain of the MOS transistor under test through the test probe. The anode of the diode is connected to the second terminal of the first current sensor; The sampling circuit acquires the drain-source voltage of the MOSFET under test through the test probe, and the sampling circuit acquires the current of the first current sensor.

3. The protection device for the test probe according to claim 1, characterized in that, In dual-pulse test mode one The source of the MOSFET under test is connected to the first terminal of the second current sensor through the test probe, the second terminal of the second current sensor is connected to the drain of the MOSFET under test through the test probe, the source of the MOSFET under test is connected to the first terminal of the third current sensor through the test probe, and the second terminal of the third current sensor is grounded. The first terminal of the first switching circuit is connected to the first terminal of the inductor and the first terminal of the discharge circuit. The second terminal of the first switching circuit is connected to the second terminal of the second current sensor. The second terminal of the first switching circuit is also connected to the drain of the MOS transistor under test through the test probe. The first terminal of the second switching circuit is connected to the second terminal of the discharge circuit, the second terminal of the second switching circuit is connected to the second terminal of the inductor and the second terminal of the third switching circuit, and the second terminal of the second switching circuit is also connected to the drain of the MOSFET under test through the test probe. The first terminal of the third switching circuit is connected to the high-voltage power supply, and the second terminal of the third switching circuit is connected to the drain of the MOSFET under test through the test probe. The sampling circuit acquires the drain-source voltage of the upper and lower MOSFETs under test through the test probe, and acquires the current of the second current sensor and the current of the third current sensor. The dual-pulse test mode one is used to test the switching characteristic parameters of the MOSFET under test and the reverse recovery characteristic parameters of the MOSFET under test.

4. The protection device for the test probe according to claim 1, characterized in that, In the double-pulse test mode two, The source of the MOSFET under test is connected to the first terminal of the fourth current sensor through the test probe, the second terminal of the fourth current sensor is connected to the drain of the MOSFET under test through the test probe, the source of the MOSFET under test is connected to the first terminal of the fifth current sensor through the test probe, and the second terminal of the fifth current sensor is grounded. The first terminal of the first switching circuit is connected to the first terminal of the inductor and the first terminal of the discharge circuit. The second terminal of the first switching circuit is connected to the second terminal of the fourth current sensor. The second terminal of the first switching circuit is also connected to the drain of the MOS transistor under test through the test probe. The first terminal of the second switching circuit is connected to the second terminal of the discharge circuit, and the second terminal of the second switching circuit is connected to the second terminal of the inductor and the second terminal of the fifth current sensor. The first terminal of the third switching circuit is connected to the high-voltage power supply, and the second terminal of the third switching circuit is connected to the drain of the MOSFET under test through the test probe. The sampling circuit acquires the drain-source voltage of the upper and lower MOSFETs under test through the test probe, and acquires the current of the fourth current sensor and the current of the fifth current sensor. The second dual-pulse test mode is used to test the switching characteristic parameters of the upper MOSFET under test and the reverse recovery characteristic parameters of the lower MOSFET under test.

5. The protective device for the test probe according to any one of claims 1-4, characterized in that, The first switching circuit, the second switching circuit, and the third switching circuit each include: a mother switch board and at least one daughter switch board, wherein... The control terminal of each of the sub-switches is connected to the controller; The first end of the at least one sub-switch board connected in series and / or parallel is connected to the first end of the mother switch board, and the second end of the at least one sub-switch board connected in series and / or parallel is connected to the second end of the mother switch board. The first end of the mother switch board is the first end of the first switch circuit, the first end of the second switch circuit, and the first end of the third switch circuit. The second end of the mother switch board is the second end of the first switch circuit, the second end of the second switch circuit, and the second end of the third switch circuit.

6. The protection device for the test probe according to claim 5, characterized in that, The sub-switch board includes: a first MOSFET, a second MOSFET, a low-voltage power supply, a first driving circuit, and a second driving circuit, wherein... The first end of the first drive circuit is connected to the controller, and the power supply end of the first drive circuit is connected to the low-voltage power supply. The first end of the second drive circuit is connected to the controller, and the power supply end of the second drive circuit is connected to the low-voltage power supply. The first terminal of the first MOSFET is the first terminal of the sub-switch board, the second terminal of the first MOSFET is connected to the second terminal of the second MOSFET, and the control terminal of the first MOSFET is connected to the second terminal of the first drive circuit. The first terminal of the second MOS transistor is the second terminal of the sub-switching board, and the control terminal of the second MOS transistor is connected to the second terminal of the second driving circuit.

7. The protective device for the test probe according to claim 1, characterized in that, The sampling circuit includes: a first sampling unit and a second sampling unit, wherein... Both the first sampling unit and the second sampling unit are used to acquire the drain-source voltage and source current of a MOSFET under test.

8. The protection device for the test probe according to claim 1, characterized in that, The discharge circuit includes at least one resistor.

9. The protective device for the test probe according to claim 1, characterized in that, Also includes: Multiple interfaces, among which, The first switching circuit, the second switching circuit, the third switching circuit, the sampling circuit, and the discharge circuit are all connected to circuits outside the protection device of the test probe via interfaces.

10. A method for protecting a test probe, characterized in that, include: The controller controls the first switching circuit to turn on and the second switching circuit to turn off, while simultaneously controlling the third switching circuit to turn on, in order to perform avalanche testing and double-pulse testing on the MOSFET. During the test, the controller determines whether the MOSFET is abnormal based on the voltage and current collected by the sampling circuit. When the MOSFET malfunctions, the controller shuts down the first switching circuit, turns on the second switching circuit, and simultaneously shuts down the third switching circuit.

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