A brain-like independent architecture-based hardware interrupt fault-tolerant emergency control method and system

Abstract

This invention overcomes the shortcomings of uncontrollable hardware interrupts in existing general control architectures and provides a hardware interrupt fault-tolerant emergency control method and system based on a brain-like independent architecture. It simulates the brain and cerebellum division of labor logic in the human brain, realizes complete isolation between the emergency control link and hardware interrupts, and completes millisecond-level emergency takeover when the main processor is abnormal, eliminating the risk of equipment loss of control.

Description

Technical Field

[0001] This invention relates to the field of edge-side intelligent device security control technology, specifically targeting platforms such as drones, autonomous driving, and intelligent robots, and discloses a brain-like independent emergency control scheme to solve the risk of operational loss of control caused by hardware interruption preemption. Background Technology

[0002] Currently, edge devices such as drones, autonomous vehicles, and intelligent robots all use general-purpose processors paired with conventional operating systems to achieve overall control, which has fundamental technical defects: the hardware interrupt mechanism of general-purpose processors is uncontrollable, and peripherals, communications, and background tasks are prone to preempting core resources, resulting in delays, stuttering, or even failures in the execution of critical control instructions; existing solutions such as redundant control and watchdog restarts cannot escape the limitations of the general architecture of interrupt contention and resource conflicts, and cannot achieve complete isolation between emergency control and interruption risks. When the main processor malfunctions, the device is very easy to lose control, making it difficult to ensure operational safety. Summary of the Invention

[0003] Purpose of the invention This invention overcomes the shortcomings of uncontrollable hardware interrupts in existing general control architectures and provides a hardware interrupt fault-tolerant emergency control method and system based on a brain-like independent architecture. It simulates the brain and cerebellum division of labor logic in the human brain, realizes complete isolation between the emergency control link and hardware interrupts, and completes millisecond-level emergency takeover when the main processor is abnormal, eliminating the risk of equipment loss of control. Technical solution A hardware interrupt fault-tolerant emergency control method based on a neuromorphic independent architecture A dual-unit independent architecture is constructed, which is divided into a main processing unit and a dedicated emergency processing unit. The two are completely isolated in terms of physical, electrical and power supply. The dedicated emergency processing unit adopts a bare-metal operation mode without an operating system and without hardware interruption. The main processing unit is only responsible for routine decision-making, generating routine control commands and sending them to the dedicated emergency processing unit. It is not directly connected to the actuator and does not have direct control authority. A dedicated emergency response unit verifies the validity of routine commands, and outputs them to the actuator once the verification is successful. The dedicated emergency response unit monitors the equipment's operational risks in real time. If a danger is detected and no corresponding emergency instruction is received from the main processing unit within a preset time window, the abnormal instruction is immediately blocked, and the pre-stored default life-saving emergency instruction is directly output. During emergency execution, the dedicated emergency handling unit does not interfere with the internal operation of the main processing unit and does not disrupt the overall system stability. A hardware interrupt fault-tolerant emergency control system based on a neuromorphic independent architecture The system includes a main processing unit, a dedicated emergency response unit, an actuator module, and an independent power supply module; Main processing unit: Equipped with a conventional system, it performs conventional intelligent decision-making and command issuance, but has no direct control over the actuators; Dedicated emergency handling unit: It runs on a standalone microcontroller without an operating system or hardware interrupt response. It is fully electrically isolated from the main processing unit and is responsible for instruction verification, risk monitoring, unified instruction output, and emergency takeover. Actuator module: It only receives instructions from the dedicated emergency handling unit and has a single instruction input channel; Independent power supply module: Provides a separate power supply for the dedicated emergency response unit, achieving complete isolation of the power supply circuit. Beneficial effects Completely avoids the risk of interruption: The dedicated emergency handling unit is uninterrupted and system-free, and is completely unaffected by resource contention, thus eliminating control failures caused by hardware interruptions from the architecture. No conflict and no hidden dangers: The actuator has a single command input, eliminating command conflicts. Emergency actions are only conservative steady-state operations, with no risk of loss of control. Complete fault isolation: If the main processing unit crashes, freezes, or is attacked, it will not affect the operation of the emergency unit, and the fault will not spread. Excellent real-time performance: minimalist bare-metal logic, emergency response latency ≤5ms, achieving millisecond-level takeover; Low implementation cost: No need to modify the existing hardware architecture, it can be implemented with a low-cost microcontroller and is compatible with a variety of edge devices. Detailed Implementation Example 1: Emergency Control of Unmanned Aerial Vehicles During normal drone flight, the main processing unit sends flight commands to the dedicated emergency processing unit. After verification, the actuators are driven to fly normally. When the main processing unit experiences command delay due to hardware interruption, the dedicated emergency processing unit detects obstacle risks and immediately executes hovering and deceleration emergency commands. After the main processing unit recovers, it automatically switches back to the normal control mode. The entire process is free from interference and conflict. Example 2: Emergency Control for Automated Driving When the vehicle is driving normally, the road condition decision command from the main processing unit is executed after being verified by the dedicated emergency processing unit. If the main processing unit is interrupted, preempted, or stuck, and fails to issue a braking command, the dedicated emergency processing unit will directly execute deceleration and braking operations after detecting the risk, ensuring driving safety without affecting the subsequent control logic of the main processing unit.

Claims

1. A hardware interrupt fault-tolerant emergency control method based on a neuromorphic independent architecture, characterized in that, Includes the following steps: The main processing unit and the dedicated emergency processing unit are set up to be independent of each other. The two are completely isolated in terms of physical, electrical and power supply. The dedicated emergency processing unit has no operating system, no hardware interruption and runs bare. The main processing unit generates regular control commands and transmits them to the dedicated emergency processing unit, without directly controlling the actuators; A dedicated emergency response unit verifies the regular control commands and outputs them to the actuator once they pass the verification. The dedicated emergency response unit monitors the operational risks of the equipment. If a danger exists and no corresponding emergency instruction is received from the main processing unit within the preset time window, it directly outputs a default life-saving emergency instruction to the actuator without interfering with the operation of the main processing unit.

2. The method according to claim 1, characterized in that, The default emergency survival command is a conservative steady-state command such as deceleration, hovering, braking, and attitude maintenance.

3. The method according to claim 1, characterized in that, The actuator only receives a single command from the dedicated emergency response unit and has no other command input channels.

4. A hardware interrupt fault-tolerant emergency control system based on a neuromorphic independent architecture, characterized in that, Includes a main processing unit, a dedicated emergency processing unit, an actuator module, and an independent power supply module; The main processing unit is used to generate and issue regular control commands, but has no authority to directly control the actuator module. The dedicated emergency response unit is fully electrically isolated from the main processing unit, has no operating system or hardware interrupt response mechanism, and is responsible for instruction verification, risk monitoring and unified instruction output. The actuator module only receives control commands from the dedicated emergency response unit; The independent power supply module provides independent power to the dedicated emergency handling unit and is completely isolated from the power supply circuit of the main handling unit.

5. The system according to claim 4, characterized in that, The dedicated emergency response unit has a built-in default emergency command library that can be directly invoked and executed when the main processing unit's commands malfunction.

6. The system according to claim 4, characterized in that, In the event of a failure in the main processing unit, the dedicated emergency processing unit can independently perform emergency control, preventing the fault from spreading.