An in-chip transport convergence management module, a PCIe subsystem and a method for transmitting data

Abstract

This invention discloses an on-chip transmission aggregation management module, which is located at the HNP interface of a PCIe subsystem. The module includes an arbitration buffer, a buffer unit, and an arbitration arrangement module. The buffer unit includes several buffer FIFOs, whose inlets and outlets are connected to the arbitration buffer and the arbitration arrangement module, respectively. The arbitration buffer receives write requests from the HNP interface, buffers the write requests into an empty buffer FIFO, and binds the buffer FIFO to the ID of the write request until the last write request of that ID is stored in the buffer FIFO, while simultaneously marking the buffer FIFO as ready for data transmission. When the arbitration arrangement module is idle, it receives write requests from the buffer FIFO and reassembles the received write requests into data packets for transmission downstream. This invention also discloses the corresponding PCIe subsystem and a method for transmitting data. This invention aggregates split write requests with the same ID at the HNP interface of the PCIe subsystem, recombining several sub-data packets into a data packet for transmission, thereby improving PCIe data transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip design, and more particularly to data transmission via the HNP interface in a PCIe subsystem. Background Technology

[0002] In the PCIe architecture, PCIe devices are allowed to read and write to each other; this read / write operation between PCIe devices is called P2P (peer-to-peer) transfer. (Reference) Figure 1 In P2P transmission using an ARM-based CPU, the request packet originates from the EP terminal, passes through the corresponding RP (root port), and is forwarded by the RNI interface of the CMN interconnect bus to the corresponding HNP interface, and then forwarded to the destination EP terminal via the root port. Burst packets are split into multiple non-Burst packets when passing through the RNI interface of the CMN interconnect bus. These split write request packets then become multiple small non-Burst payload packets when passing through the subsequent HNP interface and the PCIe root port. Due to the overhead of the PCIe header protocol, the efficiency of transmitting multiple small packets is relatively low.

[0003] Therefore, a method is needed to solve the above problems. Summary of the Invention

[0004] The purpose of this invention is to provide an on-chip transmission aggregation management module and a PCIe subsystem to solve the problem of reduced PCIe data transmission efficiency caused by the splitting of a single burst data packet by the RNI interface of the CMN interconnect bus during P2P transmission in the PCIe architecture.

[0005] To achieve the above objectives, this invention provides an on-chip transmission convergence management module. The module is located at the HNP interface of a PCIe subsystem and includes an arbitration buffer, a buffer unit, and an arbitration arrangement module. The buffer unit includes several buffer FIFOs, with their inlets connected to the arbitration buffer and their outlets connected to the arbitration arrangement module. The arbitration buffer receives write requests from the HNP interface, each request including valid data and a sideband signal. It buffers the write request in an empty buffer FIFO and binds this buffer FIFO to the ID of the write request. When a subsequent write request is received with the ID, it stores the write request in the bound buffer FIFO until the sideband signal indicates that the write request is the last one. The buffer FIFO storing the last write request is then marked as having completed data preparation. When idle, the arbitration arrangement module receives write requests from the buffer FIFOs that have completed data preparation, reassembles the received write requests into data packets, and sends them downstream.

[0006] Preferably, after receiving a write request from a cached FIFO that has completed data preparation when the arbitration arrangement module is idle, it also unbinds the cached FIFO from the write request ID, so that the cached FIFO becomes empty and waits to cache the next newly arrived write request; or, after receiving a write request from a cached FIFO that has completed data preparation when the arbitration arrangement module is idle, the cached FIFO becomes empty, and when the arbitration buffer caches the write request into an empty cached FIFO, if the cached FIFO has an already bound write request ID, then the ID bound to the cached FIFO is updated to the write request ID that is about to be stored.

[0007] Preferably, the cache unit further includes a bypass FIFO, the entry of which is connected to the arbitration buffer and its exit is connected to the arbitration arrangement module. Specifically, when the arbitration buffer receives a write request, it determines whether the ID of the write request is bound to the cache FIFO. If bound, the write request is stored in the bound cache FIFO. If not bound, it determines whether there is a free cache FIFO. If there is a free cache FIFO, the write request is selected and stored in a free cache FIFO. If there is no free cache FIFO, the write request is stored in the bypass FIFO. This bypass FIFO can solve the problem of cached storage of write requests when the cache FIFO is insufficient.

[0008] When the arbitration arrangement module is idle, it receives write requests from the bypass FIFO before the buffer FIFO, in order to ensure the normal logical function of the on-chip transmission aggregation management module and prevent upstream congestion.

[0009] Specifically, the arbitration buffer determines whether the buffer FIFO is empty by using the empty signal of the buffer FIFO.

[0010] Specifically, the arbitration buffer marks the buffer FIFO as a readable state where data preparation is complete by setting the read signal of the buffer FIFO to 1.

[0011] This invention also provides a PCIe subsystem, including an RNI interface, an HNP interface, an on-chip transmission aggregation management module built into the HNP interface, and a root port. The RNI interface splits data packets into several sub-data packets and converts the sub-data packets into write requests with sideband signals. The HNP interface receives write requests. The on-chip transmission aggregation management module is the same as described above. The root port connects the RNI interface and the HNP interface to communicate with other EP terminals, serving as the upstream of the RNI interface and the downstream of the HNP interface.

[0012] Preferably, the HNP interface also allows for configuration register settings to select whether to repackage the write request into a data packet via the on-chip transmission aggregation management module and send it to the root port, or to bypass the on-chip transmission aggregation management module and directly send the write request to the root port. This allows for proactive selection of whether to bypass the on-chip transmission aggregation management module to adapt to the transmission requirements of different data packets.

[0013] Preferably, when the HNP interface receives the write request, it also receives the target address of the write request. When receiving the write request, the write data channel is first closed so that the write address channel receives the target address, and then the write data channel is opened to receive the write request, so as to prevent data loss due to abnormal timing.

[0014] This invention also provides a method for P2P data transmission in a PCIe subsystem. When data is transmitted between multiple PCIe subsystems, the PCIe subsystem is as described above. An initial PCIe subsystem receives a data packet from an EP terminal through a root port. The root port transmits the data packet to the RNI interface of the initial PCIe subsystem. The RNI interface splits the data packet into several sub-data packets and converts the sub-data packets into write requests with sideband signals. The write requests are transmitted to the target PCIe subsystem via the CMN interconnect bus. The HNP interface of the target PCIe subsystem receives the write requests and reassembles them into data packets through the on-chip transmission convergence management module before transmitting them to a root port in the same PCIe subsystem. The root port then transmits the reassembled data packets to the target EP terminal.

[0015] The CMN interconnect bus has several sets of connection interfaces. Each connection interface includes an RNI interface and an HNP interface. Each set of connection interfaces corresponds to a PCIe subsystem, so that the RNI interface of the connection interface is used to communicate with the RNI interface of the corresponding PCIe subsystem, and the HNP interface of the connection interface is used to communicate with the HNP interface of the corresponding PCIe subsystem.

[0016] Compared to existing technologies, this invention adds an on-chip transport aggregation management module at the HNP interface of the PCIe subsystem. The arbitration buffer of this on-chip transport aggregation management module arbitrates and stores the write requests from the received sub-data packet slots in a buffer FIFO according to corresponding rules: write requests with the same ID are stored in the same buffer FIFO to organize and cache the write requests received from the HNP interface according to their IDs. The arbitration sorting module of the on-chip transport aggregation management module reads the organized write requests, reorders them, and assembles them into a single data packet before sending it downstream. This restores several sub-data packets with the same ID that were split upstream of the HNP interface into a single data packet for transmission, reducing header protocol overhead and improving PCIe data transmission efficiency. Attached Figure Description

[0017] Figure 1 This is a transmission path diagram of P2P write request packets in the PCIe system.

[0018] Figure 2 This is a structural diagram of the on-chip transmission aggregation management module.

[0019] Figure 3 This is a structural diagram of cache unit 20. Detailed Implementation

[0020] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0021] For ease of understanding, this embodiment first provides a brief explanation of the English abbreviations used in this invention: PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. ARM (Advanced RISC Machine) is a low-power RISC microprocessor architecture. CMN (Coherent Mesh Network) is a high-performance, low-latency interconnect bus. RP (Root Port) is the interface connecting the root complex and PCIe devices in the PCIe architecture. EP (End Point) is a terminal device or component in the PCIe architecture. P2P (Peer to Peer) is peer-to-peer transmission, where one EP terminal device directly accesses another EP terminal device in the PCIe architecture. HNP (Home Node with PCIe optimization) is a PCIe-optimized IO-coherent master node in the CMN interconnect bus. RNI (Remote Node Interface) is the IO-coherent master node in the CMN interconnect bus. FIFO (First In First Out) is a standard hardware circuit storage module.

[0022] refer to Figure 2 , Figure 3 This embodiment provides an on-chip transmission convergence management module. The module is located at the HNP interface of the PCIe subsystem and includes an arbitration buffer (ARB buffer) 10, a cache unit 20, and an arbitration order module (ARB and Order) 30. The cache unit 20 includes a plurality of cache FIFOs 201. The inlets of the plurality of cache FIFOs 201 are connected to the arbitration buffer 10 and their outlets are connected to the arbitration order module 30.

[0023] In this embodiment, the arbitration buffer 10 receives a write request input from the HNP interface. The write request includes valid data and a sideband signal. The write request is cached in an empty buffer FIFO 201, and the buffer FIFO 201 is bound to the ID of the write request. When a write request sent by the ID is received subsequently, the write request is stored in the bound buffer FIFO 201 until the sideband signal determines that the write request is the last one. The buffer FIFO 201 storing the last write request is then marked as having completed data preparation. When the arbitration arrangement module 30 is idle, it receives the write requests in the buffer FIFO 201 that has completed data preparation, and reassembles the received write requests into data packets before sending them downstream.

[0024] In this embodiment, reference Figure 1 At the RNI interface, the Burst data packet is split into multiple sub-data packets and transmitted downstream. When idle, the arbitration arrangement module 30 receives the write request in the buffer FIFO 201 that has completed data preparation, and reassembles the received write request into a Burst data packet before sending it downstream.

[0025] Preferably, after receiving a write request from a prepared cache FIFO 201 when idle, the arbitration arrangement module 30 also unbinds the cache FIFO 201 from the write request ID, making the cache FIFO 201 idle and waiting to cache the next newly arrived write request; or, after receiving a write request from a prepared cache FIFO 201 when idle, the arbitration arrangement module 30 makes the cache FIFO 201 idle until the next write request is stored, at which point the arbitration buffer 10 updates the ID bound to the cache FIFO 201 to the write request ID to be stored. A cache FIFO 201 can only be bound to one write request ID and caches subsequent write requests with the same ID.

[0026] In this embodiment, a WUSER signal is added to the sideband signal at the RNI interface to transmit the WLAST signal through the WUSER signal. This ensures that even if a data packet is split into multiple sub-data packets at the RNI interface, the HNP interface can still determine whether the write request is the last of the split write requests through the WUSER signal. When a specific bit of the WUSER signal for a write request stored in the buffer FIFO 201 is 0, it indicates that the write request is not the last of the split write requests for the corresponding ID, and the last write request has not yet arrived. When a specific bit of the WUSER signal for a write request stored in the buffer FIFO 201 is 1, it indicates that the write request is the last split write request for the corresponding ID. At this time, the arbitration buffer 10 marks the buffer FIFO 201 as ready for reading by setting the read signal (ready signal) of the buffer FIFO 201 to 1.

[0027] refer to Figure 3 In this embodiment, the buffer unit 20 further includes a bypass FIFO 202, the inlet of which is connected to the arbitration buffer 10 and the outlet of which is connected to the arbitration arrangement module 30.

[0028] Specifically, when the arbitration buffer 10 receives a write request, it first determines whether the ID of the write request is bound to the cache FIFO 201. If it is bound, the write request is stored in the bound cache FIFO 201. If it is not bound, it determines whether there is a spare cache FIFO 201. If there is a spare, the write request is stored in a spare cache FIFO 201. If there is no spare, the write request is stored in the bypass FIFO 202.

[0029] When the arbitration arrangement module 30 is idle, it takes priority over the buffer FIFO 201 to receive the write request of the bypass FIFO 202, so as to ensure the normal logical function of the on-chip transmission aggregation management module and prevent upstream congestion.

[0030] In this embodiment, the arbitration buffer 10 determines whether the cache FIFO 201 is in an empty state by using the empty signal of the cache FIFO 201. When the empty signal of the cache FIFO 201 is 1, it indicates that there is a write request stored in the current cache FIFO 201, which is a non-empty state; when the empty signal of the cache FIFO 201 is 0, it indicates that there is no write request stored in the current cache FIFO 201, which is an empty state.

[0031] refer to Figure 1This embodiment also discloses a PCIe subsystem, including an RNI interface, an HNP interface, an on-chip transmission aggregation management module built into the HNP interface, and a root port (RP).

[0032] The RNI interface splits the Burst data packet into several sub-data packets and converts the sub-data packets into write request outputs with sideband signals; the HNP interface is used to receive write requests; the on-chip transmission aggregation management module is the on-chip transmission aggregation management module mentioned above; the root port connects the RNI interface and the HNP interface to communicate with other EP terminals, serving as the upstream of the RNI interface and the downstream of the HNP interface.

[0033] Preferably, the HNP interface also allows for configuration register settings to select whether to repackage the write request into a data packet via the on-chip transmission aggregation management module and send it to the root port, or to bypass the on-chip transmission aggregation management module and directly send the write request to the root port. This allows for proactive selection of whether to bypass the on-chip transmission aggregation management module to adapt to the transmission requirements of different data packets.

[0034] In this embodiment, when the HNP interface receives the write request, it also receives the target address of the write request. Upon receiving the request, the write data channel is first closed to allow the write address channel to receive the target address, and then the write data channel is opened to receive the write request. When valid data arrives first, the WREADY signal is pulled low to 0 to reject data reception. The WREADY signal is then pulled high to 1 after the AWVALID signal is received to begin receiving valid data, thus preventing data loss due to abnormal timing.

[0035] This embodiment also discloses a method for P2P data transmission in a PCIe subsystem. When data is transmitted between multiple PCIe subsystems, the PCIe subsystem is the PCIe subsystem described above. The initial PCIe subsystem receives a data packet from an EP terminal through a root port. The root port transmits the data packet to the RNI interface of the initial PCIe subsystem. The RNI interface splits the data packet into several sub-data packets and converts the sub-data packets into write requests with sideband signals. The write requests are transmitted to the target PCIe subsystem through the CMN interconnect bus. The HNP interface of the target PCIe subsystem receives the write requests and reassembles them into data packets through the on-chip transmission convergence management module before transmitting them to a root port in the same PCIe subsystem. The root port transmits the reassembled data packets to the target EP terminal.

[0036] The data packets that are split and reassembled are all Burst data packets.

[0037] refer to Figure 1 In this embodiment, the CMN interconnect bus has several sets of connection interfaces. Each connection interface includes an RNI interface and an HNP interface. Each set of connection interfaces corresponds to a PCIe subsystem, so that the RNI interface of the connection interface is used to communicate with the RNI interface of the corresponding PCIe subsystem, and the HNP interface of the connection interface is used to communicate with the HNP interface of the corresponding PCIe subsystem.

[0038] Compared with existing technologies, this invention adds an on-chip transmission convergence management module at the HNP interface of the PCIe subsystem. This module includes an arbitration buffer 10, a buffer unit 20, and an arbitration arrangement module 30. The buffer unit 20 includes several buffer FIFOs 201 and a bypass FIFO 202. The arbitration buffer 30 stores write requests with the same ID into the same buffer FIFO 201 according to corresponding rules. The arbitration arrangement module 30 reads data from the prepared buffer FIFO 2010 and reassembles it into a single data packet before sending it downstream. This restores several sub-data packets with the same ID that were split at the RNI interface into a single data packet for transmission, reducing header protocol overhead and improving PCIe data transmission efficiency. Furthermore, the HNP interface can actively choose whether to bypass the on-chip transmission convergence management module through configuration registers to adapt to the transmission requirements of different data packets.

[0039] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. An on-chip transmission aggregation management module, characterized in that: Located at the HNP interface of the PCIe subsystem, it includes an arbitration buffer, a cache unit, and an arbitration arrangement module. The cache unit includes several cache FIFOs, the entrances of which are connected to the arbitration buffer and the exits of which are connected to the arbitration arrangement module. The arbitration buffer receives a write request input from the HNP interface. The write request includes valid data and a sideband signal. The write request is cached in an empty buffer FIFO and bound to the ID of the write request. When a write request sent by the ID is received later, the write request is stored in the bound buffer FIFO until the sideband signal determines that the write request is the last one. The buffer FIFO storing the last write request is then marked as having completed data preparation. When idle, the arbitration arrangement module receives write requests from the buffer FIFO that has completed data preparation, and reassembles the received write requests into data packets before sending them downstream.

2. The on-chip transmission aggregation management module as described in claim 1, characterized in that: When the arbitration buffer marks the cache FIFO storing the last write request as having completed data preparation, it also unbinds the cache FIFO from the write request ID; or, when the arbitration buffer caches the write request into an empty cache FIFO, if the cache FIFO has an already bound write request ID, it updates the ID bound to the cache FIFO to the write request ID that is about to be stored.

3. The on-chip transmission aggregation management module as described in claim 2, characterized in that: The buffer unit also includes a bypass FIFO, the entry of which is connected to the arbitration buffer and its exit is connected to the arbitration arrangement module; When the arbitration buffer receives a write request, it determines whether the ID of the write request is bound to the cache FIFO. If it is bound, the write request is stored in the bound cache FIFO. If it is not bound, it determines whether there is a spare cache FIFO. If there is a spare, the write request is selected to be stored in a spare cache FIFO. If there is no spare, the write request is stored in the bypass FIFO. When the arbitration arrangement module is idle, it takes priority over the cache FIFO in receiving write requests from the bypass FIFO.

4. The on-chip transmission aggregation management module as described in claim 3, characterized in that: The arbitration buffer determines whether the buffer FIFO is empty by using the empty signal of the buffer FIFO.

5. The on-chip transmission aggregation management module as described in claim 1, characterized in that: The arbitration buffer marks the buffer FIFO as a readable state where data preparation is complete by setting the read signal of the buffer FIFO to 1.

6. A PCIe subsystem, characterized in that: This includes an RNI interface, an HNP interface, an on-chip transmission aggregation management module built into the HNP interface, and a root port; The RNI interface splits data packets into several sub-data packets and converts the sub-data packets into write request outputs with sideband signals; The HNP interface is used to receive write requests, and the on-chip transmission aggregation management module is the on-chip transmission aggregation management module as described in any one of claims 1-3; The root port connects the RNI interface and the HNP interface for communication with other EP terminals, serving as the upstream of the RNI interface and the downstream of the HNP interface.

7. The PCIe subsystem as described in claim 6, characterized in that: The HNP interface also allows for the selection, via a configuration register, of either repackaging the write request into a data packet and sending it to the root port through the on-chip transmission aggregation management module, or bypassing the on-chip transmission aggregation management module and directly sending the write request to the root port.

8. The PCIe subsystem as described in claim 6, characterized in that: When the HNP interface receives the write request, it also receives the target address of the write request. When receiving the write request, it first closes the write data channel so that the write address channel receives the target address, and then opens the write data channel to receive the write request.

9. A method for P2P data transmission in a PCIe subsystem, characterized in that: Data is transmitted between multiple PCIe subsystems, wherein the PCIe subsystem is as described in claim 5. An initial PCIe subsystem receives a data packet from an EP terminal through a root port within it. The root port transmits the data packet to the RNI interface of the initial PCIe subsystem. The RNI interface splits the data packet into several sub-data packets and converts the sub-data packets into write requests with sideband signals. The write requests are transmitted to the target PCIe subsystem via the CMN interconnect bus. The HNP interface of the target PCIe subsystem receives the write requests and reassembles them into data packets through the on-chip transmission convergence management module before transmitting them to a root port in the same PCIe subsystem. The root port then transmits the reassembled data packets to the target EP terminal.

10. The P2P data transmission method as described in claim 9, characterized in that: The CMN interconnect bus has several sets of connection interfaces. Each connection interface includes an RNI interface and an HNP interface. Each set of connection interfaces corresponds to a PCIe subsystem, so that the RNI interface of the connection interface is used to communicate with the RNI interface of the corresponding PCIe subsystem, and the HNP interface of the connection interface is used to communicate with the HNP interface of the corresponding PCIe subsystem.

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