Method, device and apparatus for leakage optimization of integrated circuit, and computer readable storage medium

By identifying and restoring low-leakage cells in timing violation paths during integrated circuit design, the problem of timing inconsistencies in integrated circuit design is solved, achieving efficient leakage optimization and static power consumption reduction.

CN122287504APending Publication Date: 2026-06-26LOONGSON TECH CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
LOONGSON TECH CORP
Filing Date
2026-03-13
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

During the approval stage of integrated circuit design, existing technologies suffer from timing inconsistencies in leakage current optimization, leading to timing violations. Furthermore, the increased number of iterations results in excessively long optimization times, impacting the efficiency of leakage current optimization.

Method used

By acquiring the topology information of the integrated circuit, timing violation paths are identified, and high-leakage circuit cells are replaced with low-leakage cells. After identifying timing violation paths, they are restored to high-leakage cells. Timing convergence is performed first to ensure that the design file meets the timing convergence conditions.

Benefits of technology

This approach achieves reduced static power consumption while satisfying timing convergence, improves the efficiency of leakage current optimization, reduces the number of iterations, and ensures the normal operation of the integrated circuit.

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Abstract

This invention provides a method, apparatus, electronic device, and computer-readable storage medium for optimizing leakage current in integrated circuits. The method involves: acquiring topology information during the approval stage of the integrated circuit to be processed; based on the topology information, replacing high-leakage circuit units in at least a portion of multiple circuit paths with low-leakage circuit units to obtain replaced topology information; based on the replaced topology information, identifying timing violation paths in the multiple circuit paths, where the simulation parameters of the circuit path meet preset timing violation conditions; and restoring at least a portion of the replaced low-leakage circuit units in the timing violation paths to high-leakage circuit units. This method can effectively reduce the processing pressure during timing approval repair and accelerate the timing repair speed; it also allows for multi-round iterations directly using the approval tool to achieve efficient timing convergence.
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