Data buffer circuit of distributed convolutional neural network accelerator
By dividing the storage space into a primary storage module and a secondary storage module, and only monitoring the current data reception progress and the status of the secondary storage module, the problem of excessive area and power consumption of traditional buffer circuits is solved, achieving efficient data buffering and rearrangement, and improving data throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-26
AI Technical Summary
Traditional buffer circuits need to monitor the data status of the entire storage space when buffering out-of-order input data, resulting in excessive circuit area and power consumption, and cannot effectively solve the problem of out-of-order data in inter-core communication.
The data buffer circuit of the distributed convolutional neural network accelerator is used to divide the storage space into a main storage module and a secondary storage module. The main storage module is responsible for basic read and write operations, while the secondary storage module is responsible for the temporary storage and rearrangement of out-of-order data. The completeness of the data required for convolution is determined by monitoring the current data reception progress and the data status of the secondary storage module.
This reduces the use of registers, lowers circuit area and power consumption, and allows full utilization of the bandwidth of multiple single-port SRAMs when reading data, greatly improving data throughput.
Smart Images
Figure CN122287733A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital integrated circuit technology, and in particular to a data buffer circuit for a distributed convolutional neural network accelerator. Background Technology
[0002] Convolutional Neural Networks (CNNs) are neural network models specifically designed for processing network-structured data (such as images). Their core is the convolutional layer. Convolutional layers use weighted kernels to scan the entire input feature data, extracting local features (such as edges and textures) while significantly reducing the number of parameters, thus preserving key feature information. After multiple convolutions, the feature data is typically input into fully connected layers to perform tasks such as classification and detection. Compared to traditional multi-layer neural network models, CNNs can better capture the spatial relationships inherent in the input data and are widely used in image recognition, object detection, semantic segmentation, and other fields, making them a fundamental neural network model.
[0003] However, convolutional neural networks (CNNs) are characterized by high parallelism and large computational demands, which places significant demands on computing power. As Moore's Law approaches its physical limits, the rate of increase in single-core computing power is slowing down, leading to a growing computing power gap. Consequently, many-core systems have become a research hotspot. In many-core systems, inter-core communication is a crucial issue, typically addressed using on-chip networks (BTCs). While BTCs solve the communication problem between many cores, they also introduce new challenges: the timing of information transmission on BTCs cannot be guaranteed to be accurate. Therefore, data buffering and monitoring of data reception are necessary to facilitate subsequent high-parallel computation by the cores attached to the nodes.
[0004] Traditional buffer circuits, in order to buffer out-of-order input data, need to monitor the data state of the entire memory space, which in turn requires registers commensurate with the number of memory spaces, such as... Figure 1 As shown, the circuit area and power consumption are therefore large. Summary of the Invention
[0005] The purpose of this invention is to provide a data buffer circuit for a distributed convolutional neural network accelerator to solve the problems in the background art.
[0006] To address the aforementioned technical problems, this invention provides a data buffer circuit for a distributed convolutional neural network accelerator, comprising: a data collection and distribution control module, a main storage module, and a secondary storage module; The data collection and distribution control module is connected to the main storage module and the secondary storage module. The main storage module is connected to the secondary storage module. Input data enters from the data collection and distribution control module, and output data is output from the main storage module. The data buffer circuit divides the storage space into a main storage module and a secondary storage module. The main storage module does not need to monitor the data status and is only responsible for basic data reading and writing. The secondary storage module is responsible for the temporary storage and rearrangement of out-of-order data and needs to monitor the data status. The completeness of the data required for convolution is determined only by monitoring the current data receiving progress and the data status of the secondary storage module.
[0007] In one implementation, the data collection and distribution control module needs to configure the horizontal coordinate boundary w_edge and the vertical coordinate boundary h_edge of the storage space, as well as the channel depth c_depth; input data enters from the data collection and distribution control module, and the input data includes horizontal coordinate address information, vertical coordinate address information, channel information and data body information, wherein the bit width of the horizontal coordinate address, vertical coordinate address and channel information is selected according to actual needs, and the bit width of the data body information is m / 4 bits.
[0008] In one implementation, the data collection and distribution control module includes an hpos register and a collect register; The hpos register is used to indicate the address currently being written to the main memory module. Its default value is 0. The value of the hpos register consists of a horizontal coordinate and a vertical coordinate. After the address data represented by this register has been collected, the value of the hpos register is updated. The update rules are as follows: if the horizontal coordinate is not equal to w_edge, the horizontal coordinate is incremented by one, and the vertical coordinate remains unchanged; if the horizontal coordinate is equal to w_edge but the vertical coordinate is not equal to h_edge, the horizontal coordinate is reset to zero, and the vertical coordinate is incremented by one; if the horizontal coordinate is equal to w_edge and the vertical coordinate is equal to h_edge, both the horizontal and vertical coordinates are reset to zero. Whenever data is written to the address pointed to by the hpos register in the main storage module, the corresponding bit of the collect register is set to one, indicating that the data for this channel has been collected. When the required channel information has been collected, the value of the corresponding bit in the collect register is high, indicating that all channel data at the current address has been collected, an update is initiated, and the value of the collect register is set back to zero.
[0009] In one implementation, the data collection and distribution control module selects different data flow directions based on data input, secondary storage module output port status, and external module data requests, with the specific rules as follows: If an external read data request is initiated, the main storage module will execute the read data request, and the external input data will be written to the secondary storage module. If no external read data request is initiated, the output port of the secondary storage module will have no data. Then, based on the comparison between the address information of the input data and the hpos register, if they are the same, the external data will be written to the main storage module; if they are different, it will be written to the secondary storage space. If there is no external read data request and there is data at the output port of the secondary storage module, then the output data of the secondary storage module will be written into the primary storage module. If there is external data input at this time, then the external input data will be written into the secondary storage module.
[0010] In one implementation, the main storage module is composed of k×j blocks of single-port SRAM with a width of m bits and a depth of n, forming a storage space with a width of k×m and a depth of n×j. It has basic read and write ports, and can write or read a maximum of k×m bits of data in a single cycle. The depth n×j is equal to the maximum horizontal coordinate boundary multiplied by the maximum vertical coordinate boundary. The read and write control signals for different bits are independent of each other. k, j, m, and n are integers not less than 1.
[0011] In one implementation, the secondary storage module consists of a single-port SRAM with a width of m bits and a depth of n, an address directory table register, a selected address pointer, and a synchronous FIFO with a width of m / 4 + log2(c_depth) and a depth of cnum. The address directory table register consists of 4n sets of registers, each set of registers consisting of a valid bit slot_vld, an address slot_addr, and channel information slot_caddr, and each set of registers corresponds one-to-one with the address of the single-port SRAM. The selected address pointer points to the address of the SRAM currently being read or written, and has a width of log2(n) bits. The input data has a bit width of m / 4. Each address in the single-port SRAM stores 4 input data. Data entering the secondary storage module is first written to the single-port SRAM, and at the same time, the corresponding register value in the address directory table register is updated, the valid bit is pulled high, and the new address and channel information are written. Data is read from the single-port SRAM, the valid bit in the address directory table register is set to zero, and then written to the FIFO along with the corresponding channel information. The output of the FIFO is the output port of the secondary storage module.
[0012] In one implementation, the selected address pointer of the secondary storage module has the characteristic of preferentially pointing to the address that is read and written simultaneously. When there is no address that meets the requirements for simultaneous reading and writing, it points to the address that meets the requirements for reading or writing according to the needs of reading or writing.
[0013] This invention provides a data buffer circuit for a distributed convolutional neural network accelerator. It buffers and rearranges out-of-order input data with minimal circuit overhead. It determines the completeness of the data required for convolution by monitoring the current data reception progress and the data status of the secondary storage module, eliminating the need to monitor the data status of all storage spaces. This saves significant register usage and reduces circuit power consumption and area. Furthermore, when reading data, it fully utilizes the bandwidth of multiple single-port SRAMs, reading valid data from all channels in a single cycle, greatly improving data throughput. While designed for data buffering in distributed convolutional neural network hardware accelerators, this circuit design is versatile and widely applicable to situations where the input data is out of order but requires reading partial data from specific locations. Attached Figure Description
[0014] Figure 1 This is a block diagram of a traditional buffer circuit.
[0015] Figure 2 This is a circuit structure block diagram provided by the present invention.
[0016] Figure 3 These are two data flow diagrams present in the circuit provided by this invention.
[0017] Figure 4 This invention provides a conditional branch diagram and a partial signal truth table for the selected address pointer in the secondary storage module. Detailed Implementation
[0018] The data buffer circuit of a distributed convolutional neural network accelerator proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0019] This invention provides a data buffering circuit for a distributed convolutional neural network accelerator, suitable for various scenarios that require buffering of input data and confirmation of data reception progress. It can automatically determine the data reception status with minimal hardware cost, facilitating subsequent circuits to perform the next calculation, without requiring a host computer to determine the status, making it suitable for distributed application scenarios.
[0020] like Figure 2As shown, the circuit provided by this invention divides the storage space into two parts: a main storage module and a secondary storage module. The main storage module does not need to monitor the data status and is only responsible for basic data reading and writing. The secondary storage module is responsible for the temporary storage and rearrangement of out-of-order data and needs to monitor the data status. Because the data size of the secondary storage module is much smaller than that of the main storage module, the number of registers required is much smaller than that required in traditional circuits that monitor all data states, thereby reducing the circuit area and power consumption. Because the storage space is divided into two parts, there are also two data flow paths, such as... Figure 3 As shown.
[0021] The circuit of this invention includes: a data collection and distribution control module, a main storage module, and a secondary storage module. The main storage module is mainly used to store data and is also the final data read port. The main storage module is composed of k×j blocks of single-port SRAM with a width of m bits and a depth of n, forming a storage space with a width of k×m and a depth of n×j. It has basic read and write ports, and can write or read a maximum of k×m bits of data in a single cycle. The depth n×j is equal to the product of the maximum horizontal coordinate boundary and the maximum vertical coordinate boundary.
[0022] The data collection and distribution control module receives input data and controls the direction of the data flow; it is the module through which input data enters. This module requires configuration of the horizontal coordinate boundary (w_edge) and vertical coordinate boundary (h_edge) of the storage space, as well as the channel depth (c_depth). Input data enters through this module and must include horizontal coordinate address information, vertical coordinate address information, channel information, and data body information. The bit width of the address (including both horizontal and vertical coordinates) and channel information is selected according to actual needs, while the data body information has a bit width of m / 4 bits. The data collection and distribution control module includes an hpos register, which indicates the address that can currently be written to the main storage module. The default value is 0, and the value of the hpos register consists of the horizontal and vertical coordinate addresses. After data collection at the address represented by this register is complete, the value of the hpos register is updated. The update rules are as follows: If the x-coordinate is not equal to w_edge, then the x-coordinate increments by one, while the y-coordinate remains unchanged; if the x-coordinate is equal to w_edge but the y-coordinate is not equal to h_edge, then the x-coordinate is reset to zero, and the y-coordinate increments by one; if the x-coordinate is equal to w_edge and the y-coordinate is equal to h_edge, then both the x-coordinate and y-coordinate are reset to zero. The hpos register will be output as a signal from this module for other modules to listen to.
[0023] The update timing is determined by the actual data address written to the main memory module. An update is initiated when the address pointed to by the hpos register has been filled with data from all channels at that address. The mechanism for monitoring channel data collection is as follows: There is a collect register with a maximum bit width of c_depth, which defaults to 0. Whenever data is written to the address pointed to by the hpos register in the main memory module, one bit of the corresponding channel in the collect register is set to 1, indicating that the data for that channel has been collected. When the required channel information has been collected, the values at the corresponding bits of the collect register are all high, indicating that all channel data at the current address has been collected, an update is initiated, and the value of the collect register is reset to zero.
[0024] After receiving input data, the data collection and distribution control module compares the address information with the hpos register. Based on the comparison result, and considering whether an external read data request has been initiated and the validity of the output data from the secondary storage module, the data stream is selected. The specific rules are as follows: (1) If an external read data request is initiated, the read data request will be responded to first and a read data request will be initiated to the main storage module; if there is external input data at this time, the input data will be written to the secondary storage module, and the output data of the secondary storage module will not be responded to even if it is valid. (2) If there is no external read data request, the output data of the secondary storage module is invalid. Then, based on the comparison result between the address information of the input data and the hpos register, if they are the same, the data is written into the main storage module according to the address information; if they are different, the data is written into the secondary storage module. (3) If there is no external data read request and the output data of the secondary storage module is valid, then the secondary storage module will be responded to, the output data of the secondary storage module will be written into the primary storage module, and the secondary storage module will be informed that the data has been read. If there is external data input at this time, the external input data will be written into the secondary storage module.
[0025] The secondary storage module is primarily used to cache data that cannot be written to the main storage module temporarily, allowing the data to be written to the main storage module at the appropriate time. This secondary storage module also needs to monitor the value of the hpos register. It consists of a single-port SRAM with a width of m bits and a depth of n, an address directory table register, a selected address pointer, and a synchronous FIFO with a width of m / 4 + log2(c_depth) and a depth of cnum. The address directory table register consists of 4n register groups, each containing a valid bit slot_vld, an address slot_addr, and channel information slot_caddr. Each register group corresponds one-to-one with the address of the single-port SRAM. The selected address pointer points to the address of the SRAM currently being read / written, and has a width of log2(n) bits. The FIFO depth cnum is not critical; a smaller value can be chosen to make the data read timing more compact.
[0026] The input data has a bit width of m / 4, and each address in the single-port SRAM can store 4 input data. Data entering the secondary storage module is first written to the single-port SRAM, and simultaneously the corresponding register value in the address directory table register is updated, the valid bit is pulled high, and the new address and channel information are written. In some cases, data is read from the single-port SRAM, the valid bit in the address directory table register is set to zero, and then written to the FIFO along with the corresponding channel information, as will be described in detail in the rules below. The output of the FIFO is the output port of the secondary storage module.
[0027] The read / write address and read / write control of a single-port SRAM are determined by the address directory table register, hpos register, and collect register, according to the following rules: (1) There is an hpos_compare signal. When slot_vld is high and the input address is the same as the corresponding slot_addr, the hpos_compare signal is high. Otherwise, it is low. The bit width of the hpos_compare signal is 4n. (2) The four groups of slot_vld, slot_addr, slot_caddr and hpos_compare signals corresponding to each row address of the single-port SRAM are regarded as a whole. Each row address also has a line_nfull signal, a line_nempty signal, a line_hval signal and a line_nfull_nempty signal. When there is a logical value of zero in the four slot_vld signals, line_nfull is pulled high, otherwise it is pulled low. When there is a logical value of one in the four slot_vld signals, line_empty is pulled high, otherwise it is pulled low. When the hpos_compare signal is logically one in the four groups of signals, line_hval is pulled high. The line_nfull_nempty signal is the result of ANDing the line_nfull signal and the line_nempty signal. And so on, each row address has the above signals, so the bit width of the above line_nfull signal, line_nempty signal, line_hval signal and line_nfull_nempty signal is n. (3) When there is input data, if all the line_nfull_nempty signals are zero, then the selected address pointer is equal to the value of the line_nfull signal after passing through the priority decoder, line_nfull_dec signal; if the line_nfull_nempty signals are not all zero, then the selected address pointer is equal to the value of the line_nfull_nempty signal after passing through the priority decoder, line_nfull_nempty_dec signal; when there is no input data, the selected address pointer is equal to the value of the line_hval signal after passing through the priority decoder, line_hval_dec signal. (4) When no data is written to the secondary storage module, the selected address pointer is equal to the line_hval_dec signal. This address contains data that can be written to the main storage module. Then, according to the four corresponding hpos_compare signals, the lowest logical bit is selected for the read operation. The corresponding m / 4 bit width control signal is set to the read state, and the data is read out and written to the FIFO along with the corresponding channel information. The corresponding slot_vld signal is set low. When data is written to the secondary storage module, if the line_nfull_nempty signal is not all zero, the selected address pointer is equal to the line_nfull_nempty_dec signal. This address contains space that can be written to, and there is also data that has been written and can be written to the main storage module. It should be noted that the read and write control signals of SRAM can independently control read and write in different bit widths. Therefore, read and write operations can coexist for the same address. At this time, a write operation will definitely occur, and a read operation may occur. Based on the four slot_vld signals corresponding to this address, the corresponding m / 4-bit width control signal is set to write mode, data is written to SRAM, and the slot_vld signal is pulled high, updating the slot_addr and slot_caddr signals. Based on the hpos_compare signal, if logic 1 exists, the corresponding m / 4-bit width control signal is set to read mode, data is read out and written to the FIFO along with the corresponding slot_caddr channel information, and the corresponding slot_vld signal is set low. When data is written to the secondary storage module, if the line_nfull_nempty signals are all zero, the selected address pointer equals the line_nfull_dec signal. At this time, only the write process exists. Based on the four slot_vld signals corresponding to this address, the corresponding m / 4-bit width control signal is set to write mode, data is written to SRAM, and the slot_vld signal is pulled high, updating the slot_addr and slot_caddr signals. Figure 4 As shown.
[0028] In a practical circuit design, such as Figure 2 As shown, the main storage module is composed of 16 single-port SRAMs with a bit width of 256 bits and a depth of 12, forming a final storage space with a bit width of 512 bits and a depth of 96. The read and write control of the single-port SRAMs with different bit widths is independent of each other. The maximum horizontal boundary of the storage space represented by the main storage module is 32, and the maximum vertical boundary is 3.
[0029] The data collection and distribution control module needs to configure the horizontal axis boundary w_edge and vertical axis boundary h_edge of the actual storage space, as well as the channel depth c_depth, during operation. The hpos register has a width of 10 bits, the collect register has a width of 8 bits, and the input data width per cycle is 64 bits. The secondary storage module consists of a single-port SRAM with a width of 256 bits and a depth of 12, consistent with the SRAM specifications used in the main storage module. The address directory table register has 48 groups, including a 1-bit valid bit slot_vld, a 10-bit address slot_addr, and a 3-bit channel information slot_caddr. The selected address pointer has a width of 4 bits, and the synchronous FIFO used has a width of 67 bits and a depth of 4.
[0030] When data enters the data collection and distribution control module, if it differs from the hpos register, the data will enter the secondary storage module; otherwise, it will enter the primary storage module. During idle periods in the primary storage module, when there is no read / write activity, the output data from the secondary storage module will be written to the primary storage module. Each time data is written to the primary storage module, the collect register will update its status to indicate that new data has been collected. The hpos and collect registers are output for monitoring by subsequent modules. These two signals allow subsequent modules to know the current data collection status and determine whether data can be read, eliminating the need for frequent read / write requests.
[0031] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A data buffer circuit of a distributed convolutional neural network accelerator, characterized in that, include: Data collection and distribution control module, main storage module, secondary storage module; The data collection and distribution control module is connected to the main storage module and the secondary storage module. The main storage module is connected to the secondary storage module. Input data enters from the data collection and distribution control module, and output data is output from the main storage module. The data buffer circuit divides the storage space into a main storage module and a secondary storage module. The main storage module does not need to monitor the data status and is only responsible for basic data reading and writing. The secondary storage module is responsible for the temporary storage and rearrangement of out-of-order data and needs to monitor the data status. The completeness of the data required for convolution is determined only by monitoring the current data receiving progress and the data status of the secondary storage module.
2. The data buffer circuit of the distributed convolutional neural network accelerator of claim 1, wherein, The data collection and distribution control module needs to configure the horizontal coordinate boundary w_edge and the vertical coordinate boundary h_edge of the storage space, as well as the channel depth c_depth. Input data enters from the data collection and distribution control module and includes horizontal coordinate address information, vertical coordinate address information, channel information, and data body information. The bit width of the horizontal coordinate address, vertical coordinate address, and channel information is selected according to actual needs, and the bit width of the data body information is m / 4 bits.
3. The data buffer circuit of the distributed convolutional neural network accelerator of claim 2, wherein, The data collection and distribution control module includes an hpos register and a collect register; The hpos register is used to indicate the address currently being written to the main memory module. Its default value is 0. The value of the hpos register consists of a horizontal coordinate and a vertical coordinate. After the address data represented by this register has been collected, the value of the hpos register is updated. The update rules are as follows: if the horizontal coordinate is not equal to w_edge, the horizontal coordinate is incremented by one, and the vertical coordinate remains unchanged; if the horizontal coordinate is equal to w_edge but the vertical coordinate is not equal to h_edge, the horizontal coordinate is reset to zero, and the vertical coordinate is incremented by one; if the horizontal coordinate is equal to w_edge and the vertical coordinate is equal to h_edge, both the horizontal and vertical coordinates are reset to zero. Whenever data is written to the address pointed to by the hpos register in the main storage module, the corresponding bit of the collect register is set to one, indicating that the data for this channel has been collected. When the required channel information has been collected, the value of the corresponding bit in the collect register is high, indicating that all channel data at the current address has been collected, an update is initiated, and the value of the collect register is set back to zero.
4. The data buffer circuit of the distributed convolutional neural network accelerator of claim 3, wherein, The data collection and distribution control module selects different data flow directions based on data input, secondary storage module output port status, and external module data requests. The specific rules are as follows: If an external read data request is initiated, the main storage module will execute the read data request, and the external input data will be written to the secondary storage module. If no external read data request is initiated, the output port of the secondary storage module will have no data. Then, based on the comparison between the address information of the input data and the hpos register, if they are the same, the external data will be written to the main storage module; if they are different, it will be written to the secondary storage space. If there is no external read data request and there is data at the output port of the secondary storage module, then the output data of the secondary storage module will be written into the primary storage module. If there is external data input at this time, then the external input data will be written into the secondary storage module.
5. The data buffer circuit of the distributed convolutional neural network accelerator of claim 4, wherein, The main storage module is composed of k×j blocks of single-port SRAM with a width of m bits and a depth of n, forming a storage space with a width of k×m and a depth of n×j. It has basic read and write ports, and can write or read a maximum of k×m bits of data in a single cycle. The depth n×j is equal to the maximum horizontal coordinate boundary multiplied by the maximum vertical coordinate boundary. The read and write control signals for different bits are independent of each other. k, j, m, and n are integers not less than 1.
6. The data buffer circuit of the distributed convolutional neural network accelerator of claim 5, wherein, The secondary storage module consists of a single-port SRAM with a width of m bits and a depth of n, an address directory table register, a selected address pointer, and a synchronous FIFO with a width of m / 4 + log2(c_depth) and a depth of cnum. The address directory table register consists of 4n sets of registers, each set of registers consisting of a valid bit slot_vld, an address slot_addr, and channel information slot_caddr. Each set of registers corresponds one-to-one with the address of the single-port SRAM. The selected address pointer points to the address of the SRAM currently being read or written, and has a width of log2(n) bits. The input data has a bit width of m / 4. Each address in the single-port SRAM stores 4 input data. Data entering the secondary storage module is first written to the single-port SRAM, and at the same time, the corresponding register value in the address directory table register is updated, the valid bit is pulled high, and the new address and channel information are written. Data is read from the single-port SRAM, the valid bit in the address directory table register is set to zero, and then written to the FIFO along with the corresponding channel information. The output of the FIFO is the output port of the secondary storage module.
7. The data buffer circuit of the distributed convolutional neural network accelerator of claim 6, wherein, The selected address pointer of the secondary storage module has the characteristic of prioritizing the address to be read and written simultaneously. When there is no address that meets the requirements for simultaneous reading and writing, it points to the address that meets the requirements for reading or writing.