Display device and display system

Abstract

This invention provides a display device and a display system. The display device according to an embodiment of this disclosure includes: a display panel; and a pancake lens disposed on the display panel, the pancake lens comprising: a lens; and an optical film disposed on a surface of the lens, the optical film having a portion thereof cut to form a cut surface, wherein, when viewed in a plane, the cut surface does not overlap with the display panel.

Description

Technical Field

[0001] This disclosure relates to a display device and a display system. Background Technology

[0002] With the development of information technology, display devices, as the connection medium between users and information, are becoming increasingly important. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs) is increasing.

[0003] Recently, head-mounted display devices (HMDs) have been under development. HMDs are devices worn by users in the form of glasses or helmets to achieve virtual reality (VR), augmented reality (AR), or mixed reality (MR) displays that focus on objects close to the user's eyes. High-resolution panels and pancake lenses can be used in HMDs to achieve a highly immersive experience. Summary of the Invention

[0004] One aspect of this disclosure provides a display device and display system capable of reducing the risk of changes in the Chief Ray Angle (CRA).

[0005] One aspect of this disclosure provides a display device and display system that can reduce the risk of generating bubbles during the formation of optical films.

[0006] The technical problems of this invention are not limited to those mentioned above. Those skilled in the art can clearly understand other technical problems not mentioned through the following description.

[0007] The display device according to embodiments of the present disclosure may include: a display panel; and a pancake lens disposed on the display panel, wherein the pancake lens may include: a lens; and an optical film disposed on a surface of the lens, wherein the optical film may have a cut surface formed by cutting a portion thereof, and the cut surface may not overlap with the display panel when viewed in a plane.

[0008] According to an embodiment, the surface of the lens may be curved.

[0009] According to an embodiment, the surface may include a curvature variation region, which may correspond to a region including the inflection point of the curvature variation of the surface, or may correspond to a region of the surface with a slope variation of more than 10°.

[0010] According to an embodiment, the optical film may be attached to one surface of the lens.

[0011] According to an embodiment, when viewed on a plane, the optical film can completely overlap with the display panel and not overlap with a portion of the lens.

[0012] According to an embodiment, the portion of the region may correspond to the outermost contour of the lens.

[0013] According to an embodiment, when viewed in a plane, the cut surface can be arranged between the effective curvature diameter region of the lens and the flange of the lens, and when viewed in a plane, the effective curvature diameter region can correspond to the area where the display panel is arranged, and the flange can correspond to the area separated from the outermost contour of the lens by a predetermined distance.

[0014] According to an embodiment, the cutting surface may include at least one of a plane and a curved surface.

[0015] According to an embodiment, the optical film may include a first portion and a second portion that protrudes from the first portion when viewed in a plane, wherein the second portion may have at least one shape selected from circular, quadrilateral, and elliptical when viewed in a plane.

[0016] According to one embodiment, the optical film may include multiple cut regions.

[0017] According to an embodiment, the optical film can be thermally bonded to the surface of the lens or attached to the surface of the lens via an adhesive layer.

[0018] According to an embodiment, the lens may include at least one of plastic and glass, and the optical film may be a polarizing layer.

[0019] According to an embodiment, the display panel may include an organic light-emitting diode (OLED).

[0020] A method for manufacturing a display device according to an embodiment of the present disclosure may include the following steps: forming a display panel; and forming a pancake lens on the display panel, wherein the step of forming the pancake lens may include the following steps: arranging the lens; and arranging an optical film on a surface of the lens, wherein the step of arranging the optical film may include the following steps: cutting a portion of a base optical film to form the optical film having a cut surface, wherein, when viewed in a plane, the cut surface may not overlap with the display panel.

[0021] According to an embodiment, the step of arranging the optical film may further include the following step: attaching the optical film to the surface of the lens by thermal bonding or an adhesive layer, wherein the surface of the lens may be a curved surface, the curved surface may include a curvature variation region, the curvature variation region may correspond to a region including the inflection point of the curvature variation of the curved surface, or may correspond to a region of the curved surface with a slope variation of more than 10°.

[0022] According to an embodiment, when viewed in a plane, the optical film can completely overlap with the display panel and not overlap with a portion of the lens, the portion corresponding to the outermost contour of the lens. When viewed in a plane, the cut surface can be arranged between the effective curvature diameter region of the lens and the flange portion of the lens. When viewed in a plane, the effective curvature diameter region can correspond to the area where the display panel is arranged, and the flange portion can correspond to the area separated from the outermost contour of the lens by a predetermined distance.

[0023] According to an embodiment, the cutting surface may include at least one of a plane and a curved surface.

[0024] A display system according to an embodiment of the present disclosure may include: a display panel; and a pancake lens disposed on the display panel, wherein the pancake lens may include: a lens; and an optical film disposed on a surface of the lens, wherein the surface of the lens may be curved, and the optical film has a cut surface formed by cutting a portion thereof, wherein, when viewed in a plane, the cut surface may be disposed between the effective curvature diameter region of the lens and the flange portion of the lens, wherein, when viewed in a plane, the effective curvature diameter region may correspond to the area where the display panel is disposed, and the flange portion may correspond to the area spaced at a predetermined distance from the outermost contour of the lens.

[0025] According to an embodiment, the display system may include at least one of a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0026] According to an embodiment, when viewed on a plane, the optical film may overlap with the area where the image is displayed to the user, but may not overlap with the outermost contour of the lens.

[0027] According to embodiments of this disclosure, a display device, display system, and method of manufacturing the display device can be provided that can reduce the risk of changes in the chief ray angle (CRA).

[0028] According to embodiments of this disclosure, a display device, display system, and method of manufacturing the display device can be provided that can reduce the risk of generating bubbles during the formation of optical films.

[0029] The effects of the embodiments are not limited to the examples described above, and more diverse effects are included in this specification. Attached Figure Description

[0030] Figure 1 This is a schematic block diagram illustrating an embodiment of the display device.

[0031] Figure 2 It is shown Figure 1 A schematic block diagram of one embodiment of a sub-pixel.

[0032] Figure 3 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0033] Figure 4 It is shown Figure 1 A schematic plan view of an embodiment of the display panel.

[0034] Figure 5 It is shown Figure 4 A schematic exploded perspective view of a portion of the display panel.

[0035] Figure 6 It is shown Figure 5 A schematic plan view of one embodiment of the pixels.

[0036] Figure 7 It is according to an embodiment of the present invention. Figure 6 A schematic cross-sectional view of the I-I' line.

[0037] Figure 8 It is according to another embodiment of the present invention. Figure 6 A schematic cross-sectional view of the I-I' line.

[0038] Figure 9 It is shown Figure 8 A schematic enlarged view of region A.

[0039] Figure 10 It is shown that it includes Figure 7 or Figure 8 A schematic cross-sectional view of an embodiment of a portion of a light-emitting structure in one of the first to third light-emitting elements.

[0040] Figure 11 It is shown that it includes Figure 7 or Figure 8 A schematic cross-sectional view of another embodiment of a portion of a light-emitting structure in one of the first to third light-emitting elements.

[0041] Figure 12 It is shown Figure 5 A schematic plan view of another embodiment of one of the pixels.

[0042] Figure 13 It is shown Figure 5 A schematic plan view of another embodiment of one of the pixels.

[0043] Figure 14 This is a schematic cross-sectional view illustrating an embodiment of the display device.

[0044] Figure 15 This is a schematic cross-sectional view illustrating an embodiment of the lens.

[0045] Figures 16 to 18 This is a schematic diagram showing the arrangement of the lens and optical film according to an embodiment.

[0046] Figure 19 This diagram shows the arrangement of an optical film, excluding the cut area, on a lens.

[0047] Figure 20 This is a diagram showing the arrangement of an optical film, including the cut area, on a lens.

[0048] Figure 21 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0049] Figure 22 This is a block diagram illustrating an embodiment of the display system.

[0050] Figure 23 It is shown Figure 22 A schematic 3D diagram illustrating an application example of the display system.

[0051] Figure 24 It is shown Figure 23 A schematic diagram of a head-mounted display device worn by a user.

[0052] Explanation of reference numerals in the attached figures 100: Display device 1000: Display System DP: Display Panel Comparison: Pancake Lens PLS: Lens PLS1: First Lens PLS2: Second Lens PLS3: Third Lens OF: Optical film OF_CL: Cut surface DP_A: Effective curvature diameter region PK_A: Region with maximum effective diameter of curvature FL: Flange PLS_O: Outermost contour Detailed Implementation

[0053] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation of the present invention will be described, while other parts will be omitted to prevent obscuring the essence of the invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments described herein are provided merely to provide a detailed description to those skilled in the art to which this invention pertains so that the technical concept of the invention can be readily implemented.

[0054] Throughout this specification, when referring to a part being "connected" to another part, this includes not only "direct connection" but also "indirect connection" with other elements intervening. The terminology used herein is for illustrative purposes and is not intended to limit the invention. Throughout this specification, when referring to a part as "comprising" a constituent element, unless specifically stated otherwise, it means that it may also include other constituent elements, not that it excludes other constituent elements. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Here, "and / or" includes one or more combinations of the corresponding constituent elements.

[0055] Here, terms such as "first" and "second" can be used to describe multiple constituent elements, but these constituent elements are not limited to these terms. These terms are used to distinguish one constituent element from another. Therefore, without departing from the scope of this disclosure, a first constituent element may refer to a second constituent element.

[0056] Spatially relative terms such as "below" and "above" are used for illustrative purposes, thereby illustrating the relationship between one element or feature and other elements(s)(s), as shown in the figures. Spatially relative terms are intended to include different orientations during use, operation, and / or manufacture, in addition to those depicted in the figures. For example, if the device shown in the figures is flipped, the element described as being "below" another element or feature is positioned "above" another element or feature. Therefore, in one embodiment, the term "below" can include both the above and below orientations. Furthermore, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative terms used herein will be interpreted accordingly.

[0057] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate ideal embodiments. It is thus conceivable that their shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes illustrated, but rather as including variations in shape, for example, that result from manufacturing processes. As mentioned above, the shapes shown in the figures may not represent the actual shape of areas of the device, and this embodiment is not limited thereto.

[0058] Figure 1 This is a schematic block diagram illustrating an embodiment of the display device.

[0059] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0060] The display panel 110 includes sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0061] Each subpixel SP may include at least one light-emitting element configured to generate light. Thus, each subpixel SP can generate light of specific colors such as red, green, blue, cyan, magenta, and yellow. Two or more subpixels in a subpixel SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a pixel PXL.

[0062] Gate driver 120 is connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to the first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0063] In an embodiment, first light emission control lines EL1 to m-th light emission control lines ELm connected to sub-pixels SP in the row direction may also be provided. In this case, gate driver 120 may include a light emission control driver configured to control the first light emission control lines EL1 to m-th light emission control lines ELm, which can operate according to the control of controller 150.

[0064] The gate driver 120 may be arranged on one side of the display panel 110. However, the embodiments are not limited to this. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically separated, and these drivers may be arranged on one side of the display panel 110 and on the opposite side of the display panel 110. As described above, the gate driver 120 may be arranged in various forms around the periphery of the display panel 110 according to the embodiments.

[0065] The data driver 130 is connected to the sub-pixels SP arranged in the column direction via the first data lines DL1 to the nth data lines DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0066] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn using the voltage from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn. Accordingly, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image is displayed on the display panel 110.

[0067] In an embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0068] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 is a component configured to generate multiple voltages and provide the generated voltages to display device 100. For example, voltage generator 140 can be configured to generate multiple voltages by receiving an input voltage from outside display device 100, adjusting the received voltage, and correcting the adjusted voltage.

[0069] Voltage generator 140 can generate a first power supply voltage VDD and a second power supply voltage VSS, which can be provided to sub-pixels SP. The first power supply voltage VDD can have a relatively high voltage level, and the second power supply voltage VSS can have a lower voltage level than the first power supply voltage VDD. In another embodiment, the first power supply voltage VDD or the second power supply voltage VSS can be provided by an external device of display device 100.

[0070] In addition, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to sub-pixel SP. For example, during a sensing operation to sense the electrical characteristics of the transistor and / or light-emitting element of sub-pixel SP, a predetermined reference voltage can be applied to the first data line DL1 to the nth data line DLn, and voltage generator 140 can generate such a reference voltage.

[0071] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling its display from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0072] The controller 150 can convert the input image data IMG into image data DATA suitable for display device 100 or display panel 110. In an embodiment, the controller 150 can arrange the input image data IMG into sub-pixels SP suitable for row units and output image data DATA.

[0073] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally distinct components within a single driver integrated circuit (DIC). In another embodiment, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component distinct from the driver integrated circuit (DIC).

[0074] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the temperature of its surroundings and generate temperature data TEP representing the sensed temperature. In an embodiment, the temperature sensor 160 may be arranged adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0075] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In an embodiment, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can adjust the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0076] Figure 2 It is shown Figure 1 A schematic block diagram of one embodiment of a sub-pixel. Figure 2 In, an example is shown Figure 1 The sub-pixel SPij is arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the sub-pixel SP.

[0077] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0078] The light-emitting element (LD) is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. At this time, the first power supply voltage node VDDN is the transmission... Figure 1 The first power supply voltage node is VDD, and the second power supply voltage node is VSSN for transmission. Figure 1 The node is the second power supply voltage VSS. According to this disclosure, the light-emitting element LD can be an organic light-emitting diode (OLED).

[0079] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0080] Sub-pixel circuit SPC can be combined with Figure 1 The i-th gate line GLi from the first gate line GL1 to the m-th gate line GLm Figure 1 The first light emission control line EL1 to the m-th light emission control line ELm, and the i-th light emission control line ELi and Figure 1 The first data line DL1 to the j-th data line DLn of the n-th data line DLn are connected. The sub-pixel circuit SPC is configured to control the light-emitting element LD based on the signals received through these signal lines.

[0081] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as shown... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the respective sub-gate lines.

[0082] The sub-pixel circuit SPC can operate in response to a light emission control signal received via the i-th light emission control line ELi. In an embodiment, the i-th light emission control line ELi may include one or more sub-light emission control lines. When the i-th light emission control line ELi includes two or more sub-light emission control lines, the sub-pixel circuit SPC can operate in response to a light emission control signal received via the respective sub-light emission control line.

[0083] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN based on the stored voltage, in response to the light-emitting control signal received via the i-th light-emitting control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0084] Figure 3 It is shown Figure 2 Circuit diagram of an embodiment of a sub-pixel.

[0085] Reference Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0086] The sub-pixel circuit (SPC) can be connected to the i-th gate line GLi', the i-th light-emitting control line ELi', and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' may also include a third sub-gate line SGL3. Compared to... Figure 2 Compared to the i-th light emission control line ELi, the i-th light emission control line ELi' may include a first sub-light emission control line SEL1 and a second sub-light emission control line SEL2.

[0087] The sub-pixel circuit SPC may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0088] The first transistor T1 is connected between the first power supply voltage node VDDN and the first node N1. The gate of the first transistor T1 is connected to the second node N2, thereby the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0089] The second transistor T2 is connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 is connected to the first sub-gate line SGL1, thereby enabling the second transistor T2 to be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0090] The third transistor T3 is connected between the first node N1 and the second node N2. The gate of the third transistor T3 is connected to the second sub-gate line SGL2, thereby the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0091] The fourth transistor T4 is connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 is connected to the second sub-light-emitting control line SEL2, thereby the fourth transistor T4 can be turned on in response to the light-emitting control signal of the second sub-light-emitting control line SEL2.

[0092] The fifth transistor T5 is connected between the anode electrode AE ​​of the light-emitting element LD and the initialization voltage node VinTN. The initialization voltage node VinTN is configured to transmit the initialization voltage. In this embodiment, the initialization voltage can be generated by… Figure 1The voltage generator 140 provides the initial voltage. In another embodiment, the initial voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 is connected to the third sub-gate line SGL3, thereby enabling the fifth transistor T5 to be turned on in response to a gate signal on the third sub-gate line SGL3.

[0093] The sixth transistor T6 is connected between the first power supply voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 is connected to the first sub-light emission control line SEL1, thereby the sixth transistor T6 can be turned on in response to the light emission control signal of the first sub-light emission control line SEL1.

[0094] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power supply voltage node VDDN and the second node N2.

[0095] As described above, the sub-pixel circuit SPC may include first transistors T1 to sixth transistors T6, a first capacitor C1, and a second capacitor C2. However, the embodiments are not limited thereto. The sub-pixel circuit SPC may be implemented by one of various circuit configurations including multiple transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-light emission control lines included in the i-th light emission control line ELi' may vary.

[0096] The first transistor T1 through the sixth transistor T6 can be P-type transistors. Each of the first transistor T1 through the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the embodiments are not limited to this. For example, at least one of the first transistor T1 through the sixth transistor T6 can be replaced by an N-type transistor.

[0097] In the embodiments, the first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor, oxide semiconductor, etc.

[0098] The light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted through the j-th data line DLj reflects the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on when the light-emitting control signals of the first sub-light-emitting control line SEL1 and the second sub-light-emitting control line SEL2 are enabled at a low level. Furthermore, the first transistor T1 may be turned on according to the voltage of the second node N2, thereby allowing current to flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light-emitting element LD emits light according to the amount of current flowing through it.

[0099] Figure 4 It is shown Figure 1 A schematic plan view of an embodiment of the display panel.

[0100] Reference Figure 4 , Figure 1 An embodiment of the display panel 110 (hereinafter, display panel DP) may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is arranged around the periphery of the display area DA.

[0101] The display panel (DP) may include a substrate (SUB), sub-pixels (SP), and pads (PD).

[0102] When the display panel DP is used as a display screen for head-mounted displays (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, augmented reality (AR) devices, etc., the display panel DP can be very close to the user's eyes. In this case, sub-pixels SP with relatively high integration are required. To improve the integration of sub-pixels SP, the substrate SUB can be provided as a silicon substrate. Sub-pixels SP can be formed on the substrate SUB, which is a silicon substrate. Display device 100 including sub-pixels SP formed on the substrate SUB, which is a silicon substrate (see reference). Figure 1 This can be referred to as a silicon-based OLED (OLEDoS: OLED on Silicon) display device.

[0103] Subpixels SP are arranged on the substrate SUB in the display area DA. The subpixels SP can be arranged in a matrix configuration along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to this. For example, the subpixels SP can be arranged in a zigzag configuration along the first direction DR1 and the second direction DR2. For example, the subpixels SP can be arranged in a pentiline configuration. ®Arrangement. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction. Furthermore, the third direction DR3 can be the direction in which light is emitted from the display panel DP.

[0104] Two or more sub-pixels SP can form a pixel PXL.

[0105] In the non-display area NDA on the substrate SUB, components for controlling sub-pixels SP can be arranged. For example, wiring connected to the sub-pixels SP (such as...) Figure 1 The first gate line GL1 to the m gate line GLm and the first data line DL1 to the nth data line DLn can be arranged in the non-display area NDA.

[0106] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 can be integrated into the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 can be mounted on the display panel DP and disposed in the non-display area NDA. In another embodiment, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 can be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0107] A pad PD is arranged in the non-display area NDA on the substrate SUB. The pad PD can be electrically connected to the sub-pixel SP via wiring. For example, the pad PD can be connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0108] The pad PD can connect the display panel DP to the display device 100 (see reference). Figure 1 Other components of the display panel (DP) interfacing. In an embodiment, the voltages and signals required for the operation of the components included in the display panel (DP) can be obtained from... Figure 1 The driver integrated circuit (DIC) is provided via a pad (PD). For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad (PD). For example, the first power supply voltage VDD and the second power supply voltage VSS can be received from the driver integrated circuit (DIC) via the pad (PD). For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be sent from the driver integrated circuit (DIC) to the gate driver 120 via the pad (PD).

[0109] In this embodiment, the circuit board can be electrically connected to the pad PD using a conductive adhesive component such as an anisotropic conductive film. In this case, the circuit board can be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board and electrically connected to the pad PD.

[0110] In this embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape with sides including straight lines and / or curves. For example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0111] In one embodiment, the display panel DP may have a flat display surface. In another embodiment, the display panel DP may have a display surface that is at least partially rounded. In another embodiment, the display panel DP may be bendable, foldable, or rollable. In this case, the display panel DP and / or the substrate SUB may contain a material with flexible properties.

[0112] Figure 5 It is shown Figure 4 A schematic exploded perspective view of a portion of the display panel. Figure 5 In order to provide a clear and concise explanation, the diagram is schematically shown alongside... Figure 4 The two pixels PXL1 and PXL2 in pixel PXL correspond to the portion of the display panel DP. The portions of the display panel DP corresponding to the remaining pixels can also be constructed in the same way.

[0113] Reference Figure 4 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiments are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0114] exist Figure 5 In the example, when viewed from the third direction DR3, which intersects the first direction DR1 and the second direction DR2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are shown as having rectangular shapes and the same size as each other. However, the embodiment is not limited to this. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be deformed to have various shapes.

[0115] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), a protective layer (OC), and a cover window (CW).

[0116] In one embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may also be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0117] A pixel circuit layer (PCL) is disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns disposed between the insulating layer. The conductive patterns of the pixel circuit layer PCL may be used as at least a portion of circuit elements, wiring, etc. The conductive patterns may include copper, but the embodiments are not limited thereto.

[0118] The circuit elements may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see reference). Figure 2 The sub-pixel circuit (SPC) may include multiple transistors and one or more capacitors. Each transistor may include a semiconductor portion and a gate electrode overlapping the semiconductor portion, wherein the semiconductor portion includes a source region, a drain region, and a channel region. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included within the substrate SUB, and the gate electrode may be included within the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included within the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes overlapping each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other on a third direction DR3 by an insulating layer.

[0119] The wiring of the pixel circuit layer (PCL) may include signal lines (e.g., gate lines, light emission control lines, and data lines) connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The wiring may also include connections to... Figure 2The wiring is connected to the first power supply voltage node VDDN. Additionally, the wiring may include connections to... Figure 2 The wiring for the second power supply voltage node VSSN connection.

[0120] The light-emitting element layer (LDL) may include an anode electrode (AE), a pixel definition layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0121] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​can contain an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0122] A pixel definition layer (PDL) is arranged on the anode electrode AE. The PDL may include an opening OP that exposes a portion of each anode electrode AE. The light-emitting regions corresponding to the first sub-pixels SP1 to SP3 can be defined according to the opening OP of the PDL. Alternatively, it can be understood that the light-emitting regions corresponding to the first sub-pixels SP1 to SP3 are defined according to the anode electrode AE. In regions adjacent to the boundaries of adjacent sub-pixels, the PDL may include separators that cause discontinuities to form within the light-emitting structure EMS. In this case, it can also be understood that the light-emitting regions corresponding to the first sub-pixels SP1 to SP3 are defined according to the separators of the PDL.

[0123] In this embodiment, the pixel definition layer (PDL) may contain inorganic materials. In this case, the pixel definition layer (PDL) may comprise multiple stacked inorganic layers. For example, the pixel definition layer (PDL) may contain silicon oxide (SiO2). x ) and silicon nitride (SiN) x In another embodiment, the pixel definition layer (PDL) may contain organic materials. However, the materials of the pixel definition layer (PDL) are not limited to this.

[0124] The light-emitting structure (EMS) can be disposed on the anode electrode (AE) exposed by the opening (OP) of the pixel definition layer (PDL). The EMS can include a light-emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes, etc.

[0125] In an embodiment, the light-emitting structure EMS can fill the opening OP of the pixel definition layer PDL and can be integrally arranged on the upper part of the pixel definition layer PDL. In other words, the light-emitting structure EMS can extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a portion of the layers within the light-emitting structure EMS can be broken or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, the embodiment is not limited to this. For example, portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of these portions can be arranged within the opening OP of the pixel definition layer PDL.

[0126] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can extend throughout the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the cathode electrode CE can be provided as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0127] The cathode electrode CE can be a thin metal layer with a thickness sufficient to allow light emitted from the light-emitting structure EMS to pass through. The cathode electrode CE can be formed using a metallic material or a transparent conductive material with a relatively thin thickness. In embodiments, the cathode electrode CE may comprise at least one of a variety of transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In another embodiment, the cathode electrode CE may comprise at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited to these.

[0128] This can be understood as follows: a light-emitting element (LD) is composed of one part of the anode electrode AE, the overlapping part of the light-emitting structure EMS with the anode electrode AE, and the overlapping part of the cathode electrode CE with the anode electrode AE. Figure 2 In other words, each of the light-emitting elements (LDs) in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS overlapping with the anode electrode AE, and a portion of the cathode electrode CE overlapping with the anode electrode AE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE can be transferred into the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined based on the composition of the light-emitting layer.

[0129] An encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In embodiments, the encapsulation layer TFE may comprise a structure consisting of one or more inorganic films and one or more organic films alternately stacked. For example, the inorganic films may comprise silicon nitride, silicon oxide, or silicon oxide nitride (SiO2). x N y For example, organic membranes can contain organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic and inorganic membranes of the encapsulation layer TFE are not limited to these.

[0130] To improve the packaging efficiency of the TFE encapsulation layer, the TFE encapsulation layer may also include aluminum oxide (AlO2). x The thin film containing aluminum oxide may be located on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0131] Thin films containing aluminum oxide can be formed using atomic layer deposition (ALD). However, embodiments are not limited to this. The encapsulation layer TFE may also comprise a thin film formed using at least one of a variety of materials suitable for improving encapsulation efficiency.

[0132] The optical functional layer (OFL) is disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0133] A color filter layer (CFL) is disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL is configured to filter light emitted from the light-emitting structure (EMS) to selectively output light of a wavelength range or color corresponding to each sub-pixel. The CFL may include color filters (CF) corresponding to the first sub-pixels SP1 through SP3, respectively, and each of these CFs allows light within the wavelength range corresponding to the respective sub-pixel to pass through. For example, the CF corresponding to the first sub-pixel SP1 allows red light to pass through, the CF corresponding to the second sub-pixel SP2 allows green light to pass through, and the CF corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the light-emitting structure (EMS) of each sub-pixel, at least a portion of the color filter CF may be omitted.

[0134] A lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixels SP1 through SP3, respectively. Each lens LS can improve light extraction efficiency by outputting light emitted from the light-emitting structure EMS along a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the protective layer OC. In embodiments, the lenses LS may contain organic materials. In embodiments, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not limited to these.

[0135] In an embodiment, at least a portion of the color filters CF of the color filter layer CFL and at least a portion of the lenses LS of the lens array LA can be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, relative to the opening OP of the pixel definition layer PDL. Specifically, in the central region of the display area DA, when viewed in the third direction DR3, the center of the color filter and the center of the lens can be aligned with or overlap with the center of the opening OP of the corresponding pixel definition layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel definition layer PDL can completely overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter and the center of the lens can be shifted from the center of the opening OP of the corresponding pixel definition layer PDL in a planar direction. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel definition layer PDL can partially overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light-emitting structure EMS can be efficiently output in the normal direction of the display surface. At the outer edge of the display area DA, the light emitted from the light-emitting structure EMS can be efficiently output in a direction inclined at a predetermined angle relative to the normal direction of the display surface.

[0136] A protective layer OC can be disposed on the lens array LA. The protective layer OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The protective layer OC can contain various materials suitable for protecting its underlying layers from foreign matter such as dust and moisture. For example, the protective layer OC can include at least one of inorganic and organic insulating films. For example, the protective layer OC can contain epoxy resin, but the embodiments are not limited thereto. The protective layer OC can have a refractive index lower than that of the lens array LA.

[0137] A cover window CW can be disposed on a protective layer OC. The cover window CW is configured to protect its underlying layer. The cover window CW can have a higher refractive index than the protective layer OC. The cover window CW can contain glass, but the embodiments are not limited thereto. For example, the cover window CW can be an encapsulation glass configured to protect the constituent elements disposed below it. In another embodiment, the cover window CW can be omitted.

[0138] According to an embodiment, the display panel DP may further include a polarizing layer and a quarter-wave plate. According to an embodiment, the display panel DP may include multiple quarter-wave plates. According to an embodiment, the display panel DP may include two quarter-wave plates and a polarizing layer disposed therebetween. According to an embodiment, the two quarter-wave plates and the polarizing layer disposed therebetween may be arranged on a lens array LA, but this disclosure is not limited thereto.

[0139] Figure 6 It is shown Figure 5 A schematic plan view of one embodiment of the pixels. Figure 6 For clarity and conciseness, the diagram is shown schematically. Figure 5 The first pixel PXL1 is one of the first pixels PXL1 and the second pixel PXL2. The remaining pixels can also be constructed in the same way as the first pixel PXL1.

[0140] Reference Figure 5 and Figure 6 The first pixel PXL1 may include the first sub-pixels SP1 to the third sub-pixels SP3 arranged along the first direction DR1.

[0141] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0142] The first luminescent region EMA1 can be emitted from the luminescent structure EMS (see reference). Figure 5 The first light-emitting region EMA2 can be the region of the light-emitting structure EMS that emits light from the portion corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 can be the region of the light-emitting structure EMS that emits light from the portion corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 can be the region of the light-emitting structure EMS that emits light from the portion corresponding to the third sub-pixel SP3.

[0143] Figure 7 It is according to an embodiment of the present invention. Figure 6 A schematic cross-sectional view of the I-I' line.

[0144] Reference Figure 7 It provides a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0145] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, the substrate SUB may contain silicon, germanium, and / or silicon-germanium.

[0146] A pixel circuit layer PCL is disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the substrate SUB and the pixel circuit layer PCL may include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 may be a sub-pixel circuit SPC included in the first sub-pixel SP1 (see reference). Figure 2 One of the transistors in the second sub-pixel SP2, transistor T_SP2 can be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 For clarity and brevity, only one transistor for each subpixel is shown, and the rest of the circuitry is omitted.

[0147] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0148] The source region SRA and drain region DRA can be disposed within the substrate SUB. A well WL formed by ion implantation can be disposed within the substrate SUB, and the source region SRA and drain region DRA can be disposed separately from each other within the well WL. The region between the source region SRA and drain region DRA within the well WL can be defined as the channel region. The gate electrode GE can overlap with the channel region between the source region SRA and drain region DRA and can be disposed within the pixel circuit layer PCL. The gate electrode GE can be separated from the well WL or channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE can contain a conductive material.

[0149] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and these conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection SRC that penetrates one or more insulating layers.

[0150] With the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be provided as one of the transistors of the first sub-pixel SP1.

[0151] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be constructed in the same way as the transistor T_SP1 of the first sub-pixel SP1.

[0152] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0153] A via layer VIAL is disposed on the pixel circuit layer PCL. The via layer VIAL can cover the pixel circuit layer PCL and can have an overall flat surface. The via layer VIAL is configured to flatten the step differences on the pixel circuit layer PCL. The via layer VIAL can include silicon oxide (SiO2). x ), silicon nitride (SiN) x The embodiments are not limited to at least one of silicon carbide (SiCN) and silicon carbon nitride (SiCN).

[0154] A light-emitting element layer (LDL) is disposed on the via layer VIAL. The light-emitting element layer LDL may include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode electrode AE1 to a third anode electrode AE3, a pixel definition layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0155] On the via layer VIAL, a first reflective electrode RE1 to a third reflective electrode RE3 are respectively arranged on the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact the circuit elements arranged on the pixel circuit layer PCL through the vias through the via layer VIAL.

[0156] The first reflective electrodes RE1 to the third reflective electrodes RE3 can be used as full mirrors to reflect light emitted from the light-emitting structure EMS toward the display surface (or, the cover window CW). The first reflective electrodes RE1 to the third reflective electrodes RE3 can contain a metallic material suitable for reflecting light. The first reflective electrodes RE1 to the third reflective electrodes RE3 can contain at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials, but the embodiments are not limited thereto.

[0157] In this embodiment, a connecting electrode is arranged below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode can have a multilayer structure. The multilayer structure can include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited to these. In this embodiment, the corresponding reflective electrode can be located between the multiple layers of the connecting electrode.

[0158] A buffer pattern BFP may be disposed below at least one of the first reflective electrodes RE1 to the third reflective electrode RE3. The buffer pattern BFP may contain inorganic materials such as silicon carbide, but the embodiments are not limited thereto. The height on the third-direction DR3 of the respective reflective electrode can be adjusted by arranging the buffer pattern BFP. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0159] The first reflecting electrodes RE1 to RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a half-reflection mirror. For example, each of the first reflecting electrodes RE1 to RE3 and the cathode electrode CE can provide a resonant structure in the corresponding sub-pixel. Light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by oscillating between the corresponding reflecting electrode and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. As described above, the distance between each reflecting electrode and the cathode electrode CE can be understood as the resonant distance for light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0160] The first sub-pixel SP1 can have a shorter resonant distance than other sub-pixels due to the buffer pattern BFP. This adjusted resonant distance enables effective and efficient amplification of light within a specific wavelength range (e.g., red). Accordingly, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0161] exist Figure 7The illustration shows a scenario where the buffer pattern BFP is provided on the first sub-pixel SP1 but not on the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited to this. At least one of the second sub-pixel SP2 and the third sub-pixel SP3 may also be provided with a buffer pattern to adjust the resonant distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may correspond to red, green, and blue, respectively; the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE; and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0162] To flatten the step difference between the first reflective electrode RE1 and the third reflective electrode RE3, a planarization layer PLNL can be disposed on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL can completely cover the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL, and can have a flat surface. In an embodiment, the planarization layer PLNL can be omitted.

[0163] A first anode electrode AE1 to a third anode electrode AE3, respectively overlapping with the first reflective electrode RE1 to the third reflective electrode RE3, are arranged on the planarization layer PLNL. When observed on the third-direction DR3, the first anode electrode AE1 to the third anode electrode AE3 can have the same characteristics as... Figure 6 The first light-emitting regions EMA1 to EMA3 have similar shapes. The first anode electrode AE1 to the third anode electrode AE3 are respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 through a first via VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 through a second via VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 through a third via VIA3 penetrating the planarization layer PLNL.

[0164] In the embodiments, the first anode electrode AE1 to the third anode electrode AE3 may comprise, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). xThe materials used are at least one of transparent conductive materials such as zinc oxide, indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1 to the third anode electrode AE3 are not limited to these. For example, the first anode electrode AE1 to the third anode electrode AE3 may contain titanium nitride.

[0165] A pixel definition layer (PDL) is disposed on a portion of the first anode electrode AE1 to the third anode electrode AE3 and the planarization layer PLNL. The pixel definition layer PDL has an opening OP that exposes a portion of each of the first anode electrode AE1 to the third anode electrode AE3. The region that does not overlap with the opening OP of the pixel definition layer PDL can be understood as the boundary region BDA between adjacent sub-pixels.

[0166] In an embodiment, the pixel definition layer (PDL) may include multiple inorganic insulating layers. Each of the multiple inorganic insulating layers may contain silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. For example, the pixel definition layer (PDL) may include a first inorganic insulating layer (ISL1), a second inorganic insulating layer (ISL2), and a third inorganic insulating layer (ISL3) stacked sequentially. The first inorganic insulating layers (ISL1) to the third inorganic insulating layers (ISL3) may contain silicon nitride, silicon oxide, and silicon oxide nitride, but the embodiments are not limited thereto. The first inorganic insulating layers (ISL1) to the third inorganic insulating layers (ISL3) may have a stepped cross-section in the region adjacent to the opening (OP).

[0167] The pixel definition layer (PDL) can include separators (SPRs) at the boundary regions (BDAs) between adjacent sub-pixels. In other words, it can... Figure 4 Each boundary region between sub-pixels SP is provided with a separator SPR.

[0168] The separator SPR can cause a discontinuity to form within the light-emitting structure EMS at the boundary region BDA. For example, the light-emitting structure EMS can be broken or bent at the boundary region BDA by the separator SPR. Therefore, the components corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 respectively... Figure 6 The first luminous region EMA1 to the third luminous region EMA3 can be defined according to the separator SPR of the pixel definition layer PDL.

[0169] The separator SPR can be arranged inside (in) or on (on) the pixel definition layer PDL. The pixel definition layer PDL can include one or more trenches TRCH1, TRCH2 as separator SPRs at the boundary region BDA. In the embodiment, as shown... Figure 7 As shown, one or more trenches TRCH1, TRCH2 can penetrate the pixel definition layer PDL and partially penetrate the planarization layer PLNL. In another embodiment, one or more trenches TRCH1, TRCH2 can penetrate the pixel definition layer PDL and the planarization layer PLNL, and partially penetrate the via layer VIAL. In another embodiment, one or more trenches TRCH1, TRCH2 can at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel definition layer PDL can be disposed within one or more trenches TRCH1, TRCH2.

[0170] exist Figure 7 The illustration shows a scenario where two trenches TRCH1 and TRCH2 are provided at the boundary region BDA. However, the embodiment is not limited to this. For example, the pixel definition layer PDL may include one trench at the boundary region BDA. Alternatively, the pixel definition layer PDL may include three or more trenches at the boundary region BDA.

[0171] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first void VD1 and the second void VD2 can be formed in the light-emitting structure EMS at the boundary region BDA. A portion of the multiple layers stacked within the light-emitting structure EMS can be broken or bent due to the first void VD1 and the second void VD2. For example, at least one charge generation layer and at least one hole injection layer included in the light-emitting structure EMS can be broken at the first void VD1 and the second void VD2. As described above, due to the first trench TRCH1 and the second trench TRCH2, portions of the light-emitting structure EMS included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated.

[0172] Depending on the shape of the first trench TRCH1 and the second trench TRCH2, the discontinuous portion formed in the light-emitting structure EMS can be varied.

[0173] In this embodiment, the light-emitting structure EMS can be formed by processes such as vacuum deposition and inkjet printing. In this case, the same material as the light-emitting structure EMS can be disposed on the bottom surface adjacent to the via layer VIAL in the first trench TRCH1 and the second trench TRCH2.

[0174] The pixel definition layer (PDL) may include additional separators, such that the light-emitting structure (EMS) also includes a discontinuous portion adjacent to the boundary region BDA. In an embodiment, the uppermost third inorganic insulating layer ISL3 of the first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 of the pixel definition layer PDL may have a width wider than the second inorganic insulating layer ISL2 disposed immediately below it. For example, the pixel definition layer PDL may have a "T"-shaped or "I"-shaped cross-section at the boundary region BDA. Depending on the shape of this pixel definition layer PDL, the multiple layers included in the light-emitting structure EMS may be at least partially broken or bent at the boundary region BDA or in a region adjacent to the boundary region BDA.

[0175] The light-emitting structure EMS can be arranged on the anode electrode AE ​​exposed by the opening OP of the pixel definition layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel definition layer PDL and be arranged integrally throughout the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the light-emitting structure EMS can be at least partially broken or bent at the boundary region BDA by means of the separator SPR. As a result, when the display panel DP is operating, the current flowing from each of the first sub-pixel SP1 to the third sub-pixel SP3 to its adjacent sub-pixel through the layer included in the light-emitting structure EMS can be reduced. Therefore, the first light-emitting element LD1 to the third light-emitting element LD3 can operate with relatively high reliability.

[0176] The cathode electrode CE can be arranged on the light-emitting structure EMS. The cathode electrode CE can be provided together in the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can be used as a half mirror to partially transmit and partially reflect the light emitted from the light-emitting structure EMS.

[0177] The first anode electrode AE1, the portion of the light-emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 can constitute the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 can constitute the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 can constitute the third light-emitting element LD3.

[0178] A TFE encapsulation layer is arranged on the cathode electrode CE. The TFE encapsulation layer can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0179] An optical functional layer (OFL) is disposed on a packaging layer TFE. In an embodiment, the optical functional layer OFL can be attached to the packaging layer TFE via an adhesive layer APL. For example, the optical functional layer OFL can be manufactured separately and attached to the packaging layer TFE via the adhesive layer APL. The adhesive layer APL also performs the function of protecting the underlying layer including the packaging layer TFE.

[0180] The optical functional layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a first color filter CF1 to a third color filter CF3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. The first color filters CF1 to the third color filters CF3 can transmit light of different wavelength ranges. For example, the first color filters CF1 to the third color filters CF3 can transmit red, green, and blue light, respectively.

[0181] In one embodiment, the first color filter CF1 to the third color filter CF3 may partially overlap at the boundary region BDA. In another embodiment, the first color filter CF1 to the third color filter CF3 may be spaced apart from each other, and a black matrix may be provided between the first color filter CF1 to the third color filter CF3.

[0182] The lens array LA is arranged on the color filter layer CFL. The lens array LA may include a first lens LS1 to a third lens LS3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. The first lens LS1 to the third lens LS3 can improve the light extraction efficiency by outputting the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3, respectively, along a desired path.

[0183] A protective layer OC can be arranged on the lens array LA. The protective layer OC is configured to protect its underlying layer from foreign matter such as dust and moisture. A cover window CW can be arranged on the protective layer OC.

[0184] Figure 8 It is according to another embodiment of the present invention. Figure 6 A schematic cross-sectional view of the I-I' line. Figure 9 It is shown Figure 8 A schematic enlarged view of region A.

[0185] Reference Figure 8 A pixel circuit layer PCL and a via layer VIAL are arranged on the substrate SUB. Figure 8 The substrate SUB, pixel circuit layer PCL, and via layer VIAL are respectively with Figure 7 The substrate SUB, pixel circuit layer PCL, and via layer VIAL are constructed identically. Repeated descriptions will be omitted below.

[0186] A light-emitting element layer (LDL) is disposed on the via layer (VIAL). The light-emitting element layer (LDL) may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a first buffer pattern (BFP1) and a second buffer pattern (BFP2), a first cover pattern (CVP1) to a third cover pattern (CVP3), a first anode electrode (AE1) to a third anode electrode (AE3), a pixel definition layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0187] On the via layer VIAL, a first reflective electrode RE1' to a third reflective electrode RE3' are respectively arranged on the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1' to the third reflective electrode RE3' can contact the circuit elements arranged on the pixel circuit layer PCL through the vias of the via layer VIAL.

[0188] The first reflective electrodes RE1' to the third reflective electrodes RE3' are configured to reflect light emitted from the light-emitting structure EMS' toward the display surface (or, the cover window CW). The first reflective electrodes RE1' to the third reflective electrodes RE3' may contain a metallic material suitable for reflecting light. The first reflective electrodes RE1' to the third reflective electrodes RE3' may contain at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials, but the embodiments are not limited thereto.

[0189] In an embodiment, a connection electrode may also be provided between each of the first reflective electrode RE1' to the third reflective electrode RE3' and the via layer VIAL. The connection electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode can have a multilayer structure. The multilayer structure may include titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited to these. In an embodiment, the corresponding reflective electrode may also be located between the multiple layers of the connection electrode.

[0190] A buffer pattern may be arranged on at least one of the first reflective electrode RE1' to the third reflective electrode RE3'. In an embodiment, a first buffer pattern BFP1' and a second buffer pattern BFP2' may be arranged on the first reflective electrode RE1' and the third reflective electrode RE3', respectively. The first buffer pattern BFP1' and the second buffer pattern BFP2' can be used to adjust the height of the first anode electrode AE1' and the third anode electrode AE3' on the third directional DR3. The first buffer pattern BFP1' and the second buffer pattern BFP2' may contain materials such as silicon oxide (SiO2). x) and silicon nitride (SiN) x Inorganic substances such as ( ), but the embodiments are not limited thereto.

[0191] A first cover pattern CVP1 to a third cover pattern CVP3 may be respectively disposed on the first reflective electrode RE1' to the third reflective electrode RE3'. In the first sub-pixel SP1, the first cover pattern CVP1 is disposed on the first reflective electrode RE1' and the first buffer pattern BFP1'. In the second sub-pixel SP2, the second cover pattern CVP2 is disposed on the second reflective electrode RE2'. In the third sub-pixel SP3, the third cover pattern CVP3 is disposed on the third reflective electrode RE3' and the second buffer pattern BFP2'. The first cover pattern CVP1 to the third cover pattern CVP3 may be formed during the manufacturing process after the formation of the first buffer pattern BFP1' and the second buffer pattern BFP2'. The first cover pattern CVP1 to the third cover pattern CVP3 may contain the same material as the first buffer pattern BFP1' and the second buffer pattern BFP2'. For example, the first cover pattern CVP1 to the third cover pattern CVP3 may contain silicon oxide (SiO2). x ) and silicon nitride (SiN) x Inorganic substances such as ( ), but the embodiments are not limited thereto.

[0192] A first anode electrode AE1' to a third anode electrode AE3' are respectively arranged on the first covering pattern CVP1 to the third covering pattern CVP3. In an embodiment, the first anode electrode AE1' may cover the first covering pattern CVP1, the first buffer pattern BFP1', and the first reflective electrode RE1'. The second anode electrode AE2' may cover the second covering pattern CVP2 and the second reflective electrode RE2'. The third anode electrode AE3' may cover the third covering pattern CVP3, the second buffer pattern BFP2', and the third reflective electrode RE3'.

[0193] The first anode electrode AE1' to the third anode electrode AE3' can be electrically connected to the first reflective electrode RE1' to the third reflective electrode RE3', respectively. For example, each anode electrode can be connected to the end (or edge) of the corresponding reflective electrode. However, the embodiments are not limited to this. To improve the electrical connection characteristics between the anode electrode and the reflective electrode, the anode electrode can be connected to the reflective electrode in various ways.

[0194] In the embodiments, the first anode electrode AE1' to the third anode electrode AE3' may comprise, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). xThe materials are at least one of transparent conductive materials such as zinc oxide, indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1' to the third anode electrode AE3' are not limited to these. For example, the first anode electrode AE1' to the third anode electrode AE3' may contain titanium nitride.

[0195] When observed on DR3 by a third party, the first anode electrode AE1' to the third anode electrode AE3' can have the same characteristics as... Figure 6 The first luminous region EMA1 to the third luminous region EMA3 have similar shapes.

[0196] The first anode electrode AE1' to the third anode electrode AE3' and the cathode electrode CE can partially reflect the incident light. Light emitted from the light-emitting layer of the light-emitting structure EMS' can be amplified by oscillating between the corresponding anode electrode and the cathode electrode CE, and then output through the cathode electrode CE. For example, each anode electrode and cathode electrode CE can provide a resonant structure in the corresponding sub-pixel. In this case, the distance between each anode electrode and cathode electrode CE can be understood as the resonant distance for light emitted from the light-emitting layer of the light-emitting structure EMS'.

[0197] The first sub-pixel SP1 to the third sub-pixel SP3 can correspond to red, green, and blue, respectively. In this case, the height of the first anode electrode AE1' and the third anode electrode AE3' on the third-direction DR3 can be higher than the height of the second anode electrode AE2' due to the first buffer pattern BFP1' and the second buffer pattern BFP2'. Therefore, the first sub-pixel SP1 and the third sub-pixel SP3 can have a shorter resonant distance than the second sub-pixel SP2 due to the first buffer pattern BFP1' and the second buffer pattern BFP2'. Thus, the resonant distance of each sub-pixel can be adjusted to effectively and efficiently amplify light within the wavelength range of the corresponding color.

[0198] exist Figure 8The illustration shows a configuration where a first buffer pattern BFP1' and a second buffer pattern BFP2' are respectively arranged below the first anode electrode AE1' and the third anode electrode AE3', but the embodiment is not limited to this. For example, one of the first buffer pattern BFP1' and the second buffer pattern BFP2' can be omitted. As another example, both the first buffer pattern BFP1' and the second buffer pattern BFP2' can be omitted. In this case, the resonant distance between each anode electrode and the cathode electrode CE can be equal to each other. As yet another example, a buffer pattern can be arranged below each of the first anode electrodes AE1' to the third anode electrode AE3'. In this case, the buffer patterns arranged below each anode electrode can have different thicknesses, thereby allowing the resonant distance between each anode electrode and the cathode electrode CE to be different from each other. Thus, by providing a buffer pattern for adjusting the height of the corresponding anode electrode below at least one of the first anode electrodes AE1' to the third anode electrode AE3', the resonant distance in each sub-pixel can be optimized.

[0199] A pixel definition layer (PDL) is disposed on a portion of the first anode electrode AE1' to the third anode electrode AE3' and the via layer VIAL. The pixel definition layer (PDL) has an opening OP' that exposes a portion of each of the first anode electrode AE1' to the third anode electrode AE3'. The region that does not overlap with the opening OP' of the pixel definition layer (PDL) can be understood as the boundary region BDA between adjacent sub-pixels.

[0200] The pixel definition layer (PDL) may include multiple inorganic insulating layers stacked sequentially. Each of the multiple inorganic insulating layers may contain silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. However, the embodiments are not limited thereto. For example, the pixel definition layer PDL' may include an organic insulating layer.

[0201] In an embodiment, the pixel definition layer PDL' may include a first inorganic insulating layer ISL1' to a fourth inorganic insulating layer ISL4'. The first inorganic insulating layer ISL1' may cover a portion of the first anode electrode AE1' to the third anode electrode AE3' and the via layer VIAL. A second inorganic insulating layer ISL2' is disposed on the first inorganic insulating layer ISL1', a third inorganic insulating layer ISL3' is disposed on the second inorganic insulating layer ISL2', and the fourth inorganic insulating layer ISL4' is disposed on the third inorganic insulating layer ISL3'. The first inorganic insulating layer ISL1' and the third inorganic insulating layer ISL3' may contain silicon nitride (SiN). x The second inorganic insulating layer ISL2' and the fourth inorganic insulating layer ISL4' may contain silicon oxide (SiO2).x However, the embodiments are not limited thereto. In the embodiments, the first inorganic insulating layer ISL1' may be omitted.

[0202] The pixel definition layer (PDL) may include separators (SPRs) at the boundary regions (BDAs) between adjacent subpixels. The separators (SPRs) may cause discontinuities such as voids (VDs) to form in the light-emitting structure (EMS). Due to these discontinuities, at least a portion of the multiple layers included in the light-emitting structure (EMS) may be broken or bent.

[0203] The fourth inorganic insulating layer ISL4' may have a width wider than the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. In this case, the side surfaces of the second inorganic insulating layer ISL2' to the fourth inorganic insulating layer ISL4' adjacent to the opening OP' may be provided as separators SPR'.

[0204] and Figure 8 Refer to together Figure 9 The fourth inorganic insulating layer ISL4' may include a first portion P1 to a third portion P3. A second portion P2 may completely overlap with the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. The first portion P1 protrudes from the second portion P2 in a direction opposite to the first direction DR1. The third portion P3 protrudes from the second portion P2 in the first direction DR1. Thus, the width of the fourth inorganic insulating layer ISL4' may be greater than the widths of the second and third inorganic insulating layers ISL2' and ISL3'. For example, during the manufacturing process, the second and third inorganic insulating layers ISL2' and ISL3' may be undercut to exclude the portions overlapping with the first and third portions P1 and P3. For example, each of the first and third portions P1 and P3 of the fourth inorganic insulating layer ISL4' may have an eaves shape on the second and third inorganic insulating layers ISL2' and ISL3'.

[0205] In the boundary region BDA, the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have the same width. However, the embodiments are not limited to this; the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have different widths. For example, the second inorganic insulating layer ISL2' may have a wider width than the third inorganic insulating layer ISL3'. As another example, the third inorganic insulating layer ISL3' may have a wider width than the second inorganic insulating layer ISL2'.

[0206] In the second sub-pixel SP2, the first portion P1 of the fourth inorganic insulating layer ISL4' and the first side surface SSF1 of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be provided as a separator SPR'. Thus, a first gap VD1' adjacent to the first portion P1 of the fourth inorganic insulating layer ISL4' can be formed in the light-emitting structure EMS'. In the third sub-pixel SP3, the third portion P3 of the fourth inorganic insulating layer ISL4' and the second side surface SSF2 of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be provided as another separator SPR'. Thus, a second gap VD2' adjacent to the third portion P3 of the fourth inorganic insulating layer ISL4' can be formed in the light-emitting structure EMS'.

[0207] A portion of the multiple layers stacked within the light-emitting structure EMS' can be broken or bent by the first gap VD1' and the second gap VD2'. For example, at least one charge generation layer and at least one hole injection layer included in the light-emitting structure EMS' can be broken by the first gap VD1' and the second gap VD2'. Thus, due to the separator SPR', portions of the light-emitting structure EMS' included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated from each other.

[0208] The pixel definition layer (PDL) may include additional separators, such that the light-emitting structure (EMS) may also include discontinuous portions at the boundary region BDA. In embodiments, the PDL may include one or more trenches as separators at the boundary region BDA. The trenches may extend through one or more of the first inorganic insulating layers ISL1' to the fourth inorganic insulating layers ISL4'. A portion of the multiple layers stacked within the light-emitting structure (EMS) (e.g., at least one charge-generating layer and at least one hole-injecting layer) may be broken or bent by the trenches. In embodiments, the EMS may have a structure consisting of three light-emitting portions stacked, each including a light-emitting layer, and two charge-generating layers may be arranged between the three light-emitting portions. In these embodiments, the PDL may include one or more trenches at the boundary region BDA.

[0209] Refer again Figure 8The light-emitting structure EMS' can be arranged on the anode electrode exposed by the opening OP' of the pixel definition layer PDL'. The light-emitting structure EMS' can fill the opening OP' of the pixel definition layer PDL' and can be arranged integrally throughout the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the light-emitting structure EMS' can be interrupted or bent in the boundary region BDA or the region adjacent to the boundary region BDA by means of the separator SPR'. As a result, when the display panel DP is operating, the current flowing from each of the first sub-pixel SP1 to the third sub-pixel SP3 to its adjacent sub-pixel through the layer included in the light-emitting structure EMS' can be reduced. Therefore, the first light-emitting element LD1' to the third light-emitting element LD3' can operate with relatively high reliability.

[0210] In one embodiment, the light-emitting structure EMS' may include two light-emitting parts stacked sequentially, and each of the light-emitting parts may include a light-emitting layer configured to generate light according to an applied current. In another embodiment, the light-emitting structure EMS' may include three light-emitting parts stacked sequentially, and each of the light-emitting parts may include a light-emitting layer configured to generate light according to an applied current. In these embodiments, a charge-generating layer may be arranged between the light-emitting parts.

[0211] In the embodiments, the light-emitting structure EMS' can be formed by processes such as vacuum deposition and inkjet printing.

[0212] The cathode electrode CE can be arranged on the light-emitting structure EMS'. The cathode electrodes CE can be provided together in the first sub-pixel SP1 to the third sub-pixel SP3.

[0213] The first light-emitting element LD1' can be formed by the overlapping portions of the first anode electrode AE1', the light-emitting structure EMS', and the cathode electrode CE. The second light-emitting element LD2' can be formed by the overlapping portions of the second anode electrode AE2', the light-emitting structure EMS', and the cathode electrode CE. The third light-emitting element LD3' can be formed by the overlapping portions of the third anode electrode AE3', the light-emitting structure EMS', and the cathode electrode CE.

[0214] An encapsulation layer TFE is arranged on the cathode electrode CE. The encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL'.

[0215] An adhesive layer (APL), an optical functional layer (OFL), a protective layer (OC), and a cover window (CW) are disposed on the encapsulation layer (TFE). The adhesive layer (APL), optical functional layer (OFL), protective layer (OC), and cover window (CW) are respectively disposed on... Figure 7 The adhesive layer APL, optical functional layer OFL, protective layer OC, and cover window CW are all constructed in the same way. Further explanation of these will be omitted.

[0216] Figure 10 It is shown that it includes Figure 7 or Figure 8 A schematic cross-sectional view of an embodiment of a portion of a light-emitting structure in one of the first to third light-emitting elements.

[0217] Reference Figure 10 The light-emitting structure can have a tandem structure consisting of a first light-emitting part EU1 and a second light-emitting part EU2 stacked together. The light-emitting structure in... Figure 7 Each of the first light-emitting elements LD1 to the third light-emitting element LD3 can be substantially identical.

[0218] Each of the first light-emitting portion EU1 and the second light-emitting portion EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting portion EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting portion EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0219] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc., as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration as each other, or they may have different configurations.

[0220] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer, a hole blocking layer, etc., as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration as each other, or they may have different configurations.

[0221] A connecting layer, which can be provided in the form of a charge generation layer CGL, can be disposed between the first light-emitting part EU1 and the second light-emitting part EU2 to connect them to each other. In an embodiment, the charge generation layer CGL can have a stacked structure of p-type dopant layers and n-type dopant layers. For example, the p-type dopant layer can contain p-type dopants such as HAT-CN, TCNQ, NDP-9, etc., and the n-type dopant layer can contain alkali metals, alkaline earth metals, lanthanides, or combinations thereof. However, the embodiments are not limited thereto.

[0222] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 can generate light of different colors from each other. Light emitted from each of the first light-emitting layer EML1 and the second light-emitting layer EML2 can be mixed and identified as white light. For example, the first light-emitting layer EML1 can generate blue light, and the second light-emitting layer EML2 can generate yellow light. In an embodiment, the second light-emitting layer EML2 can include a structure consisting of a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light stacked together. The red light and the green light can be mixed to provide yellow light. In this case, an intermediate layer configured to perform the function of transmitting holes and / or blocking the transmission of electrons can also be arranged between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0223] In another embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 can generate light of the same color.

[0224] The luminescent structure can be formed by vacuum deposition, inkjet printing, etc., but the embodiments are not limited to these.

[0225] Figure 11 It is shown that it includes Figure 7 or Figure 8 A schematic cross-sectional view of another embodiment of a portion of a light-emitting structure in one of the first to third light-emitting elements.

[0226] Reference Figure 11 The light-emitting structure can have a series structure consisting of a first light-emitting part EU1' to a third light-emitting part EU3' stacked together. The light-emitting structure in Figure 7 Each of the first light-emitting elements LD1 to the third light-emitting element LD3 is substantially identical in composition.

[0227] Each of the first light-emitting portions EU1' to the third light-emitting portions EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting portion EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting portion EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting portion EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0228] Each of the first hole transport units HTU1' to the third hole transport units HTU3' may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc., as needed. The first hole transport units HTU1' to the third hole transport units HTU3' may have the same configuration as each other, or may have different configurations than each other.

[0229] Each of the first electron transport unit ETU1' to the third electron transport unit ETU3' may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer, a hole blocking layer, etc., as needed. The first electron transport unit ETU1' to the third electron transport unit ETU3' may have the same configuration as each other, or may have different configurations than each other.

[0230] The first charge generation layer CGL1' is disposed between the first light-emitting part EU1' and the second light-emitting part EU2'. The second charge generation layer CGL2' is disposed between the second light-emitting part EU2' and the third light-emitting part EU3'.

[0231] In this embodiment, the first light-emitting layer EML1' to the third light-emitting layer EML3' can generate light of different colors from each other. The light emitted from each of the first light-emitting layer EML1' to the third light-emitting layer EML3' can be mixed and identified as white light. For example, the first light-emitting layer EML1' can generate blue light, the second light-emitting layer EML2' can generate green light, and the third light-emitting layer EML3' can generate red light.

[0232] In another embodiment, two or more of the first light-emitting layers EML1' to the third light-emitting layers EML3' can generate light of the same color.

[0233] and Figure 10 and Figure 11 The difference is shown. Figure 7 or Figure 8 The light-emitting structure may also include a light-emitting part in each of the first light-emitting elements LD1, LD1' to the third light-emitting elements LD3, LD3'. In this case, the light-emitting parts included in each of the first light-emitting elements LD1, LD1' to the third light-emitting elements LD3, LD3' can be configured to emit light of different colors from each other. For example, the light-emitting parts of the first light-emitting elements LD1, LD1' can emit red light, the light-emitting parts of the second light-emitting elements LD2, LD2' can emit green light, and the light-emitting parts of the third light-emitting elements LD3, LD3' can emit blue light. In this case, the light-emitting parts of the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of them can be arranged in the pixel definition layer (see reference). Figure 7 PDL and Figure 8 The opening of the PDL' (refer to) Figure 7 OP and Figure 8 Within OP'). In this case, at least some of the color filters CF1 to CF3 can be omitted.

[0234] Figure 12 It is shown Figure 5 A schematic plan view of another embodiment of one of the pixels.

[0235] Reference Figure 12 The first pixel PXL1' may include the first sub-pixel SP1' to the third sub-pixel SP3'.

[0236] The first sub-pixel SP1' may include a first light-emitting region EMA1' and a non-light-emitting region NEA' surrounding the first light-emitting region EMA1'. The second sub-pixel SP2' may include a second light-emitting region EMA2' and a non-light-emitting region NEA' surrounding the second light-emitting region EMA2'. The third sub-pixel SP3' may include a third light-emitting region EMA3' and a non-light-emitting region NEA' surrounding the third light-emitting region EMA3'.

[0237] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged on the second direction DR2. The third sub-pixel SP3' can be arranged on the first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0238] The second sub-pixel SP2' can have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' can have a larger area than the second sub-pixel SP2'. Accordingly, the second light-emitting region EMA2' can have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' can have a larger area than the second light-emitting region EMA2'. However, the embodiments are not limited to this. For example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area as each other, and the third sub-pixel SP3' can have an area larger than each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thus, the areas of the first sub-pixel SP1' to the third sub-pixel SP3' can be varied according to the embodiments.

[0239] Figure 13 It is shown Figure 5 A schematic plan view of another embodiment of one of the pixels.

[0240] Reference Figure 13 The first pixel PXL1'' may include first sub-pixels SP1'' to third sub-pixels SP3''. The first sub-pixel SP1'' may include a first luminous region EMA1'' and a non-luminous region NEA'' surrounding the first luminous region EMA1''. The second sub-pixel SP2'' may include a second luminous region EMA2'' and a non-luminous region NEA'' surrounding the second luminous region EMA2''. The third sub-pixel SP3'' may include a third luminous region EMA3'' and a non-luminous region NEA'' surrounding the third luminous region EMA3''.

[0241] When viewed on DR3 from a third-party perspective, the first sub-pixel SP1" to the third sub-pixel SP3" can have a polygonal shape. For example, as Figure 13 As shown, the shapes of the first sub-pixel SP1" to the third sub-pixel SP3" can be hexagonal.

[0242] When viewed on a third-party DR3, the first luminous region EMA1" to the third luminous region EMA3" may have a circular shape. However, the embodiment is not limited to this. For example, each of the first luminous region EMA1" to the third luminous region EMA3" may have a polygonal shape.

[0243] The first sub-pixel SP1" and the third sub-pixel SP3" can be arranged in the first direction DR1. The second sub-pixel SP2" can be arranged relative to the first sub-pixel SP1" in a direction that is tilted at an acute angle (or diagonal direction) with the second direction DR2 as the reference.

[0244] Figure 6 , Figure 12 and Figure 13The arrangement of subpixels shown is exemplary, and the embodiment is not limited thereto. Each pixel may include more than two subpixels, and the subpixels may be arranged in a variety of ways, each of the subpixels may have multiple shapes, and each of its light-emitting regions may also have multiple shapes.

[0245] Figure 14 This is a schematic cross-sectional view illustrating an embodiment of the display device. Figure 15 This is a schematic cross-sectional view illustrating an embodiment of the lens. Figure 15 The lens PLS is arranged with Figure 14 The optical film OF is a lens that can contact the optical film OF, and it can correspond to one of the first lens PLS1 to the third lens PLS3. For example, lens PLS is a lens included in the pancake lens PK, and it can correspond to the first lens PLS1, or the second lens PLS2, or the third lens PLS3.

[0246] Reference Figure 14 The display device 100 may also include a pancake lens PK. A pancake lens, as a lens using folded optics, can refer to a lens structure in which multiple lenses and polarizing elements are overlapped. The number of lenses and polarizing elements in the pancake lens PK is not limited to a specific example, but for convenience, the following description will be based on an embodiment where the pancake lens PK includes three lenses PLS1, PLS2, and PLS3.

[0247] A pancake lens PK can be placed on the display surface DPSS of the display panel DP. The display surface DPSS can correspond to the surface from which light is emitted from the display panel DP.

[0248] The pancake lens PK may include a first lens PLS1, a second lens PLS2, a third lens PLS3, a half-reflective mirror HM, and an optical film OF. However, as mentioned above, this disclosure is not limited thereto; according to embodiments, the pancake lens PK may also include two or more lenses.

[0249] The first lens PLS1 can be arranged on the display panel DP with the third-direction DR3 as a reference. The first lens PLS1 can be arranged adjacent to the display surface DPSS of the display panel DP. For example, the first lens PLS1 can be arranged closer to the display surface DPSS of the display panel DP than the third lens PLS3. For example, the distance between the first lens PLS1 and the display surface DPSS can be shorter than the distance between the third lens PLS3 and the display surface DPSS.

[0250] The second lens PLS2 can be arranged on the first lens PLS1 with the third-direction DR3 as a reference. The second lens PLS2 can be arranged between the first lens PLS1 and the third lens PLS3.

[0251] The third lens PLS3 can be arranged on the second lens PLS2 with reference to the third-direction DR3. The third lens PLS3 can be arranged closer to the user's eyes of the display device 100. For example, the third lens PLS3 can be arranged closer to the user's eyes than the first lens PLS1. For example, the distance between the third lens PLS3 and the user's eyes can be shorter than the distance between the first lens PLS1 and the user's eyes.

[0252] Each of the first lens PLS1 to the third lens PLS3 may include at least one of plastic and glass. Each of the first lens PLS1 to the third lens PLS3 may have a structure consisting of a combination of a convex lens and a concave lens, including at least one of plastic and glass. Thus, the first lens PLS1 to the third lens PLS3 can magnify the image.

[0253] Reference Figure 15 At least one of the first lens PLS1 to the third lens PLS3 may have a curved surface PLSS. For example, at least one of the first lens PLS1 to the third lens PLS3 may have a curved surface PLSS. The PLSS may be the surface on which the optical film OF is attached when the optical film OF is disposed.

[0254] The curved surface of the lens PLS (e.g., the surface PLSS) may include curvature variation regions (CRS). According to an embodiment, the curvature variation regions (CRS) may correspond to regions including inflection points of curvature changes on the surface. Alternatively, according to an embodiment, the curvature variation regions (CRS) are regions where the curvature of the surface changes abruptly, for example, they may correspond to regions where the slope of the surface changes by more than 10°. According to an embodiment, the curvature variation regions (CRS) may be single or multiple, depending on the structure of the lens PLS.

[0255] Because one surface of the lens PLS is formed as a curved surface and includes a curvature variation region CRS, the display device 100 according to this disclosure can reduce the risk of changes in the chief ray angle (CRA). This improves the quality of the image provided to the user. For example, it reduces the risk of distortion and chromatic aberration in the image provided to the user.

[0256] The lens PLS may include a flange FL. The flange FL may be defined as a region separated from the outermost contour PLS_O of the edge (or edge) defined as the lens PLS by a predetermined distance. The distance may vary depending on the characteristics of the lens PLS (e.g., the size of the lens PLS), and the flange FL may refer to the region in the manufacturing process of the display device 100 where the manufacturing apparatus for manufacturing the display device 100 can be combined with the lens PLS.

[0257] Refer again Figure 14 The semi-reflective mirror HM can be arranged between the display panel DP and the first lens PLS1. The semi-reflective mirror HM can transmit light incident along the third direction DR3 (e.g., light incident from the lower part of the semi-reflective mirror HM) and can reflect light incident in the opposite direction along the third direction DR3 (e.g., light incident from the upper part of the semi-reflective mirror HM).

[0258] The optical film OF can be disposed on one surface of at least one of the first lenses PLS1 to the third lenses PLS3. The optical film OF can be attached (or bonded) to one surface of at least one of the first lenses PLS1 to the third lenses PLS3. For example, the optical film OF can be thermally bonded or attached (or bonded) to one surface of at least one of the first lenses PLS1 to the third lenses PLS3 through an adhesive layer.

[0259] Figure 14 The figure illustrates the case where the optical film OF is attached (or bonded) to the third lens PLS3. However, this disclosure is not limited thereto. According to the embodiments, the optical film OF can also be attached (or bonded) to the first lens PLS1 or to the second lens PLS2.

[0260] For example, the optical film OF can be attached (or bonded) to at least one of the lower surfaces PLS1_L of the first lens PLS1, PLS2_L of the second lens PLS2, and PLS3_L of the third lens PLS3. Alternatively, according to an embodiment, the optical film OF can also be attached (or bonded) to the upper surfaces of the first lens PLS1 to the third lens PLS3. The lower surfaces PLS1_L to PLS3_L of the first lens PLS1 to the third lens PLS3 can be defined as surfaces closer to the display panel DP arrangement, and the upper surfaces of the first lens PLS1 to the third lens PLS3 can be defined as surfaces further away from the display panel DP arrangement.

[0261] An optical film (OF) can be a polarizing layer. For example, an optical film OF may include at least one of a quarter-phase retardation layer, a linear polarizing layer, a reflective polarizing layer, and an absorptive polarizing layer. An optical film OF may be a film composed of at least two of the phase retardation layer, linear polarizing layer, reflective polarizing layer, and absorptive polarizing layer, or it may be a film composed of one of the phase retardation layer, linear polarizing layer, reflective polarizing layer, and absorptive polarizing layer.

[0262] A quarter-phase retardation layer can convert the polarization state of light passing through it from linearly polarized to circularly polarized, or vice versa. A linear polarization layer can make the polarization state of light passing through it linearly polarized. Each of the reflective polarization layer and the absorptive polarization layer can reflect or absorb a single component of light passing through each of the reflective polarization layer and the absorptive polarization layer.

[0263] Depending on the configuration of the optical film OF, the optical film OF can be configured as a single element in the pancake lens PK, or, according to an embodiment, multiple optical film OFs can be configured. When the optical film OF is configured as a single element, it can be disposed (or attached) to one surface of one of the first lenses PLS1 to the third lenses PLS3. When multiple optical film OFs are configured, they can be disposed (or attached) to at least two surfaces, the upper and lower surfaces, of the first lenses PLS1 to the third lenses PLS3.

[0264] According to the display device 100 of this disclosure, even when the optical film OF is arranged on a curved surface, the risk of air bubbles forming between the optical film OF and the lens PLS during the formation of the optical film OF can be reduced. Relatedly, reference will be made to... Figure 16 The following attached diagrams will illustrate this.

[0265] Figures 16 to 18 This is a schematic diagram illustrating the arrangement of the lens and optical film according to an embodiment. Figures 16 to 18 In the diagram, (A) is a plan view showing the arrangement of the lens and optical film according to an embodiment, and (B) is a cross-sectional view showing the arrangement of the lens and optical film according to an embodiment.

[0266] Reference Figure 16 The optical film OF can have a cut surface OF_CL. The cut surface OF_CL is a surface formed by cutting a portion OF_C of the optical film OF, and according to an embodiment, it can be planar. For example, when viewed in a planar plane, the cut surface OF_CL can have the shape of a straight line (e.g., a straight line). According to an embodiment, when viewed in a planar plane, the cut portion OF_C of the optical film OF can have an arcuate shape. For example, when viewed in a planar plane, the cut portion OF_C of the optical film OF can have a shape including curves and straight lines.

[0267] In the following, "plane" when "viewed on a plane" can be defined as a plane parallel to the display panel DP.

[0268] When viewed in a plane, the cut portion OF_C of the optical film OF can be arranged between the effective curvature diameter region DP_A and the flange portion FL of the lens PLS. For example, when viewed in a plane, the portion OF_C may not overlap with the effective curvature diameter region DP_A and the flange portion FL of the lens PLS.

[0269] The effective curvature diameter region DP_A of the lens PLS can correspond to the area where the display panel DP is arranged. For example, when viewed in a plane, the effective curvature diameter region DP_A of the lens PLS can completely overlap with the area where the display panel DP is arranged. For example, when viewed in a plane, the area and shape of the effective curvature diameter region DP_A of the lens PLS can correspond to (or be the same as) the area and shape of the display panel DP. The effective curvature diameter region DP_A can be changed according to the characteristics of the display panel DP.

[0270] When viewed in a planar surface, the optical film OF can completely overlap with the effective curvature diameter region DP_A. When viewed in a planar surface, the optical film OF can completely overlap with the display panel DP. When viewed in a planar surface, the optical film OF can have an area larger than the area of ​​the effective curvature diameter region DP_A. When viewed in a planar surface, the optical film OF can have an area larger than the area of ​​the display panel DP.

[0271] When viewed in a plane, the optical film OF can overlap with and be arranged throughout the region of maximum effective curvature PK_A. For example, when viewed in a plane, the optical film OF can be arranged extending from the center of the region of maximum effective curvature DP_A towards the outer contour of the region of maximum effective curvature PK_A. For example, when viewed in a plane, the optical film OF can be arranged further extending from the center of the region of maximum effective curvature DP_A towards the direction in which the region of maximum effective curvature PK_A is arranged along the direction of planar extension (e.g., a first direction DR1 or a second direction DR2).

[0272] When viewed in a plane, the optical film OF can extend to the outer contour of the region of maximum effective curvature PK_A, and at least a portion of the optical film OF can be arranged in the outer region of the region of maximum effective curvature PK_A. When viewed in a plane, the optical film OF can be arranged throughout the region of maximum effective curvature PK_A and can not overlap with a portion of the lens PLS. For example, the portion of the lens PLS that does not overlap with the optical film OF can correspond to the outermost contour PLS_O of the lens PLS. When viewed in a plane, the optical film OF can not overlap with the outermost contour PLS_O of the lens PLS.

[0273] The region of maximum effective curvature PK_A can correspond to (or be the same as) the area where an image is displayed to the user via the display device 100. For example, the region of maximum effective curvature PK_A can be the area where light emitted from the display panel DP passes through the pancake lens PK to display an image to the user's eye and make it recognizable. For example, the region of maximum effective curvature PK_A can correspond to the area through which the maximum amount of light transmitted from the display panel DP passes or the area through which light can be centered when the user acquires the image. When viewed on a plane, the region of maximum effective curvature PK_A can have a larger area than the region of effective curvature DP_A.

[0274] Reference Figure 17 The illustration shows an optical film OF' according to another embodiment. When compared with the optical film OF described above, the difference between the optical film OF' according to this embodiment and the optical film OF_CL' is that the cut surface OF_CL' is different. Therefore, content that may overlap with the above will be briefly described or will not be repeated.

[0275] According to an embodiment, the cut surface OF_CL' can be a curved surface. For example, when viewed in a plane, the cut surface OF_CL' can have the shape of a curved line (e.g., a curve). According to an embodiment, when viewed in a plane, the cut portion OF_C' of the optical film OF' can have the shape of a pattern comprising multiple curved surfaces.

[0276] Reference Figure 18 The illustration shows an optical film OF" according to another embodiment. When compared with the optical film OF described above, the difference between the optical film OF" according to this embodiment and the one described above is that the cut surface OF_CL" is different. Therefore, content that may overlap with the above will be briefly described or will not be repeated.

[0277] When viewed on a plane, the optical film OF" may include a first portion OF_P1 and a second portion OF_P2 protruding from the first portion OF_P1. The first portion OF_P1 may include a portion of the cut surface OF_CL", and the second portion OF_P2 may include the remaining portion of the cut surface OF_CL" not included in the first portion OF_P1.

[0278] The first portion OF_P1 may have a shape corresponding to the aforementioned optical films OF and OF'. According to an embodiment, when viewed in a plane, the second portion OF_P2 may have at least one shape selected from quadrilaterals, circles, and ellipses. When viewed in a plane, the shapes of the cut portions OF_C, OF_C', and OF_C" of the optical films OF, OF', and OF" according to this disclosure can be varied in the region arranged between the effective curvature diameter region DP_A and the flange portion FL.

[0279] When the second part OF_P2 has a quadrilateral shape when viewed in a plane, the cutting surface OF_CL" may include multiple planes. When the second part OF_P2 has at least one shape, either circular or elliptical, when viewed in a plane, the cutting surface OF_CL" may include both a plane and a curved surface. That is, the cutting surfaces OF_CL, OF_CL', and OF_CL" may include at least one of a plane and a curved surface.

[0280] exist Figures 16 to 18 The illustration depicts an embodiment where optical films OF, OF', and OF" are cut in only one region. For example, it illustrates a case where a single portion of the cut portion OF_C, OF_C', and OF_C" of the optical films OF, OF', and OF" is depicted. However, this disclosure is not limited thereto. According to embodiments, optical films OF, OF', and OF" may include multiple cut regions, and each of the multiple cut regions may also include cut surfaces OF_CL, OF_CL', and OF_CL".

[0281] When viewed on a plane, the cut surfaces OF_CL, OF_CL', and OF_CL" of the optical films OF, OF', and OF" can be arranged between the effective curvature diameter region DP_A and the flange portion FL, thereby reducing the risk of air bubbles being generated when the display device 100 according to the present disclosure forms the optical films OF, OF', and OF".

[0282] When optical films OF, OF', and OF" are directly attached (or bonded) to a curved surface without forming cut surfaces OF_CL, OF_CL', and OF_CL", air bubbles may penetrate into the edge areas of the optical films OF, OF', and OF" and thus reduce the reliability of the display device 100. For example, it may provide the user with a low-quality image.

[0283] Conversely, in the display device 100 according to the present disclosure, the optical films OF, OF', and OF" are formed such that the cut surfaces OF_CL, OF_CL', and OF_CL" of the optical films OF, OF', and OF" are arranged between the effective curvature diameter region DP_A and the flange portion FL when viewed in a plane, thereby reducing the risk of air bubbles being generated when the optical films OF, OF', and OF" are attached (or bonded) to the lens PLS.

[0284] Figure 19 This diagram shows the arrangement of an optical film, excluding the cut area, on a lens. Figure 20 This is a diagram showing the arrangement of an optical film, including the cut area, on a lens.

[0285] Reference Figure 19 If the optical film 111, excluding the cut area, is arranged on the lens PLS, and region S is examined, it can be confirmed that the edge S11 of the optical film 111 is wrinkled. This is due to the infiltration of air bubbles during the formation of the optical film 111, which may reduce the reliability of the display device 100.

[0286] On the other hand, refer to Figure 20 When optical films OF, OF', and OF" including the cut areas (e.g., the cut surfaces OF_CL, OF_CL', and OF_CL") are arranged on the lens PLS, if region S' is checked, it can be confirmed that no wrinkles occur at the edges of the optical films OF, OF', and OF" . Therefore, it can be confirmed that the optical films OF, OF', and OF" according to this disclosure reduce the risk of bubble penetration during the formation of the optical films OF, OF', and OF" .

[0287] Furthermore, according to the display device 100 of this disclosure, even without separately arranged markings for identifying the polarization axes on the optical films OF, OF', and OF" the polarization axes can be confirmed. For example, when the cut surfaces OF_CL, OF_CL', and OF_CL" of the optical films OF, OF', and OF" are formed, the polarization axes of the optical films OF, OF', and OF" can be confirmed using the angle information formed by the cut surfaces OF_CL, OF_CL', and OF_CL" with the polarization axes. For example, if the cutting surfaces OF_CL, OF_CL', and OF_CL" of the optical films OF, OF', and OF" are formed such that the cutting surfaces OF_CL, OF_CL', and OF_CL" are arranged parallel to the polarization axes of the optical films OF, OF', and OF", then if the direction in which the cutting surfaces OF_CL, OF_CL', and OF_CL" are arranged is determined, then the direction in which the polarization axes of the optical films OF, OF', and OF" are arranged can be determined.

[0288] The following will refer to Figure 21 The manufacturing method of the display device 100 will be described. Content that may overlap with the above will be briefly described or will not be repeated.

[0289] Figure 21 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment. (Refer to...) Figure 21 The manufacturing method of the display device 100 according to the embodiment may include step S100 of forming a display panel and step S200 of forming a pancake lens on the display panel.

[0290] Reference Figure 21 , combined Figures 1 to 13 The step S100 of forming a display panel may include the following steps: forming a pixel circuit layer PCL on a substrate SUB; forming a light-emitting element LD; and forming an encapsulation layer TFE.

[0291] In the step of forming a pixel circuit layer PCL on a substrate SUB, circuit elements can be patterned on the substrate SUB, and a pixel circuit layer PCL can be provided.

[0292] According to embodiments, the conductive layer and insulating layer on the substrate SUB can be formed based on general processes used for manufacturing semiconductor devices. For example, the conductive layer or insulating layer on the substrate SUB can be formed by photolithography, etched by various methods (wet etching, dry etching, etc.), and deposited by various methods (sputtering, chemical vapor deposition, etc.). This disclosure is not necessarily limited to specific examples.

[0293] In the step of forming the pixel circuit layer PCL on the substrate SUB, transistors T_SP1 to T_SP3 can be patterned on the substrate SUB. Then, a via layer VIAL can be disposed on the pixel circuit layer PCL. Furthermore, according to an embodiment, first reflective electrodes RE1 to third reflective electrodes RE3 can be patterned on the via layer VIAL, and according to an embodiment, a planarization layer PLNL can be disposed on the via layer VIAL.

[0294] Reference Figure 21 , combined Figures 7 to 9 In the step of forming the light-emitting element LD, an anode electrode (i.e., the first anode electrode AE1, AE1' to the third anode electrode AE3, AE3'), a light-emitting structure EMS, EMS', and a cathode electrode CE can be formed to form the first light-emitting element LD1, LD1' to the third light-emitting element LD3, LD3'.

[0295] In the step of forming the light-emitting element LD, the first anode electrodes AE1, AE1' to the third anode electrodes AE3, AE3' can be patterned, and the pixel definition layers PDL, PDL' overlapping with the first anode electrodes AE1, AE1' to the third anode electrodes AE3, AE3' can be patterned.

[0296] According to the embodiments (refer to) Figure 7 (etc.), as separators SPR, trenches TRCH1 and TRCH2 can be formed, and a light-emitting structure EMS can be formed. In this case, at least a portion of the light-emitting structure EMS can be disconnected. Furthermore, a cathode electrode CE can be formed on the light-emitting structure EMS.

[0297] In the step of forming the encapsulation layer TFE, the encapsulation layer TFE can be formed on the light-emitting element LD. The underlying layer of the encapsulation layer TFE can be passivated.

[0298] Subsequently, according to the embodiment, a color filter layer CFL, an optical functional layer OFL, a protective layer OC, and a cover window CW can be arranged, and a display panel DP according to the embodiment can be provided.

[0299] Reference Figure 21 , combined Figures 14 to 18 The step S200 of forming the pancake lens includes the following steps: arranging a first lens PLS1, a second lens PLS2, and a third lens PLS3; arranging a semi-reflective mirror HM; and arranging an optical film OF, OF', and OF" on one surface of at least one of the first lenses PLS1 to the third lenses PLS3. At least one of the first lenses PLS1 to the third lenses PLS3 with an optical film OF can correspond to the aforementioned lens PLS.

[0300] The semi-reflective mirror HM, the first lens PLS1, the second lens PLS2, and the third lens PLS3 can be arranged sequentially on the display panel DP, but this disclosure is not limited thereto.

[0301] The step of arranging the optical film OF may include forming an optical film OF, OF', OF" on one surface of at least one of the first lens PLS1 to the third lens PLS3.

[0302] Reference Figures 16 to 18The step of forming optical films OF, OF', and OF" may include removing a portion of the base optical film OF_C, OF_C', and OF_C"". The step of removing a portion of the base optical film OF_C, OF_C', and OF_C" may include cutting a portion of the base optical film OF_C, OF_C', and OF_C" to form optical films OF, OF', and OF" with cut surfaces OF_CL, OF_CL', and OF_CL"". The portion of the base optical film OF_C, OF_C', and OF_C" may be cut by a laser or a knife, etc.

[0303] The base optical film is the optical film before it is cut. When viewed in a plane, the base optical film can have an area larger than the region of maximum effective diameter of curvature PK_A, and an area smaller than that of the lens PLS. For example, when viewed in a plane, the base optical film can completely overlap with the region of maximum effective diameter of curvature PK_A, but not with a region of the lens PLS. For example, the base optical film can not overlap with the outermost contour PLS_O of the lens PLS.

[0304] The step of forming optical films OF, OF', and OF" may include laminating the cut optical films OF, OF', and OF" onto a surface PLSS of a lens PLS. The lamination step may include attaching the optical films OF, OF', and OF" to the surface PLSS of the lens PLS by heat or by attaching the optical films OF, OF', and OF" to the surface PLSS of the lens PLS using an adhesive layer. The adhesive layer may include at least one of pressure-sensitive adhesive (PSA) and optically clear adhesive (OCA).

[0305] Figure 22 This is a block diagram illustrating an embodiment of the display system.

[0306] Reference Figure 22 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0307] The processor 1100 can perform various tasks and calculations. In embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to and control other components of the display system 1000 via a bus system.

[0308] Figure 22 The diagram illustrates a display system 1000 including a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0309] The processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 via the first channel CH1. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be connected to a reference... Figure 1 The display device 100 described herein is configured similarly. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as follows: Figure 1 The input image data is IMG and the control signal is CTRL.

[0310] The processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 via the second channel CH2. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be connected to a reference... Figure 1 The display device 100 described herein is configured similarly. In this case, the second image data IMG2 and the second control signal CTRL2 can be provided as follows: Figure 1 The input image data is IMG and the control signal is CTRL.

[0311] Display system 1000 may include computing systems that provide image display capabilities, such as portable computers, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs). Furthermore, display system 1000 may include at least one of head-mounted display devices (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0312] Figure 23 It is shown Figure 22 A schematic 3D diagram illustrating an application example of the display system.

[0313] Reference Figure 23 , Figure 22 The display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0314] The head-mounted display device 2000 may include a headband 2100 and a display device storage case 2200. The headband 2100 may be connected to the display device storage case 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to a user's head. The horizontal strap may be configured to surround the side of the user's head, and the vertical strap may be configured to surround the upper part of the user's head. However, the embodiments are not limited to this. For example, the headband 2100 may also be implemented in the form of an eyeglass frame, a helmet, etc.

[0315] The display device storage box 2200 can store... Figure 22 The first display device 1210 and the second display device 1220. The display device storage box 2200 can also store... Figure 22 The processor is 1100.

[0316] Figure 24 It is shown Figure 23 A schematic diagram of a head-mounted display device worn by a user.

[0317] Reference Figure 24 The head-mounted display device 2000 includes a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0318] Within the display device housing 2200, the right eye lens RLNS can be positioned between the first display panel DP1 and the user's right eye. Within the display device housing 2200, the left eye lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0319] The image output from the first display panel DP1 can be seen by the user's right eye through the right eye lens RLNS. The right eye lens RLNS refracts light from the first display panel DP1 so that it is directed towards the user's right eye. The right eye lens RLNS performs an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0320] The image output from the second display panel DP2 can be seen by the user's left eye through the left eye lens LLNS. The left eye lens LLNS refracts light from the second display panel DP2 towards the user's left eye. The left eye lens LLNS performs an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0321] In one embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a pancake-shaped cross-section (e.g., the pancake lens PK described above). In another embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions having different optical properties from each other. In this case, each display panel can output an image corresponding to a sub-region of the multi-channel lens, and the output image can be viewed by the user through the respective sub-region.

[0322] While specific embodiments and application examples have been described herein, other embodiments and variations can be derived from the foregoing description. Therefore, the concept of the invention is not limited to these embodiments, but also includes the claims, various obvious variations and equivalents.

Claims

1. A display device, comprising: Display panel; as well as A pancake lens is arranged on the display panel. The pancake lens includes: Lenses; and An optical film is disposed on one surface of the lens. The optical film has a cut surface formed by cutting a portion of it. When viewed on a flat surface, the cut surface does not overlap with the display panel.

2. The display device according to claim 1, wherein, The surface of the lens is curved.

3. The display device according to claim 2, wherein, The optical film is attached to one surface of the lens. The surface includes regions of varying curvature. The curvature change region corresponds to the region including the inflection point of the curvature change of the surface, or to the region where the slope of the surface changes by more than 10°.

4. The display device according to claim 1, wherein, When viewed from a flat surface, the optical film completely overlaps with the display panel but does not overlap with a portion of the lens.

5. The display device according to claim 4, wherein, The aforementioned portion of the region corresponds to the outermost contour of the lens.

6. The display device according to claim 1, wherein, When viewed from a plane, the cut surface is arranged between the effective diameter region of the lens's curvature and the lens's flange. When viewed from a plane, the effective radius of curvature corresponds to the area where the display panel is arranged. The flange corresponds to a region spaced a predetermined distance from the outermost edge of the lens.

7. The display device according to claim 1, wherein, The optical film includes a first portion and a second portion that protrudes from the first portion when viewed in a plane. When viewed on a plane, the second part has at least one shape among a circle, a quadrilateral, and an ellipse.

8. The display device according to claim 1, wherein, The optical film is thermally bonded to one surface of the lens or attached to one surface of the lens via an adhesive layer.

9. The display device according to claim 1, wherein, The lens includes at least one of plastic and glass. The optical film is a polarizing layer. The display panel includes organic light-emitting diodes.

10. A display system, comprising: Display panel; as well as A pancake lens is arranged on the display panel. The pancake lens includes: Lenses; and An optical film is disposed on one surface of the lens. Wherein, one surface of the lens is a curved surface. The optical film has a cut surface formed by cutting a portion of it. When viewed in a plane, the cut surface is positioned between the effective diameter region of the lens's curvature and the lens's flange. When viewed on a plane, the effective radius of curvature corresponds to the area where the display panel is arranged. The flange corresponds to a region spaced a predetermined distance from the outermost edge of the lens.

Images