Display device and driving method thereof

Abstract

A display device includes: a display panel, the display panel including: a sub-pixel; a gate driver connected to the sub-pixel; and a voltage control circuit including at least one control transistor controlled based on operation of the gate driver, wherein each of the sub-pixels includes a first capacitor and a second capacitor, one end of the first capacitor is connected to the gate electrode of a driving transistor, and the other end of the first capacitor is connected to a first node defined as a second electrode of the driving transistor, one end of the second capacitor is connected to an output terminal of the voltage control circuit, and the other end of the second capacitor is connected to the first node, and the at least one control transistor is turned on based on the operation of the gate driver to apply a reference voltage to the sub-pixel.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0196942, filed on December 26, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to a display device and a driving method thereof. Background Technology

[0003] With the development of information technology, the market for display devices used to convey information to users is growing. As a result, the use of display devices such as light-emitting diode (LED) devices, quantum dot (QDD) devices, and liquid crystal display (LCD) devices is increasing.

[0004] The aforementioned display device includes: a display panel comprising sub-pixels; a driver that outputs drive signals for driving the display panel; and a power supply that generates power to be supplied to the display panel or the driver.

[0005] When drive signals such as scan signals and data signals are supplied to the sub-pixels formed on the display panel, the aforementioned display device can display an image by emitting light from the selected sub-pixels or by emitting light directly. Summary of the Invention

[0006] Therefore, this disclosure relates to a display device and a driving method thereof, which substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0007] The purpose of this disclosure is to solve the problems (voltage noise and brightness deviation, etc.) caused by high-level voltage deviation (EVDD deviation due to IR voltage drop) within the display panel by sequentially applying a reference voltage to the horizontal line of the display panel.

[0008] Another objective of this disclosure is to simplify the circuitry included in the sub-pixels and improve aperture ratio and lifespan by integrating the circuitry for applying a reference voltage to the horizontal lines of the display panel into the scan signal generator or by setting the circuitry adjacent to the scan signal generator.

[0009] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the description, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel including sub-pixels; a gate driver connected to the sub-pixels; and a voltage control circuit including at least one control transistor controlled based on operation of the gate driver, wherein each of the sub-pixels includes a first capacitor and a second capacitor, one end of the first capacitor being connected to the gate electrode of the driving transistor and the other end of the first capacitor being connected to a first node defined as a second electrode of the driving transistor, one end of the second capacitor being connected to an output terminal of the voltage control circuit and the other end of the second capacitor being connected to the first node, and wherein the at least one control transistor is turned on based on operation of the gate driver to apply a reference voltage to the sub-pixel.

[0011] The gate driver may include: a first scan signal generator configured to generate a first scan signal; a second scan signal generator configured to generate a second scan signal; a third scan signal generator configured to generate a third scan signal; and a fourth scan signal generator configured to generate a fourth scan signal, wherein the at least one control transistor is turned on based on the operation of the fourth scan signal generator to apply the reference voltage to the sub-pixel.

[0012] The fourth scan signal may not be applied to the sub-pixel.

[0013] The at least one control transistor may include a first control transistor having a gate electrode connected to the output terminal of the fourth scan signal generator, a first electrode connected to a reference voltage line, and a second electrode connected to one end of the second capacitor, the reference voltage being transmitted through the reference voltage line.

[0014] The first control transistor can be turned on during a period when the voltage of the Q node of the fourth scan signal generator is low.

[0015] The fourth scan signal generator may include: a first transistor having a gate electrode connected to the Q node, a first electrode connected to a gate low voltage line, and a second electrode connected to the output terminal; a second transistor having a gate electrode connected to a QB node operating opposite to the Q node, a first electrode connected to a gate high voltage line, and a second electrode connected to the output terminal; and a node control circuit configured to control the Q node and the QB node.

[0016] The at least one control transistor may include a first control transistor having a gate electrode connected to the QB node of the gate driver, a first electrode connected to a reference voltage line, and a second electrode connected to one end of the second capacitor, the reference voltage being transmitted through the reference voltage line.

[0017] The first control transistor can be turned on during a period when the voltage of the QB node of the fourth scan signal generator is low.

[0018] For the gate line, based on the operation of the voltage control circuit, the reference voltage can be sequentially applied to one end of the second capacitor.

[0019] In another aspect of this disclosure, a method for driving a display device includes: a display panel including sub-pixels; a gate driver connected to the sub-pixels; and a voltage control circuit including at least one control transistor controlled based on operation of the gate driver. The method includes: an initialization step of initializing nodes of the sub-pixels; a sampling step of sampling a threshold voltage of a driving transistor included in the sub-pixels; a data voltage writing step of applying a data voltage to the sub-pixels; and a light emission step of causing the sub-pixels to emit light, wherein the voltage control circuit is turned on based on operation of the gate driver to apply a reference voltage to the sub-pixels during the initialization step, the sampling step, and the data voltage writing step.

[0020] Each of the sub-pixels includes a first capacitor and a second capacitor, one end of the first capacitor being connected to the gate electrode of a driving transistor and the other end being connected to a first node defined as the second electrode of the driving transistor, one end of the second capacitor being connected to the output terminal of the voltage control circuit and the other end being connected to the first node, and wherein the reference voltage is applied to the one end of the second capacitor.

[0021] For each gate line, based on the operation of the voltage control circuit, the reference voltage is sequentially applied to one end of the second capacitor.

[0022] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the figures: Figure 1 This is a schematic diagram illustrating the display device; Figure 2 This is a block diagram illustrating the configuration of the gate driver in a display device; Figure 3 This is a schematic diagram showing some of the components included in the sub-pixel and the voltage control circuit for controlling the output of the reference voltage according to the first embodiment; Figure 4 This is a schematic diagram showing a voltage control circuit according to a first embodiment and a shift register that controls the voltage control circuit; Figure 5 It shows Figure 4 The driving waveform of the shift register shown; Figure 6 This is a circuit configuration diagram of the sub-pixels according to the second embodiment; Figure 7 It shows Figure 6 The driving waveform of the sub-pixel shown; Figure 8 This is a schematic diagram showing a voltage control circuit according to a second embodiment and a shift register that controls the voltage control circuit; Figure 9 It shows Figure 8 The driving waveform of the shift register shown; Figure 10 and Figure 11 It shows according to Figure 8 A diagram showing the voltage control circuit and the operating state of the shift register, representing the driving waveform. Figure 12 This is a schematic diagram showing a voltage control circuit according to a third embodiment and a shift register that controls the voltage control circuit; Figure 13 It shows Figure 12 The driving waveform of the shift register shown; and Figure 14 and Figure 15 It shows according to Figure 13 The diagram shows the voltage control circuit and the operating state of the shift register, along with the driving waveform. Detailed Implementation

[0024] The display device according to this disclosure can be implemented as a light-emitting display (LED) device, a quantum dot display (QDD) device, etc. However, for ease of description, the following description will take a light-emitting display device based on direct light emission from inorganic light-emitting diodes or organic light-emitting diodes as an example.

[0025] Furthermore, the light-emitting display device described below can be implemented using n-type thin-film transistors, p-type thin-film transistors, or a combination of n-type and p-type thin-film transistors. A thin-film transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a thin-film transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers are released in the thin-film transistor. In other words, charge carriers flow from the source to the drain in a thin-film transistor.

[0026] In the case of a p-type thin-film transistor (TFT), the charge carriers are holes, so the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. Since holes flow from the source to the drain in a p-type TFT, current flows from the source to the drain. On the other hand, in the case of an n-type TFT, the charge carriers are electrons, so the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. Since electrons flow from the source to the drain in an n-type TFT, current flows from the drain to the source. However, the source and drain of a TFT can be changed depending on the applied voltage. With this in mind, in the following description, one of the source and drain is described as the first electrode, and the other is described as the second electrode.

[0027] Figure 1 This is a schematic block diagram of the display device. Figure 2 This is a block diagram illustrating the configuration of the gate driver in a display device.

[0028] like Figure 1 As shown, the display device 10 may include: a display panel 100, the display panel 100 including a plurality of sub-pixels P; a controller 200; a gate driver 300, the gate driver 300 supplying gate signals to the plurality of sub-pixels P; a data driver 400, the data driver 400 supplying data signals (or data voltages) to the plurality of sub-pixels P; and a power supply 500, the power supply 500 supplying power to the plurality of sub-pixels P.

[0029] The display panel 100 may include an active area for setting multiple sub-pixels P (see reference). Figure 2 The active region AA and the passive region (see reference AA) are configured to surround the active region AA and have the gate driver 300 and data driver 400 disposed therein. Figure 2 (NA in the text).

[0030] In the display panel 100, multiple gate lines GL and multiple data lines DL intersect each other, and multiple sub-pixels P can be connected to the gate lines GL and data lines DL. Specifically, a sub-pixel P can receive a gate signal from the gate driver 300 through the gate line GL, receive a data voltage (data signal) from the data driver 400 through the data line DL, and receive a high-level voltage EVDD and a low-level voltage EVSS from the power supply 500.

[0031] Gate line GL can transmit scan signals SC and light emission control signals EM to multiple sub-pixels P, and data line DL can transmit data voltage Vdata to multiple sub-pixels P. According to various embodiments, gate line GL may include multiple scan lines SCL for supplying the scan signals SC and multiple light emission control lines EML for supplying the light emission control signals EM. Multiple sub-pixels P can receive voltages Vref and Var from multiple voltage lines VL. The voltages Vref and Var applied through the multiple voltage lines VL will be described below.

[0032] Each of the multiple sub-pixels P may include a sub-pixel driving circuit. The sub-pixel driving circuit may include multiple switching elements, driving elements, capacitors, etc. The switching elements and driving elements may be configured as thin-film transistors. The switching transistors can be switched according to the scan signal SC supplied through the scan line SCL and the light emission control signal EM supplied through the light emission control line EML. The driving transistors can control the amount of current supplied to the light-emitting element OLED according to the data voltage Vdata (emission control).

[0033] The display panel 100 can be implemented as a non-transparent display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 can also be implemented as a flexible display panel. A flexible display panel can use a plastic substrate. Multiple sub-pixels P can be divided into red sub-pixels, green sub-pixels, and blue sub-pixels for color representation. The multiple sub-pixels P may also include white sub-pixels.

[0034] A touch sensor can be disposed on the display panel 100. Touch input can be sensed using a separate touch sensor or by multiple subpixels P. The touch sensor can be implemented as an on-cell or additional type touch sensor and disposed on the screen of the display panel, or it can be implemented as an in-cell type touch sensor built into the display panel 100.

[0035] The controller 200 can process externally input image data (RGB), making the image data (RGB) suitable for the size and resolution of the display panel 100, and supply it to the data driver 400. The controller 200 can use externally input synchronization signals (e.g., clock signal CLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) to generate a gate control signal GCS and a data control signal DCS. The controller 200 can control the operating timing of the gate driver 300 by supplying the gate control signal GCS to the gate driver 300. The controller 200 can control the operating timing of the data driver 400 by supplying the data control signal DCS to the data driver 400. The controller 200 can use the gate control signal GCS and the data control signal DCS to synchronize the operating timing of the gate driver 300 with the operating timing of the data driver 400.

[0036] Depending on the device to be installed in the display device, the controller 200 can be configured to be combined with various processors, such as microprocessors, mobile processors, and application processors. The host system located in front of the controller 200 can be any of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system.

[0037] The controller 200 can multiply the input frame frequency by i and control the operation timing of the display panel driver at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency can be 60 Hz in the case of NTSC (National Television Standards Committee) and 50 Hz in the case of PAL (Progressive Line Inversion).

[0038] The controller 200 can drive the display panel 100 at various refresh rates. The controller 200 can drive the display panel 100 in variable refresh rate (VRR) mode, that is, in a mode where the display panel 100 can switch between a first refresh rate and a second refresh rate.

[0039] For example, controller 200 can drive display panel 100 at various refresh rates by simply changing the frequency of the clock signal, configuring the synchronization signal to generate horizontal or vertical blanking, or driving gate driver 300 in a mask manner. Vertical blanking can be defined as a period of time used to match the input timing of data signals and the output (display) timing of images on the display panel. Vertical blanking can repeat within a frame period, and various signals used for the operation of the display device can be synchronized during this period.

[0040] The voltage level of the gate control signal GCS output from controller 200 can be converted into gate low voltages VGL and VEL and gate high voltages VGH and VEH by a level shifter (not shown), and supplied to gate driver 300. The level shifter can convert the low level voltage of the gate control signal GCS into gate low voltages VGL and VEL, and the high level voltage of the gate control signal GCS into gate high voltages VGH and VEH. The gate control signal GCS may include a start pulse and a shift clock.

[0041] The gate driver 300 can supply a gate signal to the gate line GL according to the gate control signal GCS supplied from the controller 200. The gate driver 300 can be disposed on one or both sides of the display panel 100 with the gate integrated into the panel.

[0042] The gate driver 300 can sequentially output gate signals to multiple gate lines GL under the control of the controller 200. The gate driver 300 can use a shift register to shift the gate signals to sequentially supply signals to the gate lines GL.

[0043] The gate signals may include a scan signal SC and a light emission control signal EM in an organic light-emitting display device. The scan signal SC may include a scan pulse that oscillates between a first gate low voltage VGL and a first gate high voltage VGH. The light emission control signal EM may include a light emission control signal pulse that oscillates between a second gate low voltage VEL and a second gate high voltage VEH. The scan pulse may be used to select the sub-pixel P of the row to which data voltage Vdata is to be written. The light emission control signal EM may define the light emission time of the sub-pixel P.

[0044] The gate driver 300 may include a light emission control signal driver 310 and at least one scan driver 320. The light emission control signal driver 310 may output a light emission control signal pulse in response to a start pulse and a shift clock from the controller 200, and may shift the light emission control signal pulse sequentially according to the shift clock. At least one scan driver 320 may output a scan pulse in response to a start pulse and a shift clock from the controller 200, and may shift the scan pulse at a timing according to the shift clock.

[0045] The data driver 400 can convert image data RGB into data voltage Vdata according to the data control signal DCS supplied from the controller 200, and output the converted data voltage Vdata through the data line DL.

[0046] although Figure 1The diagram shows a data driver 400 positioned on one side of the display panel 100, but the number and location of the data drivers 400 are not limited thereto. That is, the data drivers 400 can be configured as multiple integrated circuits (ICs) and positioned separately on one side of the display panel 100.

[0047] Power supply 500 can use a DC-DC converter to generate the DC power required to drive the subpixel array and display panel driver of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, and boost converter. Power supply 500 can receive a DC input voltage applied from a host system (not shown) and generate various types of DC voltages VGL / VEL, VGH / VEH, EVDD, and EVSS.

[0048] like Figure 1 and Figure 2 As shown, the gate driver 300 may include a light emission control signal driver 310 and a scan driver 320. The scan driver 320 may include first to fourth scan drivers 321, 322, 323, and 324. The first scan driver 321 may include odd-numbered first scan driver 321_O and even-numbered first scan driver 321_E. The light emission control signal driver 310 may include a first light emission control signal driver 311 and a second light emission control signal driver 312.

[0049] The shift registers constituting the gate driver 300 can be configured symmetrically on both sides of the active region AA. The shift registers on one side may include first scan drivers 321_O and 321_E, second scan driver 322 and third scan driver 323, and the shift registers on the other side may include fourth scan driver 324, first light emission control signal driver 311 and second light emission control signal driver 312.

[0050] At the same time, Figure 2 In the example, the odd-numbered first scan driver 321_O and the even-numbered first scan driver 321_E are examples of cases where odd-numbered sub-pixels and even-numbered sub-pixels share the first scan driver 321. Therefore, the drivers included in the gate driver 300 can be configured differently, and are not limited to this.

[0051] The shift register stages STG1 to STGn may include first scan signal generators SC1_O(1) to SC1_O(n) and SC1_E(1) to SC1_E(n), second scan signal generators SC2(1) to SC2(n), third scan signal generators SC3(1) to SC3(n), fourth scan signal generators SC4(1) to SC4(n), first light emission control signal generators EM1(1) to EM1(n) and second light emission control signal generators EM2(1) to EM2(n).

[0052] The first scan signal generators SC1(1) to SC1(n) can output first scan signals SC1(1) to SC1(n) through the first scan line SC1 of the display panel 100. The second scan signal generators SC2(1) to SC2(n) can output second scan signals SC2(1) to SC2(n) through the second scan line SC2 of the display panel 100. The third scan signal generators SC3(1) to SC3(n) can output third scan signals SC3(1) to SC3(n) through the third scan line SC3 of the display panel 100. The fourth scan signal generators SC4(1) to SC4(n) can output fourth scan signals SC4(1) to SC4(n) through a line connected to the voltage control circuit (described below). The first light emission control signal generators EM1(1) to EM1(n) can output first light emission control signals EM1(1) to EM1(n) through the first light emission control line EM1 of the display panel 100. The second light emission control signal generators EM2(1) to EM2(n) can output the second light emission control signals EM2(1) to EM2(n) through the second light emission control line EM2 of the display panel 100.

[0053] A reference voltage line VrefL and an initialization voltage line VaralL can be provided between the gate driver 300 and the active region AA. The reference voltage Vref is transmitted through the reference voltage line VrefL, and the initialization voltage Varal is transmitted through the initialization voltage line VaralL. In the accompanying drawings, the reference voltage line VrefL and the initialization voltage line VaralL are shown as being located to the left and right of the active region AA, but are not limited thereto.

[0054] One or more optical regions OA1 and OA2 can be disposed within the active region AA. Optical regions OA1 and OA2 can be configured to overlap with one or more optoelectronic devices, such as imaging devices (e.g., cameras (image sensors)) and detection sensors (e.g., proximity sensors or illuminance sensors). Optical regions OA1 and OA2 can have light-transmitting structures formed therein to provide a certain level or higher transmittance for the operation of the optoelectronic devices. In other words, the number of sub-pixels P per unit area in optical regions OA1 and OA2 can be less than the number of sub-pixels P per unit area in the general area of ​​the active region AA excluding optical regions OA1 and OA2. In other words, the resolution of optical regions OA1 and OA2 can be lower than the resolution of the general area in the active region AA.

[0055] In optical regions OA1 and OA2, the light-transmitting structure can be formed by patterning a cathode in the region where no sub-pixel P is set. In this case, the cathode to be patterned can be removed using a laser, or the cathode can be selectively formed and patterned using a material such as a cathode deposition prevention layer.

[0056] Furthermore, the light-transmitting structures in optical regions OA1 and OA2 can be formed by separately forming the light-emitting element and sub-pixel driving circuit included in sub-pixel P. In other words, the light-emitting element of sub-pixel P can be located on optical regions OA1 and OA2, multiple transistors constituting the sub-pixel driving circuit can be disposed around optical regions OA1 and OA2, and the light-emitting element and sub-pixel driving circuit can be electrically connected through a transparent metal layer.

[0057] Figure 3 This is a schematic diagram showing some of the components included in the voltage control circuit for controlling the output of the reference voltage according to the first embodiment. Figure 4 This is a schematic diagram showing a voltage control circuit according to the first embodiment and a shift register for controlling the voltage control circuit, and Figure 5 It shows Figure 4 The driving waveform of the shift register is shown.

[0058] like Figure 3 As shown, the Nth sub-pixel P(n) according to the first embodiment may include a first transistor T1, a switching transistor T5, a first capacitor CST, a second capacitor CA, and a light-emitting element OLED.

[0059] The first transistor T1 can be implemented as an n-type transistor. The n-type first transistor T1 operates based on a data voltage that is applied as a high voltage and can generate a driving current that will be supplied to the light-emitting element OLED. The first transistor T1 can be defined as a driving transistor.

[0060] The switching transistor T5 can be implemented as a p-type transistor. The p-type switching transistor T5 operates based on a first light-emitting control signal EM1 applied at a low voltage, and can transmit a high-level voltage EVDD to the first transistor T1. The switching transistor T5 can be defined as a light-emitting control transistor.

[0061] The first capacitor CST can store the data voltage to be applied to the gate electrode of the first transistor T1. The second capacitor CA can store a reference voltage to uniformly compensate for the data voltage stored in the first capacitor CST across the entire display panel (or across all sub-pixels). The light-emitting element OLED can emit light in response to a drive current generated based on the operation of the first transistor T1 and the switching transistor T5.

[0062] As described above, the Nth sub-pixel P(n) can be implemented based on two types of transistors, and may also include circuitry for compensating the first transistor T1 or the light-emitting element OLED. Therefore, the circuitry included in the Nth sub-pixel P(n) can be implemented in various ways, and thus... Figure 3 It should be called an example.

[0063] The Nth sub-pixel P(n) can be connected to an Nth voltage control circuit VrefC(n) that controls the output of a reference voltage (controlling whether a reference voltage is applied). The Nth voltage control circuit VrefC(n) can include an Nth control transistor TC(n), which is turned on or off such that a reference voltage transmitted through the reference voltage line VrefL is applied to or not applied to the sub-pixel P. A reference voltage can be applied to sample the threshold voltage of the first transistor T1. As an example, the Nth control transistor TC(n) is shown as a p-type transistor, but it can also be implemented as an n-type transistor.

[0064] The Nth control transistor TC(n) may have a gate electrode connected to the Nth control scan line CS(n) to which the Nth control scan signal is applied, a first electrode connected to the reference voltage line VrefL for transmitting the reference voltage, and a second electrode connected to one end of the second capacitor CA included in the Nth sub-pixel P. In other words, the output terminal of the Nth voltage control circuit VrefC(n) may be connected to one end of the second capacitor CA included in the Nth sub-pixel P.

[0065] Meanwhile, a voltage control circuit, including the Nth voltage control circuit VrefC(n), can be configured for each gate line to apply a reference voltage to each sub-pixel of each horizontal line. Therefore, n in the Nth voltage control circuit VrefC(n) and the Nth control transistor TC(n) can be any number, and the arbitrary number n can be increased or decreased by at least 1 relative to the gate line to which the Nth sub-pixel P(n) is connected.

[0066] In the following text, for ease of description, the expression "Nth" will be omitted, and the component will be described as a single unit.

[0067] like Figure 4 As shown, the voltage control circuit VrefC(n) according to the first embodiment can be linked to the fourth scan signal generator SC4(n) included in the shift register. The voltage control circuit VrefC(n) can be turned on or off based on the fourth scan signal output from the fourth scan signal generator SC4(n). For this purpose, the gate electrode of the control transistor TC(n) included in the voltage control circuit VrefC(n) can be connected to the output terminal of the fourth scan signal generator SC4(n). The fourth scan signal output from the output terminal of the fourth scan signal generator SC4(n) is a signal used to control the voltage control circuit VrefC(n) and can be applied only to the voltage control circuit VrefC(n). That is, the fourth scan signal can be omitted from the sub-pixel P.

[0068] The fourth scan signal generator SC4(n) may include first scan transistors T1 to sixth scan transistors T6, a compensation transistor TA, a first scan capacitor CB, a second scan capacitor CQB, and a third scan capacitor CO. In the following description, examples will be given of first scan transistors T1 to sixth scan transistors T6 being implemented as p-type transistors, but this disclosure is not limited thereto.

[0069] The first scan transistor T1 may have a gate electrode connected to Q node Q, a first electrode connected to the gate low voltage line VGL, and a second electrode connected to the output terminal. The first scan transistor T1 may be turned on based on the voltage of Q node Q, and may output a fourth scan signal at a low voltage based on the gate low voltage applied through the gate low voltage line VGL. The first scan transistor T1 may be defined as a first output transistor.

[0070] The first scanning capacitor CB may have a first electrode connected to the Q node Q and a second electrode connected to the output terminal. The first scanning capacitor CB can be used to stably maintain the voltage of the Q node Q.

[0071] The second scan transistor T2 may have a gate electrode connected to node QB, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the output terminal. The second scan transistor T2 may be turned on based on the voltage of node QB, and may output a high-voltage fourth scan signal based on the gate high voltage applied through the gate high voltage line VGH. The second scan transistor T2 may be defined as a second output transistor.

[0072] The second scanning capacitor CQB may have a first electrode connected to the QB node QB and a second electrode connected to the output terminal. The second scanning capacitor CQB can be used to stably maintain the voltage of the QB node QB.

[0073] The third scan transistor T3 may have a gate electrode connected to the clock signal line GCLK, a first electrode connected to the start signal line VST (the output terminal of the previous stage or the carry output terminal CRY), and a second electrode connected to the Q2 node Q2. The third scan transistor T3 may be turned on based on the clock signal applied through the clock signal line GCLK to transmit the start signal applied through the start signal line VST to the Q2 node Q2.

[0074] The fourth scan transistor T4 may have a gate electrode connected to the clock signal line GCLK, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to node Q3. The fourth scan transistor T4 is turned on based on the clock signal applied through the clock signal line GCLK to transfer the gate high voltage applied through the gate high voltage line VGH to node Q3.

[0075] The fifth scanning transistor T5 may have a gate electrode connected to node Q3, a first electrode connected to the clock signal line GCLK, and a second electrode connected to node QB. The fifth scanning transistor T5 is turned on based on the voltage of node Q3 to transmit the clock signal applied through the clock signal line GCLK to node QB.

[0076] The third scan capacitor CO may have a first electrode connected to the clock signal line GCLK and a second electrode connected to node Q3. The third scan capacitor CO can be used to stably maintain the voltage of node Q3. The sixth scan transistor T6 may have a gate electrode connected to node Q2, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to node QB. The sixth scan transistor T6 can be turned on based on the voltage of node Q2 to transfer the gate high voltage applied through the gate high voltage line VGH to node QB.

[0077] The compensation transistor TA may have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to node Q2, and a second electrode connected to node Q. The compensation transistor TA can be turned on based on the gate low voltage and can be used to electrically stabilize node Q2 and node Q.

[0078] Meanwhile, in the fourth scan signal generator SC4(n), the third scan transistor T3 to the sixth scan transistor T6, in addition to the first scan transistor T1 and the second scan transistor T2 which are defined as output transistors, and the compensation transistor TA can be defined as node control circuits that control Q node Q, Q2 node Q2, Q3 node Q3 and QB node QB.

[0079] like Figure 4 and Figure 5 As shown, the fourth scan signal generator SC4(n) according to the first embodiment can start operating based on the fourth clock signal GCLK4, which is at a low voltage, generated at the same time as the low-voltage start signal GVST is applied.

[0080] Since the third scanning transistor T3 is turned on based on the fourth clock signal GCLK4 which is at a low voltage, the voltage Q-node of Q node Q becomes low. At this time, as the sixth scanning transistor T6 is turned on based on the low voltage Q-node of Q node Q, the voltage QB-node of QB node QB becomes high.

[0081] When the voltage at Q-node Q is low, the first scan transistor T1 can be turned on. When the voltage at QB-node QB is high, the second scan transistor T2 can be turned off. The fourth scan signal generator SC4(n) can output a low-voltage fourth scan signal via the output terminal through the turned-on first scan transistor T1.

[0082] The control transistor TC(n) included in the voltage control circuit VrefC(n) can be turned on based on a low-voltage fourth scan signal output through the output terminal of the fourth scan signal generator SC4(n). When the control transistor TC(n) is turned on, the reference voltage Vref_out applied through the reference voltage line VrefL can be output through the reference voltage output terminal Vref_out(n).

[0083] like Figure 5 As shown in the VARD, the period during which the voltage of the Q-node is low and the period during which the reference voltage Vref_out is output in response to this can occur simultaneously.

[0084] The voltage control circuit VrefC(n) according to this disclosure can be applied to various sub-pixels that require a reference voltage, and only a portion of the circuit is included in sub-pixel P as described above. However, examples of sub-pixels to which the voltage control circuit VrefC(n) according to this disclosure can be applied are described below.

[0085] Figure 6 It is a circuit diagram of the sub-pixel according to the second embodiment, and Figure 7 It shows Figure 6 The driving waveform of the sub-pixel is shown.

[0086] like Figure 6 As shown, the sub-pixel P according to the second embodiment may include a first transistor T1 to a sixth transistor T6, a first capacitor CST, a second capacitor CA, and a light-emitting element OLED. The first transistor T1 to the fourth transistor T4 and the sixth transistor T6 may be implemented as n-type transistors, and the fifth transistor T5 may be implemented as a p-type transistor, but this disclosure is not limited thereto.

[0087] The first transistor T1 may have a gate electrode connected to the second node N2, a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The first transistor T1 operates based on the data voltage stored in the first capacitor CST and can generate a drive current. The first transistor T1 can be defined as a drive transistor.

[0088] The second transistor T2 may have a gate electrode connected to the first scan line SC1, a first electrode connected to the data line DL, and a second electrode connected to the second node N2. The second transistor T2 may be turned on based on a first scan signal applied through the first scan line SC1 to transmit the data voltage applied through the data line DL to the second node N2.

[0089] The third transistor T3 may have a gate electrode connected to the second scan line SC2, a first electrode connected to the reference voltage line VrefL, and a second electrode connected to the second node N2. The third transistor T3 may be turned on based on a second scan signal applied through the second scan line SC2 to transmit a reference voltage applied through the reference voltage line VrefL to the second node N2.

[0090] The fourth transistor T4 may have a gate electrode connected to the third scan line SC3, a first electrode connected to the initialization voltage line VaralL, and a second electrode connected to the fourth node N4. The fourth transistor T4 may be turned on based on a third scan signal applied through the third scan line SC3 to transmit the initialization voltage applied through the initialization voltage line VaralL to the fourth node N4.

[0091] The fifth transistor T5 may have a gate electrode connected to the first light-emitting control line EM1, a first electrode connected to the high-level voltage line EVDD, and a second electrode connected to the third node N3. The fifth transistor T5 may be turned on based on a first light-emitting control signal applied through the first light-emitting control line EM1 to transmit a high-level voltage applied through the high-level voltage line EVDD to the third node N3.

[0092] The sixth transistor T6 may have a gate electrode connected to the second light-emitting control line EM2, a first electrode connected to the first node N1, and a second electrode connected to the fourth node N4. The sixth transistor T6 may be turned on based on a second light-emitting control signal applied through the second light-emitting control line EM2 to transmit the drive current generated by the first transistor T1 to the fourth node N4.

[0093] The first capacitor CST may have a first electrode connected to the second node N2 and a second electrode connected to the first node N1. The first capacitor CST may store a data voltage applied through the second transistor T2. The data voltage stored in the first capacitor CST may be applied to the gate electrode of the first transistor T1.

[0094] The second capacitor CA may have a first electrode connected to the first node N1 and a second electrode connected to the fifth node N5. The second capacitor CA may store a reference voltage applied through the fifth node N5. The reference voltage stored in the second capacitor CA may be applied to the first node N1. The reference voltage stored in the second capacitor CA may be used to compensate for the data voltage uniformly (balancedly) stored in the first capacitor CST across the entire display panel (or across all sub-pixels).

[0095] The OLED (Optical Display Cell) can have an anode connected to the fourth node N4 and a cathode connected to the low-level voltage line EVSS. The OLED can emit light based on a drive current transmitted from the sixth transistor T6. A parasitic capacitor CO may exist between the anode and cathode of the OLED.

[0096] like Figure 6 and Figure 7 As shown, according to the second embodiment, the sub-pixel P can be operated in the order of initialization period INIT, sampling period SAMP, data writing period WRT, and emission period EMI.

[0097] The initialization period (INIT) can be defined as the period used to initialize the first node N1 and the fourth node N4 of sub-pixel P. The sampling period (SAMP) can be defined as the period for sampling the threshold voltage of the first transistor (driving transistor) T1 of sub-pixel P. The data writing period (WRT) can be defined as the period used to apply a data voltage to the first capacitor CST of sub-pixel P. The emission period (EMI) can be defined as the period used to make the OLED light-emitting element of sub-pixel P emit light.

[0098] The first scan signal SC1 can be generated as a high voltage during the data write period (WRT) and then remain as a low voltage. The second scan signal SC2 can be generated as a high voltage during the initialization period (INIT) and the sampling period (SAMP) and then remain as a low voltage. The third scan signal SC3 can be generated as a high voltage during the initialization period (INIT), the sampling period (SAMP), the data write period (WRT), and the emission period (EMI) and then remain as a low voltage.

[0099] The first emission control signal EM1 can be generated as a high voltage during the initialization period (INIT), the data write period (WRT), and the emission period (EMI), and as a low voltage during the sampling period (SAMP). The second emission control signal EM2 can be generated as a high voltage during the initialization period (INIT) and the emission period (EMI), and as a low voltage during the data write period (WRT) and the sampling period (SAMP). A reference voltage Vref can be applied during the initialization period (INIT), the sampling period (SAMP), and the data write period (WRT).

[0100] Figure 7 It shows relative to Figure 2 The description includes an example of an odd-numbered first scan driver 321_O outputting an odd-numbered first scan signal SC1(1) to be applied to an odd-numbered sub-pixel, and an even-numbered first scan driver 321_E outputting an even-numbered first scan signal SC1(2) to be applied to an even-numbered sub-pixel.

[0101] Apart from the first scan drivers 321_O and 321_E, the other drivers can apply a common scan signal and a light emission signal without distinguishing between odd-numbered and even-numbered subpixels. Furthermore, depending on the driving method of the display panel 100, the first scan drivers 321_O and 321_E can output a common scan signal without distinguishing between odd-numbered and even-numbered subpixels.

[0102] Therefore, taking this into consideration, Figure 7 The signals applied together without distinguishing between odd-numbered and even-numbered subpixels are indicated as "SC2(1,2), EM1(1,2), EM2(1,2), and SC3(1,2)". Additionally, it should be noted that the reference voltage is also applied based on the scanning method, but is typically applied together without distinguishing between odd-numbered and even-numbered subpixels, and is therefore indicated as "Vref(1,2)".

[0103] Meanwhile, according to the second embodiment, the sub-pixel P can receive a reference voltage Vref through the second node N2 and the fifth node N5 during the initialization period (INIT), the sampling period (SAMP), and the data writing period (WRT). Since the reference voltage Vref is applied to sample the threshold voltage of the first transistor T1, which is defined as the driving transistor, deviations in each horizontal line (or each sub-pixel) may affect image quality. Therefore, the reference voltage Vref can be applied simultaneously under the control of the voltage control circuit described below to ensure uniform application to the sub-pixel P disposed on the display panel.

[0104] Figure 8 This is a schematic diagram showing a voltage control circuit according to a second embodiment and a shift register for controlling the voltage control circuit. Figure 9 It shows Figure 8 The drive waveform of the shift register shown is as follows, and Figure 10 and Figure 11 It shows according to Figure 8 The diagram shows the voltage control circuit and the operating state of the shift register, along with the driving waveform.

[0105] like Figure 8 As shown, according to the second embodiment, the fourth scan signal generator SC4(n) included in the shift register and Figure 4 The same as described in the first embodiment. Therefore, the description will focus on including the same as Figure 4 The first embodiment has a different part of the voltage control circuit VrefC(n).

[0106] According to the second embodiment, the voltage control circuit VrefC(n) may include a first control transistor T7 and a second control transistor T8. The first control transistor T7 and the second control transistor T8 may be implemented as p-type transistors, but are not limited thereto. The first control transistor T7 may have a gate electrode connected to the output terminal of the fourth scan signal generator SC4(n), a first electrode connected to the reference voltage line VrefL, and a second electrode connected to the reference voltage output terminal Vref_out(n). The first control transistor T7 may be turned on based on a low-voltage fourth scan signal output through the output terminal of the fourth scan signal generator SC4(n), and may output a reference voltage through the reference voltage output terminal Vref_out(n). The reference voltage may have a voltage level, for example, between 1V and 2V.

[0107] The second control transistor T8 may have a gate electrode connected to the QB node QB of the fourth scan signal generator SC4(n), a first electrode connected to the compensation voltage line CVL, and a second electrode connected to the reference voltage output terminal Vref_out(n). The second control transistor T8 may be turned on based on the voltage of the QB node QB of the fourth scan signal generator SC4(n), and may output the compensation voltage through the reference voltage output terminal Vref_out(n).

[0108] at the same time, Figure 8 An example is shown where the first electrode of the second control transistor T8 is connected to the compensation voltage line CVL. Here, the compensation voltage can have a level lower than the reference voltage (e.g., 1V) and will not affect image quality when the sub-pixel SP emits light. Furthermore, the first electrode of the second control transistor T8 can be electrically floated (or can be in a state where no voltage is applied to it) and is not connected to the compensation voltage line CVL.

[0109] like Figure 9 and Figure 10 As shown, a low-voltage fourth clock signal CLK4 and a low-voltage start signal GVST can be applied to the fourth scan signal generator SC4(n) during the first time period. The third scan transistor T3, fourth scan transistor T4, compensation transistor TA, sixth scan transistor T6, and first scan transistor T1 of the fourth scan signal generator SC4(n) can be turned on during the first time period. The fourth scan signal generator SC4(n) can output a low-voltage fourth scan signal through its output terminal based on the turned-on first scan transistor T1. During the first time period, the voltage control circuit VrefC(n) can output a reference voltage through the reference voltage output terminal Vref_out(n) based on the turned-on first control transistor T7.

[0110] like Figure 9 and Figure 11As shown, a low-voltage fourth clock signal CLK4 and a high-voltage start signal GVST can be applied to the fourth scan signal generator SC4(n) during the second time period. The third scan transistor T3, the fifth scan transistor T5, the compensation transistor TA, and the second scan transistor T2 of the fourth scan signal generator SC4(n) can be turned on during the second time period. The fourth scan signal generator SC4(n) can output a high-voltage fourth scan signal through its output terminal based on the turned-on second scan transistor T2. The first scan transistor T1 can be turned off by the high-voltage fourth scan signal during the second time period. On the other hand, the voltage control circuit VrefC(n) can output a compensation voltage through the reference voltage output terminal Vref_out(n), or it can not output a voltage based on the second control transistor T8 being turned on by the low voltage of node QB.

[0111] As described above, reference voltages can be sequentially applied to the horizontal lines of the display panel based on the voltage control circuit VrefC(n) and the fourth scan signal generator SC4(n) included in the shift register. Furthermore, by sequentially applying the reference voltages to the horizontal lines of the display panel, line load can be minimized and voltage transmission can be stabilized, thereby resolving problems caused by high-level voltage deviations within the display panel (EVDD deviation due to IR voltage drop) (e.g., voltage noise and brightness deviation). Additionally, when the voltage control circuit VrefC(n) is integrated into or located adjacent to the fourth scan signal generator SC4(n), the circuitry included in the sub-pixels can be simplified, thereby improving aperture ratio and lifetime.

[0112] Figure 12 This is a schematic diagram showing a voltage control circuit according to a third embodiment and a shift register that controls the voltage control circuit. Figure 13 It shows Figure 12 The drive waveform of the shift register shown is as follows, and Figure 14 and Figure 15 It shows according to Figure 13 The diagram shows the voltage control circuit and the operating state of the shift register, along with the driving waveform.

[0113] like Figure 12 As shown, according to the third embodiment, the fourth scan signal generator SC4(n) included in the shift register may include a first scan transistor T1 to a seventh scan transistor T7 and a first capacitor CQ. The following description uses the example of the first scan transistor T1, the second scan transistor T2, the fourth scan transistor T4, the sixth scan transistor T6, and the seventh scan transistor T7 being implemented as p-type transistors, and the third scan transistor T3 and the fifth scan transistor T5 being implemented as n-type transistors; however, this disclosure is not limited thereto.

[0114] The first scan transistor T1 may have a gate electrode connected to Q node Q, a first electrode connected to the gate voltage line VGL, and a second electrode connected to the output terminal. The first scan transistor T1 may be turned on based on the voltage of Q node Q and output a low-voltage fourth scan signal based on a low gate voltage applied through the compensation voltage line CVL. The first scan transistor T1 may be defined as a first output transistor.

[0115] The first capacitor CQ may have a first electrode connected to node Q and a second electrode connected to the output terminal. The first capacitor CQ can be used to stably maintain the voltage at node Q.

[0116] The second scan transistor T2 may have a gate electrode connected to the QB node QB, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to the output terminal. The second scan transistor T2 is turned on based on the voltage of the QB node QB and can output a high-voltage fourth scan signal based on the gate high voltage applied through the gate high voltage line VGH. The second scan transistor T2 can be defined as a second output transistor.

[0117] The third scan transistor T3 may have a gate electrode connected to the QB node QB, a first electrode connected to the first electrode of the first scan transistor T1, and a second gate electrode (or body electrode), and a second electrode connected to the second electrode of the first scan transistor T1. The third scan transistor T3 may be turned on during periods when the voltage at the QB node QB is high, so as to transmit a low gate voltage to the output terminal. The third scan transistor T3 may be used to maintain or compensate the output, so that a low-voltage fourth scan signal is stably output through the output terminal.

[0118] The fourth scan transistor T4 may have a gate electrode connected to the gate voltage line VGL, a first electrode connected to node Q2, and a second electrode connected to node Q. The fourth scan transistor T4 may be turned on based on a low gate voltage applied through the gate voltage line VGL and may be used to electrically stabilize nodes Q2 and Q.

[0119] The fifth scan transistor T5 may have a gate electrode connected to Q node Q, a first electrode and a second gate electrode (or body electrode) connected to the gate voltage line VGL, and a second electrode connected to QB node QB. The fifth scan transistor T5 may be turned on based on the voltage of Q node Q to transfer a low gate voltage applied through the gate voltage line VGL to QB node QB. The fifth scan transistor T5 may be turned on during periods when the voltage of Q node Q is high to stably maintain the voltage of QB node QB at a low voltage.

[0120] The sixth scan transistor T6 may have a gate electrode connected to node Q2, a first electrode connected to the gate high voltage line VGH, and a second electrode connected to node QB. The sixth scan transistor T6 may be turned on based on the voltage of node Q2 to transfer the gate high voltage applied through the gate high voltage line VGH to node QB.

[0121] The seventh scan transistor T7 may have a gate electrode connected to the clock signal line GCLK, a first electrode connected to the start signal line VST (the output terminal of the previous stage or the carry output terminal CRY), and a second electrode connected to node Q2. The seventh scan transistor T7 may be turned on based on the clock signal applied through the clock signal line GCLK to transmit the start signal applied through the start signal line VST to node Q2.

[0122] According to a third embodiment, the voltage control circuit VrefC(n) may include a first control transistor T9 and a second control transistor T8. The first control transistor T9 and the second control transistor T8 may be implemented as p-type transistors, but this disclosure is not limited thereto. The first control transistor T9 may have a gate electrode connected to the QB node QB of the fourth scan signal generator SC4(n), a first electrode connected to the reference voltage line VrefL, and a second electrode connected to the reference voltage output terminal Vref_out(n). The first control transistor T9 may be turned on based on the voltage of the QB node QB of the fourth scan signal generator SC4(n) to output a reference voltage through the reference voltage output terminal Vref_out(n).

[0123] The second control transistor T8 may have a gate electrode connected to the output terminal of the fourth scan signal generator SC4(n), a first electrode connected to the compensation voltage line CVL, and a second electrode connected to the reference voltage output terminal Vref_out(n). The second control transistor T8 may be turned on based on the fourth scan signal output through the output terminal of the fourth scan signal generator SC4(n) to output the compensation voltage through the reference voltage output terminal Vref_out(n).

[0124] at the same time, Figure 12An example is shown where the first electrode of the second control transistor T8 is connected to the compensation voltage line CVL. Here, the compensation voltage can be at a level lower than the reference voltage and does not affect image quality when the sub-pixel SP emits light. Furthermore, the first electrode of the second control transistor T8 can be electrically floated (or can be in a state where no voltage is applied to it) and not connected to the compensation voltage line CVL. Therefore, the second control transistor T8 can be turned on based on the fourth scan signal output through the output terminal of the fourth scan signal generator SC4(n) to output the compensation voltage through the reference voltage output terminal Vref_out(n), or it can not output a voltage.

[0125] Meanwhile, in the fourth scan signal generator SC4(n), in addition to the first scan transistor T1, the second scan transistor T2 and the third scan transistor T3 which are defined as output transistors, the fourth scan transistor T4 to the seventh scan transistor T7 can define the node control circuit that controls the Q node Q, the Q2 node Q2 and the QB node QB.

[0126] like Figure 13 and Figure 14 As shown, a low-voltage first clock signal GCLK1 and a high-voltage start signal GVST can be applied to the fourth scan signal generator SC4(n) during the first time period.

[0127] Since the seventh scanning transistor T7 is turned on based on the low-voltage first clock signal GCLK1, the voltage Q2-node of Q2 node Q2 and the voltage Q-node of Q node Q can become high voltage. At this time, since the fifth scanning transistor T5 is turned on based on the high voltage Q-node of Q node Q, the voltage QB-node of QB node QB can become low voltage.

[0128] When the voltage QB-node of node QB becomes low, the second scan transistor T2 and the third scan transistor T3 can be turned on. On the other hand, since the voltage Q2-node of node Q2 and the voltage Q-node of node Q are high, the first scan transistor T1 can be turned off. The fourth scan signal generator SC4(n) can output a high-voltage fourth scan signal through the output terminal based on the turned-on second scan transistor T2.

[0129] The second control transistor T8 included in the voltage control circuit VrefC(n) can be turned off based on the high voltage of the fourth scan signal output through the output terminal of the fourth scan signal generator SC4(n). On the other hand, the first control transistor T9 included in the voltage control circuit VrefC(n) can be turned on based on the low voltage of QB node QB, so as to output the reference voltage Vref_out through the reference voltage output terminal Vref_out(n).

[0130] like Figure 13 and Figure 15 As shown, a low-voltage first clock signal GCLK1 and a low-voltage start signal GVST can be applied to the fourth scan signal generator SC4(n) during the second time period.

[0131] Since the seventh scanning transistor T7 is turned on based on the low-voltage first clock signal GCLK1, the voltages at Q2 node Q2 and Q node Q become low. At this time, the fifth scanning transistor T5 can be turned off based on the low voltage at Q node Q.

[0132] When the voltage QB-node of node QB becomes high through the conducting sixth scan transistor T6, the second scan transistor T2 and the first control transistor T9 can be turned off. Conversely, when the voltages Q2-node of node Q2 and Q-node of node Q become low, the first scan transistor T1 can be turned on. The fourth scan signal generator SC4(n) can output a low-voltage fourth scan signal through its output terminal based on the conducting first scan transistor T1.

[0133] The second control transistor T8 included in the voltage control circuit VrefC(n) can be turned on based on a low-voltage fourth scan signal output through the output terminal of the fourth scan signal generator SC4(n). Therefore, the second control transistor T8 included in the voltage control circuit VrefC(n) can output a compensation voltage through the reference voltage output terminal Vref_out(n), or it can not output a voltage.

[0134] If possible Figure 13 As seen in the VARD reference voltage output period, the periods when the voltage of the QB node (QB-node) is low and the periods when the reference voltage (Vref_out) is output in response to this can occur simultaneously.

[0135] This disclosure solves problems (voltage noise, brightness deviation, etc.) caused by high-level voltage deviation within the display panel (EVDD deviation due to IR voltage drop) by sequentially applying reference voltages to corresponding horizontal lines of the display panel. Furthermore, this disclosure simplifies the circuitry included in sub-pixels and improves aperture ratio and lifetime by integrating the circuitry for applying reference voltages to the corresponding horizontal lines of the display panel into the scan signal generator or by placing the circuitry adjacent to the scan signal generator.

[0136] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A display panel, the display panel including sub-pixels; A gate driver connected to the sub-pixel; as well as A voltage control circuit, the voltage control circuit including at least one control transistor controlled based on the operation of the gate driver. Each of the sub-pixels includes a first capacitor and a second capacitor. One end of the first capacitor is connected to the gate electrode of the driving transistor, and the other end of the first capacitor is connected to a first node defined as the second electrode of the driving transistor. One end of the second capacitor is connected to the output terminal of the voltage control circuit, and the other end of the second capacitor is connected to the first node. The at least one control transistor is configured to be turned on based on the operation of the gate driver to apply a reference voltage to the sub-pixel.

2. The display device according to claim 1, wherein, The gate driver includes: A first scan signal generator, configured to generate a first scan signal; A second scan signal generator, configured to generate a second scan signal; A third scan signal generator, the third scan signal generator being configured to generate a third scan signal; and A fourth scan signal generator, configured to generate a fourth scan signal, The at least one control transistor is configured to be turned on based on the operation of the fourth scan signal generator to apply the reference voltage to the sub-pixel.

3. The display device according to claim 2, wherein, The fourth scan signal was not applied to the sub-pixel.

4. The display device according to claim 2, wherein, The at least one control transistor includes a first control transistor having a gate electrode connected to the output terminal of the fourth scan signal generator, a first electrode connected to a reference voltage line, and a second electrode connected to one end of the second capacitor, the reference voltage being transmitted through the reference voltage line.

5. The display device according to claim 4, wherein, The first control transistor is turned on during the period when the voltage of the Q node of the fourth scan signal generator is low.

6. The display device according to claim 5, wherein, The fourth scan signal generator includes: A first transistor has a gate electrode connected to the Q node, a first electrode connected to a gate low voltage line, and a second electrode connected to the output terminal; The second transistor has a gate electrode connected to a QB node operating opposite to the Q node, a first electrode connected to a gate high-voltage line, and a second electrode connected to the output terminal; and A node control circuit configured to control the Q node and the QB node.

7. The display device according to claim 2, wherein, The at least one control transistor includes a first control transistor having a gate electrode connected to the QB node of the gate driver, a first electrode connected to a reference voltage line, and a second electrode connected to one end of the second capacitor, the reference voltage being transmitted through the reference voltage line.

8. The display device according to claim 7, wherein, The first control transistor is turned on during the period when the voltage at the QB node of the fourth scan signal generator is low.

9. The display device according to claim 1, wherein, Based on the operation of the voltage control circuit, the reference voltage is sequentially applied to one end of the second capacitor for the gate line.

10. A method for driving a display device according to claim 1, the method comprising: Initialize the nodes of the sub-pixels; A sampling operation that samples the threshold voltage of the driving transistor included in the sub-pixel; The data voltage is applied to the data voltage of the sub-pixel during the data voltage write operation; as well as The light-emitting operation that makes the sub-pixel emit light. During the initialization operation, the sampling operation, and the data voltage writing operation, the voltage control circuit is turned on based on the operation of the gate driver to apply the reference voltage to the sub-pixel.

11. The method according to claim 10, wherein, The reference voltage is applied to one end of the second capacitor.

12. The method according to claim 11, wherein, For each gate line, based on the operation of the voltage control circuit, the reference voltage is sequentially applied to one end of the second capacitor.

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