A memory testing system

Abstract

This invention provides a memory testing system, comprising: a host computer; at least one card reader communicatively connected to the host computer, each card reader having a corresponding memory under test (MDT) communicatively connected to it; and a temperature chamber, in which the MDT and the card readers are placed. The host computer controls each MDT to perform a corresponding test and simultaneously controls the temperature chamber to adjust its internal temperature, enabling parallel testing of all MDTs under different ambient temperatures. This memory testing system solves the current technical problem of achieving low-cost and high-efficiency testing for memory.

Description

Technical Field

[0001] This invention relates to the field of storage, and more particularly to a testing system for memory. Background Technology

[0002] The memory is based on flash memory technology, and its reliability is highly sensitive to temperature stress. Especially in extreme temperature environments (such as -40℃, +85℃), it is prone to failure risks such as data retention degradation and bad block surge. Therefore, reliability verification is necessary.

[0003] Existing testing solutions face a dilemma: one approach is to place the terminal device equipped with the memory directly in a temperature chamber for testing. However, because other components on the terminal device may fail before the memory at extreme temperatures, this can cause system shutdown, making continuous testing of the memory itself impossible. The other approach is to use automated test equipment (ATE) to apply temperature stress to the memory separately. While this avoids interference from the terminal device, it incurs extremely high equipment procurement and maintenance costs, making it unsuitable for large-scale batch testing. Therefore, improvements are needed. Summary of the Invention

[0004] This invention provides a memory testing system to solve the current technical problem that it is difficult to achieve low cost and high efficiency in memory testing.

[0005] The present invention provides a memory testing system, comprising: Host computer; At least one card reader is communicatively connected to the host computer, and each card reader has a corresponding communication connection to a memory to be tested. The test memory and the card reader are both placed inside the temperature chamber. The host computer is used to control each memory under test to perform corresponding tests, and at the same time control the temperature chamber to adjust its internal temperature changes, so as to perform parallel tests on all memory under test under different ambient temperatures.

[0006] In one embodiment of the present invention, a hub is further included. The upstream port of the hub is communicatively connected to the host computer, and each downstream port of the hub is communicatively connected to a corresponding card reader, so that the host computer can perform parallel testing on the corresponding memory under test through each downstream port.

[0007] In one embodiment of the present invention, the memory under test connected to each downstream port satisfies the following condition: the sum of the data transmission rates between all the memory under test and the corresponding downstream port is less than or equal to the maximum data transmission rate between the host computer and the upstream port.

[0008] In one embodiment of the present invention, the host computer controls the temperature chamber to continuously change its internal ambient temperature according to a preset temperature curve within a preset temperature range; wherein the temperature curve includes at least one of a sine wave curve, a square wave curve, or a triangular wave curve.

[0009] In one embodiment of the present invention, for each memory under test, the host computer is further configured to: The preset read / write test items are executed, and simultaneously, the ambient temperature inside the chamber is controlled to continuously change according to a preset temperature curve; wherein, for any two adjacent read / write test items: After the previous read / write test item is completed and verified, the entire card of the memory under test is filled with preset verification data; Before executing the next read / write test item, the memory under test is restarted, and then the full card data in the memory under test is verified to be consistent with the verification data. If they are consistent, the next read / write test item is executed. If they are inconsistent, the subsequent test of the memory under test is stopped and an error message is output. Among them, the read / write test items currently being executed by different memory devices under test may be the same or different.

[0010] In one embodiment of the present invention, the read / write test item includes a sequential read / write test item. During the continuous change of the ambient temperature inside the incubator according to a preset temperature curve, the host computer further configures the host computer for the sequential read / write test item as follows: Acquire multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain the first test sequence; According to the logical address from low to high, each test data in the first test sequence is written sequentially and cyclically to the memory under test until the entire card is filled. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the first test sequence are repeated until the test duration for the sequential read and write test item reaches the first preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0011] In one embodiment of the present invention, the read / write test item includes a reverse read / write test item. During the continuous change of the ambient temperature inside the temperature chamber according to a preset temperature curve, the host computer further configures the host computer for the reverse read / write test item as follows: Obtain multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain the second test sequence; According to the logical address from high to low, each test data in the second test sequence is written sequentially and cyclically to the memory under test until the entire card is filled. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the second test sequence are repeated until the test duration for the reverse read / write test item reaches the second preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0012] In one embodiment of the present invention, the read / write test item includes an alternating read / write test item. During the continuous change of the ambient temperature inside the incubator according to a preset temperature curve, the host computer further configures the alternating read / write test item as follows: Obtain multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain a third test sequence; Following the alternating order of logical addresses, each test data in the third test sequence is sequentially and cyclically written to the memory under test until the entire card is filled; wherein, the alternating order of logical addresses means that each test data is written alternately in the order of logical addresses from low to high and in the order of logical addresses from high to low. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the third test sequence are repeated until the test duration for the alternating read-write test item reaches the third preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0013] In one embodiment of the present invention, the read / write test item includes a fragmented read / write test item. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer further configures the host computer to perform the fragmented read / write test item as follows: Control the memory under test to write the entire card with test data of a preset size; After performing an erase operation on the preset logical address, the full data of the memory under test is read out and verified respectively: whether the data of the erased logical address is all zeros, and whether the data of the logical address area that has not been erased is consistent with the test data that has been written. If the verification passes, the writing, erasing and verification of the test data are repeated until the test duration for the fragmented read and write test item reaches the fourth preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0014] In one embodiment of the present invention, the read / write test item includes a dual-zone switching read / write test item. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer further configures the host computer for the dual-zone switching read / write test item as follows: The user area of ​​the memory under test is filled with preset user data, and the RPMB area of ​​the memory under test is filled with preset security data. Write operations are performed alternately between the user area and the RPMB area in ascending order of logical address. After each switch back to the corresponding area, the data in that area is verified: whether the data in the area that has been written over is consistent with the corresponding written test data, and whether the data in the area that has not been written over is consistent with the user data or security data when the area was initially filled. In particular, at least one amount of test data is continuously written in one area before switching to another area. If each verification passes, continue writing alternately until any area is filled to complete one test cycle; Repeat the test loop until the test duration for the dual-zone switching read / write test item reaches the fifth preset duration; If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0015] The beneficial effects of this invention are as follows: By placing the card reader and the memory under test (MDT) together in a temperature chamber, while retaining the host computer for external control, precise and continuous temperature stress can be applied to the MDT, effectively testing its reliability under extreme temperatures, such as data retention capability and bad block rate. Simultaneously, by avoiding placing the entire device in the temperature chamber, interference from other components failing prematurely at extreme temperatures and causing test interruptions is eliminated. Furthermore, by controlling multiple card readers (each connected to one MDT) in parallel within the temperature chamber via a single host computer, the test throughput is significantly improved, overcoming the drawbacks of high cost and inability to support large-scale batch testing with ATE equipment, thus achieving low-cost, high-efficiency memory reliability verification. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1This is a schematic diagram of a memory testing system provided according to an embodiment of the present invention. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0021] Currently, high and low temperature reliability testing of embedded memories such as eMMC mainly relies on two methods: one is to place the entire terminal device containing the memory into a temperature chamber for testing. However, since many other components in the terminal device (such as the CPU, power supply chip, etc.) often have lower tolerance to extreme temperatures (e.g., -40℃, +85℃) than the memory, the terminal device may fail before the memory has been fully tested, thus making it impossible to complete the memory test. The other method is to use dedicated automated test equipment (ATE) to perform independent environmental testing on individual memories. Although this method can control the test conditions, its equipment purchase cost is extremely high and the test channels are limited, making it difficult to meet the industry's demand for large-scale, high-efficiency, and low-cost testing. Therefore, this invention discloses a memory testing system that can realize parallel, automated high and low temperature cyclic testing of multiple eMMC memories, thereby effectively solving the contradiction between insufficient test reliability and excessive test cost in the prior art.

[0022] Please see Figure 1 The memory testing system disclosed in this invention includes a host computer 100, a hub 200, a card reader 300, and a temperature chamber 400.

[0023] The host computer 100 is the device for overall test control and data processing. It is equipped with a high-speed data transmission interface for sending control commands (including test commands and adjustment commands) and test data, and for receiving response data from the memory under test 500. In actual deployment, the host computer 100 establishes a communication connection with the test hardware inside the temperature chamber 400 via physical cables.

[0024] The host computer 100 is not only responsible for sending control commands, but also has the ability to configure the hardware operating parameters of the memory under test 500, such as adjusting the operating voltage of the memory under test 500 to simulate the impact of voltage fluctuations in real application scenarios. For the memory under test 500, normal operation requires a core voltage (VCC) and an input / output interface voltage (VCCQ). VCC is the operating voltage of the flash memory core logic and memory cell array inside the memory under test 500; VCCQ is the interface voltage for data communication between the memory under test 500 and the external host (here, the card reader 300). For example, if VCC is 3.3V, VCCQ may be 1.8V (in high-speed mode) or 3.3V (in low-speed mode) depending on the operating mode. To test the stability of the memory under test 500 under high voltage conditions, the host computer 100 can configure VCC to 3.63V; simultaneously, according to the test requirements, VCCQ can be configured to 1.98V. Conversely, in order to test the performance and data retention capability of the memory under test 500 under low voltage conditions, the host computer 100 can configure VCC to 2.97V and VCCQ to 1.62V.

[0025] To enable parallel control of multiple memory-under-test (UUT) devices 500 by a single host computer 100, this embodiment introduces a hub 200. Specifically, the hub 200 can be a multi-port USB hub, featuring one upstream port and multiple downstream ports. The upstream port of the hub 200 is connected to the high-speed data transmission interface of the host computer 100 via a data cable (e.g., a USB Type-C or Type-A cable), thus establishing a communication link. Each downstream port of the hub 200 acts as a branch, and each downstream port can independently connect to an external device.

[0026] The maximum data transfer rate between the host computer 100 and the upstream port of the hub 200 is determined by the specifications of the physical interface equipped on the host computer 100. For example, when the host computer 100 uses a USB 4.0 interface, the maximum data transfer rate between it and the upstream port of the hub 200 can reach approximately 5120 MBytes / s; if a USB 3.2 Gen 2x2 interface is used, the maximum data transfer rate is approximately 2560 MBytes / s.

[0027] Card reader 300 is a hardware device that interacts with memory under test 500. Each card reader 300 has a card slot for inserting a card into the memory under test 500. The card reader 300 integrates a protocol conversion chip (e.g., a USB-to-eMMC bridge chip) that can convert test commands from the host computer 100 (such as SCSI commands under the USB Mass Storage protocol) into test commands (such as eMMC protocol commands) that the memory under test 500 can recognize. Each card reader 300 is communicatively connected to a downstream port of hub 200 via a data line.

[0028] The data transfer rate between each card reader 300 and the corresponding memory under test 500 is limited by the interface protocol performance of the memory under test 500 itself. Taking the eMMC 5.1 protocol as an example, its data transfer rate is approximately 400 MBytes / s. Even if the card reader 300 supports a higher data transfer rate, the peak data transfer rate between a single memory under test 500 and its corresponding downstream port during full-load read / write testing is still approximately 400 MBytes / s.

[0029] To ensure the stability of the entire parallel testing process and avoid test command delays or failures due to data congestion, the total number of connected memory under test (DUT) 500s needs to be rationally planned. Specifically, the sum of the data transfer rates between all DUTs 500s currently being tested and their respective downstream ports of the hub 200 should be less than or equal to the maximum data transfer rate between the host computer 100 and the upstream port of the hub 200.

[0030] Based on the above principles, flexible configuration is possible. For example, when the host computer 100 uses a USB 4.0 interface (5120 MBytes / s), if the peak data transfer rate of each device under test (DUT) 500 (based on the eMMC 5.1 protocol) is calculated at 400 MBytes / s, theoretically, 12 DUTs 500 can be supported simultaneously. That is, the hub 200 can connect 12 card readers 300, with each card reader 300 inserting one DUT 500, allowing for full-speed parallel testing without causing an upstream bandwidth bottleneck. Similarly, if the host computer 100 uses a USB 3.2 Gen2x2 interface (2560 MBytes / s), approximately 6 DUTs 500 can be supported simultaneously.

[0031] This configuration method allows testers to flexibly determine the number of card readers 300 that can be connected in this test based on the existing hardware interface capabilities of the host computer 100. It fully utilizes the existing host computer's USB 3.2 or even USB 4.0 interfaces, maximizing test throughput by connecting an appropriate number of card readers 300. This greatly reuses existing test resources, effectively controlling hardware procurement costs while meeting testing requirements, achieving a balance between high efficiency and low cost.

[0032] The temperature chamber 400 provides a controllable temperature environment, and all card readers 300 and all memory devices under test 500 are placed inside the chamber. During placement, ensure that the data cables connecting the card readers 300 pass through dedicated interfaces (such as cable holes) on the chamber 400 wall panel to achieve electrical connection between the inside and outside of the chamber, while maintaining the chamber's airtightness to maintain a stable and uniform internal temperature. The chamber 400 itself has an independent temperature controller, which can receive adjustment commands from the host computer 100 via a communication interface (such as RS232, Ethernet, or USB), thereby dynamically changing its internal temperature during testing to simulate cyclic changes from low to high temperatures.

[0033] The host computer 100 controls each memory under test 500 to perform its corresponding test, and simultaneously controls the temperature chamber 400 to adjust its internal temperature change, so as to perform parallel testing on all memory under test 500 under different ambient temperatures. Specifically, the host computer 100 controls the temperature chamber 400 to continuously change its internal ambient temperature according to a preset temperature curve within a preset temperature range; wherein the temperature curve includes at least one of a sine wave curve, a square wave curve, or a triangular wave curve.

[0034] In the host computer 100, the tester can preset a temperature range, such as setting the lower limit to -40℃ and the upper limit to +85℃. This temperature range covers the temperature limits of common industrial applications. The host computer 100 can also provide a variety of preset temperature curves for the tester to choose from. For example, after selecting the sine curve, the ambient temperature inside the temperature chamber 400 will smoothly and periodically rise and fall between -40℃ and +85℃ according to a sine function, simulating a scenario of continuous temperature fluctuation. As another example, after selecting the square wave curve, the ambient temperature inside the temperature chamber 400 will rapidly switch between a high temperature point (such as +85℃) and a low temperature point (such as -40℃), and maintain a preset constant time at each temperature point to simulate the scenario of the memory under test 500 rapidly starting and stopping or being subjected to severe temperature shocks in extreme environments. For example, after selecting the triangular wave curve, the ambient temperature inside the temperature chamber 400 will rise linearly to the highest point at a constant rate, and then fall linearly to the lowest point at a constant rate, repeating this process to simulate the regular and gradual cyclical change of temperature.

[0035] Before the test begins, the tester inserts each memory device under test (DUT) 500 into the corresponding card slot of the card reader 300. Through this connection method, the host computer 100 can create an independent test thread for each DUT 500. The test thread sends read, write, erase, and configuration test commands to the corresponding DUT 500 via its downstream port of the hub 200 and the card reader 300, and receives response data, thereby achieving parallel testing of all DUTs 500.

[0036] At the start of the test, the host computer 100 also executes preset read / write test items, and simultaneously controls the ambient temperature inside the temperature chamber 400 to continuously change according to a preset temperature curve. Specifically, for any two adjacent read / write test items: after the previous read / write test item is completed and verified, the entire card of the memory under test is filled with preset verification data; before executing the next read / write test item, the memory under test is restarted, and then the data on the entire card of the memory under test is verified to be consistent with the verification data: if consistent, the next read / write test item is executed; if inconsistent, the subsequent test of the memory under test is terminated and an error message is output.

[0037] Specifically, the host computer 100 generates a series of real-time adjustment commands based on the selected temperature curve and the set temperature range, and continuously sends these commands through the communication link with the temperature chamber 400. Upon receiving these commands, the temperature controller inside the temperature chamber 400 drives its cooling and heating modules to adjust the ambient temperature within the sealed cavity, causing it to continuously change according to the preset temperature curve. In this mode, all card readers 300 placed inside the temperature chamber 400 and the memory devices under test 500 inserted therein are placed in a dynamic temperature environment. At this time, while the host computer 100 performs parallel tests on multiple memory devices under test 500 through the hub 200 and the card readers 300, these memory devices under test 500 themselves are also undergoing high-intensity, repeatable temperature cycling stress.

[0038] Each test thread executes a series of preset read / write tests in a pre-defined order to comprehensively evaluate the functionality and data integrity of the memory under test (MUT) 500 under different read / write test items. The read / write test items specifically include sequential read / write tests, reverse read / write tests, alternating read / write tests, fragmented read / write tests, and dual-segment switching read / write tests. The execution order of these five read / write tests is not fixed for all MUTs 500; the host computer 100 can independently set a preset order for each MUT 500. This preset order is the result of randomly sorting the above five read / write test items. For example, for a certain MUT 500, its preset order is set as follows: first execute the fragmented read / write test item, then the reverse read / write test item, followed by the dual-segment switching read / write test item, then the sequential read / write test item, and finally the alternating read / write test item. For the other memory under test, 500, the preset order may be completely different. For example, it may start with alternating read and write test items, followed by sequential read and write test items, fragmented read and write test items, reverse read and write test items, and finally dual-zone switching read and write test items.

[0039] This method of randomly setting the execution order of read and write test items for each memory under test 500 creates a diverse concurrent testing environment. Once the test starts, because each memory under test 500 executes read and write test items step-by-step according to a specific preset order, at any given moment, the specific read and write test items being executed by different memory under test 500s may be different or the same. For example, the first memory under test may be executing sequential read and write test items, while the second memory under test may be executing reverse-order read and write test items, and the third memory under test may abort the test due to data verification failure.

[0040] This approach enables the entire testing system to simultaneously apply various types of workloads and access pressures to a batch of memory devices under test (MDTs) 500. Overall, this more closely resembles simulating a real-world scenario where multiple memory devices process different tasks concurrently. More importantly, the randomization of the test order effectively avoids potential timing-related defects or stress accumulation effects that might be hidden due to a fixed execution order of read / write test items. Therefore, this approach not only improves test throughput through parallelism but also enhances the ability to verify the performance margins and potential defects of different MDTs 500 by introducing the randomness of the test order.

[0041] To ensure the rigor and isolation of the test, the host computer 100 embeds a verification step between any two adjacent read / write test items. Specifically, after the previous read / write test item for a certain memory under test 500 is completed and its own data verification passes, the test process does not immediately start the next read / write test item. Instead, it first writes preset verification data to the memory under test 500 until all its addressable storage space is filled, that is, the entire card of the memory under test 500 is filled.

[0042] Before executing the next read / write test, the host computer 100 initiates a restart operation on the memory under test 500. The purpose of this restart is to simulate a power outage and restart scenario and to verify the data retention capability of the memory under test 500 after the previous read / write test and before the next test begins. After the restart operation, the host computer 100 immediately reads and verifies the data in the entire memory under test 500, confirming that the contents of all storage cells are completely consistent with the previously written verification data.

[0043] If the verification results are completely consistent, it indicates that the data in the memory under test 500 remains intact after undergoing the previous read / write test and restart operation, and the scheduled next read / write test will then be executed. If any inconsistency is found during verification, even if only a single data bit is incorrect, the host computer 100 will immediately terminate all subsequent tests on the memory under test 500. Simultaneously, the host computer 100 will record the identifier of the memory under test 500 that encountered the error, along with the specific error information, and output detailed error messages for the testers to analyze.

[0044] During the sequential read / write test performed by the host computer 100 on a specific memory under test 500, the host computer 100 also simultaneously controls the ambient temperature inside the temperature chamber 400 to continuously change according to a preset temperature curve. For the sequential read / write test, the host computer is also used for: Acquire multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain the first test sequence; Write the test data in the first test sequence sequentially and cyclically to the memory under test in order of logical address from low to high, until the entire card is filled. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the first test sequence are repeated until the test duration for the sequential read and write test item reaches the first preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0045] Specifically, the sequential read / write test is used to verify the stability and correctness of the memory under test 500 when continuously reading and writing data in ascending logical address order. The sequential read / write test involves repeatedly filling and verifying the entire storage space of the memory under test 500 with a series of test data of different data sizes.

[0046] At the start of the test, the host computer 100 first acquires a preset test data set. This set contains multiple test data sets of varying amounts, represented in hexadecimal, such as 0xFFFF, 0x8001, 0x8000, 0x7FFF, 0x4001, 0x4000, 0x3FFF, 0x2001, 0x2000, 0x1FFF, 0x1001, 0x1000, 0xFFF, and 0x... Test data with data sizes ranging from 801, 0x800, 0x7FF, 0x401, 0x400, 0x3FF, 0x201, 0x200, 0x1FF, 0x101, 0x100, 0xFF, 0x81, 0x80, 0x7F, 0x41, 0x40, 0x3F, 0x21, 0x20, 0x1F, 0x11, 0x10, 0xF, 0x9, 0x8, 0x7, and 0x1 are used. These data sizes cover a range from a single logic block to the maximum preset number of logic blocks, and the purpose is to test the processing capability of the memory under test 500 for test data of different sizes.

[0047] Subsequently, the host computer 100 randomly arranges these test data of different amounts to generate a randomized first test sequence. For example, the originally ordered test data set is randomly shuffled to form a new sequence such as 0x1000, 0x7FFF, 0x1, 0x4001…0x8. This randomization process avoids test blind spots that may be caused by fixed data patterns or fixed-size sequences, increasing the randomness and comprehensiveness of the test.

[0048] Then, starting from the starting logical address of the memory under test 500 (e.g., LBA=0x0), the test data in the first test sequence are written sequentially in ascending order of logical address. Specifically, the host computer 100 will start with the first test data in the first test sequence (e.g., data size 0x1000) and write it into a contiguous space starting from the starting logical address. Next, starting with the second test data in the first test sequence (e.g., data size 0x7FFF), it will continue writing immediately after the end address of the previous write. This process will cycle through the test data in the first test sequence until the entire storage space of the memory under test 500 is completely filled, i.e., the entire card is filled.

[0049] After the full card writing is completed, the data verification phase begins. The host computer 100 reads all the data from the entire card in the memory under test 500 and compares the read data bit by bit with the previously written data to verify its integrity. If the full card data verification passes completely, it indicates that the memory under test 500 has functioned normally in this sequential write and read cycle.

[0050] The sequential read / write test item does not execute the write and verification loop only once. For extended stress testing, the host computer 100 will repeatedly execute the write and verification of the first test sequence. This repeated execution will continue until the test duration for the sequential read / write test item reaches a preset duration, such as 32 hours. Only if the data verification in each loop meets expectations throughout the entire 32-hour test period is the sequential read / write test item considered passed.

[0051] If any full card data verification reveals any inconsistency between the read and written data, the host computer 100 will immediately determine that the sequential read / write test item has failed and terminate all subsequent tests for this memory under test 500. It will output detailed error information, record the time of the error, the logical address, and the specific details of the data mismatch, in order to conduct subsequent fault analysis.

[0052] During the reverse read / write test performed by the host computer 100 on a specific memory under test 500, the host computer 100 also simultaneously controls the ambient temperature inside the temperature chamber 400 to continuously change according to a preset temperature curve. For the reverse read / write test, the host computer is also used for: Obtain multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain the second test sequence; Write the test data in the second test sequence sequentially and cyclically to the memory under test in descending order of logical address until the entire card is filled. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the second test sequence will be repeated until the test duration for the reverse read / write test item reaches the second preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0053] Specifically, the reverse read / write test is used to verify the stability and correctness of the memory under test 500 when continuously reading and writing data in descending logical address order. The reverse read / write test involves repeatedly filling and verifying the entire storage space of the memory under test 500 with a series of test data of different data sizes.

[0054] At the start of the test, the host computer 100 first acquires the aforementioned preset test data set and randomly arranges these test data of different amounts to generate a randomized second test sequence. The order of the test data in the second test sequence may differ from the order of the test data in the first test sequence.

[0055] Then, starting from the end logical address of the memory under test 500, the test data in the second test sequence are written in reverse order, following the logical address order from high to low. Specifically, the host computer 100 will start with the first test data in the second test sequence (e.g., data size 0x1000) and write it into a continuous space decreasing from the end logical address. Next, starting with the second test data in the second test sequence (e.g., data size 0x7FFF), it will continue writing into a continuous space decreasing from the starting address of the previous write. This process will cycle through the test data in the second test sequence, writing them in reverse order, until the entire storage space of the memory under test 500 is completely filled, i.e., the entire card is filled.

[0056] After the full card writing is completed, the data verification phase begins. The host computer 100 reads all the data from the entire card in the memory under test 500 and compares the read data bit by bit with the previously written data to verify its integrity. If the full card data verification passes completely, it indicates that the memory under test 500 has functioned normally during this reverse write and read cycle.

[0057] The reverse read / write test item does not execute the write and verification loop only once. For extended stress testing, the host computer 100 will repeatedly execute the write and verification of the second test sequence. This repeated execution will continue until the test duration for the reverse read / write test item reaches a second preset duration, such as 32 hours. Only if the data verification in each loop meets expectations throughout the entire 32-hour test period is the reverse read / write test item considered passed.

[0058] If any full card data verification reveals any inconsistency between the read and written data, the host computer 100 will immediately determine that the reverse read / write test item has failed, and will terminate all subsequent tests for this memory under test 500, output detailed error information, and record the time of the error, logical address, and specific details of the data mismatch for subsequent fault analysis.

[0059] During the alternating read / write test performed by the host computer 100 on a specific memory under test 500, the host computer 100 also simultaneously controls the ambient temperature inside the temperature chamber 400 to continuously change according to a preset temperature curve. For the alternating read / write test, the host computer is also used for: Obtain multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain a third test sequence; Following the alternating order of logical addresses, the test data in the third test sequence are sequentially and cyclically written to the memory under test until the entire card is filled; where the alternating order means that the test data are written alternately in the order of logical addresses from low to high and in the order of logical addresses from high to low. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the third test sequence will be repeated until the test duration for the alternating read and write test item reaches the third preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0060] Specifically, the alternating read / write test is used to verify the stability and correctness of the memory under test 500 when performing continuous data read / write operations under non-contiguous, jump-type address access modes. The alternating read / write test simulates this stress by alternating the write order from beginning to end.

[0061] At the start of the test, the host computer 100 first acquires the aforementioned preset test data set and randomly arranges these test data of different amounts to generate a randomized third test sequence. The order of the test data in the third test sequence may differ from the order of the test data in the first / second test sequences.

[0062] Then, following the alternating logical address order, each test data in the third test sequence is sequentially written to the memory under test 500 until its entire storage space is filled. Specifically, the alternating logical address order means that the written logical address jumps back and forth between the two ends of the storage space. The host computer 100 first writes the first test data in the third test sequence (e.g., data size 0x1000) into a continuous space starting from the starting logical address, following the logical address order from low to high. Then, it writes the second test data into a continuous space decreasing from the ending logical address, following the logical address order from high to low. Then, it writes the third test data into the lowest logical address of the remaining unwritten space, following the logical address order from low to high. Finally, it writes the fourth test data into the highest logical address of the remaining unwritten space in reverse order, following the logical address order from high to low. This process is repeated, alternating between the beginning and the end, until the entire storage space of the memory under test 500 is completely filled, i.e., the entire card is written. This writing method significantly increases the management pressure on the memory controller's address mapping table and cache.

[0063] After the full card writing is completed, the data verification phase begins. The host computer 100 reads all the data from the entire card in the memory under test 500 and compares the read data bit by bit with the previously written data to verify its integrity. If the full card data verification passes completely, it indicates that the memory under test 500 has functioned normally during this alternating write and read cycle.

[0064] The alternating read / write test item does not execute the write and verification cycle only once. For extended stress testing, the host computer 100 will repeatedly execute the write and verification of the third test sequence. This repetitive execution will continue until the test duration for the alternating read / write test item reaches the third preset duration, such as 32 hours. Only if the data verification in each cycle meets expectations throughout the entire 32-hour test period is the alternating read / write test item considered passed.

[0065] If any full card data verification reveals any inconsistency between the read and written data, the host computer 100 will immediately determine that the alternating read / write test item has failed and will terminate all subsequent tests for this memory under test 500, output detailed error information, and record the time of the error, logical address, and specific details of the data mismatch for subsequent fault analysis.

[0066] During the fragmentation read / write test performed by the host computer 100 on a specific memory under test 500, the host computer 100 also simultaneously controls the ambient temperature inside the temperature chamber 400 to continuously change according to a preset temperature curve. For the fragmentation read / write test, the host computer is also used for: Control the memory under test to write the entire card with test data of a preset size; After performing an erase operation on the preset logical address, the full data of the memory under test is read out and verified respectively: whether the data of the erased logical address is all zeros, and whether the data of the logical address area that has not been erased is consistent with the test data that has been written. If the verification passes, the writing, erasing and verification of test data will be repeated until the test duration for the fragmented read and write test item reaches the fourth preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0067] Specifically, the fragmentation read / write test item is used to verify the data retention capability and address management accuracy of the memory under test 500 after performing a partial erase operation, simulating the usage scenario of generating fragmentation and reclaiming space in the memory.

[0068] When the test begins, the host computer 100 will first use a preset size of test data (e.g., 32KBytes) to continuously and repeatedly write this test data from the starting logical block address of the memory under test 500 until the entire storage space of the memory under test 500 is filled, that is, the entire card is filled.

[0069] After the full card write is completed, the host computer 100 sends a specific erase command to the memory under test 500 to erase a selected portion of the logical addresses according to preset rules. Specifically, the host computer 100 presets an erase address rule, such as erasing all memory areas with even logical addresses, while leaving all memory areas with odd logical addresses unerased. After executing this erase command, theoretically, the data at all selected even logical addresses will be cleared and reset to a state of all zeros, while the data at all unselected odd logical addresses should remain unchanged.

[0070] After the erasure operation is completed, the data verification phase begins immediately. The host computer 100 reads all the data from the entire test memory 500 and then performs two verifications on the read data. The first verification is for the erased logical addresses; the host computer 100 checks the data corresponding to all erased logical addresses (e.g., all even-numbered LBAs) to verify that they are all zeros. The second verification is for the unerased logical addresses; the host computer 100 checks the data corresponding to all retained logical addresses (e.g., all odd-numbered LBAs) to verify that they are completely consistent with the initially written test data. Both verifications must pass simultaneously to prove the accuracy of the erasure operation and the stability of the data in the unerased areas.

[0071] The fragmented read / write test item does not execute the write, erase, and verification cycle of test data only once. For extended stress testing, the host computer 100 repeatedly performs the write, erase, and verification of test data. This repetitive execution continues until the test duration for the fragmented read / write test item reaches the fourth preset duration, such as 32 hours. Only if the data verification in each loop meets expectations throughout the entire 32-hour test period is the fragmented read / write test item considered passed.

[0072] If either of the two checks fails in any test cycle, the host computer 100 will immediately determine that the fragmentation read / write test item has failed, and will stop all subsequent tests for this memory under test 500, output detailed error information, and record the time of the error, logical address, and specific details of the data mismatch for subsequent fault analysis.

[0073] During the dual-zone switching read / write test performed by the host computer 100 on a specific memory under test 500, the host computer 100 also simultaneously controls the ambient temperature inside the temperature chamber 400 to continuously change according to a preset temperature curve. For the dual-zone switching read / write test, the host computer is also used for: The user area of ​​the memory under test is filled with preset user data, and the RPMB area of ​​the memory under test is filled with preset security data. Write operations are performed alternately between the user area and the RPMB area in ascending order of logical address. After each switch back to the corresponding area, the data in that area is verified: whether the data in the area that has been written over is consistent with the corresponding test data, and whether the data in the area that has not been written over is consistent with the user data or security data when the area was initially filled. At least one amount of test data is continuously written in one area before switching to another area. If each verification passes, continue writing alternately until any area is filled to complete one test cycle; Repeat the test loop until the test duration for the dual-zone switching read / write test item reaches the fifth preset duration; If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

[0074] Specifically, the dual-zone switching read / write test item is used to verify the management capabilities, data isolation, and stability of the switching process of the memory under test 500 when it frequently switches between the user area and the RPMB area.

[0075] At the start of the test, the host computer 100 first initializes and fills two areas of the memory under test 500. The host computer 100 fills the user area of ​​the memory under test with preset user data and fills the RPMB area of ​​the memory under test with preset security data.

[0076] After initialization, the host computer 100 will perform write operations alternately between the user area and the RPMB area, following the logical address order from low to high. Specifically, the host computer 100 will first write at least one preset data size of test data in the user area, starting from the beginning logical address of that user area. For example, it will first write 4KBytes of test data, followed by 8KBytes of test data. After completing this continuous write, the host computer 100 will not erase but will immediately switch to the RPMB area. In the RPMB area, it will also start from its beginning logical address and continuously write at least one preset data size of test data, for example, another 4KBytes of test data and another 8KBytes of test data. It will continue writing at least one data size of test data in one area before switching to another area.

[0077] Each time the host computer switches from the user area to the RPMB area, or vice versa, it immediately performs an area verification on the corresponding area. For example, after performing write operations on the user area and the RPMB area in sequence, the host computer 100 will first switch to the user area for an area verification, and then switch to the RPMB area for another area verification. After both area verifications pass, the host computer 100 will continue to perform write operations alternately between the user area and the RPMB area.

[0078] The region verification consists of two parts: The first part verifies the portion of the region overwritten by the test data. The host computer 100 reads the data at these addresses and checks if it is completely consistent with the test data written to this region before the switch. The second part verifies the portion of the region not overwritten by the current write operation. The host computer 100 reads the data at these addresses and checks if it remains completely consistent with the original data (user data for the user region, security data for the RPMB region) that filled the region during initialization. This verification ensures that a single write operation will not accidentally interfere with or corrupt data at other addresses within the same region, verifying the memory's addressing capabilities and data retention within the region.

[0079] After a write, switch, and verification cycle is completed, the host computer 100 records the logical address that has been written to each region. Then, the test continues with the next alternation cycle. The host computer 100 continues writing the next set of test data (e.g., 4KBytes and 8KBytes of test data) from the logical address where the previous cycle ended in that region, and then switches to another region, repeating the same write and verification process. This write, switch, and verification cycle continues until all logical addresses of any region in the user region or RPMB region are sequentially filled with test data. A complete test cycle ends when any region is filled first.

[0080] The dual-zone switching read / write test item does not execute the test data writing, switching, and verification loop only once. For extended stress testing, the host computer 100 will repeatedly execute the test data writing, switching, and verification. This repetitive execution will continue until the test duration for the dual-zone switching read / write test item reaches the fifth preset duration, such as 32 hours. Only if the data verification in each loop meets expectations throughout the entire 32-hour test period is the dual-zone switching read / write test item considered passed.

[0081] If a failure occurs in any test cycle, the host computer 100 will immediately determine that the dual-zone switching read / write test item has failed, and will stop all subsequent test items for this memory under test 500, output detailed error information, and record the time of the error, logical address, and specific details of the data mismatch for subsequent fault analysis.

[0082] As can be seen, the above scheme, by placing the card reader and the memory under test (DUT) together in the temperature chamber and retaining the host computer for external control, can apply precise and continuous temperature stress to the DUT, effectively testing its reliability under extreme temperatures, such as data retention capability and bad block rate. Simultaneously, by avoiding placing the entire device in the temperature chamber, interference from other components failing prematurely at extreme temperatures and causing test interruptions is eliminated. Furthermore, controlling multiple card readers (each connected to one DUT) in parallel within the temperature chamber via a single host computer significantly improves test throughput, overcoming the drawbacks of high cost and inability to support large-scale batch testing with ATE equipment, thus achieving low-cost, high-efficiency memory reliability verification.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A testing system for a memory, characterized in that, include: Host computer; At least one card reader is communicatively connected to the host computer, and each card reader has a corresponding communication connection to a memory to be tested. The test memory and the card reader are both placed inside the temperature chamber. The host computer is used to control each memory under test to perform corresponding tests, and at the same time control the temperature chamber to adjust its internal temperature changes, so as to perform parallel tests on all memory under test under different ambient temperatures.

2. The memory testing system according to claim 1, characterized in that, It also includes a hub, the upstream port of which is communicatively connected to the host computer, and each downstream port of the hub is communicatively connected to a corresponding card reader, so that the host computer can perform parallel testing on the corresponding memory under test through each downstream port.

3. The memory testing system according to claim 2, characterized in that, The memory under test connected to each downstream port satisfies the following condition: the sum of the data transmission rates between all the memory under test and their corresponding downstream ports is less than or equal to the maximum data transmission rate between the host computer and the upstream port.

4. The memory testing system according to claim 1, characterized in that, The host computer controls the temperature chamber to continuously change its internal ambient temperature according to a preset temperature curve within a preset temperature range; wherein the temperature curve includes at least one of a sine wave curve, a square wave curve, or a triangular wave curve.

5. The memory testing system according to claim 1, characterized in that, For each memory under test, the host computer is also used to: The preset read / write test items are executed, and simultaneously, the ambient temperature inside the chamber is controlled to continuously change according to a preset temperature curve; wherein, for any two adjacent read / write test items: After the previous read / write test item is completed and verified, the entire card of the memory under test is filled with preset verification data; Before executing the next read / write test item, the memory under test is restarted, and then the full card data in the memory under test is verified to be consistent with the verification data. If they are consistent, the next read / write test item is executed. If they are inconsistent, the subsequent test of the memory under test is stopped and an error message is output. Among them, the read / write test items currently being executed by different memory devices under test may be the same or different.

6. The memory testing system according to claim 5, characterized in that, The read / write test items include sequential read / write test items. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer is further configured to perform the sequential read / write test items as follows: Acquire multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain the first test sequence; According to the logical address from low to high, each test data in the first test sequence is written sequentially and cyclically to the memory under test until the entire card is filled. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the first test sequence are repeated until the test duration for the sequential read and write test item reaches the first preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

7. The memory testing system according to claim 5, characterized in that, The read / write test items include a reverse read / write test item. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer is further configured to perform the reverse read / write test item as follows: Obtain multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain the second test sequence; According to the logical address from high to low, each test data in the second test sequence is written sequentially and cyclically to the memory under test until the entire card is filled. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the second test sequence are repeated until the test duration for the reverse read / write test item reaches the second preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

8. The memory testing system according to claim 5, characterized in that, The read / write test items include an alternating read / write test item. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer is further configured to perform the alternating read / write test item as follows: Obtain multiple test data sets of different preset sizes, and randomly arrange each test data set to obtain a third test sequence; Following the alternating order of logical addresses, each test data in the third test sequence is sequentially and cyclically written to the memory under test until the entire card is filled; wherein, the alternating order of logical addresses means that each test data is written alternately in the order of logical addresses from low to high and in the order of logical addresses from high to low. Read out all the data from the memory card under test and verify it against the data already written. If the verification passes, the writing and verification of the third test sequence are repeated until the test duration for the alternating read-write test item reaches the third preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

9. The memory testing system according to claim 5, characterized in that, The read / write test items include fragmented read / write test items. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer is further configured to perform the fragmented read / write test items as follows: Control the memory under test to write the entire card with test data of a preset size; After performing an erase operation on the preset logical address, the full data of the memory under test is read out and verified respectively: whether the data of the erased logical address is all zeros, and whether the data of the logical address area that has not been erased is consistent with the test data that has been written. If the verification passes, the writing, erasing and verification of the test data are repeated until the test duration for the fragmented read and write test item reaches the fourth preset duration. If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

10. The memory testing system according to claim 5, characterized in that, The read / write test includes a dual-zone switching read / write test. During the continuous change of the ambient temperature inside the chamber according to a preset temperature curve, the host computer is further configured to perform the dual-zone switching read / write test as follows: The user area of ​​the memory under test is filled with preset user data, and the RPMB area of ​​the memory under test is filled with preset security data. Write operations are performed alternately between the user area and the RPMB area in ascending order of logical address. After each switch back to the corresponding area, the data in that area is verified: whether the data in the area that has been written over is consistent with the corresponding written test data, and whether the data in the area that has not been written over is consistent with the user data or security data when the area was initially filled. In this case, at least one amount of test data is continuously written in one area before switching to another area. If each verification passes, continue writing alternately until any area is filled to complete one test cycle; Repeat the test loop until the test duration for the dual-zone switching read / write test item reaches the fifth preset duration; If any of the checks fails, the subsequent testing of the memory under test will be terminated and an error message will be output.

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