DAC output buffer with decoding function, DAC system and quantization method

Abstract

This application relates to a DAC output BUF with decoding function, a DAC system, and a quantization method. The DAC output BUF includes: a decoding circuit, whose input terminal receives the low-order signal from the DAC, a complementary signal, the voltage to be quantized, and the power supply voltage, and is used to decode the low-order signal to output a decoded voltage signal; and an operational amplifier, whose positive input terminal is connected to the output terminal of the decoding circuit, for receiving the decoded voltage signal, and whose output terminal outputs an analog signal with enhanced driving capability. The decoding circuit is integrated into the input terminal of the operational amplifier, and is used to directly quantize the low-order bits of the DAC through the operational amplifier. Using this device can avoid signal attenuation caused by output impedance and switch on-resistance in traditional resistor string networks, thus improving the conversion accuracy of the DAC.

Description

Technical Field

[0001] This application relates to the field of digital-to-analog conversion technology, and in particular to a DAC output BUF with decoding function, a DAC system, and a quantization method. Background Technology

[0002] In digital-to-analog conversion systems, the DAC output buffer (BUF) is a crucial module connecting the DAC main body to the subsequent analog signal processing circuitry. Its primary functions are to isolate the mutual interference between the DAC main body and the load, enhance signal driving capability, and ensure the integrity and stability of the analog signal. With the continuous development of embedded systems, process control, audio processing, and precision instruments, the quality requirements for DAC output signals are increasingly stringent, making the design of the BUF circuit an indispensable and critical element in DAC application systems.

[0003] However, in interpolation DACs, the lower three or four bits of the decoding circuit typically use a resistor series network for voltage division. This resistor series network, connected in parallel with the DAC body, causes output signal attenuation, and the on-resistance of the decoding switches further attenuates the signal amplitude. The finite output impedance of the resistor series network and the non-ideal characteristics of the switch on-resistance directly affect the DAC's conversion accuracy, especially in applications with high accuracy requirements. Therefore, how to solve these problems to improve the quality of the DAC output signal has become a pressing technical issue for those skilled in the art. Summary of the Invention

[0004] A DAC output BUF with decoding function includes:

[0005] The decoding circuit has an input terminal for receiving the low-order signal from the DAC, the complementary signal, the voltage to be quantized, and the power supply voltage. The decoding circuit is used to decode the low-order signal to output the decoded voltage signal. An operational amplifier, wherein the positive input terminal of the operational amplifier is connected to the output terminal of the decoding circuit, for receiving the decoded voltage signal, and the output terminal of the operational amplifier is used to output an analog signal enhanced by driving capability; The decoding circuit is integrated into the input of the operational amplifier and is used to directly quantize the low-order bits of the DAC through the operational amplifier.

[0006] In one embodiment, the decoding circuit includes: a decoder, the input of which is used to receive the low-order signal, perform logic decoding on the low-order signal, and output a corresponding control signal; and a transmission gate array, including multiple transmission gates, the control terminal of each transmission gate being connected to the output terminal of the decoder, the input terminal of each transmission gate being used to receive the voltage to be quantized, and the output terminals of each transmission gate being connected to the positive input terminal of the operational amplifier; wherein the transmission gate array is selectively turned on according to the control signal output by the decoder to transmit the corresponding voltage to the operational amplifier.

[0007] In one embodiment, the transmission gate array includes multiple CMOS transmission gates connected in parallel. The input of each CMOS transmission gate is connected to a corresponding reference voltage node, and the outputs are all connected to the non-inverting input of the operational amplifier. The NMOS control terminal and the PMOS control terminal are respectively connected to the complementary control signal output of the decoder.

[0008] In one embodiment, the inverting input terminal of the operational amplifier is connected to the output terminal to form a voltage follower structure.

[0009] In one embodiment, the voltage to be quantized includes an upper reference voltage and a lower reference voltage quantized by the high-order bits of the DAC.

[0010] In one embodiment, the low-order signal is the lower four-bit signal or the lower three-bit signal of the DAC.

[0011] A DAC system includes a DAC body and a DAC output BUF with decoding function as described in any of the preceding claims, the DAC output BUF being connected between the output of the DAC body and a subsequent load.

[0012] A decoding and quantization method, based on the output BUF of a DAC with decoding function as described in any of the preceding claims, the method comprising: The low-order signal of the DAC is acquired, and the low-order signal is decoded to generate a decoding control signal. Based on the decoding control signal, the corresponding quantization voltage is selected; The quantized voltage after gating is directly input to the positive input terminal of the operational amplifier, which performs voltage following or amplification to output the final analog signal.

[0013] The aforementioned DAC output BUF with decoding function, DAC system, and quantization method integrate the decoding circuit into the input of the operational amplifier, and directly quantize the low-order bits of the DAC through the operational amplifier. This avoids the signal attenuation and accuracy loss caused by the limited output impedance and switching on-resistance of traditional resistor series networks, thereby significantly improving the quality and conversion accuracy of the DAC output signal. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall structure of a DAC output BUF with decoding function in one embodiment; Figure 2 This is a schematic diagram of the package structure of the decoding circuit in one embodiment; Figure 3 This is a schematic diagram of the internal structure of the decoding circuit in one embodiment; Figure 4 This is a schematic diagram of the circuit structure of an operational amplifier in one embodiment; Figure 5 This is a schematic diagram of the OUT0 section of the decoder's internal logic circuit in one embodiment; Figure 6 A schematic diagram of the OUT1 part of the decoder's internal logic circuit in one embodiment; Figure 7 This is a schematic diagram of the OUT2 part of the decoder's internal logic circuit in one embodiment; Figure 8 This is a schematic diagram of the OUT3 part of the decoder's internal logic circuit in one embodiment; Figure 9 This is a schematic diagram of the OUT4 section of the decoder's internal logic circuit in one embodiment; Figure 10 This is a schematic diagram of the OUT5 part of the decoder's internal logic circuit in one embodiment; Figure 11 This is a schematic diagram of the OUT6 part of the decoder's internal logic circuit in one embodiment; Figure 12 This is a schematic diagram of the OUT7 part of the decoder's internal logic circuit in one embodiment; Figure 13 This is a schematic diagram of the OUT8 part of the decoder's internal logic circuit in one embodiment; Figure 14 This is a schematic diagram of the OUT9 part of the decoder's internal logic circuit in one embodiment; Figure 15 This is a schematic diagram of the OUT10 part of the decoder's internal logic circuit in one embodiment; Figure 16 This is a schematic diagram of the OUT11 section of the decoder's internal logic circuit in one embodiment; Figure 17 This is a schematic diagram of the OUT12 section of the decoder's internal logic circuit in one embodiment; Figure 18 This is a schematic diagram of the OUT13 section of the decoder's internal logic circuit in one embodiment; Figure 19 This is a schematic diagram of the OUT14 section of the decoder's internal logic circuit in one embodiment. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0016] The DAC output BUF with decoding function provided in this application can be applied to various digital-to-analog conversion systems, especially suitable for interpolation-type DACs that require high-precision output. This BUF circuit is connected between the DAC main body and the subsequent load stage to isolate the load's influence and enhance the driving capability, while simultaneously performing direct quantization of the DAC's low-order signals.

[0017] In one embodiment, such as Figure 1 As shown, a DAC output BUF with decoding function is provided, including a decoding circuit (DECODE) and an operational amplifier (OPA). Wherein: The inputs of the decoding circuit are used to receive the low-order signals from the DAC (e.g., IN0 to IN3) and their complementary signals (IN0B to IN3B), the voltages to be quantized (VUP, VDOWN), and the power supply voltage (VDDA). The decoding circuit decodes the low-order signals and outputs the decoded voltage signals (O1 to O16).

[0018] The positive input of the operational amplifier is connected to the output of the decoding circuit to receive the decoded voltage signal; the output of the operational amplifier is used to output the analog signal after its driving capability has been enhanced. The decoding circuit is integrated into the input of the operational amplifier, so that the low-order quantization process of the DAC is directly completed through the operational amplifier, thereby avoiding the accuracy loss caused by the output impedance and switching on-resistance of traditional resistor series networks.

[0019] In this embodiment, the decoding circuit converts the low-order signal into a corresponding voltage value, which is directly fed into the operational amplifier. The operational amplifier isolates the quantization network from the influence of the subsequent load with its high input impedance, while providing sufficient driving capability. This structure fundamentally eliminates the signal attenuation problem caused by series and parallel resistors.

[0020] In one embodiment, Figure 2 This is a schematic diagram of the package structure of the decoding circuit, such as... Figure 3 The diagram illustrates the internal structure of a decoding circuit. The decoder's input receives low-order signals, such as IN0 to IN3, performs logic decoding on these low-order signals, and outputs corresponding control signals. The transmission gate array includes multiple transmission gates (TGs). The control terminal of each TG is connected to the decoder's output. The input of each TG receives the voltages to be quantized, such as VUP and VDOWN, after being divided by an internal resistor series. The outputs of each TG are connected to the positive input of an operational amplifier (VIP<15:0>). The TG array selectively turns on the gates according to the control signals output by the decoder, thereby transmitting the voltage of the corresponding node to the operational amplifier.

[0021] By controlling the conduction of the transmission gate using a decoder, precise selection from low-order digital signals to analog voltages is achieved. Since the voltage is directly transmitted to the op-amp input through a low-impedance path after the transmission gate is turned on, the additional voltage drop caused by the switch conduction resistor in series in the signal path, as in traditional resistor-string networks, is avoided.

[0022] In one embodiment, such as Figure 3 As shown, the transmission gate array comprises multiple CMOS transmission gates connected in parallel. The input of each CMOS transmission gate is connected to a corresponding reference voltage node, such as the voltage nodes generated by the internal resistor series divider between VUP and VDOWN. The outputs are collectively connected to the non-inverting input of an operational amplifier. Each CMOS transmission gate is composed of an NMOS transistor and a PMOS transistor connected in parallel. The NMOS control terminal and PMOS control terminal are respectively connected to the complementary control signal output of the decoder, such as the control signal and its inverted signal. This complementary control method ensures that the transmission gate has a low on-resistance when turned on and can conduct uniformly within the input voltage range, improving the linearity of signal transmission.

[0023] In one embodiment, such as Figure 4 As shown, the inverting input of the operational amplifier is connected to its output, forming a voltage follower structure. The voltage follower features high input impedance and low output impedance, effectively isolating the load from the preceding decoding stage while providing current drive capability. By connecting the decoded voltage signal to the positive input of the voltage follower, the output voltage becomes the input voltage, achieving impedance transformation and drive enhancement.

[0024] In one embodiment, the voltages to be quantized include the upper reference voltage VUP and the lower reference voltage VDOWN, quantized by the high-order bits of the DAC. In a practical DAC architecture, the high-order bits, such as 8 bits, generate coarse-tuned voltages through a resistor string or current source, outputting VUP and VDOWN as reference boundaries for the low-order quantization. The low-order bits, such as 4 bits, are finely divided between these two boundaries. In this application, VUP and VDOWN serve as inputs to the decoding circuit, passing through an internal resistor string or directly as reference nodes for the transmission gate, and are combined with the low-order signals to select precise voltage values.

[0025] In one embodiment, the low-order signal is the lower four or lower three bits of the DAC. For example, for a 12-bit DAC, the high-order part can be quantized using a resistor string network, while the low-order part can be quantized using the operational amplifier method described in this application; for other resolutions, the lower three bits can also use a similar structure. This allocation method leverages the high efficiency of traditional high-order quantization while solving the problem of low-order precision being susceptible to interference through operational amplifier quantization.

[0026] like Figures 5-19 The diagram shows the circuit structure of the entire decoder (DECODE internal decoder). This decoder receives the lower four bits of the DAC signals IN0 to IN3 and their complementary signals IN0B to IN3B as inputs. After processing by internal logic gates, it generates output signals O1 to O16. Figures 5-19 As can be seen, this decoder is composed of multiple inverters and NAND gates. It performs logical operations on the low-order input signals to control the selection of 16 output channels. Specifically, when the combination of low-order input signals changes, the corresponding output terminal outputs a high-level control signal, while the other output terminals remain low. These output signals O1 to O16 are respectively connected to... Figure 3 The control terminals of each transmission gate in the transmission gate array are used to control the conduction and cutoff of the corresponding transmission gate, thereby selecting the voltage of the corresponding node to the input terminal of the operational amplifier.

[0027] In one embodiment, a DAC system is provided, including a DAC body and a DAC output BUF with decoding function as described in any of the above embodiments. The DAC output BUF is connected between the output terminal of the DAC body and the subsequent load. The DAC body generates high-order quantized voltages VUP and VDOWN and provides low-order digital signals; after receiving these signals, the decoding circuit outputs the final high-precision analog voltage to the load through an operational amplifier.

[0028] In one embodiment, a decoding quantization method is provided, which is implemented based on the DAC output BUF with decoding function described in any of the above embodiments. The method includes the following steps: Step S1: Obtain the low-order signal of the DAC and decode it to generate a decoding control signal. Specifically, the low-order digital signal (such as the lower four bits of the DAC) is input to the decoder, and the decoder generates a corresponding control signal based on the truth table to select the corresponding transmission gate.

[0029] Step S2: Select the corresponding quantization voltage according to the decoding control signal. The control signal output by the decoder controls the conduction of the corresponding transmission gates in the transmission gate array, selecting the voltage of the corresponding reference voltage node to the common output node.

[0030] In step S3, the selected quantized voltage is directly input to the positive input terminal of the operational amplifier. The operational amplifier performs voltage following or amplification to output the final analog signal. The operational amplifier operates as a voltage follower, transmitting the input voltage to the output terminal without loss, while providing driving capability.

[0031] This method uses operational amplifiers to directly participate in low-bit quantization, avoiding the attenuation effect of traditional resistor string networks and improving the overall accuracy of the DAC.

[0032] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0033] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A DAC output BUF with decoding function, characterized in that, include: The decoding circuit has an input terminal for receiving the low-order signal from the DAC, the complementary signal, the voltage to be quantized, and the power supply voltage. The decoding circuit is used to decode the low-order signal to output the decoded voltage signal. An operational amplifier, wherein the positive input terminal of the operational amplifier is connected to the output terminal of the decoding circuit, for receiving the decoded voltage signal, and the output terminal of the operational amplifier is used to output an analog signal enhanced by driving capability; The decoding circuit is integrated into the input of the operational amplifier and is used to directly quantize the low-order bits of the DAC through the operational amplifier.

2. The DAC output BUF with decoding function according to claim 1, characterized in that, The decoding circuit includes: A decoder, wherein the input terminal of the decoder is used to receive the low-order signal, perform logic decoding on the low-order signal, and output the corresponding control signal; A transmission gate array includes multiple transmission gates, the control terminal of each transmission gate is connected to the output terminal of the decoder, the input terminal of each transmission gate is used to receive the voltage to be quantized, and the output terminal of each transmission gate is connected to the positive input terminal of the operational amplifier; wherein, the transmission gate array is selectively turned on according to the control signal output by the decoder to transmit the corresponding voltage to the operational amplifier.

3. The DAC output BUF with decoding function according to claim 2, characterized in that, The transmission gate array includes multiple CMOS transmission gates connected in parallel. The input terminal of each CMOS transmission gate is connected to the corresponding reference voltage node, and the output terminals are all connected to the non-inverting input terminal of the operational amplifier. The NMOS control terminal and the PMOS control terminal are respectively connected to the complementary control signal output terminal of the decoder.

4. The DAC output BUF with decoding function according to claim 1, characterized in that, The inverting input terminal and the output terminal of the operational amplifier are connected to form a voltage follower structure.

5. The DAC output BUF with decoding function according to any one of claims 1 to 4, characterized in that, The voltages that need to be quantized include the upper reference voltage and the lower reference voltage quantized by the high-order bits of the DAC.

6. The DAC output BUF with decoding function according to any one of claims 1 to 4, characterized in that, The low-order signal is the lower four-bit signal or the lower three-bit signal of the DAC.

7. A DAC system, characterized in that, It includes a DAC body and a DAC output BUF with decoding function as described in any one of claims 1 to 6, wherein the DAC output BUF is connected between the output terminal of the DAC body and the subsequent load.

8. A decoding and quantization method based on the DAC output BUF with decoding function according to any one of claims 1 to 6, characterized in that, The method includes: The low-order signal of the DAC is acquired, and the low-order signal is decoded to generate a decoding control signal. Based on the decoding control signal, the corresponding quantization voltage is selected; The quantized voltage after gating is directly input to the positive input terminal of the operational amplifier, which performs voltage following or amplification to output the final analog signal.

Images