A method and apparatus for advanced operation of gaussian elimination
By constructing a cascaded architecture of dual-column elimination units, two columns of data can be processed within one clock cycle, solving the problems of latency and low resource utilization in the Gaussian elimination process, improving decoding performance, and making it suitable for ultra-reliable low-latency communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-02-11
- Publication Date
- 2026-06-26
AI Technical Summary
In existing technologies, Gaussian elimination processes suffer from high processing latency and low resource utilization in polar code decoding, which limits decoding performance and makes it difficult to meet the requirements, especially in ultra-reliable low-latency communication scenarios.
The Gaussian elimination method with look-ahead operation is adopted. By constructing an elimination architecture consisting of multiple cascaded two-column elimination units, the two columns of data of the generated matrix are processed within one clock cycle. Candidate vectors are pre-calculated to reduce data dependencies, thereby reducing processing time and resource consumption.
It effectively shortens processing latency, improves resource utilization, and enhances decoding performance, making it suitable for ultra-reliable low-latency communication systems.
Smart Images
Figure CN122293262A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a method and apparatus for Gaussian elimination with lookahead computation. Background Technology
[0002] Polar codes have been theoretically proven to reach the Shannon limit and are used in high-reliability communication scenarios. In future ultra-reliable and low-latency communication (uRLLC) scenarios (such as industrial automation and vehicle-to-everything (V2X) communication), extremely stringent requirements are placed on the error correction performance and processing latency of decoders. Among the many polar code decoding algorithms, ordered statistical decoding (OSD) has become the preferred solution for high-reliability scenarios due to its excellent error correction performance, approaching maximum likelihood decoding, even with short code lengths. The OSD decoding process generally includes: reliability sorting of the received sequence, hard decision, transforming the generator matrix into a system generator matrix through Gaussian elimination, and error pattern testing. Among these, Gaussian elimination is the most time-consuming and resource-intensive process, limiting decoding performance due to high processing latency and low resource utilization. Summary of the Invention
[0003] In view of this, the purpose of this application is to provide a method and apparatus for Gaussian elimination with lookahead computation.
[0004] To achieve the above objectives, embodiments of this application provide a look-ahead Gaussian elimination method, comprising:
[0005] Within one clock cycle, a first input vector and a second input vector are acquired for inputting the target bicolumn elimination unit; wherein, when the target bicolumn elimination unit is a first-level bicolumn elimination unit, the first input vector and the second input vector are read from the generator matrix, and when the target bicolumn elimination unit is a subsequent-level bicolumn elimination unit, the first input vector and the second input vector are the outputs of the previous-level bicolumn elimination unit; Based on the current initialization state of the target bicolumn elimination unit, candidate vectors are calculated using the first and second input vectors. Based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated.
[0006] Optionally, the target double-column elimination unit includes a first logic elimination unit and a second logic elimination unit, wherein the first logic elimination unit and the second logic elimination unit are respectively provided with corresponding pivot bits and storage units for storing elimination vectors; Based on the current initialization state of the target bicolumn elimination unit, and using the first and second input vectors, candidate vectors are calculated, including: When the first logic elimination unit is not initialized, the candidate vector is determined according to the values of the principal bits of the first logic elimination unit and the second logic elimination unit corresponding to the first input vector and the second input vector. When the first logic elimination unit is initialized, the candidate vector is determined based on the values of the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector, and the first elimination vector corresponding to the first logic elimination unit.
[0007] Optionally, when the first logic elimination unit is not initialized, candidate vectors are determined based on the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit and the pivot bits of the second logic elimination unit, including: If the principal bits of the first input vector and the second input vector corresponding to the first logic elimination unit are both 1, the value of the principal bit of the first input vector corresponding to the first logic elimination unit is set to 0, and then an XOR operation is performed with the second input vector to obtain the first candidate vector. Otherwise, if the principal bit of the first input vector corresponding to the first logic elimination unit is 1 and the principal bit of the second input vector corresponding to the first logic elimination unit is 0, the second input vector is used as the second candidate vector. Otherwise, if the principal bits of the first input vector and the second input vector corresponding to the second logic elimination unit are both 1, the value of the principal bit of the first input vector corresponding to the second logic elimination unit is set to 0, and then an XOR operation is performed with the second input vector to obtain the third candidate vector; Otherwise, if the principal bit of the first input vector corresponding to the second logic elimination unit is 1 and the principal bit of the second input vector corresponding to the second logic elimination unit is 0, the second input vector is used as the fourth candidate vector.
[0008] Optionally, when the first logic elimination unit is initialized, candidate vectors are determined based on the values of the principal bits of the first input vector and the second input vector corresponding to the first logic elimination unit and the first elimination vector corresponding to the first logic elimination unit, including: If the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector are both 1, calculate the XOR value between the first input vector and the first elimination vector corresponding to the first logic elimination unit to obtain the fifth candidate vector, and calculate the XOR value between the second input vector and the first elimination vector to obtain the sixth candidate vector. If the principal bit values of the first input vector and the second input vector corresponding to the first logic elimination unit are both 0, the first input vector and the second input vector are respectively regarded as the seventh candidate vector and the eighth candidate vector.
[0009] Optionally, based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When both the first and second logic elimination units are in an uninitialized state, if the values of the principal bits of the first and second input vectors corresponding to the first and second logic elimination units are both 0, the target double-column elimination unit maintains an uninitialized state, directly outputs the first and second input vectors, and inputs them to the next level double-column elimination unit.
[0010] Optionally, based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When both the first and second logic elimination units are in an uninitialized state, the output of the target double-column elimination unit is determined according to the values of the principal bits of the first and second input vectors corresponding to the first and second logic elimination units, and the initialization state of the target double-column elimination unit is updated using the first input vector, the second input vector, the first candidate vector, the second candidate vector, and / or the fourth candidate vector.
[0011] Optionally, based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When one of the first logic elimination unit and the second logic elimination unit is initialized and the other is not initialized, the output of the target double column elimination unit is determined according to the values of the principal bits of the first logic elimination unit and the second logic elimination unit corresponding to the first input vector, the second input vector, the fifth candidate vector, the sixth candidate vector, the seventh candidate vector and / or the eighth candidate vector. The initialization state of the target double column elimination unit is updated using the first input vector, the second input vector, the fifth candidate vector, the sixth candidate vector, the seventh candidate vector and / or the eighth candidate vector.
[0012] Optionally, based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When both the first and second logic elimination units are in the initialized state, the output of the double-column elimination unit is determined according to the values of the principal bits of the second logic elimination unit corresponding to the fifth and sixth candidate vectors.
[0013] Optionally, the number of the dual-column elimination units is obtained by rounding down half the number of information bits.
[0014] This application also provides a look-ahead Gaussian elimination device, including: The acquisition module is used to acquire a first input vector and a second input vector for inputting the target bicolumn elimination unit within one clock cycle; wherein, when the target bicolumn elimination unit is a first-level bicolumn elimination unit, the first input vector and the second input vector are read from the generator matrix; when the target bicolumn elimination unit is a subsequent-level bicolumn elimination unit, the first input vector and the second input vector are the outputs of the previous-level bicolumn elimination unit. The calculation module is used to calculate the candidate vector based on the first input vector and the second input vector, according to the current initialization state of the target bicolumn elimination unit. The elimination processing module is used to determine the output of the target double-column elimination unit based on the first input vector, the second input vector, and / or the candidate vector according to the current initialization state of the target double-column elimination unit, and update the initialization state of the target double-column elimination unit.
[0015] As can be seen from the above description, the Gaussian elimination method and apparatus provided in this application, within one clock cycle, acquires a first input vector and a second input vector for inputting the target double-column elimination unit. Based on the current initialization state of the target double-column elimination unit, candidate vectors are calculated using the first and second input vectors. Based on the current initialization state of the target double-column elimination unit, the output of the target double-column elimination unit is determined using the first input vector, the second input vector, and the candidate vectors, and the initialization state of the target double-column elimination unit is updated. This application can process two columns of data in the generator matrix using the double-column elimination unit within one clock cycle, effectively reducing processing time and resource consumption, and improving processing efficiency. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of the OSD decoding process according to an embodiment of this application; Figure 2 This is a schematic diagram of the cascaded structure of single-column elimination units in some embodiments; Figure 3 This is a schematic diagram of the elimination process of a single-column elimination unit in some embodiments; Figure 4 This is a schematic diagram of the cascaded structure of the double-column elimination unit in an embodiment of this application; Figure 5 This is a schematic diagram of the cascaded structure of a double-row elimination unit according to another embodiment of this application; Figure 6 This is a schematic diagram of the cascaded structure of a double-row elimination unit according to another embodiment of this application; Figure 7 This is a schematic diagram of the elimination process of the dual-column elimination unit in an embodiment of this application; Figure 8 This is a block diagram of the device structure according to an embodiment of this application; Figure 9 This is a block diagram of the electronic device structure according to an embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0020] like Figure 1 As shown, in the OSD decoding process, the receiver sorts the original received sequence by reliability to obtain the sorted first sequence index. The generator matrix is then sorted according to the first sequence index. Gaussian elimination is used to transform the sorted generator matrix to obtain the system generator matrix consisting of the identity matrix and the parity check matrix, as well as the transformed second sequence index. After hard decision on the received sequence, it is rearranged according to the first and second sequence indices. The rearranged codewords and the system generator matrix are then subjected to matrix operations to obtain the recovered estimated codewords. It is determined whether the estimated codewords can pass the parity check. If they pass the parity check, the decoding ends. If they fail the parity check, bit flipping is performed on the remaining unreliable positions according to the pre-configured error pattern. Different error patterns are tested until a codeword that can pass the parity check is determined.
[0021] In OSD decoding, transforming the generator matrix using Gaussian elimination is the most resource-intensive step. For example... Figure 2 , 3 As shown, in the related technologies of Gaussian elimination based on hardware architecture, multiple cascaded single-column elimination units are used to implement elimination. Each single-column elimination unit can be used to perform one column transformation. The number of single-column elimination units is consistent with the number of information bits. For example, if there are k information bits in a linear block code (k, n), then k single-column elimination units are needed for Gaussian elimination. Each single-column elimination unit is set with a pivot bit and a storage unit for storing the elimination vector. The pivot bits of each cascaded single-column elimination unit correspond to the pivot bits on the diagonal of the identity matrix. For example, the pivot bit of the first single-column elimination unit is P1, which corresponds to the first row and first column of the top left corner of the identity matrix, and the pivot bit of the last single-column elimination unit is Pk, which corresponds to the kth row and kth column of the bottom right corner of the identity matrix.
[0022] During elimination, a column of data is read sequentially from the generator matrix according to the first sequence index. The first column of data is used as the input vector and input to the first single-column elimination unit. The process continues until the last column of data is output from the last single-column elimination unit, thus completing the overall elimination process.
[0023] The elimination method of a single-column elimination unit includes: In the first clock cycle, the first column of data is read and input into the first single-column elimination unit. It is determined whether the value of the pivot bit P1 corresponding to the input vector in the first single-column elimination unit is 1. If it is 1, and the first single-column elimination unit has not yet been initialized, the input vector is used to initialize the first single-column elimination unit. After changing the value of 1 in the pivot bit of the input vector to 0, it is used as the elimination vector 1 corresponding to the first single-column elimination unit and saved. Then, the input vector is set to all 0s and output, and then input into the second single-column elimination unit. That is, this input vector has already initialized one single-column elimination unit, and it will not be used to initialize other single-column elimination units subsequently; only the sequence index corresponding to this input vector is recorded. If the value of the pivot bit P1 corresponding to the input vector is 0, the input vector is directly output through the first single-column elimination unit and input into the second single-column elimination unit.
[0024] In the second clock cycle, the second column of data is read and input into the first single-column elimination unit. It is determined whether the value of the pivot bit P1 of the first single-column elimination unit corresponding to the input vector is 1. If it is 1, it is determined whether the first single-column elimination unit has been initialized. If it has been initialized, that is, the elimination vector 1 has been recorded, the input vector and the elimination vector 1 are XORed (i.e., elimination is performed), the result is output and input into the second single-column elimination unit, and the all-zero vector of the second single-column elimination unit continues to be passed to the third single-column elimination unit.
[0025] In the third clock cycle, it is determined whether the value of the pivot bit P2 of the second single-column elimination unit is 1. If it is 1 and the second single-column elimination unit is not initialized, the second single-column elimination unit is initialized using this input vector. The value of 1 in the pivot bit of the input vector is changed to 0, and this is used as the elimination vector 1 corresponding to the second single-column elimination unit and saved. Then, the input vector is set to all 0s and input to the third single-column elimination unit. If the value of the pivot bit P2 of the second single-column elimination unit is 0, the input vector cannot initialize the second single-column elimination unit. It is output by the second single-column elimination unit and input to the third single-column elimination unit. In parallel within this clock cycle, the all-zero vector of the third single-column elimination unit continues to be passed to the fourth single-column elimination unit.
[0026] Following the above process, a column of data is read sequentially from the generator matrix. In each clock cycle, each single-column elimination unit performs pivot bit determination, calculation, and output processing on its respective input vector in parallel. One clock cycle completes the processing for one single-column elimination unit. After all k single-column elimination units are initialized, the input vectors corresponding to the identity matrix are output as all zeros, and the sequence indices corresponding to each output input vector are recorded. The remaining nk columns of data are then processed by each initialized single-column elimination unit and output in their eliminated form, thus obtaining the parity check matrix. The known identity matrix and the obtained parity check matrix are concatenated to obtain the system generator matrix, which is then used for decoding.
[0027] In the elimination scheme described above using single-column elimination units, the mechanism of reading data column by column and processing it serially by the single-column elimination units requires at least k clock cycles to complete Gaussian elimination of k information bits. As the code length n and the number of information bits k increase, the decoding delay increases linearly. This cumulative delay affects the performance of ultra-reliable low-latency communication systems. Furthermore, cascaded single-column elimination units exhibit strong data dependencies; that is, the processing of the current single-column elimination unit depends on the result of the previous single-column elimination unit. This strong coupling makes it difficult to integrate into an efficient pipeline. Forcibly inserting pipeline registers into the hardware would generate a large number of idle wait cycles, reducing hardware resource utilization.
[0028] In view of this, this application provides a look-ahead Gaussian elimination method, which constructs an elimination architecture consisting of multiple cascaded bi-column elimination units. Each bi-column elimination unit is formed by merging two single-column elimination units. Only a storage area and a small amount of computation are added within the bi-column elimination unit, which can reduce the number of single-column elimination units by half, reduce data connections between elimination units, reduce resource consumption, and improve resource utilization. At the same time, two columns of data are read from the generator matrix, and candidate vectors are obtained through look-ahead computation. The data required by the bi-column elimination unit can be obtained directly, breaking the data dependency. The relevant processing of a bi-column elimination unit can be completed in one clock cycle, which reduces the time consumed by matrix operations by half and effectively reduces processing latency.
[0029] The technical solution of this application will be further described in detail below through specific embodiments.
[0030] like Figure 4 , 5 As shown, this application embodiment constructs an elimination architecture composed of multiple cascaded double-column elimination units. The number of double-column elimination units is obtained by rounding down half the number of information bits. For example, for k information bits, it is necessary to... Gaussian elimination is performed using two bi-column elimination units. Each bi-column elimination unit has two pivot bits and a storage unit for storing the two elimination vectors. The pivot bits of each cascaded bi-column elimination unit correspond to the pivot bits on the diagonal of the identity matrix.
[0031] In some methods, for linear block codes, the first bit of the first column of the generator matrix is set to 1. When the number of information bits is odd, an additional cancellation vector is set. Gaussian elimination can be achieved with a double-column elimination unit.
[0032] like Figure 6 As shown, for ease of understanding, a double-column elimination unit can be considered equivalent to a logical combination of two single-column elimination units. That is, a double-column elimination unit includes a first logical elimination unit and a second logical elimination unit. The first and second logical elimination units each have corresponding pivot bits and storage units for storing elimination vectors. For example, the pivot bit of the first logical elimination unit is P1, corresponding to the first row and first column of the top-left corner of the identity matrix, and it is configured with the first elimination vector. The pivot bit of the second logical elimination unit is P2, corresponding to the second row and second column of the identity matrix, and it is configured with the second elimination vector. It should be noted that a double-column elimination unit is actually a single elimination unit; that is, it contains two pivot bits and two elimination vectors. The first and second logical elimination units are a logical division based on a single elimination unit, not two single-column elimination units that require data connection.
[0033] During elimination, the first and second columns of data are sequentially read from the generator matrix according to the first sequence index. These read columns are then used as the first and second input vectors, respectively, and input into the first two-column elimination unit. This process continues until the last two columns of data are output from the last two-column elimination unit, completing the overall elimination process. Since the first input vector is read first, followed by the second, the first input vector has higher priority than the second in the order of input to the two-column elimination units. In other words, the first input vector is input first, then the second; or, the first input vector is processed first, then the second.
[0034] like Figure 7 As shown, the Gaussian elimination method with lookahead operation provided in this application is based on an elimination architecture composed of multiple cascaded bi-column elimination units. The method includes: S701: Within one clock cycle, acquire the first input vector and the second input vector used to input the target double column elimination unit; wherein, when the target double column elimination unit is a first-level double column elimination unit, the first input vector and the second input vector are read from the generator matrix, and when the target double column elimination unit is a subsequent-level double column elimination unit, the first input vector and the second input vector are the outputs of the previous-level double column elimination unit; In this embodiment, two columns of data are read simultaneously within one clock cycle, and a single dual-column elimination unit processes both input vectors concurrently. For example... Figure 5 , 6 As shown, multiple double-column elimination units are cascaded sequentially to form a first-level double-column elimination unit, a second-level double-column elimination unit, and so on. The first-level double-column elimination unit (PCU) is used to initialize two columns of data read from the generator matrix. These two columns are either initialized by performing an XOR operation on the input vectors using the already initialized PCU, or the PCU is output directly without processing. These two vectors then serve as the two input vectors for the second-level PCU. The second-level PCU is initialized by performing the XOR operation on the input vectors using the already initialized PCU, or the PCU is output directly without processing. In other words, except for the first-level PCU, whose input is directly read from the generator matrix, the two input vectors for all other levels of PCU are the two output vectors of the previous level's PCU.
[0035] S702: Based on the current initialization state of the target bicolumn elimination unit, calculate the candidate vector based on the first input vector and the second input vector; In this embodiment, while acquiring the two input vectors of the target bi-column elimination unit, the current initialization state of the target bi-column elimination unit is read, and candidate vectors are pre-calculated based on the first and second input vectors according to the current initialization state. The pre-calculated candidate vectors reduce the time occupied by subsequent processing.
[0036] In some implementations, candidate vectors are calculated based on the first input vector and the second input vector, according to the current initialization state of the target bicolumn elimination unit, including: When the first logic elimination unit is not initialized, the candidate vector is determined according to the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit and the pivot bits of the second logic elimination unit. When the first logic elimination unit has been initialized, the candidate vector is determined according to the values of the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector, and the first elimination vector corresponding to the first logic elimination unit.
[0037] Specifically, when the first logic elimination unit is not initialized, candidate vectors are determined based on the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit and the pivot bits of the second logic elimination unit, including: If the principal bits of the first input vector and the second input vector corresponding to the first logic elimination unit are both 1, the value of the principal bit of the first input vector corresponding to the first logic elimination unit is set to 0, and then XORed with the second input vector to obtain the first candidate vector. Otherwise, if the principal bit of the first input vector corresponding to the first logic elimination unit is 1 and the principal bit of the second input vector corresponding to the first logic elimination unit is 0, the second input vector is taken as the second candidate vector. Otherwise, if the principal bits of the first and second input vectors corresponding to the second logic elimination unit are both 1, the value of the principal bit of the first input vector corresponding to the second logic elimination unit is set to 0, and then an XOR operation is performed with the second input vector to obtain the third candidate vector; Otherwise, if the principal bit of the first input vector corresponding to the second logic elimination unit is 1, and the principal bit of the second input vector corresponding to the second logic elimination unit is 0, the second input vector is used as the fourth candidate vector.
[0038] When the first logic elimination unit is initialized, the second look-ahead operation vector is determined based on the values of the pivot bits of the first logic elimination unit corresponding to the first input vector and the second input vector, and the first elimination vector corresponding to the first logic elimination unit. This includes: If the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector are both 1, calculate the XOR value between the first input vector and the first elimination vector corresponding to the first logic elimination unit to obtain the fifth candidate vector, and calculate the XOR value between the second input vector and the first elimination vector to obtain the sixth candidate vector. If the principal bit values of the first logic elimination unit corresponding to the first input vector and the second input vector are both 0, the first input vector and the second input vector are respectively regarded as the seventh candidate vector and the eighth candidate vector.
[0039] For example, the exemplary first and second input vectors are represented as follows: (The right column of the matrix represents the first input vector, and the left column represents the second input vector.) The pivot bit of the first logic elimination unit is P1, meaning that the values of both the first and second input vectors at pivot bit P1 are 1. Therefore, after setting the value of the first input vector at pivot bit P1 to 0 and XORing it with the second input vector, the first candidate vector is calculated as follows: .
[0040] The first input vector and the second input vector are represented as follows: If the value of the first input vector at pivot P1 is 1 and the value of the second input vector at pivot P1 is 0, then the second candidate vector is the second input vector. .
[0041] The first input vector and the second input vector are represented as follows: The pivot bit of the second logic elimination unit is P2, meaning the value of the first input vector at pivot bit P2 is 1, and the value of the second input vector at pivot bit P2 is also 1. Therefore, after setting the value of the first input vector at pivot bit P2 to 0, and then XORing it with the second input vector, the third candidate vector is calculated. .
[0042] The first input vector and the second input vector are represented as follows: If the value of the first input vector at pivot P2 is 1 and the value of the second input vector at pivot P2 is 0, then the fourth candidate vector is the second input vector. .
[0043] S703: Based on the current initialization state of the target bicolumn elimination unit, determine the output of the target bicolumn elimination unit based on the first input vector, the second input vector, and / or the candidate vector, and update the initialization state of the target bicolumn elimination unit.
[0044] In some embodiments, when both the first logic elimination unit and the second logic elimination unit are in an uninitialized state, the output of the target double-column elimination unit is determined according to the values of the principal bits of the first and second logic elimination units corresponding to the first and second input vectors, and the initialization state of the target double-column elimination unit is updated using the first input vector, the second input vector, the first candidate vector, the second candidate vector, and / or the fourth candidate vector.
[0045] Specifically, when the first and second logic elimination units of the target double-column elimination unit are both uninitialized, if the values of the principal bits of the first and second input vectors corresponding to the first and second logic elimination units are both 0, then neither the first nor the second input vectors can initialize the first and second logic elimination units. The target double-column elimination unit remains uninitialized, and the first and second input vectors are directly output and input to the next level double-column elimination unit.
[0046] For example, the first input vector and the second input vector are represented as follows: If the values of the two input vectors are both 0 at the pivot bit P1 of the first logic elimination unit and the pivot bit P2 of the second logic elimination unit, it means that neither input vector can initialize the two double-column elimination units. The two input vectors are directly output from the current double-column elimination unit and enter the next level double-column elimination unit. The processing of the next level double-column elimination unit is performed according to the initialization state of the next level double-column elimination unit and the values of the input vectors at the corresponding pivot bits.
[0047] When both the first and second logical elimination units of the target double-column elimination unit are uninitialized, if the value of the pivot bit of the first input vector corresponding to the first logical elimination unit is 0, the value of the pivot bit of the first input vector corresponding to the second logical elimination unit is 1, and the value of the pivot bit of the second input vector corresponding to the first logical elimination unit is 1, the second logical elimination unit is initialized using the first input vector. The second elimination vector of the second logical elimination unit is the vector after setting the pivot bit of the second logical elimination unit corresponding to the first input vector to 0. The first logical elimination unit is initialized using the second input vector (i.e., the fourth candidate vector). The first elimination vector of the first logical elimination unit is the vector after setting the pivot bit of the first logical elimination unit corresponding to the second input vector to 0. In this case, both logical elimination units of the target double-column elimination unit are initialized, and the output is the first and second input vectors set to all zeros, used to record the index.
[0048] For example, the first input vector and the second input vector are represented as follows: The first input vector has a value of 0 at the pivot bit P1 of the first logic elimination unit and a value of 1 at the pivot bit P2 of the second logic elimination unit. The second input vector has a value of 1 at the pivot bit P1 of the first logic elimination unit and a value of 0 at the pivot bit P2 of the second logic elimination unit. The first input vector can directly initialize the second logic elimination unit, and the second input vector can directly initialize the first logic elimination unit.
[0049] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the first input vector corresponds to a pivot bit of 1 for the first logic elimination unit and a pivot bit of 0 for the second logic elimination unit, and the second input vector corresponds to a pivot bit of 0 for the first logic elimination unit and a pivot bit of 1 for the second logic elimination unit, the first logic elimination unit is initialized using the first input vector, and the second logic elimination unit is initialized using the second candidate vector (i.e., the second input vector). In this case, both column elimination units of the target double-column elimination unit are initialized, and the output is the first and second input vectors set to all zeros.
[0050] For example, the first input vector and the second input vector are represented as follows: The first input vector has a value of 1 at the pivot bit P1 of the first logic elimination unit and a value of 0 at the pivot bit P2 of the second logic elimination unit. The second input vector has a value of 0 at the pivot bit P1 of the first logic elimination unit and a value of 1 at the pivot bit P2 of the second logic elimination unit. The first input vector can directly initialize the first logic elimination unit, and the second candidate vector can directly initialize the second logic elimination unit.
[0051] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the pivot bits of the first and second input vectors corresponding to the first logic elimination unit are both 1, and the pivot bits of the first and second input vectors corresponding to the second logic elimination unit are different, the first logic elimination unit is initialized using the first input vector, and the second logic elimination unit is initialized using the first candidate vector. In this case, both logic elimination units of the target double-column elimination unit are initialized, and the output is the first and second input vectors set to all zeros.
[0052] For example, the first input vector and the second input vector are represented as follows: or The first input vector and the second input vector both have a principal bit P1 of 1 in the first logic elimination unit. The first input vector and the second input vector have different values in the principal bit P2 of the second logic elimination unit. The first input vector can initialize the first logic elimination unit, and the first candidate vector can initialize the second logic elimination unit.
[0053] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit are both 1, and the values of the pivot bits of the first and second input vectors corresponding to the second logic elimination unit are the same, the first logic elimination unit is initialized using the first input vector, while the second logic elimination unit cannot be initialized. In this case, the first input vector is set to all 0s and then output, and the first candidate vector is directly output to the next level of the double-column elimination unit.
[0054] For example, the first input vector and the second input vector are represented as follows: or The first input vector and the second input vector both have a value of 1 in the pivot bit P1 of the first logic elimination unit. The first input vector and the second input vector have the same value in the pivot bit P2 of the second logic elimination unit. The first input vector can initialize the first logic elimination unit. The first candidate vector cannot initialize the second logic elimination unit because its value in the pivot bit P2 is 0.
[0055] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the values of the pivot bits of the first and second logic elimination units corresponding to the first and second logic elimination units are both 0, and the value of the pivot bit of the first logic elimination unit corresponding to the second input vector is 1, the first logic elimination unit is initialized using the second input vector. The second logic elimination unit cannot be initialized. The first input vector is output directly, and the second input vector is set to all 0s before being output.
[0056] For example, the first input vector and the second input vector are represented as follows: or The values of the pivot bits P1 and P2 corresponding to the first input vector are both 0, so the first and second logic elimination units cannot be initialized and are directly output. The value of the pivot bit P1 corresponding to the second input vector is 1, so the first logic elimination unit can be initialized.
[0057] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the values of the pivot bits of the first and second input vectors corresponding to the second logic elimination unit are both 1 and the values of the pivot bits corresponding to the first logic elimination unit are both 0, the second logic elimination unit is initialized using the first input vector. If the first logic elimination unit cannot be initialized, the first input vector is set to 0 and then output, and the third candidate vector is output directly.
[0058] For example, the first input vector and the second input vector are represented as follows: The values of the pivot bit P1 corresponding to the first logic elimination unit are both 0 for the first input vector and the pivot bit P2 corresponding to the second logic elimination unit. The first input vector can initialize the second logic elimination unit, but the second input vector cannot initialize the first logic elimination unit. The third candidate vector is directly output.
[0059] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit are both 0, the value of the pivot bit of the first input vector corresponding to the second logic elimination unit is 1, and the value of the pivot bit of the second input vector corresponding to the second logic elimination unit is 0, the second logic elimination unit is initialized using the first input vector. If the first logic elimination unit cannot be initialized, the first input vector is set to all 0 and then output, and the fourth candidate vector (i.e., the second input vector) is directly output.
[0060] For example, the first input vector and the second input vector are represented as follows: The values of the pivot bit P1 corresponding to the first logic elimination unit of the first input vector and the second input vector are both 0. The value of the pivot bit P2 corresponding to the second logic elimination unit of the first input vector is 1. The value of the pivot bit P2 corresponding to the second logic elimination unit of the second input vector is 0. The first input vector can initialize the second logic elimination unit, but the second input vector cannot initialize the first logic elimination unit. The fourth candidate vector is directly output.
[0061] When neither the first nor the second logic elimination unit of the target double-column elimination unit is initialized, if the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit are both 0, the value of the pivot bit of the first input vector corresponding to the second logic elimination unit is 0, and the value of the pivot bit of the second input vector corresponding to the second logic elimination unit is 1, the second logic elimination unit is initialized using the second input vector. The first logic elimination unit cannot be initialized, the first input vector is output directly, and the second input vector is set to all 0s before being output.
[0062] For example, the first input vector and the second input vector are represented as follows: The values of the first input vector and the second input vector corresponding to the pivot bit P1 of the first logic elimination unit are both 0. The value of the first input vector corresponding to the pivot bit P2 of the second logic elimination unit is 0, and the value of the second input vector corresponding to the pivot bit P2 is 1. The first input vector is directly output, and the second input vector is used to initialize the second logic elimination unit.
[0063] In some embodiments, when one of the first logic elimination unit and the second logic elimination unit is initialized and the other is not initialized, the output of the target double column elimination unit is determined according to the values of the principal bits of the first logic elimination unit and the second logic elimination unit corresponding to the first input vector, the second input vector, the fifth candidate vector, the sixth candidate vector, the seventh candidate vector and / or the eighth candidate vector, and the initialization state of the target double column elimination unit is updated using the first input vector, the second input vector, the fifth candidate vector, the sixth candidate vector, the seventh candidate vector and / or the eighth candidate vector.
[0064] Specifically, when the first logic elimination unit has been initialized and the second logic elimination unit has not been initialized, if the value of the pivot bit of the fifth candidate vector (the XOR value of the first input vector and the first elimination vector) corresponding to the second logic elimination unit is 1, the second logic elimination unit is initialized using the fifth candidate vector. After the fifth candidate vector is set to all 0s, it is output. It is then determined whether the value of the pivot bit of the sixth candidate vector (the XOR value of the second input vector and the first elimination vector) corresponding to the second logic elimination unit is 1. If it is 1, the XOR value of the sixth candidate vector and the second elimination vector of the second logic elimination unit is calculated and the XOR value is output. If it is 0, the sixth candidate vector is output directly.
[0065] If the value of the pivot bit of the fifth candidate vector corresponding to the second logic elimination unit is 0, the fifth candidate vector cannot initialize the second logic elimination unit, and the fifth candidate vector is directly output. Then, it is determined whether the value of the pivot bit of the sixth candidate vector corresponding to the second logic elimination unit is 1. If it is 1, the sixth candidate vector is used to initialize the second logic elimination unit. The sixth candidate vector is set to all 0 and then output. If it is 0, the second logic elimination unit cannot be initialized, and the sixth candidate vector is directly output.
[0066] When the first logic elimination unit has been initialized and the second logic elimination unit has not been initialized, if the value of the principal bit of the seventh candidate vector (first input vector) corresponding to the second logic elimination unit is 1, the second logic elimination unit is initialized using the seventh candidate vector. After the seventh candidate vector is set to all 0s, it is output. It is then determined whether the value of the principal bit of the eighth candidate vector (second input vector) corresponding to the second logic elimination unit is 1. If it is 1, the XOR value of the eighth candidate vector and the second elimination vector of the second logic elimination unit is calculated and the XOR value is output. If it is 0, the eighth candidate vector is output directly.
[0067] If the value of the pivot bit of the seventh candidate vector corresponding to the second logic elimination unit is 0, the seventh candidate vector cannot initialize the second logic elimination unit, and the seventh candidate vector is directly output. Then, it is determined whether the value of the pivot bit of the eighth candidate vector corresponding to the second logic elimination unit is 1. If it is 1, the second logic elimination unit is initialized using the eighth candidate vector, and the eighth candidate vector is set to all 0s and then output. If it is 0, the second logic elimination unit cannot be initialized, and the eighth candidate vector is directly output.
[0068] When the first logic elimination unit is not initialized and the second logic elimination unit is initialized, if the values of the pivot bits of the first input vector and the second input vector corresponding to the first logic elimination unit are both 0, the first logic elimination unit cannot be initialized. It is then determined whether the value of the pivot bit of the first input vector corresponding to the second logic elimination unit is 1. If it is 1, the XOR value of the first input vector and the second elimination vector is calculated and output. If it is 0, the first output vector is output directly. It is then determined whether the value of the pivot bit of the second input vector corresponding to the second logic elimination unit is 1. If it is 1, the XOR value of the second input vector and the second elimination vector is calculated and output. If it is 0, the second output vector is output directly.
[0069] When the first logic elimination unit is not initialized and the second logic elimination unit is initialized, if the value of the pivot bit of the first input vector corresponding to the first logic elimination unit is 1 and the value of the pivot bit of the second input vector corresponding to the first logic elimination unit is 0, the first logic elimination unit is initialized using the first input vector. After the first input vector is set to all 0, it is output. The XOR value of the second candidate vector and the second elimination vector is calculated and the XOR value is output.
[0070] When the first logic elimination unit is not initialized and the second logic elimination unit is initialized, if the value of the pivot bit of the first input vector corresponding to the first logic elimination unit is 0, determine whether the value of the pivot bit of the first input vector corresponding to the second logic elimination unit is 1. If it is 1, calculate the XOR value of the first input vector and the second elimination vector and output the XOR value. If it is 0, output the first input vector. If the value of the pivot bit of the second input vector corresponding to the first logic elimination unit is 1, initialize the first logic elimination unit using the second input vector, set the second input vector to all 0s, and then output it.
[0071] In some embodiments, when both the first logic elimination unit and the second logic elimination unit are in an initialized state, the output of the double-column elimination unit is determined based on the values of the principal bits of the second logic elimination unit corresponding to the fifth and sixth candidate vectors.
[0072] Specifically, when both the first and second logic elimination units are initialized, it is determined whether the value of the pivot bit of the fifth candidate vector corresponding to the second logic elimination unit is 1. If it is 1, the XOR value of the fifth candidate vector and the second elimination vector is calculated and output. If it is 0, the fifth candidate vector is output. It is also determined whether the value of the pivot bit of the sixth candidate vector corresponding to the second logic elimination unit is 1. If it is 1, the XOR value of the sixth candidate vector and the second elimination vector is calculated and output. If it is 0, the sixth candidate vector is output.
[0073] The Gaussian elimination method provided in this application employs a two-column elimination unit comprising two pivot bits and two elimination vectors. Within one clock cycle, this unit can process two columns of data in the generated matrix. Compared to a single-column elimination unit, although the resource consumption of each two-column unit is slightly increased (requiring storage of two elimination vectors) and candidate vectors need to be pre-calculated, the total number of elimination units is halved, the data connections between elimination units are correspondingly reduced, and the overall resource consumption is significantly reduced. The total clock cycle required for the Gaussian elimination process is halved, effectively improving processing efficiency and resource utilization, significantly reducing decoding latency, and greatly enhancing the response speed of the communication system. This meets the extreme real-time requirements of ultra-reliable, low-latency communication systems. The provided advance candidate vector calculation scheme can solve the logic contention problem when using two or more parallel inputs, breaking through the current technology's ceiling on parallelism, significantly improving the overall throughput of the decoder, and providing a scalable foundation for future designs of polar code decoding architectures with higher parallelism.
[0074] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method described.
[0075] It should be noted that the above description describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims may be performed in a different order than that shown in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0076] like Figure 8 As shown in the figure, this application embodiment also provides a look-ahead Gaussian elimination device, including: The acquisition module is used to acquire the first input vector and the second input vector for the target bi-column elimination unit within one clock cycle; wherein, when the target bi-column elimination unit is a first-level bi-column elimination unit, the first input vector and the second input vector are read from the generator matrix; when the target bi-column elimination unit is a subsequent-level bi-column elimination unit, the first input vector and the second input vector are the outputs of the previous-level bi-column elimination unit. The calculation module is used to calculate the candidate vector based on the first input vector and the second input vector, according to the current initialization state of the target bicolumn elimination unit. The elimination processing module is used to determine the output of the target bi-column elimination unit based on the first input vector, the second input vector, and / or the candidate vector, according to the current initialization state of the target bi-column elimination unit, and to update the initialization state of the target bi-column elimination unit.
[0077] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing the embodiments of this application, the functions of each module can be implemented in one or more software and / or hardware.
[0078] The apparatus described above is used to implement the corresponding methods in the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0079] Figure 9 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.
[0080] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.
[0081] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.
[0082] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.
[0083] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).
[0084] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.
[0085] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.
[0086] The electronic devices described above are used to implement the corresponding methods in the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0087] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.
[0088] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.
[0089] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.
[0090] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.
[0091] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this disclosure.
Claims
1. A Gaussian elimination method with look-ahead computation, characterized in that, include: Within one clock cycle, a first input vector and a second input vector are acquired for inputting the target bicolumn elimination unit; wherein, when the target bicolumn elimination unit is a first-level bicolumn elimination unit, the first input vector and the second input vector are read from the generator matrix, and when the target bicolumn elimination unit is a subsequent-level bicolumn elimination unit, the first input vector and the second input vector are the outputs of the previous-level bicolumn elimination unit; Based on the current initialization state of the target bicolumn elimination unit, candidate vectors are calculated using the first and second input vectors. Based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated.
2. The method according to claim 1, characterized in that, The target double-column elimination unit includes a first logic elimination unit and a second logic elimination unit. The first logic elimination unit and the second logic elimination unit are respectively configured with corresponding pivot bits and storage units for storing elimination vectors. Based on the current initialization state of the target bicolumn elimination unit, and using the first and second input vectors, candidate vectors are calculated, including: When the first logic elimination unit is not initialized, the candidate vector is determined according to the values of the principal bits of the first logic elimination unit and the second logic elimination unit corresponding to the first input vector and the second input vector. When the first logic elimination unit is initialized, the candidate vector is determined based on the values of the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector, and the first elimination vector corresponding to the first logic elimination unit.
3. The method according to claim 2, characterized in that, When the first logic elimination unit is not initialized, candidate vectors are determined based on the values of the pivot bits of the first and second input vectors corresponding to the first logic elimination unit and the pivot bits of the second logic elimination unit, including: If the principal bits of the first input vector and the second input vector corresponding to the first logic elimination unit are both 1, the value of the principal bit of the first input vector corresponding to the first logic elimination unit is set to 0, and then an XOR operation is performed with the second input vector to obtain the first candidate vector. Otherwise, if the principal bit of the first input vector corresponding to the first logic elimination unit is 1 and the principal bit of the second input vector corresponding to the first logic elimination unit is 0, the second input vector is used as the second candidate vector. Otherwise, if the principal bits of the first input vector and the second input vector corresponding to the second logic elimination unit are both 1, the value of the principal bit of the first input vector corresponding to the second logic elimination unit is set to 0, and then an XOR operation is performed with the second input vector to obtain the third candidate vector; Otherwise, if the principal bit of the first input vector corresponding to the second logic elimination unit is 1 and the principal bit of the second input vector corresponding to the second logic elimination unit is 0, the second input vector is used as the fourth candidate vector.
4. The method according to claim 3, characterized in that, When the first logic elimination unit is initialized, candidate vectors are determined based on the values of the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector, and the first elimination vector corresponding to the first logic elimination unit. These candidate vectors include: If the principal bits of the first logic elimination unit corresponding to the first input vector and the second input vector are both 1, calculate the XOR value between the first input vector and the first elimination vector corresponding to the first logic elimination unit to obtain the fifth candidate vector, and calculate the XOR value between the second input vector and the first elimination vector to obtain the sixth candidate vector. If the principal bit values of the first input vector and the second input vector corresponding to the first logic elimination unit are both 0, the first input vector and the second input vector are respectively regarded as the seventh candidate vector and the eighth candidate vector.
5. The method according to claim 2, characterized in that, Based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When both the first and second logic elimination units are in an uninitialized state, if the values of the principal bits of the first and second input vectors corresponding to the first and second logic elimination units are both 0, the target double-column elimination unit maintains an uninitialized state, directly outputs the first and second input vectors, and inputs them to the next level double-column elimination unit.
6. The method according to claim 3, characterized in that, Based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When both the first and second logic elimination units are in an uninitialized state, the output of the target double-column elimination unit is determined according to the values of the principal bits of the first and second input vectors corresponding to the first and second logic elimination units, and the initialization state of the target double-column elimination unit is updated using the first input vector, the second input vector, the first candidate vector, the second candidate vector, and / or the fourth candidate vector.
7. The method according to claim 4, characterized in that, Based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When one of the first logic elimination unit and the second logic elimination unit is initialized and the other is not initialized, the output of the target double column elimination unit is determined according to the values of the principal bits of the first logic elimination unit and the second logic elimination unit corresponding to the first input vector, the second input vector, the fifth candidate vector, the sixth candidate vector, the seventh candidate vector and / or the eighth candidate vector. The initialization state of the target double column elimination unit is updated using the first input vector, the second input vector, the fifth candidate vector, the sixth candidate vector, the seventh candidate vector and / or the eighth candidate vector.
8. The method according to claim 4, characterized in that, Based on the current initialization state of the target bicolumn elimination unit, the output of the target bicolumn elimination unit is determined based on the first input vector, the second input vector, and / or the candidate vector, and the initialization state of the target bicolumn elimination unit is updated, including: When both the first and second logic elimination units are in the initialized state, the output of the double-column elimination unit is determined according to the values of the principal bits of the second logic elimination unit corresponding to the fifth and sixth candidate vectors.
9. The method according to any one of claims 1-8, characterized in that, The number of dual-column elimination units is obtained by rounding down half the number of information bits.
10. A Gaussian elimination device with lookahead calculation, characterized in that, include: The acquisition module is used to acquire a first input vector and a second input vector for inputting the target bicolumn elimination unit within one clock cycle; wherein, when the target bicolumn elimination unit is a first-level bicolumn elimination unit, the first input vector and the second input vector are read from the generator matrix; when the target bicolumn elimination unit is a subsequent-level bicolumn elimination unit, the first input vector and the second input vector are the outputs of the previous-level bicolumn elimination unit. The calculation module is used to calculate the candidate vector based on the first input vector and the second input vector, according to the current initialization state of the target bicolumn elimination unit. The elimination processing module is used to determine the output of the target double-column elimination unit based on the first input vector, the second input vector, and / or the candidate vector according to the current initialization state of the target double-column elimination unit, and update the initialization state of the target double-column elimination unit.