A compatibility testing method and apparatus for different generations of switching chips, electronic equipment, and computer-readable medium.

Abstract

This invention discloses a compatibility testing method, apparatus, electronic device, and computer-readable medium for different generations of switching chips. The method identifies key fields in the stacked message header that affect packet parsing, matching, and editing, constructs a test packet set, and inputs these test packets through the stacking port of the switching chip under test. The switching chip then performs parsing, matching, and editing operations on the packets and outputs forwarded packets from the panel port. During processing, internal intermediate data from key pipeline stages is collected using a hardware counter configured within the chip. Simultaneously, packet capture analysis is performed on the forwarded packets, comparing the stacked message header fields with the internal intermediate data and actual forwarding behavior to determine if hidden incompatibility issues caused by field reuse exist. This invention can systematically expose compatibility defects in multi-protocol interaction scenarios, improve test coverage and location accuracy, and reduce hardware upgrade risks.

Description

Technical Field

[0001] This invention relates to the field of compatibility testing technology for switch chips, and particularly to a compatibility testing method and apparatus, electronic device, and computer-readable medium for different generations of switch chips. Background Technology

[0002] Chassis-based switches typically consist of multiple line cards and switching network boards. When forwarding Ethernet packets between the line card switching chips and the switching network board switching chips, a vendor-defined stacking header (such as Broadcom's HiGig and HiGig2) is usually inserted before the Ethernet packet header to convey intermediate data required for internal forwarding between the switching chips (such as forwarding path identifiers and encapsulation control information). When upgrading switch hardware, to protect investment, some hardware boards are usually replaced to achieve a gradual upgrade. This can lead to the mixing of different generations of switching chips from the same manufacturer within the same chassis. Newer generations of switching chips are designed to be compatible with the stacking headers of older chips, thus ensuring basic functionality compatibility.

[0003] The main drawback is: To achieve line-speed forwarding between boards, the length of the stack header is limited. New switching chips, due to added functionalities, reuse some fields of the stack header, thus reducing compatibility with older switching chips. While analyzing the reused fields in the stack header can provide a direct assessment of the affected functionalities, the complex internal logic of the switching chip, coupled with compatibility requirements, can lead to hidden incompatibility issues. For example: 1. Packet loss in scenarios involving the combination of "L3 multicast + tunnel decapsulation + INT"; 2. Priority editing in the "SRv6 forwarding + VLAN addition / deletion + QoS priority editing" scenario does not meet expectations.

[0004] Existing technologies rely solely on field value comparisons or single message testing, failing to systematically cover the interactive impacts of multiple protocols and scenarios, leading to hidden faults (such as message loss or policy failure) after upgrades. Summary of the Invention

[0005] This invention aims to solve the hidden incompatibility problem caused by the reuse of stacked message header fields in the prior art, and designs a compatibility testing method and device for different generations of switching chips.

[0006] According to a first aspect of the present invention, a compatibility testing method for switching chips of different generations is provided, comprising the following steps: Identify the reused fields in the stacked message header and the key fields that may affect the message parsing, matching and editing process; Based on the identified key fields, test message field value combinations are generated to construct a test message set, which covers a variety of mainstream protocol types and edge operation scenarios; Construct test messages based on the test message set, and input the test messages to the switch chip under test through the stacking port of the switch chip under test; After receiving the test message, the switch chip under test performs parsing, matching-action and message editing on the test message, and outputs the processed forwarded message from the panel port of the switch chip under test; During the processing of test messages, the internal intermediate data generated by the test messages in key pipeline stages such as parsing, matching-action, and message editing is collected by the hardware counter configured in the switch chip under test. Meanwhile, forwarded packets are captured at the panel port of the switching chip. The stacked message header field value of the captured forwarded packet is compared with the corresponding field value of the internal intermediate data. The actual forwarding behavior of the captured forwarded packet is compared with the expected forwarding behavior. Based on the comparison results, it is determined whether there are any hidden incompatibilities.

[0007] Furthermore, the reusable fields in the stacked message header and the key fields that may affect the message parsing, matching, and editing process are specifically identified as follows: Obtain the stack message header definition and its internal intermediate data structure of the switching chip under test; Obtain the stack message header definition and corresponding field mapping relationship of the old switching chip; Compare the stack message header field mapping relationship between the switch chip under test and the old switch chip; Based on the comparison results, determine the fields that are reused and the key fields that may affect the message parsing, matching or editing process.

[0008] Furthermore, based on the identified key fields, the test message set is constructed as follows: Select extreme values ​​and boundary values ​​for each key field; The selected values ​​of each key field are cross-combined to generate test message field value combinations, thereby constructing a test message set.

[0009] Furthermore, the specific steps for constructing test messages based on the test message set are as follows: Insert the stacking message header of the switch chip under test before the Ethernet packet header; Set the values ​​of each key field in the stacked message header according to the combination of test message field values; Fill the payload portion of the test message with fixed test data.

[0010] According to a second aspect of the present invention, a compatibility testing apparatus for different generations of switching chips is provided, comprising: The identification module is used to identify reused fields in stacked message headers and key fields that may affect the message parsing, matching and editing process. The building module is used to generate test message field value combinations based on the identified key fields to build a test message set, which covers a variety of mainstream protocol types and edge operation scenarios; The construction module is used to construct test messages based on the test message set and input the test messages to the switch chip under test through the stacking port of the switch chip under test; The processing module is used to perform parsing, matching-action and message editing on the test message after the switch chip under test receives the test message, and output the processed forwarded message from the panel port of the switch chip under test. The acquisition module is used to acquire internal intermediate data generated during the critical pipeline stages of parsing, matching-action, and message editing of the test message by using a hardware counter configured in the switch chip under test during the processing of the test message. The comparison module is used to capture forwarded packets at the panel port of the switching chip while the acquisition module is collecting data. It compares the stacked message header field values ​​of the captured forwarded packets with the corresponding field values ​​of the internal intermediate data, and compares the actual forwarding behavior of the captured forwarded packets with the expected forwarding behavior. Based on the comparison results, it determines whether there are any hidden incompatibilities.

[0011] Furthermore, the reusable fields in the stacked message header and the key fields that may affect the message parsing, matching, and editing process are specifically identified as follows: Obtain the stack message header definition and its internal intermediate data structure of the switching chip under test; Obtain the stack message header definition and corresponding field mapping relationship of the old switching chip; Compare the stack message header field mapping relationship between the switch chip under test and the old switch chip; Based on the comparison results, determine the fields that are reused and the key fields that may affect the message parsing, matching or editing process.

[0012] Furthermore, based on the identified key fields, the test message set is constructed as follows: Select extreme values ​​and boundary values ​​for each key field; The selected values ​​of each key field are cross-combined to generate test message field value combinations, thereby constructing a test message set.

[0013] Furthermore, the specific steps for constructing test messages based on the test message set are as follows: Insert the stacking message header of the switch chip under test before the Ethernet packet header; Set the values ​​of each key field in the stacked message header according to the combination of test message field values; Fill the payload portion of the test message with fixed test data.

[0014] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor executes the computer program to perform a compatibility testing method for different generations of switching chips according to the first aspect.

[0015] According to a fourth aspect of the present invention, a computer-readable medium having processor-executable non-volatile program code is provided, characterized in that the program code causes the processor to run a compatibility testing method for different generations of switching chips according to the first aspect.

[0016] A compatibility testing method for different generations of switching chips according to embodiments of the present invention can identify interactive faults that cannot be detected by existing technologies. It exposes compatibility defects before hardware deployment, avoiding network failures and protecting user investments. It automates the generation of high-coverage test cases, reducing manual troubleshooting costs. Internal intermediate data is extracted through the chip debugging interface and directly compared with stack header fields, avoiding misjudgments based solely on external packet captures. The test set forcibly covers protocol stack interaction scenarios (e.g., MPLS multicast packet multiplexing SRv6 fields), exposing problems that cannot be found by single-protocol testing. Counters are dynamically bound to field combinations to achieve accurate problem attribution.

[0017] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a compatibility testing method for different generations of switching chips according to an embodiment of the present invention.

[0019] Figure 2 This is an example diagram of a test message for a compatibility testing method for different generations of switching chips according to an embodiment of the present invention.

[0020] Figure 3 This is a test structure diagram for a chassis-type switch.

[0021] Figure 4 A simplified test structure diagram for a chassis-type switch test environment.

[0022] Figure 5 This is a structural diagram of a compatibility testing device for different generations of switching chips according to an embodiment of the present invention.

[0023] Figure 6 This is a structural diagram of an electron according to an embodiment of the present invention. Detailed Implementation

[0024] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, further illustrating the present invention.

[0025] In conjunction with the description in the background technology section, such as Figure 3 The chassis-type switch shown consists of multiple line cards and switching network boards with different generations of switching chips, which can simplify the test environment as follows: Figure 4 As shown. Figure 4 The tester simulates the stacking message header of the m-th generation switching chip and sends the constructed message to the stacking port of line card x (the n-th generation switching chip). After being processed by the line card switching chip, the message is forwarded from the line card panel port to the tester, which then captures and analyzes the packets.

[0026] First, combine Figures 1-4 This invention describes a compatibility testing method for different generations of switching chips, applicable to a wide range of scenarios.

[0027] like Figures 1-4 As shown, an embodiment of the present invention provides a compatibility testing method for switching chips of different generations, comprising the following steps: like Figure 1 As shown, in S1, the reused fields in the stacked message header and the key fields that may affect the message parsing, matching, and editing processes are identified. Specifically, this involves: obtaining the stacked message header definition and its internal intermediate data structure of the switch chip under test; obtaining the stacked message header definition and corresponding field mapping relationships of the old switch chip; comparing the stacked message header field mapping relationships between the switch chip under test and the old switch chip; and determining the reused fields and the key fields that may affect the message parsing, matching, or editing processes based on the comparison results.

[0028] It should be noted that reused fields include: the "Reserved" field in the old stack header is reused as "SRv6 identifier" in the new stack header, and the high-order bits of the "timestamp" field are reused as "QoS priority".

[0029] Key fields in the parsing phase (Parser): During the parsing phase, fields in the stacked message header determine the parsing path and protocol identification method of the message, thus affecting whether the message can be parsed correctly. For example, the tunnel type field indicates the type of tunnel protocol to which the message belongs, thus affecting the parsing process of the message entering MPLS, SRv6, or other tunnel protocols. Correspondingly, key fields in the parsing phase include, but are not limited to: protocol type identifier field (3~8 bits) and encapsulation format identifier field (2~4 bits).

[0030] Key fields for the Match-Action phase: During the match-action phase, fields in the stacked message header are used to participate in the matching process of forwarding table entries, access control lists, or policy rules, and to determine the forwarding path or policy binding behavior of the packet. For example, the QoS priority field can trigger the corresponding hardware counter or policy rule. Correspondingly, the key fields in the match-action phase include, but are not limited to: ingress index (10~14 bits), forwarding domain ID (8~16 bits), multicast group ID (12~16 bits), MPLS label (20 bits), and ingressACL label (10~16 bits).

[0031] Key fields in the Edit stage: During the editing phase, fields in the stacked message header control the editing operations on the packet at the outgoing port, thus affecting the encapsulation format and field content of the final forwarded packet. For example, the VLAN tag field controls the addition, deletion, or modification of VLAN tags at the outgoing port. Correspondingly, key fields in the editing phase include, but are not limited to: VLAN tag (12 bits), VLAN operation (3 bits), QoS information (4~6 bits), ECN enable bit (1 bit), Teletry type identifier (2~4 bits), tunnel encapsulation / decapsulation control bit (2 bits), and SRv6 end behavior (5 bits).

[0032] like Figure 1 As shown, in S2, based on the identified key fields, combinations of test packet field values ​​are generated to construct a test packet set. This test packet set covers various mainstream protocol types and edge operation scenarios. Specifically, constructing the test packet set based on the identified key fields involves: selecting extreme values ​​(e.g., 0xFF, 0x00) and boundary values ​​for each key field; and cross-combining the selected values ​​of each key field (e.g., Tunnel_Type=0x03 + QoS_Priority=7 + VLAN operation=Delete) to generate combinations of test packet field values ​​to construct the test packet set.

[0033] It should be noted that the mainstream protocol types include: L2 unicast / multicast, L3 unicast / multicast, MPLS, VXLAN-base / VXLAN-GPE / Geneve / GTP / GRE / NVGRE / CAPWAP tunnels, SRv6, VM (BPE / NIV), INT / IFA / IOAMTelemetry; edge operation scenarios include: tunnel encapsulation / decapsulation, VLAN addition, deletion and modification, QoS remarking, multicast replication, ECMP, LAG, mirroring, Telemtry information recording and reporting.

[0034] like Figure 1 , 2 As shown, in S3, a test message is constructed based on the test message set, and then input to the switch under test (DUT) through the stacking port of the DUT. A traffic generation tool (such as an IXIA tester or Scapy software) can be used to construct the test message. Specifically, constructing the test message based on the test message set involves: inserting the stacking message header of the DUT before the Ethernet packet header; setting the values ​​of each key field in the stacking message header according to the test message field value combinations; and filling the payload portion of the test message with fixed test data (such as 0x00-0xFF cyclic data) to facilitate integrity verification after packet capture.

[0035] like Figure 1 As shown, in S4, after the switch chip under test receives the test message, it performs parsing, matching-action and message editing on the test message, and outputs the processed forwarded message from the panel port of the switch chip under test.

[0036] like Figure 1 As shown, in S5, during the processing of the test message, the internal intermediate data generated by the test message in key pipeline stages such as parsing, matching-action and message editing is collected by the hardware counter configured in the switch chip under test (the hardware counter is bound to the characteristics of the test message (such as: destination MAC + Tunnel_Type combination)).

[0037] like Figure 1 As shown, in S6, while the test packet is being processed, the panel port of the switching chip captures the forwarded packet. The stack header field value of the captured forwarded packet is compared with the corresponding field value in the internal intermediate data (verifying conversion consistency). The actual forwarding behavior of the captured forwarded packet is also compared with the expected forwarding behavior (e.g., SRv6 packets should retain the VLAN tag, but packet capture shows the VLAN has been deleted). Based on the comparison results, it is determined whether there are any hidden incompatibilities. If the internal intermediate data does not match the stack header field, or the forwarding result is abnormal, then a hidden incompatibility is identified.

[0038] As described above, in a compatibility testing method for different generations of switching chips according to an embodiment of the present invention, by constructing a test set covering multi-dimensional message characteristics and combining internal intermediate data comparison and forwarding behavior analysis, potential fault points when new and old chips are mixed are accurately identified, thus avoiding hardware upgrade risks.

[0039] The above combined with the appendix Figures 1-4 A compatibility testing method for different generations of switching chips according to an embodiment of the present invention is described. Furthermore, the present invention can also be applied to a compatibility testing apparatus for different generations of switching chips.

[0040] like Figure 5 As shown, according to a second aspect of the present invention, a compatibility testing apparatus for different generations of switching chips is provided, comprising: The identification module 100 is used to identify reused fields in the stacked message header and key fields that may affect the message parsing, matching, and editing process. Further, identifying reused fields in the stacked message header and key fields that may affect the message parsing, matching, and editing process specifically involves: obtaining the stacked message header definition and its internal intermediate data structure of the switch chip under test; obtaining the stacked message header definition and corresponding field mapping relationships of the old switch chip; comparing the stacked message header field mapping relationships between the switch chip under test and the old switch chip; and determining the reused fields and key fields that may affect the message parsing, matching, or editing process based on the comparison results.

[0041] The construction module 200 is used to generate combinations of test message field values ​​based on the identified key fields, in order to construct a test message set. The test message set covers multiple mainstream protocol types and edge operation scenarios. Further, constructing the test message set based on the identified key fields specifically involves: selecting extreme values ​​and boundary values ​​for each key field; and cross-combining the selected values ​​of each key field to generate combinations of test message field values ​​to construct the test message set.

[0042] The construction module 300 is used to construct test messages based on the test message set and input the test messages to the switch under test (SUT) through the stacking port of the SUT. Specifically, constructing the test messages based on the test message set involves: inserting the stacking message header of the SUT before the Ethernet message header; setting the values ​​of each key field in the stacking message header according to the test message field value combinations; and filling the payload portion of the test messages with fixed test data.

[0043] The processing module 400 is used to perform parsing, matching-action and message editing on the test message after the switch chip under test receives the test message, and output the processed forwarded message from the panel port of the switch chip under test.

[0044] The acquisition module 500 is used to acquire internal intermediate data generated during key pipeline stages such as parsing, matching-action, and message editing of the test message by using a hardware counter configured in the switch chip under test during the processing of the test message.

[0045] The comparison module 600 is used to capture forwarded packets at the panel port of the switching chip while the acquisition module is collecting data. It compares the stack message header field value of the captured forwarded packet with the corresponding field value of the internal intermediate data, and compares the actual forwarding behavior of the captured forwarded packet with the expected forwarding behavior. Based on the comparison results, it determines whether there are any hidden incompatibilities.

[0046] The above combined with the appendix Figure 5 This paper describes an apparatus embodiment corresponding to a compatibility testing method for different generations of switching chips according to an embodiment of the present invention. Therefore, the description of relevant details will not be repeated and is consistent with the method embodiment. Furthermore, the present invention can also be applied to an electronic device.

[0047] like Figure 6 As shown, according to a third aspect of the present invention, an electronic device is provided, comprising: a memory 1, a processor 2, and a computer program 3, wherein the computer program 3 is stored in the memory 1, and the processor 2 executes the computer program 3 to perform a compatibility testing method for different generations of switching chips according to the first aspect.

[0048] According to a fourth aspect of the present invention, a computer-readable medium having processor-executable non-volatile program code is provided, characterized in that the program code causes the processor to run a compatibility testing method for different generations of switching chips according to the first aspect.

[0049] The readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of a computer program from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the ASIC can reside within a device. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc. The present invention also provides a program product comprising executable instructions stored in the readable storage medium. At least one processor of the device can read the executable instructions from the readable storage medium, and the at least one processor executes the executable instructions, causing the device to implement the compatibility testing method for different generations of switching chips provided in the various embodiments described above. In the embodiments of the above-described device, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0050] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0051] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A compatibility testing method for switching chips of different generations, characterized in that, It includes the following steps: Identify the reused fields in the stacked message header and the key fields that may affect the message parsing, matching and editing process; Based on the identified key fields, a combination of test message field values ​​is generated to construct a test message set, which covers multiple mainstream protocol types and edge operation scenarios; A test message is constructed based on the test message set, and the test message is input to the switch under test through the stacking port of the switch under test. After receiving the test message, the switch chip under test performs parsing, matching-action and message editing on the test message, and outputs the processed forwarded message from the panel port of the switch chip under test. During the processing of the test message, the internal intermediate data generated by the test message in key pipeline stages such as parsing, matching-action and message editing is collected by the hardware counter configured in the switch chip under test. Meanwhile, the forwarded packets are captured at the panel port of the switching chip. The stacked message header field value of the captured forwarded packet is compared with the corresponding field value of the internal intermediate data. The actual forwarding behavior of the captured forwarded packet is compared with the expected forwarding behavior. Based on the comparison results, it is determined whether there are any hidden incompatibilities.

2. The compatibility testing method for different generations of switching chips as described in claim 1, characterized in that, The specific fields identified in the stacked message header that are reused, as well as key fields that may affect the message parsing, matching, and editing process, are as follows: Obtain the stack message header definition and its internal intermediate data structure of the switching chip under test; Obtain the stack message header definition and corresponding field mapping relationship of the old switching chip; Compare the stack message header field mapping relationship between the switch chip under test and the old switch chip; Based on the comparison results, determine the fields that are reused and the key fields that may affect the message parsing, matching or editing process.

3. The compatibility testing method for different generations of switching chips as described in claim 1, characterized in that, The specific steps for constructing the test message set based on the identified key fields are as follows: For each of the key fields, select extreme values ​​and boundary values; The selected values ​​of each key field are cross-combined to generate test message field value combinations, thereby constructing a test message set.

4. The compatibility testing method for different generations of switching chips as described in claim 1, characterized in that, The specific steps of constructing a test message based on the test message set are as follows: Insert the stacking message header of the switch chip under test before the Ethernet packet header; Set the values ​​of each key field in the stacked message header according to the test message field value combination; Fill the payload portion of the test message with fixed test data.

5. A compatibility testing device for different generations of switching chips, characterized in that, Include: The identification module is used to identify reused fields in stacked message headers and key fields that may affect the message parsing, matching and editing process. The construction module is used to generate test message field value combinations based on the identified key fields to construct a test message set, which covers multiple mainstream protocol types and edge operation scenarios; The construction module is used to construct test messages based on the test message set and input the test messages to the switch chip under test through the stacking port of the switch chip under test; The processing module is used to perform parsing, matching-action and message editing on the test message after the switch chip under test receives the test message, and output the processed forwarded message from the panel port of the switch chip under test; The acquisition module is used to acquire internal intermediate data generated by the test message during key pipeline stages such as parsing, matching-action, and message editing through a hardware counter configured in the switch chip under test during the processing of the test message. The comparison module is used to capture forwarded packets at the panel port of the switching chip while the acquisition module is collecting data. It compares the stacked message header field value of the captured forwarded packet with the corresponding field value of the internal intermediate data, and compares the actual forwarding behavior of the captured forwarded packet with the expected forwarding behavior. Based on the comparison results, it determines whether there are any hidden incompatibilities.

6. The compatibility testing device for different generations of switching chips as described in claim 5, characterized in that, The specific fields identified in the stacked message header that are reused, as well as key fields that may affect the message parsing, matching, and editing process, are as follows: Obtain the stack message header definition and its internal intermediate data structure of the switching chip under test; Obtain the stack message header definition and corresponding field mapping relationship of the old switching chip; Compare the stack message header field mapping relationship between the switch chip under test and the old switch chip; Based on the comparison results, determine the fields that are reused and the key fields that may affect the message parsing, matching or editing process.

7. The compatibility testing device for different generations of switching chips as described in claim 5, characterized in that, The specific steps for constructing the test message set based on the identified key fields are as follows: For each of the key fields, select extreme values ​​and boundary values; The selected values ​​of each key field are cross-combined to generate test message field value combinations, thereby constructing a test message set.

8. The compatibility testing device for different generations of switching chips as described in claim 5, characterized in that, The specific steps of constructing a test message based on the test message set are as follows: Insert the stacking message header of the switch chip under test before the Ethernet packet header; Set the values ​​of each key field in the stacked message header according to the test message field value combination; Fill the payload portion of the test message with fixed test data.

9. An electronic device, characterized in that, include: The device includes a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor executes the computer program to perform a compatibility testing method for different generations of switching chips as described in any one of claims 1 to 4.

10. A computer-readable medium having processor-executable non-volatile program code, characterized in that, The program code causes the processor to run a compatibility testing method for different generations of switching chips as described in any one of claims 1-4.

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