A preparation method of a multi-layer silicon oxide anti-ultraviolet attenuation film layer structure battery and a battery with the structure

Abstract

This application provides a method for fabricating a multilayer silicon oxide anti-UV degradation film structure solar cell, relating to the field of solar cells. The method includes sequentially arranging the following layers in the P+ direction of an N-type crystalline silicon substrate: a first silicon oxide layer, a boron-doped layer, a first aluminum oxide layer, a second silicon oxide layer, a second aluminum oxide layer, a third silicon oxide layer, a first silicon nitride antireflection layer, and a fourth silicon oxide layer; and sequentially arranging the following layers in the N+ direction of the N-type crystalline silicon substrate: a fifth silicon oxide layer, a phosphorus-doped layer, and a second silicon nitride antireflection layer. The fabrication method of the multilayer silicon oxide anti-UV degradation film structure solar cell provided by this application has high controllability and repeatability, and can precisely control the thickness and refractive index of the film layers. Simultaneously, the relatively low price of multilayer silicon oxide materials helps reduce the fabrication cost of the cell, promoting the application and promotion of photovoltaic technology in a wider range of fields.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a method for preparing a multilayer silicon oxide anti-ultraviolet degradation film structure solar cell and a solar cell having the structure. Background Technology

[0002] N-type TOPCon cells exhibit superior photoelectric conversion efficiency. The laboratory efficiency limit of N-type TOPCon cells can reach 28.7%, closest to the theoretical efficiency limit of 29.43% for crystalline silicon solar cells. Currently, the highest known conversion rate has reached 26.7%, and mass-produced efficiencies can also exceed 24.6%, far surpassing the efficiency of traditional P-type PERC cells. They can be widely used in photovoltaic power plants, aerospace, military, and other fields to meet the demand for efficient, stable, and reliable energy supply.

[0003] In recent years, with the rapid development of photovoltaic technology, N-type solar cell modules have attracted much attention due to their high efficiency and low degradation. However, in practical applications, researchers have found that N-type solar cell modules may experience performance degradation under ultraviolet (UV) irradiation. This is because when exposed to UV light, the hydrogen bonds in the surface passivation layer break, generating excessive hydrogen atom clusters, which causes the passivation layer to lose some of its passivation function. Therefore, how to fabricate a solar cell that can block the penetration of UV light and thus reduce the breaking of hydrogen bonds in the passivation layer has become an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a method for preparing a multilayer silicon oxide anti-ultraviolet decay film structure battery and a battery having the structure, so as to solve the above-mentioned problems.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] This application provides a method for preparing a multilayer silicon oxide anti-ultraviolet degradation film structure battery.

[0007] A first silicon oxide layer, a boron doped layer, a first aluminum oxide layer, a second silicon oxide layer, a second aluminum oxide layer, a third silicon oxide layer, a first silicon nitride antireflection layer, and a fourth silicon oxide layer are sequentially disposed in the P+ direction of an N-type crystalline silicon substrate.

[0008] A fifth silicon oxide layer, a phosphorus doped layer, and a second silicon nitride antireflection layer are sequentially disposed in the N+ direction on an N-type crystalline silicon substrate.

[0009] Optionally, the phosphorus doping concentration in the phosphorus-doped layer is 10. 22 -10 23 cm -3 ;

[0010] Optionally, the boron doping concentration in the boron-doped layer is 10. 20 -10 22 cm -3 .

[0011] Preferably, in the P+ layer direction of the N-type crystalline silicon substrate: a first silicon oxide layer and a first intrinsic amorphous silicon layer are formed to obtain a first intermediate morphology; a first mask layer is deposited on the first intermediate morphology to obtain a second intermediate morphology; the first intrinsic amorphous silicon layer is polycrystalline to form a first intrinsic polycrystalline silicon layer, and the first mask layer is removed; then, the first intrinsic polycrystalline silicon layer is subjected to boron diffusion to form a boron-doped layer, the boron-doped layer further including a second mask layer, to obtain a third intermediate morphology; after removing the second mask layer, the third intermediate morphology undergoes a first reaction to deposit a first intermediate morphology. An aluminum oxide passivation layer is formed to obtain a fourth intermediate morphology. Then, a second reaction is performed in the fourth intermediate morphology to generate a second silicon oxide layer, resulting in a fifth intermediate morphology. Then, a third reaction is performed in the fifth intermediate morphology to generate a second aluminum oxide layer, resulting in a sixth intermediate morphology. Then, a fourth reaction is performed in the sixth intermediate morphology to grow a third silicon oxide layer, resulting in a seventh intermediate morphology. Then, a fifth reaction is performed in the seventh intermediate morphology to generate a first silicon nitride antireflection layer, resulting in an eighth intermediate morphology. Then, a sixth reaction is performed in the eighth intermediate morphology to generate a fourth silicon oxide layer, resulting in a ninth intermediate morphology.

[0012] Optionally, the first silicon oxide layer is prepared by LPCVD.

[0013] Optionally, in the first reaction, the first alumina passivation layer is generated by the ALD method.

[0014] Optionally, in the second reaction, the nitrous oxide flow rate is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 100-200 s, to generate the second silicon oxide layer.

[0015] Optionally, in the third reaction, the pressure is 1400-1800 mtorr, the radio frequency power is 6000-9000 W, the flow rate of trimethylaluminum is 40-70 sccm / min, the flow rate of nitrous oxide is 3000-5000 sccm / min, and the time is 30-90 s, to generate a second alumina layer.

[0016] Optionally, in the fourth reaction, the nitrous oxide flow rate is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 100-300 s, to generate the third silicon oxide layer.

[0017] Optionally, in the fifth reaction, the silane flow rate is 1200-1800 sccm / min, the ammonia flow rate is 8500-12000 sccm / min, the pressure is 1500-1700 mtorr, and the time is 600-900 s, to generate the first silicon nitride antireflection layer.

[0018] Optionally, in the sixth reaction, the nitrous oxide flow rate is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 200-800 s, to generate the fourth silicon oxide layer.

[0019] Optionally, the first mask layer is deposited using PECVD at a temperature of 330-380°C.

[0020] Optionally, the thickness of the first silicon oxide layer is 1-3 nm.

[0021] Optionally, the thickness of the first intrinsic amorphous silicon layer is 30-120 nm.

[0022] Optionally, the thickness of the first alumina layer is 1-10 nm.

[0023] Optionally, the thickness of the second silicon oxide layer is 1-3 nm.

[0024] Optionally, the thickness of the second alumina layer is 1-10 nm.

[0025] Optionally, the thickness of the third silicon oxide layer is 1-3 nm.

[0026] Optionally, the thickness of the first silicon nitride antireflection layer is 60-80 nm, and the refractive index is 2.15.

[0027] Optionally, the thickness of the fourth silicon oxide layer is 2-10 nm.

[0028] Optionally, the first mask layer includes a silicon oxynitride mask layer with a thickness of 60-120 nm.

[0029] Optionally, the second mask layer is boron-doped silicon oxide.

[0030] Preferably, in the N+ layer direction of the N-type crystalline silicon substrate: a fifth silicon oxide layer and a second intrinsic amorphous silicon layer are formed on the N-type crystalline silicon substrate to obtain a tenth intermediate morphology; the second intrinsic amorphous silicon layer is polycrystalline to form a second intrinsic polycrystalline silicon layer on the tenth intermediate morphology; phosphorus diffusion is performed on the second intrinsic polycrystalline silicon layer to form a phosphorus-doped layer, and a third mask layer is also included on the phosphorus-doped layer to obtain an eleventh intermediate morphology; after printing a silver electrode on the eleventh intermediate morphology and removing the second mask layer, a seventh reaction is performed on the phosphorus-doped layer to generate a second silicon nitride antireflection layer.

[0031] Optionally, the fifth silicon oxide layer is prepared by LPCVD.

[0032] Optionally, in the seventh reaction, deposition is carried out using a PECVD device at a deposition temperature of 450-500℃.

[0033] Optionally, the thickness of the fifth silicon oxide layer is 1-3 nm.

[0034] Optionally, the thickness of the second intrinsic amorphous silicon layer is 30-220 nm.

[0035] Optionally, the thickness of the second silicon nitride antireflection layer is 50-90 nm.

[0036] Optionally, the third mask layer is a temporary mask layer.

[0037] Optionally, silver electrodes can be printed using screen printing, with a sintering temperature of 300-900℃.

[0038] This application also provides a multilayer silicon oxide anti-ultraviolet degradation film structure battery, which is prepared by the preparation method of the multilayer silicon oxide anti-ultraviolet degradation film structure battery.

[0039] Compared with the prior art, the beneficial effects of this application include:

[0040] This application provides a method for fabricating a multilayer silicon oxide anti-UV degradation film structure battery. The design of the multilayer silicon oxide film structure can effectively block and reflect ultraviolet light. Since silicon oxide has a certain absorption and scattering effect on ultraviolet light, a denser film structure can be formed through multilayer stacking, thereby further improving the battery's anti-UV degradation capability. This structure can effectively extend the battery's lifespan and reduce performance degradation caused by ultraviolet radiation. On the P+ side of the N-type crystalline silicon substrate, a first silicon oxide layer is used to separate the P+ passivated emitter and the boron-doped layer, which can significantly reduce carrier recombination losses between the P-type emitter and the boron-doped layer. This helps reduce charge loss during transmission, thereby improving the photoelectric conversion efficiency of solar cells. The first alumina layer provides negative charge, reducing electron recombination caused by electrons jumping to the front surface of the cell. On the other hand, the alumina contains a large number of hydrogen bonds, which can provide sufficient hydrogen passivation to improve cell efficiency. The third silicon oxide layer is used to weaken the penetration of short-wavelength light and block hydrogen accumulation between the two alumina layers, reducing ultraviolet decay. The second alumina layer provides sufficient negative charge to reduce electron migration to the surface and reduce recombination. The fourth silicon oxide layer is a silicon oxide medium inserted between alumina and silicon nitride, which can weaken the penetration of short-wavelength light. The outermost silicon oxide and silicon nitride layers together form a passivation contact structure. This structure can effectively reduce surface recombination and metal contact recombination, providing more room for further improvement of cell conversion efficiency.

[0041] This method offers high controllability and repeatability, enabling precise control over the film thickness and refractive index. Furthermore, the relatively low cost of multilayer silicon oxide materials helps reduce the manufacturing cost of solar cells. It also provides new ideas for the innovative development of photovoltaic technology, promoting its application and widespread adoption in a wider range of fields.

[0042] The battery with the multilayer silicon oxide anti-UV degradation film structure provided in this application has high conversion efficiency and excellent electrical performance. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0044] Figure 1 This is a schematic diagram of the multilayer silicon oxide anti-UV degradation film structure battery prepared in Example 1.

[0045] Key symbols: 10 - N-type crystalline silicon substrate; 101 - P-type emitter; 102 - First silicon oxide layer; 103 - Boron doped layer; 104 - First aluminum oxide layer; 105 - Second silicon oxide layer; 106 - Second aluminum oxide layer; 107 - Third silicon oxide layer; 108 - First silicon nitride antireflection layer; 109 - Fourth silicon oxide layer; 201 - Fifth silicon oxide layer; 202 - Phosphorus doped layer; 203 - Second silicon nitride layer. Detailed Implementation

[0046] To better illustrate the technical solution provided in this application, the technical solution will be described in its entirety before the embodiments, as follows:

[0047] In a first aspect, this application provides a method for preparing a battery with a multilayer silicon oxide anti-UV degradation film structure:

[0048] A first silicon oxide layer, a boron doped layer, a first aluminum oxide layer, a second silicon oxide layer, a second aluminum oxide layer, a third silicon oxide layer, a first silicon nitride antireflection layer, and a fourth silicon oxide layer are sequentially disposed in the P+ direction of an N-type crystalline silicon substrate.

[0049] A fifth silicon oxide layer, a phosphorus doped layer, and a second silicon nitride antireflection layer are sequentially disposed in the N+ direction on an N-type crystalline silicon substrate.

[0050] In an optional embodiment, the phosphorus doping concentration in the phosphorus-doped layer is 10. 22 -10 23 cm -3 ;

[0051] In an optional embodiment, the boron doping concentration in the boron-doped layer is 10. 20 -10 22 cm -3 .

[0052] In an optional embodiment, in the P+ layer direction of the N-type crystalline silicon substrate: a first silicon oxide layer and a first intrinsic amorphous silicon layer are formed to obtain a first intermediate morphology; a first mask layer is deposited on the first intermediate morphology to obtain a second intermediate morphology; the first intrinsic amorphous silicon layer is polycrystalline to form a first intrinsic polycrystalline silicon layer, and the first mask layer is removed; then, the first intrinsic polycrystalline silicon layer is subjected to boron diffusion to form a boron-doped layer, the boron-doped layer further including a second mask layer, to obtain a third intermediate morphology; after removing the second mask layer, the third intermediate morphology undergoes a first reaction. A first alumina passivation layer is deposited to obtain a fourth intermediate morphology; then a second reaction is performed in the fourth intermediate morphology to generate a second silicon oxide layer, resulting in a fifth intermediate morphology; then a third reaction is performed in the fifth intermediate morphology to generate a second alumina layer, resulting in a sixth intermediate morphology; then a fourth reaction is performed in the sixth intermediate morphology to grow a third silicon oxide layer, resulting in a seventh intermediate morphology; then a fifth reaction is performed in the seventh intermediate morphology to generate a first silicon nitride antireflection layer, resulting in an eighth intermediate morphology; then a sixth reaction is performed in the eighth intermediate morphology to generate a fourth silicon oxide layer, resulting in a ninth intermediate morphology.

[0053] In an alternative embodiment, the first silicon oxide layer is prepared by LPCVD.

[0054] In an optional embodiment, the first alumina passivation layer is generated by the ALD method in the first reaction.

[0055] In an optional embodiment, in the second reaction, the nitrous oxide flow rate is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 100-200 s, to generate the second silicon oxide layer.

[0056] Optionally, the flow rate of nitrous oxide can be 8000 sccm / min, 8500 sccm / min, 9000 sccm / min, 9500 sccm / min, 10000 sccm / min, 10500 sccm / min, 11000 sccm / min, or any value between 8000 and 11000 sccm / min. The pressure can be 1500 mtorr, 1550 mtorr, 1600 mtorr, 1650 mtorr, 1700 mtorr, 1750 mtorr, 1800 mtorr, 1850 mtorr, 1900 mtorr, 1950 mtorr, 2000 mtorr, or any value between 1500 and 2000 mtorr. The radio frequency can be 7000W, 7500W, 8000W, 8500W, 9000W, 9500W, 10000W, 10500W, 11000W, 11500W, or 12000W, or any value between 7000W and 12000W. The response time can be 100s, 110s, 120s, 130s, 140s, 150s, 160s, 170s, 180s, 190s, or 200s, or any value between 100s and 200s.

[0057] In an optional embodiment, in the third reaction, the pressure is 1400-1800 mtorr, the radio frequency power is 6000-9000 W, the flow rate of trimethylaluminum is 40-70 sccm / min, the flow rate of nitrous oxide is 3000-5000 sccm / min, and the time is 30-90 s, to generate a second alumina layer.

[0058] The pressure can be 1400 mtorr, 1450 mtorr, 1500 mtorr, 1550 mtorr, 1600 mtorr, 1650 mtorr, 1700 mtorr, 1750 mtorr, 1800 mtorr, or any value between 1400 and 1800 mtorr. The radio frequency power can be 6000 W, 6500 W, 7000 W, 7500 W, 8000 W, 8500 W, 9000 W, or any value between 6000 and 9000 W. The flow rate of the trimethylaluminum can be 40 sccm / min, 45 sccm / min, 50 sccm / min, 55 sccm / min, 60 sccm / min, 65 sccm / min, 70 sccm / min, or any value between 40 and 70 sccm / min. The flow rate of nitrous oxide can be 3000 sccm / min, 4000 sccm / min, 5000 sccm / min, or any value between 3000 and 5000 sccm / min.

[0059] In an optional embodiment, in the fourth reaction, the nitrous oxide flow rate is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 100-300 s, to generate the third silicon oxide layer.

[0060] Optionally, the amount of nitrous oxide used can be 8000 sccm / min, 8500 sccm / min, 9000 sccm / min, 9500 sccm / min, 10000 sccm / min, 10500 sccm / min, 11000 sccm / min, or any value between 8000 and 11000 sccm / min. The pressure can be 1500 mtorr, 1550 mtorr, 1600 mtorr, 1650 mtorr, 1700 mtorr, 1750 mtorr, 1800 mtorr, 1850 mtorr, 1900 mtorr, 1950 mtorr, 2000 mtorr, or any value between 1500 and 2000 mtorr. The radio frequency (RF) can be 7000W, 7500W, 8000W, 8500W, 9000W, 9500W, 10000W, 10500W, 11000W, 11500W, or 12000W, or any value between 7000W and 12000W. The time can be 100s, 150s, 200s, 250s, or 300s, or any value between 100s and 300s.

[0061] In an optional embodiment, in the fifth reaction, the silane flow rate is 1200-1800 sccm / min, the ammonia flow rate is 8500-12000 sccm / min, the pressure is 1500-1700 mtorr, and the time is 600-900 s, to generate the first silicon nitride antireflection layer.

[0062] Optionally, the silane flow rate is 1200 sccm / min, 1250 sccm / min, 1300 sccm / min, 1350 sccm / min, 1400 sccm / min, 1450 sccm / min, 1500 sccm / min, 1550 sccm / min, 1600 sccm / min, 1650 sccm / min, 1700 sccm / min, 1750 sccm / min, 1800 sccm / min, or any value between 1200 and 1800 sccm / min. The ammonia flow rate can be 8500 sccm / min, 9000 sccm / min, 9500 sccm / min, 10000 sccm / min, 10500 sccm / min, 11000 sccm / min, 11500 sccm / min, 12000 sccm / min, or any value between 8500 and 12000 sccm / min. The pressure can be 1500 mtorr, 1600 mtorr, 1700 mtorr, or any value between 1500 and 1700 mtorr. The time can be 600 s, 650 s, 700 s, 750 s, 800 s, 850 s, 900 s, or any value between 600 and 900 s.

[0063] In an optional embodiment, in the sixth reaction, the nitrous oxide flow rate is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 200-800 s, to generate the fourth silicon oxide layer.

[0064] Optionally, the flow rate of nitrous oxide can be 8000 sccm / min, 9000 sccm / min, 10000 sccm / min, 11000 sccm / min, or any value between 8000 and 11000 sccm / min. The pressure can be 1500 mtorr, 1600 mtorr, 1700 mtorr, 1800 mtorr, 1900 mtorr, 2000 mtorr, or any value between 1500 and 2000 mtorr. The radio frequency can be 7000 W, 8000 W, 9000 W, 10000 W, 11000 W, 12000 W, or any value between 7000 and 12000 W. The time can be 200s, 300s, 400s, 500s, 600s, 700s, 800s, or any value between 200 and 800s.

[0065] In one optional embodiment, the first mask layer is deposited using PECVD at a deposition temperature of 330-380°C.

[0066] The deposition temperature can be 330℃, 340℃, 350℃, 360℃, 370℃, 380℃, or any value between 330℃ and 380℃.

[0067] In one alternative embodiment, the thickness of the first silicon oxide layer is 1-3 nm.

[0068] Optionally, the thickness of the first silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0069] In one alternative implementation, the thickness of the first intrinsic amorphous silicon layer is 30-120 nm.

[0070] Optionally, the thickness of the first amorphous silicon layer can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, or any value between 30 and 120nm.

[0071] In one optional embodiment, the thickness of the first alumina layer is 1-10 nm.

[0072] Optionally, the thickness of the first alumina layer can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or any value between 1 and 10nm.

[0073] In one alternative embodiment, the thickness of the second silicon oxide layer is 1-3 nm.

[0074] Optionally, the thickness of the second silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0075] In one optional embodiment, the thickness of the second alumina layer is 1-10 nm.

[0076] Optionally, the thickness of the second alumina layer can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or any value between 1 and 10nm.

[0077] In one optional embodiment, the thickness of the third silicon oxide layer is 1-3 nm.

[0078] Optionally, the thickness of the third silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0079] In one optional embodiment, the thickness of the first silicon nitride antireflection layer is 60-80 nm and the refractive index is 2.15.

[0080] Optionally, the thickness of the first silicon nitride antireflection layer can be 60nm, 65nm, 70nm, 75nm, 80nm, or any value between 60-80nm.

[0081] In one optional embodiment, the thickness of the fourth silicon oxide layer is 2-10 nm.

[0082] Optionally, the thickness of the fourth silicon oxide layer can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or any value between 2 and 10nm.

[0083] In an optional embodiment, the first mask layer includes a silicon oxynitride mask layer with a thickness of 60-120 nm.

[0084] Optionally, the thickness of the silicon oxynitride mask layer can be 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, or any value between 60-120nm.

[0085] In an optional embodiment, the second mask layer is boron-doped silicon oxide.

[0086] In an optional embodiment, in the N+ layer direction of the N-type crystalline silicon substrate: a fifth silicon oxide layer and a second intrinsic amorphous silicon layer are formed on the N-type crystalline silicon substrate to obtain a tenth intermediate morphology; the second intrinsic amorphous silicon layer is polycrystalline to form a second intrinsic polycrystalline silicon layer on the tenth intermediate morphology; phosphorus diffusion is performed on the second intrinsic polycrystalline silicon layer to form a phosphorus-doped layer, and a third mask layer is also included on the phosphorus-doped layer to obtain an eleventh intermediate morphology; after printing a silver electrode on the eleventh intermediate morphology and removing the second mask layer, a seventh reaction is performed on the phosphorus-doped layer to generate a second silicon nitride antireflection layer.

[0087] In an optional embodiment, the fifth silicon oxide layer is prepared by LPCVD.

[0088] Optionally, the seventh reaction is carried out using a PECVD device at a deposition temperature of 450-500℃.

[0089] Optionally, the deposition temperature can be 450°C, 460°C, 470°C, 480°C, 490°C, 500°C, or any value between 450°C and 500°C.

[0090] In one optional embodiment, the thickness of the fifth silicon oxide layer is 1-3 nm.

[0091] Optionally, the thickness of the fifth silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0092] In one alternative embodiment, the thickness of the second intrinsic amorphous silicon layer is 30-220 nm.

[0093] Optionally, the thickness of the second intrinsic amorphous silicon layer can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, or any value between 30 and 120nm.

[0094] In one optional embodiment, the thickness of the second silicon nitride antireflection layer is 50-90 nm.

[0095] Optionally, the thickness of the second silicon nitride antireflection layer can be 50nm, 60nm, 70nm, 80nm, 90nm, or any value between 50-90nm.

[0096] In an optional implementation, the third mask layer is a temporary mask layer.

[0097] In one alternative embodiment, silver electrodes are printed using screen printing at a sintering temperature of 300-900°C.

[0098] Optionally, the sintering temperature can be 300℃, 350℃, 400℃, 450℃, 500℃, 550℃, 600℃, 650℃, 700℃, 750℃, 800℃, 850℃, 900℃, or any value between 300℃ and 900℃.

[0099] Secondly, this application also provides a multilayer silicon oxide anti-ultraviolet degradation film structure battery, which is prepared by the preparation method of the multilayer silicon oxide anti-ultraviolet degradation film structure battery.

[0100] The implementation schemes of this application will be described in detail below with reference to specific embodiments. However, those skilled in the art will understand that the following embodiments are only for illustrating this application and should not be regarded as limiting the scope of this application. Unless otherwise specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used without specified manufacturers are all conventional products that can be purchased commercially.

[0101] Example 1

[0102] This embodiment provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, the specific process of which is as follows:

[0103] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0104] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0105] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0106] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 1 nm, the thickness of the fifth silicon oxide layer 201 is 1.5 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0107] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 330 °C.

[0108] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0109] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0110] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0111] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0112] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0113] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0114] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0115] Step 12: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide to 4000sccm / min; and time to 60s.

[0116] Step 13: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0117] Step 14: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0118] Step 15: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0119] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0120] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0121] Step 18: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450 °C.

[0122] This embodiment also provides a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method. A schematic diagram of the prepared multilayer silicon oxide anti-UV degradation film structure battery is shown below. Figure 1 As shown.

[0123] Example 2

[0124] This embodiment provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, the specific process of which is as follows:

[0125] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0126] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0127] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0128] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 1.5 nm, the thickness of the fifth silicon oxide layer 201 is 1.5 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0129] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 340 °C.

[0130] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0131] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0132] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0133] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0134] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0135] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0136] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0137] Step 12: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide to 4000sccm / min; and time to 60s.

[0138] Step 13: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0139] Step 14: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0140] Step 15: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0141] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0142] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0143] Step 18: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 460 °C.

[0144] This embodiment also provides a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method. A schematic diagram of the prepared multilayer silicon oxide anti-UV degradation film structure battery is shown below. Figure 1 As shown.

[0145] Example 3

[0146] This embodiment provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, the specific process of which is as follows:

[0147] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0148] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0149] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0150] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 2 nm, the thickness of the fifth silicon oxide layer 201 is 2 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0151] Step 5: Deposit a first mask layer on the P+ layer of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition temperature is 350 °C.

[0152] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0153] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0154] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0155] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0156] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0157] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0158] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0159] Step 12: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide to 4000sccm / min; and time to 60s.

[0160] Step 13: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0161] Step 14: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0162] Step 15: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0163] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0164] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0165] Step 18: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 470 °C.

[0166] This embodiment also provides a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method. A schematic diagram of the prepared multilayer silicon oxide anti-UV degradation film structure battery is shown below. Figure 1 As shown.

[0167] Example 4

[0168] This embodiment provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, the specific process of which is as follows:

[0169] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0170] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0171] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0172] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 2.5 nm, the thickness of the fifth silicon oxide layer 201 is 2.5 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0173] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 360 °C.

[0174] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0175] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0176] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0177] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0178] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0179] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0180] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0181] Step 12: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide to 4000sccm / min; and time to 60s.

[0182] Step 13: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0183] Step 14: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0184] Step 15: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0185] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0186] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0187] Step 18: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 480 °C.

[0188] This embodiment also provides a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method. A schematic diagram of the prepared multilayer silicon oxide anti-UV degradation film structure battery is shown below. Figure 1 As shown.

[0189] Example 5

[0190] This embodiment provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, the specific process of which is as follows:

[0191] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0192] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0193] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0194] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 3 nm, the thickness of the fifth silicon oxide layer 201 is 3 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0195] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 380 °C.

[0196] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0197] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0198] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0199] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0200] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0201] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0202] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0203] Step 12: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide to 4000sccm / min; and time to 60s.

[0204] Step 13: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0205] Step 14: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0206] Step 15: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0207] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0208] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0209] Step 18: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 500 °C.

[0210] This embodiment also provides a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method. A schematic diagram of the prepared multilayer silicon oxide anti-UV degradation film structure battery is shown below. Figure 1 As shown.

[0211] Comparative Example 1

[0212] This comparative example provides a conventional solar cell, the fabrication process of which is as follows:

[0213] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0214] Step 2: Using a boron diffusion furnace, boron diffusion is performed on the outer side of the P+ layer of the texturized crystalline silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 1020 cm-3 and a diffusion junction depth of 0.5 μm at a boron concentration of 1017 cm-3.

[0215] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0216] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0217] Step 14: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0218] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0219] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0220] Step 18: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450 °C.

[0221] Comparative Example 2

[0222] This comparative example provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method.

[0223] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0224] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0225] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0226] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 1 nm, the thickness of the fifth silicon oxide layer 201 is 1 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0227] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 330 °C.

[0228] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0229] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0230] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0231] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0232] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0233] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0234] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0235] Step 12: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0236] Step 13: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0237] Step 14: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0238] Step 15: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0239] Step 16: Remove the second mask layer in the N+ direction by chain cleaning.

[0240] Step 17: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD equipment. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450 °C.

[0241] Comparative Example 3

[0242] This comparative example provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method.

[0243] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0244] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0245] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0246] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 1 nm, the thickness of the fifth silicon oxide layer 201 is 1 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0247] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 330 °C.

[0248] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0249] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0250] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0251] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0252] Step 10: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also passivate the dangling bonds of the surface silicon, reducing surface recombination.

[0253] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0254] Step 11: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide flow rate to 4000sccm / min; time to 60s.

[0255] Step 12: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0256] Step 13: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0257] Step 14: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0258] Step 15: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0259] Step 16: Remove the second mask layer in the N+ direction using a chain cleaning method;

[0260] Step 17: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD equipment. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450 °C.

[0261] Comparative Example 4

[0262] This comparative example provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method.

[0263] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0264] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0265] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0266] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 1 nm, the thickness of the fifth silicon oxide layer 201 is 1 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0267] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 330 °C.

[0268] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0269] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0270] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0271] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0272] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0273] Step 11: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide flow rate to 4000sccm / min; time to 60s.

[0274] Step 12: Continue growing a 2nm third silicon oxide layer 107 to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 9000 sccm / min, pressure to 1700 mtorr, RF power to 10500W, and time to 180s.

[0275] Step 13: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0276] Step 14: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0277] Step 15: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0278] Step 16: Remove the second mask layer in the N+ direction using a chain cleaning method;

[0279] Step 17: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD equipment. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450 °C.

[0280] Comparative Example 5

[0281] This comparative example provides a method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, which is prepared by the above method.

[0282] Step 1: Clean the N-type crystalline silicon substrate 10, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0283] Step 2: Using a boron diffusion furnace, boron is diffused outward along the P+ layer of the texturized silicon substrate to form a p-type emitter 101 with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0284] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0285] Step 4: Using LPCVD, grow a first silicon oxide layer 102 and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer 201 and a second intrinsic amorphous silicon layer in the N+ direction. The thickness of the first silicon oxide layer 102 is 1 nm, the thickness of the fifth silicon oxide layer 201 is 1 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.

[0286] Step 5: Deposit a first mask layer in the P+ layer direction of the N-type crystalline silicon substrate 10 using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 330 °C.

[0287] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm -3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0288] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0289] Step 8: Boron doping layer 103 is formed by diffusion of boron into the first intrinsic polysilicon layer in the P+ direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0290] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0291] Step 10: Deposit a first alumina layer 104 with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0292] Step 11: Grow a 1.5nm second silicon oxide layer 105 on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also have the function of passivating the dangling bonds of the surface silicon and reducing surface recombination.

[0293] The flow rate of nitrous oxide was 8000 sccm / min, the pressure was 1600 mtorr, the RF power was 9500 W, and the time was 150 s; RF power.

[0294] Step 12: Continue growing a second alumina layer 106 of 2nm, set the pressure to 1600mtorr; RF power to 7000W; trimethylaluminum to 50sccm / min; nitrous oxide to 4000sccm / min; and time to 60s.

[0295] Step 13: Grow a 70nm first silicon nitride antireflection layer 108, set the silane flow rate to 1550sccm / min, the ammonia flow rate to 9600sccm / min, the pressure to 1600mtorr, the time to 700s, and the silicon nitride film thickness to 70nm.

[0296] Step 14: Continue growing a 5nm fourth silicon oxide layer 109 to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 10000 sccm / min, pressure to 1800 mtorr, RF power to 10500W, and time to 450s.

[0297] Step 15: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0298] Step 16: Remove the second mask layer in the N+ direction using a chain cleaning method;

[0299] Step 17: Deposit an antireflection layer, namely the second silicon nitride antireflection layer 203, on the phosphorus doped layer on the back side using a PECVD equipment. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450 °C.

[0300] The electrical performance of the N-type TOPCON batteries prepared in the examples and comparative examples was tested, and the results are shown in Table 1:

[0301] Table 1 shows the electrical performance tests of the N-type TOPCON batteries prepared in the examples and comparative examples.

[0302]

[0303]

[0304] It is evident that by setting multiple anti-reflection coatings with different media on the front side of the cell, the penetration ability of ultraviolet light is reduced, thereby greatly alleviating the ultraviolet degradation of the solar cell. The introduction of a stacked passivation structure on the front side of the cell achieves good chemical passivation and field-effect passivation of the surface of the doped polycrystalline silicon layer, reducing the loss of charge carriers caused by recombination in the polycrystalline silicon layer and improving the effective output of photogenerated charge carriers. Furthermore, the setting of boron doping layers with different doping concentrations creates a potential difference, providing a certain driving force for the output of photogenerated charge carriers to the external circuit, thereby further increasing the effective output of charge carriers and effectively improving the conversion efficiency of the solar cell.

[0305] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0306] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing a multilayer silicon oxide anti-UV degradation film structure battery, characterized in that, A first silicon oxide layer, a boron doped layer, a first aluminum oxide layer, a second silicon oxide layer, a second aluminum oxide layer, a third silicon oxide layer, a first silicon nitride antireflection layer, and a fourth silicon oxide layer are sequentially disposed in the P+ direction of an N-type crystalline silicon substrate. A fifth silicon oxide layer, a phosphorus doped layer, and a second silicon nitride antireflection layer are sequentially disposed in the N+ direction on an N-type crystalline silicon substrate.

2. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 1, characterized in that, At least one of the following conditions must be met: (1) In the phosphorus-doped layer, the phosphorus doping concentration is 10. 22 -10 23 cm -3 ; (2) In the boron-doped layer, the boron doping concentration is 10. 20 -10 22 cm -3 .

3. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 1, characterized in that, include: In the P+ layer direction of the N-type crystalline silicon substrate: a first silicon oxide layer and a first intrinsic amorphous silicon layer are formed to obtain a first intermediate morphology. A first mask layer is deposited on the first intermediate morphology to obtain a second intermediate morphology. After polycrystalline treatment of the first intrinsic amorphous silicon layer, a first intrinsic polycrystalline silicon layer is formed, and the first mask layer is removed. Then, boron diffusion is performed on the first intrinsic polycrystalline silicon layer to form a boron-doped layer, and the boron-doped layer also includes a second mask layer to obtain a third intermediate morphology. After removing the second mask layer, a first reaction is performed on the third intermediate morphology to deposit a first silicon oxide layer. An aluminum passivation layer is formed to obtain a fourth intermediate morphology; then a second reaction is performed in the fourth intermediate morphology to generate a second silicon oxide layer, resulting in a fifth intermediate morphology; then a third reaction is performed in the fifth intermediate morphology to generate a second aluminum oxide layer, resulting in a sixth intermediate morphology; then a fourth reaction is performed in the sixth intermediate morphology to grow a third silicon oxide layer, resulting in a seventh intermediate morphology; then a fifth reaction is performed in the seventh intermediate morphology to generate a first silicon nitride antireflection layer, resulting in an eighth intermediate morphology; then a sixth reaction is performed in the eighth intermediate morphology to generate a fourth silicon oxide layer, resulting in a ninth intermediate morphology.

4. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 3, characterized in that, At least one of the following conditions must be met: (3) The first silicon oxide layer is prepared by LPCVD; (4) In the first reaction, the first alumina passivation layer is generated by the ALD method; (5) In the second reaction, the flow rate of nitrous oxide is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 100-200 s, to generate the second silicon oxide layer; (6) In the third reaction, the pressure is 1400-1800 mtorr, the radio frequency power is 6000-9000 W, the flow rate of trimethylaluminum is 40-70 sccm / min, the flow rate of nitrous oxide is 3000-5000 sccm / min, and the time is 30-90 s, to generate a second aluminum oxide layer. (7) In the fourth reaction, the flow rate of nitrous oxide is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 100-300 s, to generate the third silicon oxide layer; (8) In the fifth reaction, the silane flow rate is 1200-1800 sccm / min, the ammonia flow rate is 8500-12000 sccm / min, the pressure is 1500-1700 mtorr, and the time is 600-900 s, to generate the first silicon nitride antireflection layer. (9) In the sixth reaction, the flow rate of nitrous oxide is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency is 7000-12000 W, and the time is 200-800 s, to generate the fourth silicon oxide layer; (10) The first mask layer is deposited by PECVD at a temperature of 330-380℃.

5. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 4, characterized in that, At least one of the following conditions must be met: (11) The thickness of the first silicon oxide layer is 1-3 nm; (12) The thickness of the first intrinsic amorphous silicon layer is 30-120 nm; (13) The thickness of the first alumina layer is 1-10 nm; (14) The thickness of the second silicon oxide layer is 1-3 nm; (15) The thickness of the second alumina layer is 1-10 nm; (16) The thickness of the third silicon oxide layer is 1-3 nm; (17) The thickness of the first silicon nitride antireflection layer is 60-80 nm and the refractive index is 2.15; (18) The thickness of the fourth silicon oxide layer is 2-10 nm; (19) The first mask layer includes a silicon oxynitride mask layer with a thickness of 60-120 nm; (20) The second mask layer is boron-doped silicon oxide.

6. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to any one of claims 1-5, characterized in that, include: In the N+ layer direction of the N-type crystalline silicon substrate: a fifth silicon oxide layer and a second intrinsic amorphous silicon layer are formed on the N-type crystalline silicon substrate to obtain a tenth intermediate morphology; The second intrinsic amorphous silicon layer is polycrystalline to form a second intrinsic polycrystalline silicon layer on the tenth intermediate morphology. The second intrinsic polycrystalline silicon layer is then subjected to phosphorus diffusion to form a phosphorus-doped layer. The phosphorus-doped layer also includes a third mask layer to obtain an eleventh intermediate morphology. After printing a silver electrode on the eleventh intermediate morphology and removing the second mask layer, a seventh reaction is performed on the phosphorus-doped layer to generate a second silicon nitride antireflection layer.

7. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 6, characterized in that, At least one of the following conditions must be met: (21) The fifth silicon oxide layer is prepared by LPCVD. (22) In the seventh reaction, deposition is carried out using a PECVD device at a deposition temperature of 450-500℃.

8. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 7, characterized in that, At least one of the following conditions must be met: (23) The thickness of the fifth silicon oxide layer is 1-3 nm; (24) The thickness of the second intrinsic amorphous silicon layer is 30-220 nm; (25) The thickness of the second silicon nitride antireflection layer is 50-90 nm; (26) The third mask layer is a temporary mask layer.

9. The method for preparing a multilayer silicon oxide anti-UV degradation film structure battery according to claim 1, characterized in that, Silver electrodes are printed using screen printing, with a sintering temperature of 300-900℃.

10. A battery with a multilayer silicon oxide anti-UV degradation film structure, characterized in that, The battery was prepared using the method described in any one of claims 1-9 for the fabrication of a multilayer silicon oxide anti-UV degradation film structure.

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