Display device and method of manufacturing a display device

Abstract

This disclosure relates to a display device and a method of manufacturing the display device. The display device includes: a substrate including a display area and a non-display area outside the display area; light-emitting elements in pixels in the display area; trimming holes in the edges of the non-display area; crack detection lines disposed between the trimming holes and the display area and surrounding the display area; and bridging patterns in the trimming holes.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0196879, filed in Korea on December 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices (e.g., display apparatuses) and methods of manufacturing display devices, and more specifically to display devices that can be easily assembled into a complete set and methods of manufacturing the display devices. Background Technology

[0004] With the development of information technology, various types of small and thin display devices, such as liquid crystal displays, organic light-emitting diode displays, plasma displays, and micro LED displays, have been introduced. These display devices are used in various electronic devices such as smartphones and tablets.

[0005] Display devices comprise various electrodes, organic or inorganic layers, and various components that display the actual image. In such devices, cracks can appear due to external impacts. If moisture from the outside penetrates the display device through these cracks, problems arise such as electrode corrosion or deterioration of the organic light-emitting layer. Summary of the Invention

[0006] This disclosure relates to a display device and a method of manufacturing the display device, which substantially eliminates one or more of the problems associated with the limitations and disadvantages of related conventional technologies.

[0007] One of the purposes of this disclosure is to provide a display device and a method for manufacturing the display device, which can reduce or prevent defects caused by static electricity during the formation of crack detection lines.

[0008] Additional features and advantages of this disclosure are set forth in the description which follows, and will be apparent from the description, or may become apparent by practice of this disclosure. The purposes and other advantages of this disclosure are realized and obtained through the features described herein and in the accompanying drawings.

[0009] In order to achieve these and other advantages of the embodiments according to this disclosure, as described herein, one aspect of this disclosure is a display device comprising: a substrate including a display area and a non-display area outside the display area; light-emitting elements in pixels in the display area; trimming holes in the edges of the non-display area; crack detection lines disposed between the trimming holes and the display area and surrounding the display area; and bridging patterns in the trimming holes.

[0010] Another aspect of this disclosure is a method of manufacturing a display device, the method comprising: forming a buffer layer on a substrate including a display area and a non-display area; forming a semiconductor layer on the buffer layer and in the display area; forming a gate insulating layer on the buffer layer to cover the semiconductor layer; forming a trimming hole along the periphery of the display area by etching the buffer layer and the gate insulating layer; forming a metal layer on the gate insulating layer and in the trimming hole; forming a first photoresist pattern on the metal layer and corresponding to the display area, forming a second photoresist pattern on the metal layer and corresponding to the non-display area, and forming a third photoresist pattern on the metal layer and corresponding to the trimming hole; patterning the metal layer using the first to third photoresist patterns to form a gate electrode in the display area, a crack detection line in the non-display area, and a bridging pattern in the trimming hole; forming an interlayer insulating layer on the gate electrode and the crack detection line; forming a source electrode and a drain electrode on the interlayer insulating layer and in the display area; forming a light-emitting element above the drain electrode; and cutting and trimming the substrate along the trimming hole.

[0011] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to further illustrate the claimed contents of this disclosure. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0013] Figure 1 This is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure.

[0014] Figure 2 This is a schematic block diagram illustrating sub-pixels of a display device according to an embodiment of the present disclosure.

[0015] Figure 3 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0016] Figure 4 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0017] Figure 5 yes Figure 4 An enlarged view of area "A" in the image.

[0018] Figure 6 It is along Figure 4 The cross-sectional view taken from line I-I' in the diagram.

[0019] Figure 7 yes Figure 6 Enlarged cross-sectional view of area "B" in the image.

[0020] Figures 8A to 8F This is a schematic cross-sectional view illustrating the process of manufacturing a display device according to an embodiment of the present disclosure.

[0021] Figure 9A and Figure 9B This is a view showing the loss of the photoresist pattern used to form crack detection lines when no photoresist pattern is formed in the finishing hole.

[0022] Figure 10 This is a schematic plan view of a display device according to another embodiment of the present disclosure. Detailed Implementation

[0023] Reference will now be made in detail to various aspects of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where such unnecessarily obscures the gist of the inventive concept. The progression of the described processing steps and / or operations is a non-limiting example. The order of steps and / or operations is not limited to the order set forth herein, except that they must occur in a specific order, and may be altered to occur in an order different from that described herein. In one or more examples, depending on the function or operation involved, two consecutive operations may be performed substantially simultaneously, or the two operations may be performed in reverse or a different order. The same reference numerals denote the same elements throughout. The names of the various elements used in the following description are chosen solely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0024] Refer to the following and appendix Figure 1 The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become apparent from the aspects described in detail below. However, this disclosure is not limited to the aspects disclosed below, but can be implemented in various different forms, and only these aspects complete the disclosure. This disclosure is provided to fully inform those skilled in the art of this disclosure of its scope.

[0025] The shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings to illustrate various aspects of this disclosure are illustrative, and this disclosure is not limited to the matters shown. Throughout the specification, the same reference numerals refer to the same elements. Furthermore, in describing this disclosure, detailed descriptions of related known technologies may be omitted if it is determined that such detailed descriptions unnecessarily obscure the subject matter of this disclosure. When terms such as "comprising," "including," "having," or "consisting of" are used in this specification, additional parts may be added unless terms such as "only" or "merely" are used. When components are referred to in a singular form, the plural cases are included unless specifically stated.

[0026] The expression "at least one of a, b, and c" throughout this specification may include "a alone," "b alone," "c alone," "a and b," "a and c," "b and c," or "all of a, b, and c." See the appendix below for further details. Figure 1 The advantages and features of the present invention, as well as the methods for achieving these advantages and features, will become apparent from the detailed description of the embodiments.

[0027] When interpreting components, although the error or tolerance range is not explicitly described, the component is interpreted as including such an error or tolerance range.

[0028] When describing positional relationships, for example, when the positional relationship between two parts is described as such as "on," "above," "below," and "adjacent," one or more other parts may be placed between the two parts unless more restrictive terms such as "exactly" or "directly" are used.

[0029] When describing temporal relationships, such as when time sequence is described as "after", "following", "next", and "before", discontinuous situations may be included unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0030] For ease of illustration, the area, length, or thickness of each component described in the specification is shown, and the invention is not necessarily limited to the area and thickness of the components shown.

[0031] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0032] The various aspects of this disclosure may be coupled or combined with each other, either partially or in whole, and may interoperate and be technically driven with each other in various ways, as will be fully understood by those skilled in the art. The aspects of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0033] In this disclosure, "display device" can include display devices in the narrow sense, such as display modules that include a display panel and driving units for driving the display panel. Additionally, "display device" can also include complete electronic devices or assemblies, such as laptops, televisions, computer monitors, automotive displays, equipment displays, smartphones, wearable devices such as smartwatches, personal multimedia players (PMPs), personal digital assistants (PDAs), electronic boards, etc., which are complete products (or final products) including display modules.

[0034] Therefore, the display device in this invention may include a display device in the narrow sense, such as a display module, as well as a complete set of equipment that includes an application product or final consumer device.

[0035] Reference will now be made in detail to some of the examples and preferred embodiments shown in the accompanying drawings.

[0036] Figure 1 This is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 2 This is a schematic block diagram illustrating sub-pixels of a display device according to an embodiment of the present disclosure.

[0037] like Figure 1 As shown, the display device 100 of this disclosure includes an image processing unit 102, a timing control unit 104, a gate driving unit 106, a data driving unit 107, a power supply unit 108, and a display panel 109.

[0038] The image processing unit 102 outputs image data supplied from an external source and drive signals for driving various components. For example, the drive signals output from the image processing unit 102 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0039] The timing control unit 104 receives image data and drive signals from the image processing unit 102. Based on the drive signals input from the image processing unit 102, the timing control unit 104 generates and outputs a gate timing control signal GDC for controlling the operation timing of the gate driving unit 106 and a data timing control signal DDC for controlling the operation timing of the data driving unit 107.

[0040] The gate driving unit 106 responds to the gate timing control signal GDC supplied from the timing control unit 104 and outputs a scan signal to the display panel 109. The gate driving unit 106 outputs the scan signal through multiple gate lines GL1 to GLm. In this case, the gate driving unit 106 can be formed in the form of an IC (integrated circuit), but is not limited thereto. The gate driving unit 106 includes various gate driving circuits, and the gate driving circuits can be directly formed on the substrate of the display panel 109. In this case, the gate driving unit 106 can be a GIP (gate in panel).

[0041] The data driving unit 107 responds to the data timing control signal DDC input from the timing control unit 104 and outputs a data voltage to the display panel 109. The data driving unit 107 samples and latches the digital data signal DATA supplied from the timing control unit 104. The data driving unit 107 converts the digital data signal DATA into an analog data voltage based on the gamma voltage. The data driving unit 107 outputs the data voltage through multiple data lines DL1 to DLn. In this case, the data driving unit 107 can be formed in the form of an IC, but is not limited thereto.

[0042] The power supply unit 108 outputs a high-potential voltage VDD and a low-potential voltage VSS, and supplies these voltages to the display panel 109. The high-potential voltage VDD is supplied to the display panel 109 via a first power line EVDD, and the low-potential voltage VSS is supplied to the display panel 109 via a second power line EVSS. In this configuration, the voltage output from the power supply unit 108 can be supplied to either the gate driving unit 106 or the data driving unit 107.

[0043] The display panel 109 displays an image in response to a scan signal from the gate driving unit 106, a data voltage from the data driving unit 107, and a voltage from the power supply unit 108.

[0044] Display panel 109 includes multiple subpixels SP and displays the actual image. Subpixels SP may include red, green, and blue subpixels. Subpixels SP may also include white subpixels. The white, red, green, and blue (W, R, G, B) subpixels SP may have the same area. Alternatively, the white, red, green, and blue (W, R, G, B) subpixels SP may have different areas.

[0045] like Figure 2As shown, a sub-pixel SP can be connected to gate line GL1, data line DL1, first power line EVDD, and second power line EVSS. Depending on the configuration of the pixel circuit, the sub-pixel SP may include multiple thin-film transistors and storage capacitors. For example, the sub-pixel SP may include two transistors and one capacitor (e.g., a 2T1C structure). Alternatively, the sub-pixel SP may have one of the following structures: 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, and 8T2C.

[0046] Figure 3 This is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0047] like Figure 3 As shown, the display device includes a gate line GL, a data line DL, and a power line PL. The gate line GL intersects with the data line DL and the power line PL to define a sub-pixel SP. A switching transistor Ts, a driving transistor Td, a storage capacitor Cst, and a light-emitting element D are disposed in the sub-pixel SP.

[0048] The switching transistor Ts is connected to the gate line GL and the data line DL, and the driving transistor Td and the storage capacitor Cst are connected to the switching transistor Ts and the power line PL. The light-emitting element D is connected to the driving transistor Td.

[0049] In an organic light-emitting display device, when the switching transistor Ts is turned on by the gate signal applied through the gate line GL, the data signal from the data line DL is applied to the gate electrode of the driving transistor Td and the electrode of the storage capacitor Cst.

[0050] When the driving transistor Td is turned on by the data signal, current is supplied from the power line PL to the light-emitting element D. Therefore, the light-emitting element D emits light. In this case, when the driving transistor Td is turned on, the level of the current applied from the power line PL to the light-emitting element D is determined to allow the light-emitting element D to produce grayscale levels.

[0051] The storage capacitor Cst is used to maintain the voltage at the gate electrode of the driving transistor Td when the switching transistor Ts is turned off.

[0052] Therefore, even if the switching transistor (e.g., thin-film transistor (TFT)) Ts is turned off, the level of the current applied from the power line PL to the light-emitting element D remains unchanged until the next frame.

[0053] exist Figure 3 In this configuration, the subpixel SP includes two transistors Td and Ts and a storage capacitor Cst. Alternatively, the subpixel SP may include three or more transistors and two or more storage capacitors.

[0054] Figure 4 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0055] like Figure 4 As shown, the display device 100 of this disclosure includes a display panel PNL, a flexible printed circuit board (e.g., a flexible printed circuit) FPC, and a printed circuit board PCB. The display panel PNL includes a display area AA for displaying images and a non-display area NA outside the display area AA.

[0056] In the display area AA, a sub-pixel SP is set, comprising multiple sub-pixels SP1, SP2, and SP3. Sub-pixels SP1, SP2, and SP3 may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Additionally, sub-pixel SP may also include a white sub-pixel W.

[0057] Multiple gate lines and multiple data lines are provided in the display area AA, and sub-pixels SP are located at the intersection of the gate lines and data lines. In each of the sub-pixels SP1, SP2 and SP3, a transistor and a display element are provided as switching elements and / or driving elements.

[0058] Display elements can include a variety of display elements. For example, display elements can be organic light-emitting display elements (or organic electroluminescent display elements), liquid crystal display elements, quantum dot display elements, micro LED display elements, or mini LED display elements.

[0059] Gate driving units (e.g., for applying signals to sub-pixels SP1, SP2, and SP3) can be provided in the non-display area NA. Figure 1 Gate driving unit 106) and data driving unit (e.g.) Figure 1 The data driving unit 107 in the substrate provides a scan signal (e.g., a gate signal) to the sub-pixel via a gate line, and the data driving unit provides an image signal (e.g., a data signal) to the sub-pixel via a data line. The gate driving unit may be a gate in panel (GIP) circuit to be formed in the non-display area NA of the substrate.

[0060] One end of the flexible printed circuit board (FPC) is attached to the bottom side of the non-display area NA, which is located on the display area AA, and the printed circuit board (PCB) is attached to the other end of the FPC. The data driving unit and multiple signal lines can be housed within the FPC, while the timing control unit and power supply unit can be housed within the PCB. In this case, the gate driving unit can be directly mounted on the display panel PNL.

[0061] Control signals and voltages from the timing control unit and power supply unit in the printed circuit board (PCB) can be provided to the gate drive unit and data drive unit via signal lines.

[0062] A crack detection line PCD is set around the periphery of the display area AA of the display panel PNL. The crack detection line PCD can surround three sides of the display area AA. For example, the crack detection line PCD can be U-shaped or frame-shaped with one side open.

[0063] The crack detection line PCD is electrically connected to the signal line of the flexible printed circuit board FPC.

[0064] The flexible printed circuit board (FPC) or printed circuit board (PCB) is equipped with a resistance measurement unit to measure the resistance value of the crack detection line (PCD). If the measured resistance value is detected as infinite, it is determined that a crack has appeared in the crack detection line (PCD) and has extended to or is close to the display area (AA). If the output resistance value is detected as less than the set resistance value of infinity, it is determined that no crack has appeared in the crack detection line (PCD).

[0065] Figure 5 yes Figure 4 An enlarged view of area "A" in the image. (See image below.) Figure 5 As shown, trimming holes (TRIMs) are formed on the outer edge of the non-display area NA of the display panel PNL. The trimming holes (TRIMs) are used to separate the mother substrate, on which multiple display panels (PNLs) are formed. The mother substrate is cut into at least one display panel (PNL).

[0066] When manufacturing irregularly shaped display devices such as clock displays or vehicle displays, a display panel is formed on a rectangular mother substrate, and then cutting and trimming processes are performed to create the display device of the desired shape. Trimming holes (TRIMs) can be formed for trimming processes of irregularly shaped display devices. Trimming holes (TRIMs) can be formed by removing multiple insulating layers formed in the display panel PNL.

[0067] The trimming hole (TRIM) extends from the outer edge of the non-display area NA toward the display area AA, with a width defined by a set length. The trimming hole (TRIM) will be described in detail later.

[0068] A crack detection line (PCD) is disposed between the trimming hole (TRIM) and the display area (AA). The PCD is positioned at a predetermined distance from the trimming hole (TRIM). Since the trimming hole (TRIM) is formed along the entire periphery of the display panel (PNL), and the PCD is disposed along at least three sides of the display panel (PNL), the trimming hole (TRIM) and the PCD can be disposed adjacent to each other along at least three sides of the display panel (PNL).

[0069] A bridging pattern BPAT is formed within a trimming tunnel TRIM. The bridging pattern BPAT may be formed solely within the trimming tunnel TRIM, but is not limited to this. At least a portion of the bridging pattern BPAT may be formed within the trimming tunnel TRIM. For example, a portion of the bridging pattern BPAT (which may be referred to as the first bridging pattern portion) may be formed within the trimming tunnel TRIM, while another portion of the bridging pattern BPAT (which may be referred to as the second bridging pattern portion) may extend outside the trimming tunnel TRIM. The first bridging pattern portion may continuously cover the inner wall of the trimming tunnel TRIM and connect with the second bridging pattern portion. The second bridging pattern portion may increase the contact area between the bridging pattern BPAT and the attached layer on the substrate, thereby increasing the stability of the formed structure and thus facilitating subsequent cutting and trimming processes.

[0070] The bridging pattern BPAT can extend a predetermined distance toward the display area AA. The bridging pattern BPAT is arranged at a predetermined distance from the crack detection line PCD.

[0071] The bridging pattern (BPAT) can have a strip pattern with a predetermined width. Multiple bridging patterns (BPAT) can be arranged at predetermined intervals along the periphery of the display panel (PNL). For example, the bridging pattern (BPAT) can include multiple patterns arranged along trimming holes (TRIM) and spaced apart from each other. Alternatively, bridging patterns (BPAT) as an integrated unit can be arranged continuously along the periphery of the display panel (PNL). For example, bridging patterns (BPAT) as an integrated unit can be arranged along trimming holes (TRIM).

[0072] Figure 6 This is a view showing the structure of the display panel to which this disclosure is made, and is along... Figure 4 The cross-sectional view taken from line I-I' in the diagram.

[0073] For ease of explanation, Figure 6 The image shows a subpixel of the display area AA and the non-display area NA.

[0074] The substrate 140 includes a display area AA and a non-display area NA. The substrate 140 may be formed of a rigid material (e.g., glass) or a flexible plastic material.

[0075] For example, substrate 140 may be formed of at least one of polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone and polycarbonate, but is not limited thereto.

[0076] In embodiments of this disclosure, substrate 140 may include a plurality of polyimide layers and an inorganic layer between the polyimide layers, but is not limited thereto.

[0077] A buffer layer 142 is provided on the substrate 140. The buffer layer 142 may be provided on the entire surface of the substrate 140 to enhance the adhesion between the substrate 140 and the layers formed on the substrate 140, and to block impurities from the substrate 140, such as alkaline components. In addition, the buffer layer 142 may delay the diffusion of moisture or oxygen that has already penetrated into the substrate 140.

[0078] Buffer layer 142 may include a first buffer layer 142a, a second buffer layer 142b on the first buffer layer 142a, and a third buffer layer 142c on the second buffer layer 142b. For example, each of the first buffer layer 142a and the third buffer layer 142c may be formed of silicon oxide (SiOx), and the second buffer layer 142b may be formed of silicon nitride (SiNx). However, it is not limited thereto.

[0079] A thin-film transistor (TFT) T is disposed on the buffer layer 142 in the display area AA.

[0080] For ease of explanation, Figure 6 The driving TFT (e.g.) is shown Figure 3 The driving transistor Td in the middle). Other TFTs, such as switching TFTs (e.g., Td), can also be set on the buffer layer 142 and in the display area AA. Figure 3 (The switching transistor Ts in the middle). Figure 6 The TFT T in the example has a top-gate structure. Alternatively, the TFT T can have a bottom-gate structure.

[0081] The TFT T includes a semiconductor layer 112 on a buffer layer 142, a gate insulating layer 144 on the semiconductor layer 112, a gate electrode 114 on the gate insulating layer 144, an interlayer insulating layer 146 on the gate electrode 114, and a source electrode 115 and a drain electrode 116 on the interlayer insulating layer 146.

[0082] The semiconductor layer 112 can be formed of a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material can be low-temperature polycrystalline silicon (LTPS), but is not limited to this.

[0083] In embodiments of this disclosure, the semiconductor layer 112 may be formed of an oxide semiconductor material. For example, the semiconductor layer 112 may be formed of one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto. The semiconductor layer 112 may include a channel region 112a, a source region 112b on one side of the channel region 112a, and a drain region 112c on the other side of the channel region 112a.

[0084] The gate insulating layer 144 may cover the display area AA and the non-display area NA. The gate insulating layer 144 may cover only the display area AA. The gate insulating layer 144 may be formed of an inorganic insulating material (e.g., silicon oxide or silicon nitride) and may have a single-layer or multi-layer structure. However, it is not limited thereto.

[0085] Interlayer insulating layer 146 may cover the display area AA and the non-display area NA. Interlayer insulating layer 146 may cover only the display area AA. Interlayer insulating layer 146 may be formed of an organic insulating material (e.g., photoacrylic acid) or an inorganic insulating material (e.g., silicon oxide or silicon nitride), and may have a single-layer or multi-layer structure. For example, interlayer insulating layer 146 may have a multi-layer structure including organic insulating material layers and inorganic insulating material layers. However, it is not limited to this.

[0086] Each of the gate electrode 114, source electrode 115, and drain electrode 116 may be formed of a conductive material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), and may have a single-layer or multi-layer structure. However, it is not limited thereto. The source electrode 115 and drain electrode 116 may be connected to (e.g., contacted) the source region 112b and drain region 112c of the semiconductor layer 112 through contact holes in the gate insulating layer 144 and the interlayer insulating layer 146, respectively.

[0087] A bottom shielding metal layer may be disposed between the semiconductor layer 112 and the substrate 140. The bottom shielding metal layer can reduce or minimize the back channel phenomenon caused by charges trapped in the substrate 140, thereby reducing or preventing afterimages or performance degradation of the TFT T. The bottom shielding metal layer may be formed of a conductive material (e.g., titanium (Ti), molybdenum (Mo), or alloys thereof) and may have a single-layer or multi-layer structure. However, it is not limited to this.

[0088] A planarization layer 148 is formed over a substrate 140 including the TFT T. The planarization layer 148 may be formed of an organic insulating material (e.g., photoacrylic acid), but is not limited thereto. The planarization layer 148 may have a multilayer structure including an inorganic insulating layer and an organic insulating layer, or a multilayer structure including two or more organic insulating layers.

[0089] The first electrode 132 is disposed on the planarization layer 148 and connected to the drain electrode 116 of the TFTT through a contact hole in the planarization layer 148. The first electrode 132 may be formed of at least one of aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and alloys thereof. Alternatively, the first electrode 132 may comprise a transparent conductive oxide material layer formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0090] In the top-emitting display device 100, the first electrode 132 may include an opaque (or reflective) conductive material layer having a transparent conductive oxide material layer. In the bottom-emitting display device 100, the first electrode 132 may include a transparent conductive oxide material layer but not an opaque conductive material layer.

[0091] A dam BNK is set at the boundary of each subpixel and on the planarization layer 148. The dam BNK can be a separator used to define the subpixel. The dam BNK surrounds the subpixel, making it possible to reduce or prevent color mixing in adjacent subpixels.

[0092] The dam BNK can be made of inorganic insulating materials (such as silicon nitride (SiNx) or silicon oxide (SiO2)). x It can be formed from organic insulating materials (such as benzocyclobutene (BCB), acrylic resins, epoxy resins, phenolic resins, polyamide resins, or polyimide resins), or photosensitive materials including black pigments. However, it is not limited to these.

[0093] A light-emitting layer 134 may be formed on the upper surface of the first electrode 132 in the display area AA, the inclined surface of the embankment BNK, and a portion of the upper surface of the embankment BNK. The light-emitting layer 134 may extend into at least a portion of the non-display area NA.

[0094] The light-emitting layer 134 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The red light-emitting layer is disposed in the red sub-pixel and provides red light emission, the green light-emitting layer is disposed in the green sub-pixel and provides green light emission, and the blue light-emitting layer is disposed in the blue sub-pixel and provides blue light emission. For example, the light-emitting layer 134 may include an organic light-emitting layer or an inorganic light-emitting layer, such as a nanoscale material layer, a quantum dot layer, a micro-LED light-emitting layer, or a mini LED light-emitting layer. However, it is not limited to this.

[0095] The light-emitting layer 134 may include a light-emitting material layer. Additionally, the light-emitting layer 134 may also include at least one of a hole injection layer for injecting holes, an electron injection layer for injecting electrons, a hole transport layer for transporting holes, an electron transport layer for transporting electrons, a hole blocking layer, and an electron blocking layer. However, it is not limited thereto.

[0096] A second electrode 136 is disposed on the light-emitting layer 134. The second electrode 136 may be formed of metal or alloy and may have a single-layer structure or a multi-layer structure. In embodiments of this disclosure, the second electrode 136 may be formed of a transparent conductive oxide material. However, it is not limited thereto.

[0097] In the top-emitting display device 100, the second electrode 136 may have a thin profile to be transparent or translucent. For example, the second electrode 136 may be formed of at least one alloy of LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, or LiF / Ca:Ag.

[0098] In the bottom-emitting display device 100, the second electrode 136 may be formed of an opaque conductive material to serve as a reflective electrode. For example, the second electrode 136 may be formed of at least one of Ag, Al, Au, Mo, W, Cr, or alloys thereof.

[0099] The first electrode 132, the light-emitting layer 134, and the second electrode 136 constitute a light-emitting element D. The light-emitting element D can be an organic light-emitting element where the light-emitting layer 134 is an organic light-emitting layer, or an inorganic light-emitting element where the light-emitting layer 134 is an inorganic light-emitting layer. The light-emitting element D can be a light-emitting diode (LED).

[0100] The light-emitting element D can have a series structure. In the series-structured light-emitting element D, the light-emitting layer 134 includes multiple light-emitting material layers and one or more charge-generating layers between adjacent light-emitting material layers. The charge-generating layers control the charge balance among the multiple light-emitting material layers and can have a multilayer structure including n-type and p-type charge-generating layers. The charge-generating layers can be doped with alkali metals (e.g., Li, Na, K, Cs, etc.) and alkaline earth metals (e.g., Mg, Sr, Ba, Ra, etc.). However, it is not limited to these.

[0101] An encapsulation layer 180 is provided on the display area AA and the non-display area NA to cover or seal the light-emitting element D. When the light-emitting element D is exposed to oxygen and / or moisture, pixel shrinkage may occur, in which the light-emitting area shrinks, or defects such as dark spots appear in the light-emitting area. In addition, moisture or oxygen may oxidize the electrodes made of metal. The encapsulation layer 180 prevents moisture and / or oxygen from penetrating from the outside, thereby reducing or preventing defects in the light-emitting element D and various electrodes.

[0102] The encapsulation layer 180 may include a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186. In embodiments of this disclosure, the encapsulation layer 180 may have a two-layer structure or a multi-layer structure including four or more layers.

[0103] Each of the first encapsulation layer 182 and the third encapsulation layer 186 may be formed of an inorganic insulating material (e.g., silicon oxide (SiOx), silicon oxide nitride (SiON), or silicon nitride (SiNx)) and may have a single-layer or multi-layer structure. Each of the first encapsulation layer 182 and the third encapsulation layer 186 may also include an organic insulating material. The second encapsulation layer 184 may be formed of an organic material such as epoxy resin.

[0104] Touch elements can be configured. Touch elements can be placed in the display area AA to detect touch input. Touch elements can use the user's finger or stylus to detect external touch information.

[0105] A dam DAM is provided in the non-display area NA. The organic material forming the second encapsulation layer 184 has fluidity. When the second encapsulation layer 184 is formed, due to its fluidity, the organic material can flow from the outside of the non-display area NA to the outside of the substrate 140. When the second encapsulation layer 184 is formed, a dam DAM is formed to surround the display area AA to restrict the flow of organic material from the substrate 140. Therefore, the flow of organic material from the substrate 140 can be reduced or prevented. Figure 6 A single dam DAM is shown. Alternatively, multiple dam DAMs can be arranged.

[0106] The dam DAM can have a multi-layered structure. For example, the dam DAM may include a first layer formed of the same material as the planarization layer 148 and a second layer formed of the same material as the embankment BNK. Alternatively, the dam DAM may have a single-layered structure or a multi-layered structure comprising three or more layers.

[0107] The crack detection line PCD is disposed in the non-display area NA and outside the dam DAM. The crack detection line PCD can be disposed on the gate insulating layer 144, but is not limited thereto. When the crack detection line PCD is disposed on the gate insulating layer 144 (i.e., on the same layer as the gate electrode 114), the crack detection line PCD can be formed of the same metal as the gate electrode 114 of the TFT T. However, it is not limited thereto.

[0108] For example, the crack detection line PCD can be disposed on the interlayer insulating layer 146. In this case, the encapsulation layer 180 can extend to cover and protect the crack detection line PCD, and since the crack detection line PCD is located on the same layer as the source electrode 115 and drain electrode 116 of the TFT T, the crack detection line PCD can be formed of the same metal as the source electrode 115 and drain electrode 116. At this time, the second bridging pattern portion of the bridging pattern BPAT can be located on the same layer as the crack detection line PCD. Therefore, the second bridging pattern portion can be formed on the same layer as at least one of the gate electrode 114, source electrode 115, and drain electrode 116 of the TFT T and the crack detection line PCD. The first bridging pattern portion and the second bridging pattern portion can be formed of the same material as at least one of the gate electrode 114, source electrode 115, and drain electrode 116 of the TFT T and the crack detection line PCD. Thus, the crack detection line PCD and the bridging pattern BPAT can be formed together with the TFT T, thereby reducing or preventing a decrease in process efficiency.

[0109] Trimmed holes are formed at the edge of the display device 100. Trimmed holes can be formed by removing at least some of the interlayer insulating layer 146, gate insulating layer 144, and buffer layer 142. Since the trimmed hole is the area where the display panel PNL is cut and trimmed, the finished (or final) trimmed hole of the display panel PNL may only have half the size of the original trimmed hole, and the remaining portion of the trimmed hole can be removed through a trimming process.

[0110] At least a portion of the bridging pattern BPAT can be formed in the trimming via TRIM. The bridging pattern BPAT can extend from the trimming via TRIM to a portion on the gate insulating layer 144, thus having a second bridging pattern portion located on the gate insulating layer 144 (i.e., on the same layer as the gate electrode 114). The bridging pattern BPAT is arranged to be spaced apart from the crack detection line PCD. The bridging pattern BPAT can be formed of the same metal as the crack detection line PCD or the gate electrode 114, but is not limited thereto.

[0111] A capping layer 149 is formed in the trimming tunnel (TRIM) to cover the bridging pattern BPAT. The capping layer 149 may cover a portion of the side surface and the top surface of the interlayer insulating layer 146. The capping layer 149 reduces or prevents moisture and / or oxygen from penetrating through the trimming tunnel into the display panel PNL. The capping layer 149 may be formed of organic or inorganic materials, but is not limited to these.

[0112] Figure 7 yes Figure 6 An enlarged cross-sectional view of region "B" in the image. (Using...) Figure 7 Further explanation of trimming holes TRIM.

[0113] like Figure 7 As shown, the buffer layer 142 on the substrate 140 includes a first buffer layer to a third buffer layer 142a, 142b and 142c. Each of the first buffer layer 142a and the third buffer layer 142c may be formed of silicon oxide (SiOx) and the second buffer layer 142b may be formed of silicon nitride (SiNx).

[0114] A gate insulating layer 144 is disposed on a buffer layer 142, and an interlayer insulating layer 146 is disposed on the gate insulating layer 144. A trimming via TRIM can be formed by removing a portion of the gate insulating layer 144, the interlayer insulating layer 146, and the buffer layer 142, or a portion of the gate insulating layer 144 and the buffer layer 142. In this case, the first buffer layer 142a disposed on the substrate 140 is partially removed, such that a thin first buffer layer 142a remains on the substrate 140 within the trimming via TRIM. That is, the first buffer layer 142a has a first thickness within the trimming via TRIM and a second thickness greater than the first thickness outside the trimming via TRIM.

[0115] As described later, buffer layer 142, gate insulating layer 144, or interlayer insulating layer 146 can be removed by dry etching. First buffer layer 142a and third buffer layer 142c are formed of silicon oxide, and second buffer layer 142b is formed of silicon nitride. When buffer layer 142 is etched by dry etching, a difference in etching rate between the silicon oxide layer and the silicon nitride layer causes the second buffer layer 142b to protrude from the sidewall of the trimmed via TRIM, i.e., protruding further than the first buffer layer 142a and the second buffer layer 142c. Of course, this disclosure is not limited to the configuration where the first buffer layer 142a and the third buffer layer 142c are formed of silicon oxide and the second buffer layer 142b is formed of silicon nitride. Under predetermined process conditions, the etching rate of the materials of the first buffer layer 142a and the third buffer layer 142c is greater than the etching rate of the material of the second buffer layer 142b, causing the second buffer layer 142b to protrude from the sidewall of the trimmed via TRIM.

[0116] A bridging pattern BPAT is formed in the trimming aperture TRIM and on the upper surface of the gate insulating layer 144. The bridging pattern BPAT extends from the outer edge of the display panel PNL to the trimming aperture TRIM and the upper surface of the gate insulating layer 144. Since the second buffer layer 142b protrudes from the side surfaces of the first buffer layer 142a and the third buffer layer 142c toward the trimming aperture TRIM, the bridging pattern BPAT has a step difference in the side surface of the trimming aperture TRIM. Because the second buffer layer 142b protrudes from the sidewall of the trimming aperture TRIM, a portion of the side surface of the second buffer layer 142b (e.g., the side surface of the protrusion), a portion of the lower surface of the second buffer layer 142b (e.g., the lower surface of the protrusion), and a portion of the upper surface of the second buffer layer 142b (e.g., the upper surface of the protrusion) can be covered or contacted by the bridging pattern BPAT. The buffer layer 142 with such a protrusion increases the contact area with the bridging pattern BPAT, thereby increasing the stability of the formed structure and making subsequent cutting and trimming processes more favorable.

[0117] As described above, since the display device 100 according to this disclosure includes a crack detection line PCD arranged along the outer periphery of the non-display area NA, the occurrence of cracks in the non-display area NA can be detected quickly. Therefore, when a crack occurs, measures can be taken quickly, and defects in the display device 100 can be reduced or prevented.

[0118] A method for manufacturing the display device 100 described herein will be presented.

[0119] Figures 8A to 8F This is a schematic cross-sectional view illustrating the process of manufacturing a display device according to an embodiment of the present disclosure.

[0120] like Figure 8A As shown, a buffer layer 142 is formed on the entire surface of a first substrate 140, including a display area AA and a non-display area NA. The substrate 140 may be formed of a rigid material (e.g., glass) or a flexible plastic material (e.g., polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate).

[0121] The buffer layer 142 can be formed by sequentially depositing a first buffer layer 142a of silicon oxide, a second buffer layer 142b of silicon nitride, and a third buffer layer 142c of silicon oxide.

[0122] Next, a semiconductor layer 112 is formed on the buffer layer 142 by forming and etching a polysilicon layer or an oxide semiconductor layer, such as IGZO, IZO, IGTO, or IGO. In addition, impurities may be doped into both ends of the semiconductor layer 112 to form a source region 112b and a drain region 112c on both sides of the channel region 112a.

[0123] Next, a gate insulating layer 144 is formed by depositing an inorganic insulating material (such as silicon oxide or silicon nitride). The gate insulating layer 144 is disposed in the display area AA and the non-display area NA, and covers the semiconductor layer 112.

[0124] Next, as Figure 8B As shown, etching gas is used to etch the first buffer layer to the third buffer layers 142a, 142b, and 142c, as well as the gate insulating layer 144, to form a trimming via TRIM in the non-display area NA. In this case, the etching rates of the first buffer layer 142a and the third buffer layer 142c are different from the etching rate of the second buffer layer 142b, such that the end of the second buffer layer 142b can protrude from the side surface of the trimming via TRIM into the interior (e.g., the center) of the trimming via TRIM.

[0125] Next, as Figure 8C As shown, a metal layer 114a is formed over the entire surface of substrate 140 by depositing a metal (e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, or Cu) using a sputtering method. A photoresist (PR) is applied and developed to form a first PR pattern 160a on the metal layer 114a in the display area AA, and a second PR pattern 160b and a third PR pattern 160c are formed on the metal layer 114a and the non-display area NA. The first PR pattern 160a corresponds to the channel region 112a, and the second PR pattern 160b corresponds to (…). Figure 6 The crack detection line PCD, and the third PR pattern 160c corresponds to ( Figure 8B The trimmed hole TRIM. The third PR pattern 160c corresponds to and / or covers the metal layer 114a on the bottom and sides of the trimmed hole TRIM. In other words, the third PR pattern 160c corresponds to and / or covers the metal layer 114a on the upper surface of the first buffer layer 142a and the side surfaces of the gate insulating layer 144 and the first to third buffer layers 142a to 142c.

[0126] Next, as Figure 8DAs shown, the metal layer 114a is etched using the first to third PR patterns 160a, 160b, and 160c as an etching mask to form the gate electrode 114, the crack detection line PCD, and the bridging pattern BPAT. The gate electrode 114 is disposed above the semiconductor layer 112, and the crack detection line PCD and the bridging pattern BPAT are disposed in the non-display area NA. The bridging pattern BPAT may be disposed in a portion of the upper surface of the trimming via TRIM and the gate insulating layer 144. Since the first buffer layer 142a is partially removed, the bridging pattern BPAT in the trimming via TRIM contacts the upper surface of the first buffer layer 142a.

[0127] In this disclosure, a bridging pattern BPAT is formed during the formation of the gate electrode 114 and the crack detection line PCD for the following reasons.

[0128] When depositing the metal layer 114a, the thickness of the metal layer 114a at the side surface (e.g., the inclined surface) in the trimmed via TRIM is less than the thickness of the metal layer 114a on the upper surface of the gate insulating layer 144. Therefore, as... Figure 9A As shown, when for those that do not have a TRIM corresponding to the trimming hole ( Figure 8C When the metal layer 114a of the third PR pattern 160c is etched (e.g., dry etching), the metal layer 114a at the side surface in the trimming hole TRIM is removed first.

[0129] Therefore, as Figure 9B As shown, during the etching process, the metal layer 114a1 on the gate insulating layer 144 and the metal layer 114a2 on the bottom of the trimming hole TRIM are electrically insulated by the inclined surface of the trimming hole TRIM therebetween.

[0130] Because dry etching processes use plasma or reactive gases, static electricity may be generated during etching. This static electricity creates a potential difference between the metal layer 114a1 on the upper surface of the gate insulating layer 144 and the metal layer 114a2 on the bottom of the trimming via TRIM, and this potential difference causes an arc discharge between the metal layer 114a1 on the upper surface of the gate insulating layer 144 and the metal layer 114a2 on the bottom of the trimming via TRIM. The second PR pattern 160b on the metal layer 114a1 may be damaged due to this arc discharge. Therefore, the second PR pattern 160b may be damaged or lost.

[0131] Additionally, surge voltages caused by static electricity during the etching process may be generated in the protruding portion of the second buffer layer 142b, and the second PR pattern 160b may be damaged or lost due to surge voltages.

[0132] Due to damage or loss of the second PR pattern 160b, there may be issues with the crack detection line PCD being damaged or broken during its formation. In other words, problems such as the crack detection line PCD not being formed or having poor linewidth may exist.

[0133] On the other hand, in this disclosure, by forming a third PR pattern 160c in the trimming hole TRIM, the metal layer 114a formed on the inclined surface of the trimming hole TRIM during the etching process of the metal layer 114a is prevented from being etched. Therefore, the metal layer 114a on the upper surface of the gate insulating layer 144 and the metal layer 114a inside the trimming hole TRIM are electrically connected during the etching process, which makes it possible to reduce or prevent arc discharge caused by static electricity generated during the etching process.

[0134] Additionally, by blocking the interior of the trimming hole TRIM from the outside by the third PR pattern 160c, surge voltages caused by static electricity generated during the etching process can be reduced or prevented from forming in the protruding portion of the second buffer layer 142b.

[0135] As described above, in this disclosure, by forming a third PR pattern 160c corresponding to the trimming hole TRIM, defects in the crack detection line PCD caused by static electricity during processing can be reduced or prevented.

[0136] Reference Figure 8E An interlayer insulating layer 146 is formed by depositing an organic insulating material (e.g., photoacrylic acid) or an inorganic insulating material (e.g., silicon nitride (SiNx) or silicon oxide (SiOx)). A metal (e.g., Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy) is deposited on the interlayer insulating layer 146 by sputtering and etched to form a source electrode 115 and a drain electrode 116. The source electrode 115 and the drain electrode 116 ohmically contact the source region 112b and the drain region 112c of the semiconductor layer 112 through contact holes in the interlayer insulating layer 146, respectively. A TFT T is fabricated through the above process.

[0137] Next, a planarization layer 148 in the display area AA and a capping layer 149 in the non-display area NA are formed by depositing an organic insulating material (e.g., photoacrylic acid) or an inorganic insulating material (e.g., silicon nitride (SiNx) or silicon oxide (SiOx)). The planarization layer 148 and the capping layer 149 can be formed using the same process. That is, the steps of forming the planarization layer 148 and forming the capping layer 149 are performed simultaneously. Alternatively, the planarization layer 148 and the capping layer 149 can be formed using different processes. The planarization layer 148 is positioned in the display area AA. The capping layer 149 is positioned in a trimming hole TRIM. For example, the capping layer 149 includes a first capping layer at a first portion of the trimming hole TRIM and a second capping layer at a second portion of the trimming hole TRIM. The first and second capping layers are spaced apart from each other relative to the center of the trimming hole TRIM.

[0138] Next, a first electrode 132 is formed on the planarization layer 148. For example, a transparent conductive oxide material (e.g., ITO or IZO), a metal (e.g., Ag, Au, Mo, W, or Cr), and a transparent conductive oxide material (e.g., ITO or IZO) are sequentially stacked and etched to form a first electrode 132 with a three-layer structure of a transparent conductive layer, a metal layer, and a transparent conductive layer. The first electrode 132 is connected to the drain electrode 116 of the TFT T through contact holes in the planarization layer 148.

[0139] Next, at least one of the following materials is deposited on the planarization layer 148: an inorganic insulating material (e.g., SiNx or SiOx), an organic insulating material (e.g., benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin), or a photosensitizer containing a black pigment, and etched using a dry etching process to form a dam BNK. Additionally, a dam DAM is formed in the non-display area NA, comprising a first layer made of the same material as the planarization layer 148 and a second layer made of the same material as the dam BNK.

[0140] Next, a light-emitting material is coated onto the display area AA, and a translucent (e.g., semi-transparent) alloy, such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, or LiF / Ca:Ag, is deposited to form the light-emitting layer 134 and the second electrode 136.

[0141] Next, an encapsulation layer 180 is formed, comprising a first inorganic layer (e.g., a first encapsulation layer 182) formed of an inorganic insulating material, an organic layer (e.g., a second encapsulation layer 184) formed of an organic insulating material, and an inorganic layer (e.g., a third encapsulation layer 186) formed of an inorganic insulating material. The display device 100 (or a light-emitting element (e.g., an OLED) D) is encapsulated by the encapsulation layer 180.

[0142] Next, the substrate 140 is cut and trimmed along the trimming hole to provide... Figure 8F The display device 100 in the middle.

[0143] Various methods can be used to cut the substrate 140. For example, the substrate 140 can be cut using mechanical cutting equipment such as a cutting wheel, or it can be cut using a laser. However, it is not limited to these methods. When using laser cutting equipment, a carbon dioxide laser can be used primarily, but it is not limited to these methods.

[0144] Various methods can be used to trim the substrate 140. For example, a laser can be used to trim the substrate 140. The laser can be an Nd-Yag laser, but is not limited to this. By cutting and trimming, the outer region of the display area AA is removed around the center of the trimming hole TRIM. Therefore, a display device 100 of the desired shape can be provided.

[0145] As described above, in the display device of this disclosure, a trimming hole (TRIM) is provided in a trimming region where the substrate is cut and trimmed, and a PR pattern is formed in the trimming hole during the process of forming the crack detection line (PCD). Therefore, the crack detection line (PCD) and the bridging pattern (BPAT) are maintained at the same potential, making it possible to reduce or prevent damage or loss of the PR pattern used to form the crack detection line (PCD). Thus, defects in the crack detection line (PCD) caused by damage and / or loss of the PR pattern can be reduced or prevented.

[0146] Figure 10 This is a schematic plan view of a display device according to another embodiment of the present disclosure.

[0147] like Figure 10 As shown, the display device 200 includes ( Figure 4 The display panel PNL includes a display area AA for displaying images and a non-display area NA outside the display area AA. Trimming holes (TRIMs) are formed on the outer edge of the non-display area NA of the display panel PNL. The trimming holes (TRIMs) are used to separate a mother substrate on which multiple display panels PNLs are formed into display panel PNL units or to manufacture display devices of different shapes.

[0148] A trimming hole TRIM is formed with a predetermined width from the outer edge of the non-display area NA toward the display area AA. A crack detection line PCD is provided between the trimming hole TRIM and the display area AA. The crack detection line PCD is located at a predetermined distance from the trimming hole TRIM. The trimming hole TRIM is formed along the entire periphery of the display panel PNL, and the crack detection line PCD is arranged along at least three sides of the display panel PNL. Therefore, the trimming hole TRIM and the crack detection line PCD can be arranged adjacent to each other along at least three sides of the display panel PNL.

[0149] A bridging pattern BPAT is formed in the trimming tunnel TRIM. The bridging pattern BPAT extends from the trimming tunnel TRIM to the crack detection line PCD and can be electrically connected to the crack detection line PCD. In this case, the crack detection line PCD and the bridging pattern BPAT can be formed integrally.

[0150] It will be apparent to those skilled in the art that various modifications and alterations can be made to the embodiments of this disclosure without departing from the technical concept or scope thereof. Therefore, it is intended that such modifications and alterations cover this disclosure, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area outside the display area; Light-emitting elements in the pixels of the display area; Trimming holes in the edge of the non-display area; A crack detection line is disposed between the trimming hole and the display area and surrounds the display area; as well as At least the bridging pattern in the trimming hole.

2. The display device according to claim 1, further comprising: Buffer layer on the substrate; as well as Thin-film transistors in the pixel and on the buffer layer, The thin-film transistor includes a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the gate electrode, a source electrode and a drain electrode on the interlayer insulating layer.

3. The display device according to claim 2, wherein, The crack detection line and the gate electrode are formed of the same material and are disposed in the same layer.

4. The display device according to claim 2, wherein, The bridging pattern and the gate electrode are formed of the same material and disposed in the same layer.

5. The display device according to claim 1, wherein, The bridging pattern includes a plurality of patterns arranged along the trimming hole and spaced apart from each other.

6. The display device according to claim 1, wherein, The bridging pattern, which is part of the assembly, is disposed along the trimming hole.

7. The display device according to claim 2, wherein, The bridging pattern extends from the trimming hole to the upper surface of the gate insulating layer outside the trimming hole.

8. The display device according to claim 7, wherein, The bridging pattern is connected to the crack detection line on the gate insulating layer.

9. The display device according to claim 2, wherein, The buffer layer includes a first buffer layer on the substrate, a second buffer layer on the first buffer layer, and a third buffer layer on the second buffer layer.

10. The display device according to claim 9, wherein, The trimming hole is disposed in the first buffer layer to the third buffer layer and the gate insulating layer, and From the side surface of the trimming hole, the second buffer layer protrudes further than the first and third buffer layers.

11. The display device according to claim 10, wherein, The side surface of the second buffer layer, a portion of the lower surface of the second buffer layer, and a portion of the upper surface of the second buffer layer are covered by the bridging pattern.

12. The display device according to claim 1, further comprising: A cover layer that is in the trimming hole and covers the bridging pattern.

13. The display device according to claim 1, wherein, The bridging pattern includes a first bridging pattern portion located in the trimming hole and a second bridging pattern portion located outside the trimming hole.

14. The display device according to claim 13, wherein, The first bridging pattern portion continuously covers the inner wall of the trimming hole and is connected to the second bridging pattern portion.

15. A method for manufacturing a display device, comprising: A buffer layer is formed on a substrate including both display and non-display areas; A semiconductor layer is formed on the buffer layer and in the display area; A gate insulating layer is formed on the buffer layer to cover the semiconductor layer; A trimming hole is formed along the periphery of the display area by etching the buffer layer and the gate insulating layer; A metal layer is formed on the gate insulating layer and in the trimming hole; A first photoresist pattern is formed on the metal layer and corresponding to the display area; a second photoresist pattern is formed on the metal layer and corresponding to the non-display area; and a third photoresist pattern is formed on the metal layer and corresponding to the trimming hole. The metal layer is patterned using the first to the third photoresist patterns to form a gate electrode in the display area, a crack detection line in the non-display area, and a bridging pattern in the trimming hole. An interlayer insulating layer is formed on the gate electrode and the crack detection line; Source and drain electrodes are formed on the interlayer insulating layer and in the display area; A light-emitting element is formed above the drain electrode; The substrate is cut and trimmed along the trimming holes.

16. The method according to claim 15, wherein, The step of patterning the metal layer includes etching the metal layer using an etching gas, and The etching gas reaching the trimmed hole is blocked by the third photoresist pattern.

17. The method of claim 15, further comprising: A planarization layer is formed on the drain electrode and under the light-emitting element.

18. The method of claim 17, further comprising: A covering layer is formed to cover the trimming hole.

19. The method according to claim 18, wherein, The steps of forming the planarization layer and forming the cover layer are performed simultaneously.

20. The method of claim 15, wherein, The buffer layer includes a first buffer layer on the substrate, a second buffer layer on the first buffer layer, and a third buffer layer on the second buffer layer. The trimming hole is disposed in the first buffer layer to the third buffer layer and the gate insulating layer, and From the side surface of the trimming hole, the second buffer layer protrudes further than the first and third buffer layers.

Images